Re: [PATCH v3] Add support for sparc compare-and-branch
David Miller writes: > I started working on this patch again, in order to incorporate > Richard Henderson's feedback, and I am now getting a comparison > failure. Is this what you're seeing? > > Comparing stages 2 and 3 > warning: gcc/cc1-checksum.o differs > warning: gcc/cc1plus-checksum.o differs > warning: gcc/cc1obj-checksum.o differs > Bootstrap comparison failure! > libdecnumber/decNumber.o differs > make[2]: *** [compare] Error 1 > make[1]: *** [stage3-bubble] Error 2 > make: *** [all] Error 2 > > In any case, I'm looking into it. No, if I did get the comparison failures, it seems every single file was different. It only happened for Solaris 11 bootstraps (on different machines running either 11.0 or 11.1, with either as or gas, with a vanilla tree or your patch), and was totally intermittent. So far, it seemed to affect Solaris 11 only, though, Solaris 10 didn't show it. I still haven't managed to investigate more closely. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Eric Botcazou Date: Tue, 13 Nov 2012 22:50:49 +0100 >> Thanks for finding this, that's definitely incorrect behavior. I bet there >> is some unintended override triggered by sparc4 selection, and I'll go and >> fix that soon. > > You're welcome. That's the reason why I needed to go the ASM_ARCH way, the > straightforward approach would have put the -32/-64 first. Right. And meanwhile I found the problem, there is this code block in the Sparc option parser of GAS that goes: case OPTION_XARCH: #ifdef OBJ_ELF if (strncmp (arg, "v9", 2) != 0) md_parse_option (OPTION_32, NULL); else md_parse_option (OPTION_64, NULL); #endif /* Fall through. */ And that's where the unexpected size override is happening. That test simply needs to be adjusted and I'll try to sort that out tonight. > And I managed to miss a substitution in the previous patch, so please drop it > and use the attached one instead. Thanks for this, I was just starting to work on integrating our work together and debugging the result.
Re: [PATCH v3] Add support for sparc compare-and-branch
> Thanks for finding this, that's definitely incorrect behavior. I bet there
> is some unintended override triggered by sparc4 selection, and I'll go and
> fix that soon.
You're welcome. That's the reason why I needed to go the ASM_ARCH way, the
straightforward approach would have put the -32/-64 first.
And I managed to miss a substitution in the previous patch, so please drop it
and use the attached one instead.
--
Eric BotcazouIndex: config/sparc/sparc.h
===
--- config/sparc/sparc.h (revision 193416)
+++ config/sparc/sparc.h (working copy)
@@ -195,7 +195,7 @@ extern enum cmodel sparc_cmodel;
#endif
#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG
+#define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG
#endif
#else
@@ -337,7 +337,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=niagara:%{!mv8plus:-Av9b}} \
%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
%{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
-%{mcpu=niagara4:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
+%{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \
%{!mcpu*:%(asm_cpu_default)} \
"
@@ -1746,6 +1747,12 @@ extern int sparc_indent_opcode;
#define AS_NIAGARA3_FLAG "b"
#endif
+#ifdef HAVE_AS_SPARC4
+#define AS_NIAGARA4_FLAG "-xarch=sparc4"
+#else
+#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
+#endif
+
/* We use gcc _mcount for profiling. */
#define NO_PROFILE_COUNTERS 0
Index: config/sparc/sol2.h
===
--- config/sparc/sol2.h (revision 193416)
+++ config/sparc/sol2.h (working copy)
@@ -54,19 +54,56 @@ along with GCC; see the file COPYING3.
/* Supposedly the same as vanilla sparc svr4, except for the stuff below: */
-/* This is here rather than in sparc.h because it's not known what
- other assemblers will accept. */
+/* If the assembler supports -xarch=sparc4, we switch to the explicit
+ word size selection mechanism available both in GNU as and Sun as,
+ for the Niagara4 and above configurations. */
+#ifdef HAVE_AS_SPARC4
+
+#define AS_SPARC32_FLAG ""
+#define AS_SPARC64_FLAG ""
#ifndef USE_GAS
-#define AS_SPARC64_FLAG "-xarch=v9"
-#else
-#define AS_SPARC64_FLAG "-TSO -64 -Av9"
+#undef ASM_ARCH32_SPEC
+#define ASM_ARCH32_SPEC "-m32"
+#undef ASM_ARCH64_SPEC
+#define ASM_ARCH64_SPEC "-m64"
#endif
+/* Both Sun as and GNU as understand -K PIC. */
+#undef ASM_SPEC
+#define ASM_SPEC ASM_SPEC_BASE " %(asm_arch)" ASM_PIC_SPEC
+
+#else /* HAVE_AS_SPARC4 */
+
+#define AS_SPARC32_FLAG "-xarch=v8plus"
+#define AS_SPARC64_FLAG "-xarch=v9"
+
+#undef AS_NIAGARA4_FLAG
+#define AS_NIAGARA4_FLAG AS_NIAGARA3_FLAG
+
+#undef ASM_ARCH32_SPEC
+#define ASM_ARCH32_SPEC ""
+
+#undef ASM_ARCH64_SPEC
+#define ASM_ARCH64_SPEC ""
+
+#undef ASM_ARCH_DEFAULT_SPEC
+#define ASM_ARCH_DEFAULT_SPEC ""
+
+#undef ASM_ARCH_SPEC
+#define ASM_ARCH_SPEC ""
+
+/* Both Sun as and GNU as understand -K PIC. */
+#undef ASM_SPEC
+#define ASM_SPEC ASM_SPEC_BASE ASM_PIC_SPEC
+
+#endif /* HAVE_AS_SPARC4 */
+
+
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC ""
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9"
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
#undef CPP_CPU64_DEFAULT_SPEC
@@ -83,7 +120,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusa"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "a"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9a"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -94,7 +131,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -105,7 +142,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -116,7 +153,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -127,7 +164,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" AS_NIAGARA3_FLAG
#undef ASM_CPU64_D
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Eric Botcazou Date: Tue, 13 Nov 2012 20:32:40 +0100 > Working on this, I discovered an oddity in GNU as: -xarch=sparc4 -64 yields a > 64-bit object file whereas -64 -xarch=sparc4 yields a 32-bit object file. My > understanding is that Sun as will generate a 64-bit object file in both cases. Thanks for finding this, that's definitely incorrect behavior. I bet there is some unintended override triggered by sparc4 selection, and I'll go and fix that soon.
Re: [PATCH v3] Add support for sparc compare-and-branch
> We really need to start using the newer names, as Sun is not going to
> provide single letter indicators for sparc4 or future xarch values.
>
> In fact, that's exactly what needed to be worked on from the beginning
> for the solaris side of this cbcond patch. We're talking in circles.
OK, sorry for the fiasco... I can propose the attached patch (for sparc.h and
sol2.h only).
Working on this, I discovered an oddity in GNU as: -xarch=sparc4 -64 yields a
64-bit object file whereas -64 -xarch=sparc4 yields a 32-bit object file. My
understanding is that Sun as will generate a 64-bit object file in both cases.
* config/sparc/sparc.h (ASM_CPU64_DEFAULT_SPEC): Adjust for Niagara4.
(ASM_CPU_SPEC): Likewise.
(AS_NIAGARA4_FLAG): Define.
* config/sparc/sol2.h (AS_SPARC32_FLAG): Define.
(AS_SPARC64_FLAG): Drop -TSO and adjust.
(AS_NIAGARA4_FLAG): Redefine if !HAVE_AS_SPARC4.
(ASM_CPU32_DEFAULT_SPEC): Use AS_SPARC32_FLAG for Niagara4 only.
(ASM_CPU64_DEFAULT_SPEC): Likewise with AS_NIAGARA4_FLAG.
(ASM_CPU_SPEC): Adjust similarly.
(ASM_SPEC): Add " %(asm_arch)" if HAVE_AS_SPARC4 and adjust.
(ASM_ARCH32_SPEC): Redefine if USE_GAS.
(ASM_ARCH64_SPEC): Likewise.
--
Eric BotcazouIndex: config/sparc/sparc.h
===
--- config/sparc/sparc.h (revision 193416)
+++ config/sparc/sparc.h (working copy)
@@ -195,7 +195,7 @@ extern enum cmodel sparc_cmodel;
#endif
#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG
+#define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG
#endif
#else
@@ -337,7 +337,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=niagara:%{!mv8plus:-Av9b}} \
%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
%{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
-%{mcpu=niagara4:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
+%{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \
%{!mcpu*:%(asm_cpu_default)} \
"
@@ -1746,6 +1747,12 @@ extern int sparc_indent_opcode;
#define AS_NIAGARA3_FLAG "b"
#endif
+#ifdef HAVE_AS_SPARC4
+#define AS_NIAGARA4_FLAG "-xarch=sparc4"
+#else
+#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
+#endif
+
/* We use gcc _mcount for profiling. */
#define NO_PROFILE_COUNTERS 0
Index: config/sparc/sol2.h
===
--- config/sparc/sol2.h (revision 193416)
+++ config/sparc/sol2.h (working copy)
@@ -54,13 +54,14 @@ along with GCC; see the file COPYING3.
/* Supposedly the same as vanilla sparc svr4, except for the stuff below: */
-/* This is here rather than in sparc.h because it's not known what
- other assemblers will accept. */
-
-#ifndef USE_GAS
-#define AS_SPARC64_FLAG "-xarch=v9"
+#ifdef HAVE_AS_SPARC4
+#define AS_SPARC32_FLAG ""
+#define AS_SPARC64_FLAG ""
#else
-#define AS_SPARC64_FLAG "-TSO -64 -Av9"
+#define AS_SPARC32_FLAG "-xarch=v8plus"
+#define AS_SPARC64_FLAG "-xarch=v9"
+#undef AS_NIAGARA4_FLAG
+#define AS_NIAGARA4_FLAG AS_NIAGARA3_FLAG
#endif
#undef ASM_CPU32_DEFAULT_SPEC
@@ -83,7 +84,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusa"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "a"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9a"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -94,7 +95,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -105,7 +106,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -116,7 +117,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b"
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
#endif
@@ -127,7 +128,7 @@ along with GCC; see the file COPYING3.
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" AS_NIAGARA3_FLAG
#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA3_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9" AS_NIAGARA3_FLAG
#undef ASM_CPU_DEFAULT_SPEC
#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPE
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Rainer Orth Date: Fri, 26 Oct 2012 11:14:33 +0200 > I tried a bootstrap on Solaris 11.1, but ran into lots of comparison > failures I've not yet investigated. I started working on this patch again, in order to incorporate Richard Henderson's feedback, and I am now getting a comparison failure. Is this what you're seeing? Comparing stages 2 and 3 warning: gcc/cc1-checksum.o differs warning: gcc/cc1plus-checksum.o differs warning: gcc/cc1obj-checksum.o differs Bootstrap comparison failure! libdecnumber/decNumber.o differs make[2]: *** [compare] Error 1 make[1]: *** [stage3-bubble] Error 2 make: *** [all] Error 2 In any case, I'm looking into it.
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Richard Henderson Date: Mon, 12 Nov 2012 09:56:21 -0800 > On 10/22/2012 08:39 PM, David Miller wrote: >> + /* Compare and Branch is limited to +-2KB. If it is too far away, >> + change >> + >> + cxbne X, Y, .LC30 >> + >> + to >> + >> + cxbe X, Y, .+12 >> + ba,pt xcc, .LC30 >> + nop */ > > Based on your no-control-after cbcond comment at the top > of the patch, surely this should contain another nop as well. Indeed, I'll fix this up. > And surely all this code isn't so performance sensitive that > it needs to be written in such an unreadable way. Sure, I'll change the code to use one of the the clearer mechanisms you suggested. Thanks for the review.
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Eric Botcazou Date: Mon, 12 Nov 2012 09:35:48 +0100 >> I strongly doubt that they will be different from the options >> supported both in cc and fbe in the Solaris Studio 12.3 release: > > They need to provide some form of backward compatibility though, they cannot > break the interface of 'as' like that. Apparently 'fbe' has had its own set > of -xarch values for a while and they haven't been compatible with 'as'. You give them far too much credit :-) The 'as' updates constantly add inconsistencies in options and behavior, and even worse (in my opinion) they effectively stopped updating the 'as' manual page in this area.
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Rainer Orth Date: Mon, 12 Nov 2012 16:46:37 +0100 > Eric Botcazou writes: > >>> No, quite the contrary. as is just a (sometimes partial) backport of >>> Studio fbe, though it's hard to tell exactly which Studio version of fbe >>> forms the basis of as. Especially for the Solaris 10 as patches, only >>> particular bugfixes/enhancements have been backported. >>> >>> Backward compatibility is maintained, of course. as(1) lists >>> >>> -xarch=v9 >>> >>> Equivalent to: -m64 -xarch=sparc >>> >>> and many more. >> >> Does it list -xarch=v8pluse/-xarch=v9e as equivalent to -m32/64 >> -xarch=sparc4? >> If so, I don't think that we need to change our scheme, using 'e' instead of >> 'd' for SPARC4 instructions should work just fine with both GNU and Sun as. > > as(1) mentions no -xarch value beyond v9b, while strings on the as binary > reveals v9, v9[a-dv], but no v9e. Seems to be a gas invention. It is indeed, a gas invention. We really need to start using the newer names, as Sun is not going to provide single letter indicators for sparc4 or future xarch values. In fact, that's exactly what needed to be worked on from the beginning for the solaris side of this cbcond patch. We're talking in circles. :-)
Re: [PATCH v3] Add support for sparc compare-and-branch
On 10/22/2012 08:39 PM, David Miller wrote:
> + /* Compare and Branch is limited to +-2KB. If it is too far away,
> + change
> +
> + cxbne X, Y, .LC30
> +
> + to
> +
> + cxbe X, Y, .+12
> + ba,pt xcc, .LC30
> + nop */
Based on your no-control-after cbcond comment at the top
of the patch, surely this should contain another nop as well.
> + *p++ = '\t';
> + *p++ = '%';
> + *p++ = '1';
> + *p++ = ',';
> + *p++ = ' ';
> + *p++ = '%';
> + *p++ = '2';
> + *p++ = ',';
> + *p++ = ' ';
And surely all this code isn't so performance sensitive that
it needs to be written in such an unreadable way.
p = stpcpy (p, "\t%1, %2, ");
is at least a little better.
Though really there's just 3 variable portions of the pattern, so
I wonder if a lesser number of snprintf calls might be good enough.
if (far)
{
if (veryfar)
snprintf (buf, sizeof(buf), "c%cb%s\t%%1, %%2, .+16\n\t"
"b\t%%l3\n\t nop", size_char, cond_str);
else
snprintf (buf, sizeof(buf), "c%cb%s\t%%1, %%2, .+16\n\t"
"ba,pt\t%%xcc,%%l3\n\t nop", size_char, cond_str);
}
else
snprintf (buf, sizeof(buf), "c%cb%s\t%%1, %%2, %%l3", size_char, cond_str);
r~
Re: [PATCH v3] Add support for sparc compare-and-branch
Eric Botcazou writes: >> No, quite the contrary. as is just a (sometimes partial) backport of >> Studio fbe, though it's hard to tell exactly which Studio version of fbe >> forms the basis of as. Especially for the Solaris 10 as patches, only >> particular bugfixes/enhancements have been backported. >> >> Backward compatibility is maintained, of course. as(1) lists >> >> -xarch=v9 >> >> Equivalent to: -m64 -xarch=sparc >> >> and many more. > > Does it list -xarch=v8pluse/-xarch=v9e as equivalent to -m32/64 -xarch=sparc4? > If so, I don't think that we need to change our scheme, using 'e' instead of > 'd' for SPARC4 instructions should work just fine with both GNU and Sun as. as(1) mentions no -xarch value beyond v9b, while strings on the as binary reveals v9, v9[a-dv], but no v9e. Seems to be a gas invention. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Re: [PATCH v3] Add support for sparc compare-and-branch
> No, quite the contrary. as is just a (sometimes partial) backport of > Studio fbe, though it's hard to tell exactly which Studio version of fbe > forms the basis of as. Especially for the Solaris 10 as patches, only > particular bugfixes/enhancements have been backported. > > Backward compatibility is maintained, of course. as(1) lists > > -xarch=v9 > > Equivalent to: -m64 -xarch=sparc > > and many more. Does it list -xarch=v8pluse/-xarch=v9e as equivalent to -m32/64 -xarch=sparc4? If so, I don't think that we need to change our scheme, using 'e' instead of 'd' for SPARC4 instructions should work just fine with both GNU and Sun as. -- Eric Botcazou
Re: [PATCH v3] Add support for sparc compare-and-branch
Eric Botcazou writes: >> I strongly doubt that they will be different from the options >> supported both in cc and fbe in the Solaris Studio 12.3 release: > > They need to provide some form of backward compatibility though, they cannot > break the interface of 'as' like that. Apparently 'fbe' has had its own set > of -xarch values for a while and they haven't been compatible with 'as'. No, quite the contrary. as is just a (sometimes partial) backport of Studio fbe, though it's hard to tell exactly which Studio version of fbe forms the basis of as. Especially for the Solaris 10 as patches, only particular bugfixes/enhancements have been backported. Backward compatibility is maintained, of course. as(1) lists -xarch=v9 Equivalent to: -m64 -xarch=sparc and many more. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Re: [PATCH v3] Add support for sparc compare-and-branch
> I strongly doubt that they will be different from the options > supported both in cc and fbe in the Solaris Studio 12.3 release: They need to provide some form of backward compatibility though, they cannot break the interface of 'as' like that. Apparently 'fbe' has had its own set of -xarch values for a while and they haven't been compatible with 'as'. -- Eric Botcazou
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Eric Botcazou Date: Sun, 11 Nov 2012 23:28:38 +0100 >> Eric and Rainer, I think that functionally this patch is fully ready >> to go into the tree except for the Solaris aspects which I do not have >> the means to work on. Have either of you made any progress in this >> area? > > Rainer, could you post an excerpt of the man page of a recent 'as' supporting > the SPARC-T4? I'm mainly interested in the values of the -xarch= option. > > Thanks in advance. I strongly doubt that they will be different from the options supported both in cc and fbe in the Solaris Studio 12.3 release: -xarch=sparc Enables the assembler to accept instructions defined in the SPARC-V9 architecture. The resulting object code is in ELF32 format when compiled with -m32, ELF64 format with -m64. It will not execute on a Oracle Solaris V8 system (a machine with a V8 processor). It will exe- cute on a Oracle Solaris V8+ system. -xarch=sparcvis Enables the assembler to accept instructions defined in the SPARC-V9 architecture plus the instructions in the Visual Instruction Set (VIS) version 1.0. The resulting object code is in V8+ ELF32 format when compiled with -m32, ELF64 format with -m64. It will not execute on a Oracle Solaris system with a V8 processor. It will execute on a Oracle Solaris system with a V8+ processor. -xarch=sparcvis2 Enables the assembler to accept instructions defined in the SPARC-V9 architecture, plus the instructions in the Visual Instruction Set (VIS) version 2.0, with UltraSPARC-III exten- sions. The resulting object code is in V8+ ELF32 format when compiled with -m32, ELF64 format with -m64. -xarch=sparcvis3 Accept instructions defined for the SPARC VIS version 3 of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the fused multiply-add instructions, and the Visual Instruction Set (VIS) version 3.0 -xarch=sparcfmaf Accept instructions defined for the sparcfmaf version of the SPARC-V9 ISA, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, and the SPARC64 VI extensions for floating-point multiply-add. -xarch=sparcima Accept instructions defined for the sparcima version of the SPARC-V9 ISA which are instruc- tions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add. -xarch=sparc4 Accept instructions defined for the sparc4 ver- sion of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS 2.0, the fused floating-point multiply-add instructions, VIS 3.0, and SPARC4 instructions.
Re: [PATCH v3] Add support for sparc compare-and-branch
> Eric and Rainer, I think that functionally this patch is fully ready > to go into the tree except for the Solaris aspects which I do not have > the means to work on. Have either of you made any progress in this > area? Rainer, could you post an excerpt of the man page of a recent 'as' supporting the SPARC-T4? I'm mainly interested in the values of the -xarch= option. Thanks in advance. -- Eric Botcazou
Re: [PATCH v3] Add support for sparc compare-and-branch
From: Eric Botcazou
Date: Fri, 26 Oct 2012 10:57 +0200
>> @@ -1088,7 +1093,12 @@ sparc_option_override (void)
>>if (TARGET_VIS3)
>> target_flags |= MASK_VIS2 | MASK_VIS;
>>
>> - /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
>> + /* -mcbcond implies -mvis3, -mvis2 and -mvis */
>> + if (TARGET_CBCOND)
>> +target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS;
>
>> +@item -mcbcond
>> +@itemx -mno-cbcond
>> +@opindex mcbcond
>> +@opindex mno-cbcond
>> +With @option{-mcbcond}, GCC generates code that takes advantage of
>> +compare-and-branch instructions, as defined in the Sparc Architecture 2011.
>> +The default is @option{-mcbcond} when targeting a cpu that supports such
>> +instructions, such as niagara-4 and later. Setting @option{-mcbcond} also
>> +sets @option{-mvis3}, @option{-mvis2}, and @option{-mvis}.
>
> Why? If -mcpu=niagara4 implies -mcbcond and -mvis3, I don't see the point.
Ok. I'll make cbcond independent of the other switches.
>> + if (TARGET_CBCOND
>> + && GET_CODE (operands[1]) == REG
>> + && (GET_MODE (operands[1]) == SImode
>> + || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
>> + && (GET_CODE (operands[2]) != CONST_INT
>> + || SPARC_SIMM5_P (INTVAL (operands[2]
>> +{
>> + emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2],
>> operands[3]); + return;
>> +}
>
> Long line.
Thanks, will fix.
>> +#ifndef HAVE_AS_SPARC4
>> +#define AS_NIAGARA4_FLAG " -xarch=v9b"
>> +#else
>> +#define AS_NIAGARA4_FLAG " -xarch=sparc4"
>> +#endif
>
> Won't this override the AS_NIAGARA3_FLAG logic for -mcpu=niagara4? You'll
> have v9d for -mcpu=niagara3 but v9b for -mcpu=niagara4 if the assembler
> doesn't support sparc4.
This is part of what we need to sort out. What I'd really like is for
both the Solaris and generic definitions to share the switch since they
can be the same.
I'll make sure this uses the NIAGARA3 switch as the backup in the final
version I commit.
>> +;; True if we are making use of compare-and-branch instructions.
>> +;; True if we should emit a nop after a cbcond instruction
>> +(define_attr "emit_cbcond_nop" "false,true"
>> + (symbol_ref "(emit_cbcond_nop (insn)
>> +? EMIT_CBCOND_NOP_TRUE : EMIT_CBCOND_NOP_FALSE)"))
>> +
>> (define_attr "branch_type" "none,icc,fcc,reg"
>>(const_string "none"))
>
> There seems to be one superfluous comment line.
Thanks for pointing that out, I'll fix it up.
> Otherwise looks good. Thanks for having introduced the -mcbcond switch, I
> think that's perfectly appropriate for a feature like this brand new set of
> branch instructions.
Thanks for reviewing.
Re: [PATCH v3] Add support for sparc compare-and-branch
David Miller writes: >> Eric and Rainer, I think that functionally this patch is fully ready >> to go into the tree except for the Solaris aspects which I do not have >> the means to work on. Have either of you made any progress in this >> area? > > Just wondering if either of you have had a chance to look into this? I tried a bootstrap on Solaris 11.1, but ran into lots of comparison failures I've not yet investigated. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Re: [PATCH v3] Add support for sparc compare-and-branch
> Eric and Rainer, I think that functionally this patch is fully ready
> to go into the tree except for the Solaris aspects which I do not have
> the means to work on. Have either of you made any progress in this
> area?
Not yet, but I'll have a look at the beginning of next week.
Some remarks:
> @@ -1088,7 +1093,12 @@ sparc_option_override (void)
>if (TARGET_VIS3)
> target_flags |= MASK_VIS2 | MASK_VIS;
>
> - /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
> + /* -mcbcond implies -mvis3, -mvis2 and -mvis */
> + if (TARGET_CBCOND)
> +target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS;
> +@item -mcbcond
> +@itemx -mno-cbcond
> +@opindex mcbcond
> +@opindex mno-cbcond
> +With @option{-mcbcond}, GCC generates code that takes advantage of
> +compare-and-branch instructions, as defined in the Sparc Architecture 2011.
> +The default is @option{-mcbcond} when targeting a cpu that supports such
> +instructions, such as niagara-4 and later. Setting @option{-mcbcond} also
> +sets @option{-mvis3}, @option{-mvis2}, and @option{-mvis}.
Why? If -mcpu=niagara4 implies -mcbcond and -mvis3, I don't see the point.
> + /* If we can tell early on that the comparison is against a constant
> + that won't fit in the 5-bit signed immediate field of a cbcond,
> + use one of the other v9 conditional branch sequences. */
> + if (TARGET_CBCOND
> + && GET_CODE (operands[1]) == REG
> + && (GET_MODE (operands[1]) == SImode
> + || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
> + && (GET_CODE (operands[2]) != CONST_INT
> + || SPARC_SIMM5_P (INTVAL (operands[2]
> +{
> + emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2],
> operands[3]); + return;
> +}
Long line.
> +#ifndef HAVE_AS_SPARC4
> +#define AS_NIAGARA4_FLAG " -xarch=v9b"
> +#else
> +#define AS_NIAGARA4_FLAG " -xarch=sparc4"
> +#endif
Won't this override the AS_NIAGARA3_FLAG logic for -mcpu=niagara4? You'll
have v9d for -mcpu=niagara3 but v9b for -mcpu=niagara4 if the assembler
doesn't support sparc4.
> +;; True if we are making use of compare-and-branch instructions.
> +;; True if we should emit a nop after a cbcond instruction
> +(define_attr "emit_cbcond_nop" "false,true"
> + (symbol_ref "(emit_cbcond_nop (insn)
> +? EMIT_CBCOND_NOP_TRUE : EMIT_CBCOND_NOP_FALSE)"))
> +
> (define_attr "branch_type" "none,icc,fcc,reg"
>(const_string "none"))
There seems to be one superfluous comment line.
Otherwise looks good. Thanks for having introduced the -mcbcond switch, I
think that's perfectly appropriate for a feature like this brand new set of
branch instructions.
--
Eric Botcazou
Re: [PATCH v3] Add support for sparc compare-and-branch
From: David Miller Date: Mon, 22 Oct 2012 23:39:23 -0400 (EDT) > Eric and Rainer, I think that functionally this patch is fully ready > to go into the tree except for the Solaris aspects which I do not have > the means to work on. Have either of you made any progress in this > area? Just wondering if either of you have had a chance to look into this? Thanks!
