Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-11 Thread Ramana Radhakrishnan 



On 10/05/15 23:16, Martin Galvan wrote:

Hi Ramana! Sorry to bother, but I looked at the repository and didn't
see this committed. As I don't have write access could you please
commit this for me?

Thanks a lot!



sorry about the slow response, I was travelling for a bit and missed 
your emails. Trying your patch out gives me failures possibly because my 
mail client munged it when it received this inline.


Can you please rebase if necessary, test and send it again as an 
attachment ?


patch -p1 --dry-run < ~/Downloads/martin-patch.txt
checking file libgcc/config/arm/ieee754-df.S
Hunk #2 FAILED at 57.
Hunk #3 succeeded at 70 with fuzz 2.
Hunk #4 FAILED at 86.
Hunk #5 FAILED at 153.
Hunk #6 FAILED at 418.
Hunk #7 FAILED at 425.
Hunk #8 FAILED at 440.
Hunk #9 FAILED at 462.
Hunk #10 FAILED at 485.
Hunk #11 FAILED at 555.
Hunk #12 FAILED at 566.
Hunk #13 FAILED at 601.
Hunk #14 FAILED at 653.
Hunk #15 FAILED at 720.
Hunk #16 FAILED at 868.
Hunk #17 FAILED at 1057.
Hunk #18 FAILED at 1068.
Hunk #19 FAILED at 1082.
Hunk #20 FAILED at 1090.
Hunk #21 FAILED at 1122.
Hunk #22 FAILED at 1133.
Hunk #23 succeeded at 1145 with fuzz 2.
Hunk #24 FAILED at 1155.
Hunk #25 FAILED at 1168.
Hunk #26 FAILED at 1228.
Hunk #27 succeeded at 1236 with fuzz 2.
Hunk #28 FAILED at 1254.
Hunk #29 succeeded at 1263 with fuzz 2.
Hunk #30 FAILED at 1297.
Hunk #31 succeeded at 1306 with fuzz 2.
Hunk #32 FAILED at 1336.
Hunk #33 succeeded at 1345 with fuzz 2.
Hunk #34 FAILED at 1410.
27 out of 34 hunks FAILED
checking file libgcc/config/arm/ieee754-sf.S
Hunk #1 FAILED at 31.
Hunk #4 FAILED at 294.
Hunk #9 FAILED at 460.
Hunk #10 FAILED at 471.
Hunk #16 FAILED at 845.
Hunk #20 FAILED at 898.
6 out of 27 hunks FAILED
checking file libgcc/config/arm/lib1funcs.S

regards
Ramana


On Tue, Apr 28, 2015 at 2:07 PM, Martin Galvan
 wrote:

Thanks a lot. I don't have write access to the repository, could you
commit this for me?

On Tue, Apr 28, 2015 at 1:21 PM, Ramana Radhakrishnan
 wrote:

On Tue, Apr 28, 2015 at 4:19 PM, Martin Galvan
 wrote:

This patch adds CFI directives to the soft floating point support code for ARM.

Previously, if we tried to do a backtrace from that code in a debug session we'd
get something like this:

(gdb) bt
#0  __nedf2 () at 
../../../../../../gcc-4.9.2/libgcc/config/arm/ieee754-df.S:1082
#1  0x0db6 in __aeabi_cdcmple () at 
../../../../../../gcc-4.9.2/libgcc/config/arm/ieee754-df.S:1158
#2  0xf5c28f5c in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)

Now we'll get something like this:

(gdb) bt
#0  __nedf2 () at 
../../../../../../gcc-4.9.2/libgcc/config/arm/ieee754-df.S:1156
#1  0x0db6 in __aeabi_cdcmple () at 
../../../../../../gcc-4.9.2/libgcc/config/arm/ieee754-df.S:1263
#2  0x0dc8 in __aeabi_dcmpeq () at 
../../../../../../gcc-4.9.2/libgcc/config/arm/ieee754-df.S:1285
#3  0x0504 in main ()

I have a company-wide copyright assignment. I don't have commit access, though, 
so it would be great if anyone could commit this for me.

Thanks a lot!



this is OK , thanks. Sorry about the delay in reviewing this.

Ramana

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-12 Thread Ramana Radhakrishnan 



On 11/05/15 20:44, Martin Galvan wrote:

On Mon, May 11, 2015 at 4:45 AM, Ramana Radhakrishnan 
 wrote:

sorry about the slow response, I was travelling for a bit and missed your
emails. Trying your patch out gives me failures possibly because my mail
client munged it when it received this inline.

Can you please rebase if necessary, test and send it again as an attachment?


I checked it again and it seems to be a whitespace issue.
I re-generated the patch and this one seems to apply just fine; try it out
again.



That's what I mean when I say email clients "munged it" : email clients 
and / or some popular email servers appear to end up munging white 
spaces and patches don't apply cleanly.


So, no it doesn't work - once you've sent it through your email client / 
server. I am unable to apply the patch as it stands today either taking 
the raw text from the gcc-patches archive or from your email message in 
my inbox. It's not like line endings and things have been munged but 
every whitespace / tab is in trouble here.


Please send it back as an attachment if you want me to apply it.

regards
Ramana



---
libgcc/config/arm/ieee754-df.S | 177 +---
libgcc/config/arm/ieee754-sf.S | 101 ++--
libgcc/config/arm/lib1funcs.S  |  10 ++
3 files changed, 261 insertions(+), 27 deletions(-)

diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index f75630b..d1f9066 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -33,8 +33,12 @@
   * Only the default rounding mode is intended for best performances.
   * Exceptions aren't supported yet, but that can be added quite easily
   * if necessary without impacting performances.
+ *
+ * In the CFI related comments, 'previousOffset' refers to the previous offset
+ * from sp used to compute the CFA.
   */

+.cfi_sections .debug_frame

  #ifndef __ARMEB__
  #define xl r0
@@ -53,11 +57,13 @@

  ARM_FUNC_START negdf2
  ARM_FUNC_ALIAS aeabi_dneg negdf2
+CFI_START_FUNCTION

  @ flip sign bit
  eor xh, xh, #0x8000
  RET

+CFI_END_FUNCTION
  FUNC_END aeabi_dneg
  FUNC_END negdf2

@@ -66,6 +72,7 @@ ARM_FUNC_ALIAS aeabi_dneg negdf2
  #ifdef L_arm_addsubdf3

  ARM_FUNC_START aeabi_drsub
+CFI_START_FUNCTION

  eor xh, xh, #0x8000 @ flip sign bit of first arg
  b   1f
@@ -81,7 +88,11 @@ ARM_FUNC_ALIAS aeabi_dsub subdf3
  ARM_FUNC_START adddf3
  ARM_FUNC_ALIAS aeabi_dadd adddf3

-1:  do_push {r4, r5, lr}
+1:  do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp to sp + 8
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8

  @ Look for zeroes, equal values, INF, or NAN.
  shift1  lsl, r4, xh, #1
@@ -148,6 +159,11 @@ ARM_FUNC_ALIAS aeabi_dadd adddf3
  @ Since this is not common case, rescale them off line.
  teq r4, r5
  beq LSYM(Lad_d)
+
+@ CFI note: we're lucky that the branches to Lad_* that appear after this 
function
+@ have a CFI state that's exactly the same as the one we're in at this
+@ point. Otherwise the CFI would change to a different state after the branch,
+@ which would be disastrous for backtracing.
  LSYM(Lad_x):

  @ Compensate for the exponent overlapping the mantissa MSB added later
@@ -413,6 +429,7 @@ LSYM(Lad_i):
  orrne   xh, xh, #0x0008 @ quiet NAN
  RETLDM  "r4, r5"

+CFI_END_FUNCTION
  FUNC_END aeabi_dsub
  FUNC_END subdf3
  FUNC_END aeabi_dadd
@@ -420,12 +437,19 @@ LSYM(Lad_i):

  ARM_FUNC_START floatunsidf
  ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
+CFI_START_FUNCTION

  teq r0, #0
  do_it   eq, t
  moveq   r1, #0
  RETc(eq)
-do_push {r4, r5, lr}
+
+do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
  mov r4, #0x400  @ initial exponent
  add r4, r4, #(52-1 - 1)
  mov r5, #0  @ sign bit is 0
@@ -435,17 +459,25 @@ ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
  mov xh, #0
  b   LSYM(Lad_l)

+CFI_END_FUNCTION
  FUNC_END aeabi_ui2d
  FUNC_END floatunsidf

  ARM_FUNC_START floatsidf
  ARM_FUNC_ALIAS aeabi_i2d floatsidf
+CFI_START_FUNCTION

  teq r0, #0
  do_it   eq, t
  moveq   r1, #0
  RETc(eq)
-do_push {r4, r5, lr}
+
+do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
  mov r4, #0x400  @ initial exponent
  add r4, r4, #(52-1 - 1)
  andsr5, r0, #0x8000 @ sign bit in r5
@@ -457,11 +489,13 @@ ARM_FUNC_ALIAS aeabi_i2d floatsidf
  mov xh, #0
  b   LSYM(

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-12 Thread Martin Galvan 
On Tue, May 12, 2015 at 5:49 AM, Ramana Radhakrishnan
 wrote:
> That's what I mean when I say email clients "munged it" : email clients and
> / or some popular email servers appear to end up munging white spaces and
> patches don't apply cleanly.
>
> So, no it doesn't work - once you've sent it through your email client /
> server. I am unable to apply the patch as it stands today either taking the
> raw text from the gcc-patches archive or from your email message in my
> inbox. It's not like line endings and things have been munged but every
> whitespace / tab is in trouble here.
>
> Please send it back as an attachment if you want me to apply it.

Oh, I see! Sorry for that, I thought the problem was on my side.
Here's the patch, it's the cfi.patch file.
diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index f75630b..d1f9066 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -33,8 +33,12 @@
  * Only the default rounding mode is intended for best performances.
  * Exceptions aren't supported yet, but that can be added quite easily
  * if necessary without impacting performances.
+ *
+ * In the CFI related comments, 'previousOffset' refers to the previous offset
+ * from sp used to compute the CFA.
  */

+.cfi_sections .debug_frame

 #ifndef __ARMEB__
 #define xl r0
@@ -53,11 +57,13 @@

 ARM_FUNC_START negdf2
 ARM_FUNC_ALIAS aeabi_dneg negdf2
+CFI_START_FUNCTION

 @ flip sign bit
 eor xh, xh, #0x8000
 RET

+CFI_END_FUNCTION
 FUNC_END aeabi_dneg
 FUNC_END negdf2

@@ -66,6 +72,7 @@ ARM_FUNC_ALIAS aeabi_dneg negdf2
 #ifdef L_arm_addsubdf3

 ARM_FUNC_START aeabi_drsub
+CFI_START_FUNCTION

 eor xh, xh, #0x8000 @ flip sign bit of first arg
 b   1f
@@ -81,7 +88,11 @@ ARM_FUNC_ALIAS aeabi_dsub subdf3
 ARM_FUNC_START adddf3
 ARM_FUNC_ALIAS aeabi_dadd adddf3

-1:  do_push {r4, r5, lr}
+1:  do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp to sp + 8
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8

 @ Look for zeroes, equal values, INF, or NAN.
 shift1  lsl, r4, xh, #1
@@ -148,6 +159,11 @@ ARM_FUNC_ALIAS aeabi_dadd adddf3
 @ Since this is not common case, rescale them off line.
 teq r4, r5
 beq LSYM(Lad_d)
+
+@ CFI note: we're lucky that the branches to Lad_* that appear after this function
+@ have a CFI state that's exactly the same as the one we're in at this
+@ point. Otherwise the CFI would change to a different state after the branch,
+@ which would be disastrous for backtracing.
 LSYM(Lad_x):

 @ Compensate for the exponent overlapping the mantissa MSB added later
@@ -413,6 +429,7 @@ LSYM(Lad_i):
 orrne   xh, xh, #0x0008 @ quiet NAN
 RETLDM  "r4, r5"

+CFI_END_FUNCTION
 FUNC_END aeabi_dsub
 FUNC_END subdf3
 FUNC_END aeabi_dadd
@@ -420,12 +437,19 @@ LSYM(Lad_i):

 ARM_FUNC_START floatunsidf
 ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
+CFI_START_FUNCTION

 teq r0, #0
 do_it   eq, t
 moveq   r1, #0
 RETc(eq)
-do_push {r4, r5, lr}
+
+do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
 mov r4, #0x400  @ initial exponent
 add r4, r4, #(52-1 - 1)
 mov r5, #0  @ sign bit is 0
@@ -435,17 +459,25 @@ ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
 mov xh, #0
 b   LSYM(Lad_l)

+CFI_END_FUNCTION
 FUNC_END aeabi_ui2d
 FUNC_END floatunsidf

 ARM_FUNC_START floatsidf
 ARM_FUNC_ALIAS aeabi_i2d floatsidf
+CFI_START_FUNCTION

 teq r0, #0
 do_it   eq, t
 moveq   r1, #0
 RETc(eq)
-do_push {r4, r5, lr}
+
+do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
 mov r4, #0x400  @ initial exponent
 add r4, r4, #(52-1 - 1)
 andsr5, r0, #0x8000 @ sign bit in r5
@@ -457,11 +489,13 @@ ARM_FUNC_ALIAS aeabi_i2d floatsidf
 mov xh, #0
 b   LSYM(Lad_l)

+CFI_END_FUNCTION
 FUNC_END aeabi_i2d
 FUNC_END floatsidf

 ARM_FUNC_START extendsfdf2
 ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
+CFI_START_FUNCTION

 movsr2, r0, lsl #1  @ toss sign bit
 mov xh, r2, asr #3  @ stretch exponent
@@ -480,34 +514,54 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2

 @ value was denormalized.  We can normalize it now.
 do_push {r4, r5, lr}
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
 mov r4, #0x380

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-13 Thread Ramana Radhakrishnan 



On 12/05/15 14:01, Martin Galvan wrote:

On Tue, May 12, 2015 at 5:49 AM, Ramana Radhakrishnan
 wrote:

That's what I mean when I say email clients "munged it" : email clients and
/ or some popular email servers appear to end up munging white spaces and
patches don't apply cleanly.

So, no it doesn't work - once you've sent it through your email client /
server. I am unable to apply the patch as it stands today either taking the
raw text from the gcc-patches archive or from your email message in my
inbox. It's not like line endings and things have been munged but every
whitespace / tab is in trouble here.

Please send it back as an attachment if you want me to apply it.


Oh, I see! Sorry for that, I thought the problem was on my side.
Here's the patch, it's the cfi.patch file.




I'm not sure what's going on here and couldn't figure out what was going 
wrong in the 20 minutes I spent on it just now.


Applying the patch downloaded from 2 different inboxes still gives me 
the same result.


$> patch -p1 --dry-run < /work/cfi.patch
checking file libgcc/config/arm/ieee754-df.S
Hunk #2 FAILED at 57.
Hunk #3 succeeded at 70 with fuzz 2.
Hunk #4 FAILED at 86.
Hunk #5 FAILED at 153.
Hunk #6 FAILED at 418.
Hunk #7 FAILED at 425.
Hunk #8 FAILED at 440.
Hunk #9 FAILED at 462.
Hunk #10 FAILED at 485.
Hunk #11 FAILED at 555.
Hunk #12 FAILED at 566.
Hunk #13 FAILED at 601.
Hunk #14 FAILED at 653.
Hunk #15 FAILED at 720.
Hunk #16 FAILED at 868.
Hunk #17 FAILED at 1057.
Hunk #18 FAILED at 1068.
Hunk #19 FAILED at 1082.
Hunk #20 FAILED at 1090.
Hunk #21 FAILED at 1122.
Hunk #22 FAILED at 1133.
Hunk #23 succeeded at 1145 with fuzz 2.
Hunk #24 FAILED at 1155.
Hunk #25 FAILED at 1168.
Hunk #26 FAILED at 1228.
Hunk #27 succeeded at 1236 with fuzz 2.
Hunk #28 FAILED at 1254.
Hunk #29 succeeded at 1263 with fuzz 2.
Hunk #30 FAILED at 1297.
Hunk #31 succeeded at 1306 with fuzz 2.
Hunk #32 FAILED at 1336.
Hunk #33 succeeded at 1345 with fuzz 2.
Hunk #34 FAILED at 1410.
27 out of 34 hunks FAILED
checking file libgcc/config/arm/ieee754-sf.S
Hunk #1 FAILED at 31.
Hunk #2 succeeded at 49 with fuzz 2.
Hunk #3 FAILED at 285.
Hunk #4 FAILED at 293.
Hunk #5 FAILED at 317.
Hunk #6 succeeded at 324 with fuzz 2.
Hunk #7 FAILED at 411.
Hunk #8 succeeded at 422 with fuzz 2.
Hunk #9 FAILED at 457.
Hunk #10 FAILED at 468.
Hunk #11 FAILED at 621.
Hunk #12 FAILED at 761.
Hunk #13 FAILED at 785.
Hunk #14 FAILED at 799.
Hunk #15 FAILED at 807.
Hunk #16 FAILED at 826.
Hunk #17 FAILED at 835.
Hunk #18 succeeded at 847 with fuzz 2.
Hunk #19 FAILED at 860.
Hunk #20 FAILED at 869.
Hunk #21 FAILED at 927.
Hunk #22 succeeded at 935 with fuzz 2.
Hunk #23 FAILED at 952.
Hunk #24 succeeded at 961 with fuzz 2.
Hunk #25 FAILED at 995.
Hunk #26 succeeded at 1004 with fuzz 2.
Hunk #27 FAILED at 1034.
20 out of 27 hunks FAILED
checking file libgcc/config/arm/lib1funcs.S




@@ -1149,12 +1250,16 @@ ARM_FUNC_START aeabi_cdrcmple
 mov r3, ip
 b   6f

-ARM_FUNC_START aeabi_cdcmpeq
+; ARM_FUNC_START aeabi_cdcmpeq
 ARM_FUNC_ALIAS aeabi_cdcmple aeabi_cdcmpeq



There appears  to be a stray `;' there. How has this been tested ?



 @ The status-returning routines are required to preserve all
 @ registers except ip, lr, and cpsr.
 6:  do_push {r0, lr}
+.cfi_adjust_cfa_offset 8  @ CFA is now sp + previousOffset + 8.
+.cfi_rel_offset r0, 0 @ Previous r0 is saved at sp.
+.cfi_rel_offset lr, 4 @ Previous lr is saved at sp + 4.
+
 ARM_CALL cmpdf2
 @ Set the Z flag correctly, and the C flag unconditionally.
 cmp r0, #0



Can you please generate a diff using svn diff from a pristine checkout 
of the sources, please and resend it as an attachment, making sure you 
test this properly with a regression run.


regards
Ramana

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-13 Thread Ramana Radhakrishnan 



On 13/05/15 17:37, Ramana Radhakrishnan wrote:



On 12/05/15 14:01, Martin Galvan wrote:

On Tue, May 12, 2015 at 5:49 AM, Ramana Radhakrishnan
 wrote:

That's what I mean when I say email clients "munged it" : email
clients and
/ or some popular email servers appear to end up munging white spaces
and
patches don't apply cleanly.

So, no it doesn't work - once you've sent it through your email client /
server. I am unable to apply the patch as it stands today either
taking the
raw text from the gcc-patches archive or from your email message in my
inbox. It's not like line endings and things have been munged but every
whitespace / tab is in trouble here.

Please send it back as an attachment if you want me to apply it.


Oh, I see! Sorry for that, I thought the problem was on my side.
Here's the patch, it's the cfi.patch file.




I'm not sure what's going on here and couldn't figure out what was going
wrong in the 20 minutes I spent on it just now.




Bah, I must be going blind.



@@ -53,11 +57,13 @@

 ARM_FUNC_START negdf2
 ARM_FUNC_ALIAS aeabi_dneg negdf2
+CFI_START_FUNCTION

 @ flip sign bit
 eor xh, xh, #0x8000


Either the mail server you are using or the source repository you have 
has replaced tabs with spaces, the eor here has a tab in the sources 
between eor and xh. Thus the patch is malformed according to the 
sources. I suspect that's the reason why all the other hunks are not 
applying.


Before reposting -

0. Please take care of the issue I mentioned in the previous email .

1. Please mail the patch so created to yourself on a different account 
and applying the patch you receive on pristine sources. Identify a mail 
server that you can use to send emails to lists that don't munge patches 
in this manner.


2. Please test such a tree and ensure no regressions in a run of the GCC 
testsuite.


3. Post the patch back to gcc-patches@gcc.gnu.org from the mail server 
that doesn't munge patches in this manner. I'll review it again then.


Thanks,
Ramana





 RET

+CFI_END_FUNCTION
 FUNC_END aeabi_dneg
 FUNC_END negdf2









Applying the patch downloaded from 2 different inboxes still gives me
the same result.

$> patch -p1 --dry-run < /work/cfi.patch
checking file libgcc/config/arm/ieee754-df.S
Hunk #2 FAILED at 57.
Hunk #3 succeeded at 70 with fuzz 2.
Hunk #4 FAILED at 86.
Hunk #5 FAILED at 153.
Hunk #6 FAILED at 418.
Hunk #7 FAILED at 425.
Hunk #8 FAILED at 440.
Hunk #9 FAILED at 462.
Hunk #10 FAILED at 485.
Hunk #11 FAILED at 555.
Hunk #12 FAILED at 566.
Hunk #13 FAILED at 601.
Hunk #14 FAILED at 653.
Hunk #15 FAILED at 720.
Hunk #16 FAILED at 868.
Hunk #17 FAILED at 1057.
Hunk #18 FAILED at 1068.
Hunk #19 FAILED at 1082.
Hunk #20 FAILED at 1090.
Hunk #21 FAILED at 1122.
Hunk #22 FAILED at 1133.
Hunk #23 succeeded at 1145 with fuzz 2.
Hunk #24 FAILED at 1155.
Hunk #25 FAILED at 1168.
Hunk #26 FAILED at 1228.
Hunk #27 succeeded at 1236 with fuzz 2.
Hunk #28 FAILED at 1254.
Hunk #29 succeeded at 1263 with fuzz 2.
Hunk #30 FAILED at 1297.
Hunk #31 succeeded at 1306 with fuzz 2.
Hunk #32 FAILED at 1336.
Hunk #33 succeeded at 1345 with fuzz 2.
Hunk #34 FAILED at 1410.
27 out of 34 hunks FAILED
checking file libgcc/config/arm/ieee754-sf.S
Hunk #1 FAILED at 31.
Hunk #2 succeeded at 49 with fuzz 2.
Hunk #3 FAILED at 285.
Hunk #4 FAILED at 293.
Hunk #5 FAILED at 317.
Hunk #6 succeeded at 324 with fuzz 2.
Hunk #7 FAILED at 411.
Hunk #8 succeeded at 422 with fuzz 2.
Hunk #9 FAILED at 457.
Hunk #10 FAILED at 468.
Hunk #11 FAILED at 621.
Hunk #12 FAILED at 761.
Hunk #13 FAILED at 785.
Hunk #14 FAILED at 799.
Hunk #15 FAILED at 807.
Hunk #16 FAILED at 826.
Hunk #17 FAILED at 835.
Hunk #18 succeeded at 847 with fuzz 2.
Hunk #19 FAILED at 860.
Hunk #20 FAILED at 869.
Hunk #21 FAILED at 927.
Hunk #22 succeeded at 935 with fuzz 2.
Hunk #23 FAILED at 952.
Hunk #24 succeeded at 961 with fuzz 2.
Hunk #25 FAILED at 995.
Hunk #26 succeeded at 1004 with fuzz 2.
Hunk #27 FAILED at 1034.
20 out of 27 hunks FAILED
checking file libgcc/config/arm/lib1funcs.S




@@ -1149,12 +1250,16 @@ ARM_FUNC_START aeabi_cdrcmple
 mov r3, ip
 b   6f

-ARM_FUNC_START aeabi_cdcmpeq
+; ARM_FUNC_START aeabi_cdcmpeq
 ARM_FUNC_ALIAS aeabi_cdcmple aeabi_cdcmpeq



There appears  to be a stray `;' there. How has this been tested ?



 @ The status-returning routines are required to preserve all
 @ registers except ip, lr, and cpsr.
 6:  do_push {r0, lr}
+.cfi_adjust_cfa_offset 8  @ CFA is now sp + previousOffset + 8.
+.cfi_rel_offset r0, 0 @ Previous r0 is saved at sp.
+.cfi_rel_offset lr, 4 @ Previous lr is saved at sp + 4.
+
 ARM_CALL cmpdf2
 @ Set the Z flag correctly, and the C flag unconditionally.
 cmp r0, #0



Can you please generate a diff using svn diff from a pristine checkout
of the sources, please and resend it as an attachment, making sure you
test this properly with a regression run.

regards
Ramana

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-13 Thread Martin Galvan 
On Wed, May 13, 2015 at 1:58 PM, Ramana Radhakrishnan
 wrote:
> On 13/05/15 17:37, Ramana Radhakrishnan wrote:
>> I'm not sure what's going on here and couldn't figure out what was going
>> wrong in the 20 minutes I spent on it just now.
>>
> Bah, I must be going blind.
>
>>
>> @@ -53,11 +57,13 @@
>>
>>  ARM_FUNC_START negdf2
>>  ARM_FUNC_ALIAS aeabi_dneg negdf2
>> +CFI_START_FUNCTION
>>
>>  @ flip sign bit
>>  eor xh, xh, #0x8000
>
>
> Either the mail server you are using or the source repository you have has
> replaced tabs with spaces, the eor here has a tab in the sources between eor
> and xh. Thus the patch is malformed according to the sources. I suspect
> that's the reason why all the other hunks are not applying.

That makes sense. I downloaded the gcc sources from the git mirror at
github-- perhaps that's what's munging the patch?

> Before reposting -
>
> 0. Please take care of the issue I mentioned in the previous email .

Will do. I honestly have no idea how that semicolon ended there, since
I tried a dry run of the file I sent you and it didn't complain.
Perhaps I accidentally typed it in before closing the file, I don't
know.

> 1. Please mail the patch so created to yourself on a different account and
> applying the patch you receive on pristine sources. Identify a mail server
> that you can use to send emails to lists that don't munge patches in this
> manner.

I used git send-email through gmail when contributing to various
projects such as gdb, and so far haven't had any problems like this
one.

> 2. Please test such a tree and ensure no regressions in a run of the GCC
> testsuite.
>
> 3. Post the patch back to gcc-patches@gcc.gnu.org from the mail server that
> doesn't munge patches in this manner. I'll review it again then.

Will do. Thanks a lot!

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-13 Thread Marek Polacek 
On Wed, May 13, 2015 at 02:07:34PM -0300, Martin Galvan wrote:
> That makes sense. I downloaded the gcc sources from the git mirror at
> github-- perhaps that's what's munging the patch?

That mirror seems to be out-of-date.  I suggest using
.

Marek

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-13 Thread Martin Galvan 
Here's the new patch. I downloaded the gcc sources from the SVN
repository, removed the extra semicolon from my version of the files
and re-generated the patch using svn diff, making sure the context
info had all the tabs from the original. I then e-mailed the patch to
myself as an attachment, applied it to the fresh SVN sources by doing
patch --dry-run -p0 < cfi-svn.patch and checked that the compilation
and tests were successful.
Index: libgcc/config/arm/ieee754-df.S
===
--- libgcc/config/arm/ieee754-df.S	(revision 223171)
+++ libgcc/config/arm/ieee754-df.S	(working copy)
@@ -33,8 +33,12 @@
  * Only the default rounding mode is intended for best performances.
  * Exceptions aren't supported yet, but that can be added quite easily
  * if necessary without impacting performances.
+ *
+ * In the CFI related comments, 'previousOffset' refers to the previous offset
+ * from sp used to compute the CFA.
  */
 
+	.cfi_sections .debug_frame
 
 #ifndef __ARMEB__
 #define xl r0
@@ -53,11 +57,13 @@
 
 ARM_FUNC_START negdf2
 ARM_FUNC_ALIAS aeabi_dneg negdf2
+	CFI_START_FUNCTION
 
 	@ flip sign bit
 	eor	xh, xh, #0x8000
 	RET
 
+	CFI_END_FUNCTION
 	FUNC_END aeabi_dneg
 	FUNC_END negdf2
 
@@ -66,6 +72,7 @@
 #ifdef L_arm_addsubdf3
 
 ARM_FUNC_START aeabi_drsub
+	CFI_START_FUNCTION
 
 	eor	xh, xh, #0x8000	@ flip sign bit of first arg
 	b	1f	
@@ -81,7 +88,11 @@
 ARM_FUNC_START adddf3
 ARM_FUNC_ALIAS aeabi_dadd adddf3
 
-1:	do_push	{r4, r5, lr}
+1:  do_push {r4, r5, lr}@ sp -= 12
+	.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+	.cfi_rel_offset r4, 0   @ Registers are saved from sp to sp + 8
+	.cfi_rel_offset r5, 4
+	.cfi_rel_offset lr, 8
 
 	@ Look for zeroes, equal values, INF, or NAN.
 	shift1	lsl, r4, xh, #1
@@ -148,6 +159,11 @@
 	@ Since this is not common case, rescale them off line.
 	teq	r4, r5
 	beq	LSYM(Lad_d)
+
+@ CFI note: we're lucky that the branches to Lad_* that appear after this function
+@ have a CFI state that's exactly the same as the one we're in at this
+@ point. Otherwise the CFI would change to a different state after the branch,
+@ which would be disastrous for backtracing.
 LSYM(Lad_x):
 
 	@ Compensate for the exponent overlapping the mantissa MSB added later
@@ -413,6 +429,7 @@
 	orrne	xh, xh, #0x0008	@ quiet NAN
 	RETLDM	"r4, r5"
 
+	CFI_END_FUNCTION
 	FUNC_END aeabi_dsub
 	FUNC_END subdf3
 	FUNC_END aeabi_dadd
@@ -420,12 +437,19 @@
 
 ARM_FUNC_START floatunsidf
 ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
+	CFI_START_FUNCTION
 
 	teq	r0, #0
 	do_it	eq, t
 	moveq	r1, #0
 	RETc(eq)
-	do_push	{r4, r5, lr}
+
+	do_push {r4, r5, lr}@ sp -= 12
+	.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+	.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+	.cfi_rel_offset r5, 4
+	.cfi_rel_offset lr, 8
+
 	mov	r4, #0x400		@ initial exponent
 	add	r4, r4, #(52-1 - 1)
 	mov	r5, #0			@ sign bit is 0
@@ -435,17 +459,25 @@
 	mov	xh, #0
 	b	LSYM(Lad_l)
 
+	CFI_END_FUNCTION
 	FUNC_END aeabi_ui2d
 	FUNC_END floatunsidf
 
 ARM_FUNC_START floatsidf
 ARM_FUNC_ALIAS aeabi_i2d floatsidf
+	CFI_START_FUNCTION
 
 	teq	r0, #0
 	do_it	eq, t
 	moveq	r1, #0
 	RETc(eq)
-	do_push	{r4, r5, lr}
+
+	do_push {r4, r5, lr}@ sp -= 12
+	.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+	.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+	.cfi_rel_offset r5, 4
+	.cfi_rel_offset lr, 8
+
 	mov	r4, #0x400		@ initial exponent
 	add	r4, r4, #(52-1 - 1)
 	ands	r5, r0, #0x8000	@ sign bit in r5
@@ -457,11 +489,13 @@
 	mov	xh, #0
 	b	LSYM(Lad_l)
 
+	CFI_END_FUNCTION
 	FUNC_END aeabi_i2d
 	FUNC_END floatsidf
 
 ARM_FUNC_START extendsfdf2
 ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
+	CFI_START_FUNCTION
 
 	movs	r2, r0, lsl #1		@ toss sign bit
 	mov	xh, r2, asr #3		@ stretch exponent
@@ -480,22 +514,34 @@
 
 	@ value was denormalized.  We can normalize it now.
 	do_push	{r4, r5, lr}
+	.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+	.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+	.cfi_rel_offset r5, 4
+	.cfi_rel_offset lr, 8
+
 	mov	r4, #0x380		@ setup corresponding exponent
 	and	r5, xh, #0x8000	@ move sign bit in r5
 	bic	xh, xh, #0x8000
 	b	LSYM(Lad_l)
 
+	CFI_END_FUNCTION
 	FUNC_END aeabi_f2d
 	FUNC_END extendsfdf2
 
 ARM_FUNC_START floatundidf
 ARM_FUNC_ALIAS aeabi_ul2d floatundidf
+	CFI_START_FUNCTION
+	.cfi_remember_state@ Save the current CFA state.
 
 	orrs	r2, r0, r1
 	do_it	eq
 	RETc(eq)
 
-	do_push	{r4, r5, lr}
+	do_push {r4, r5, lr}   @ sp -= 12
+	.cfi_adjust_cfa_offset 12  @ CFA is now sp + previousOffset + 12
+	.cfi_rel_offset r4, 0  @ Registers are saved from sp + 0 to sp + 8
+	.cfi_rel_offset r5, 4
+	.cfi_rel_offset lr, 8
 
 	mov	r5, #0
 	b	2f
@@ -502,12 +548,20 @@
 
 ARM_FUNC_START floatdidf
 ARM_FUNC_ALIAS aeabi_l2d floatdidf
+	.cfi_restore_state
+	@ Restore the CFI state w

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-13 Thread Martin Galvan 
Forgot to mention: I first did a --dry-run of the patch and then
applied it to the gcc sources.

On Wed, May 13, 2015 at 3:11 PM, Martin Galvan
 wrote:
> Here's the new patch. I downloaded the gcc sources from the SVN
> repository, removed the extra semicolon from my version of the files
> and re-generated the patch using svn diff, making sure the context
> info had all the tabs from the original. I then e-mailed the patch to
> myself as an attachment, applied it to the fresh SVN sources by doing
> patch --dry-run -p0 < cfi-svn.patch and checked that the compilation
> and tests were successful.



-- 


Martin Galvan

Software Engineer

Taller Technologies Argentina


San Lorenzo 47, 3rd Floor, Office 5

Córdoba, Argentina

Phone: 54 351 4217888 / +54 351 4218211

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-15 Thread Ramana Radhakrishnan 



On 13/05/15 19:11, Martin Galvan wrote:

Here's the new patch. I downloaded the gcc sources from the SVN
repository, removed the extra semicolon from my version of the files
and re-generated the patch using svn diff, making sure the context
info had all the tabs from the original. I then e-mailed the patch to
myself as an attachment, applied it to the fresh SVN sources by doing
patch --dry-run -p0 < cfi-svn.patch and checked that the compilation
and tests were successful.



Thanks for doing this now the patch looks much better and I can apply it 
! Unfortunately there are still problems with it and I'm not sure about 
your testing procedures.





mov ip, r0
mov r0, r2
@@ -1149,12 +1250,15 @@
mov r3, ip
b   6f

-ARM_FUNC_START aeabi_cdcmpeq
 ARM_FUNC_ALIAS aeabi_cdcmple aeabi_cdcmpeq


How did this even build ?

I've cleaned up some lines which were > 80 characters, added a 
definition for aeabi_cdcmpeq again and applied the attached after 
*doing* a full bootstrap and test run on arm-none-linux-gnueabihf along 
with a test run on arm-none-eabi.



regards
Ramana

2015-05-15  Martin Galvan  

* config/arm/lib1funcs.S (CFI_START_FUNCTION, CFI_END_FUNCTION):
New macros.
* config/arm/ieee754-df.S: Add CFI directives.
* config/arm/ieee754-sf.S: Add CFI directives.

Index: libgcc/config/arm/ieee754-df.S
===
--- libgcc/config/arm/ieee754-df.S  (revision 223219)
+++ libgcc/config/arm/ieee754-df.S  (working copy)
@@ -33,8 +33,12 @@
  * Only the default rounding mode is intended for best performances.
  * Exceptions aren't supported yet, but that can be added quite easily
  * if necessary without impacting performances.
+ *
+ * In the CFI related comments, 'previousOffset' refers to the previous offset
+ * from sp used to compute the CFA.
  */
 
+   .cfi_sections .debug_frame
 
 #ifndef __ARMEB__
 #define xl r0
@@ -53,11 +57,13 @@
 
 ARM_FUNC_START negdf2
 ARM_FUNC_ALIAS aeabi_dneg negdf2
+   CFI_START_FUNCTION
 
@ flip sign bit
eor xh, xh, #0x8000
RET
 
+   CFI_END_FUNCTION
FUNC_END aeabi_dneg
FUNC_END negdf2
 
@@ -66,6 +72,7 @@
 #ifdef L_arm_addsubdf3
 
 ARM_FUNC_START aeabi_drsub
+   CFI_START_FUNCTION
 
eor xh, xh, #0x8000 @ flip sign bit of first arg
b   1f  
@@ -81,7 +88,11 @@
 ARM_FUNC_START adddf3
 ARM_FUNC_ALIAS aeabi_dadd adddf3
 
-1: do_push {r4, r5, lr}
+1:  do_push {r4, r5, lr}@ sp -= 12
+   .cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+   .cfi_rel_offset r4, 0   @ Registers are saved from sp to sp + 8
+   .cfi_rel_offset r5, 4
+   .cfi_rel_offset lr, 8
 
@ Look for zeroes, equal values, INF, or NAN.
shift1  lsl, r4, xh, #1
@@ -148,6 +159,11 @@
@ Since this is not common case, rescale them off line.
teq r4, r5
beq LSYM(Lad_d)
+
+@ CFI note: we're lucky that the branches to Lad_* that appear after this 
function
+@ have a CFI state that's exactly the same as the one we're in at this
+@ point. Otherwise the CFI would change to a different state after the branch,
+@ which would be disastrous for backtracing.
 LSYM(Lad_x):
 
@ Compensate for the exponent overlapping the mantissa MSB added later
@@ -413,6 +429,7 @@
orrne   xh, xh, #0x0008 @ quiet NAN
RETLDM  "r4, r5"
 
+   CFI_END_FUNCTION
FUNC_END aeabi_dsub
FUNC_END subdf3
FUNC_END aeabi_dadd
@@ -420,12 +437,19 @@
 
 ARM_FUNC_START floatunsidf
 ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
+   CFI_START_FUNCTION
 
teq r0, #0
do_it   eq, t
moveq   r1, #0
RETc(eq)
-   do_push {r4, r5, lr}
+
+   do_push {r4, r5, lr}@ sp -= 12
+   .cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+   .cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+   .cfi_rel_offset r5, 4
+   .cfi_rel_offset lr, 8
+
mov r4, #0x400  @ initial exponent
add r4, r4, #(52-1 - 1)
mov r5, #0  @ sign bit is 0
@@ -435,17 +459,25 @@
mov xh, #0
b   LSYM(Lad_l)
 
+   CFI_END_FUNCTION
FUNC_END aeabi_ui2d
FUNC_END floatunsidf
 
 ARM_FUNC_START floatsidf
 ARM_FUNC_ALIAS aeabi_i2d floatsidf
+   CFI_START_FUNCTION
 
teq r0, #0
do_it   eq, t
moveq   r1, #0
RETc(eq)
-   do_push {r4, r5, lr}
+
+   do_push {r4, r5, lr}@ sp -= 12
+   .cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+   .cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+   .cfi_rel_offset r5, 4
+   .cfi_rel_offset lr, 8
+
mov r4, #0x400  @ initial exponent
add r4, r4, #(52-1 -

Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-15 Thread Martin Galvan 
On Fri, May 15, 2015 at 1:58 PM, Ramana Radhakrishnan
 wrote:
> Thanks for doing this now the patch looks much better and I can apply it !
> Unfortunately there are still problems with it and I'm not sure about your
> testing procedures.
>
>>
>>
>> mov ip, r0
>> mov r0, r2
>> @@ -1149,12 +1250,15 @@
>> mov r3, ip
>> b   6f
>>
>> -ARM_FUNC_START aeabi_cdcmpeq
>>  ARM_FUNC_ALIAS aeabi_cdcmple aeabi_cdcmpeq
>
>
> How did this even build ?
>
> I've cleaned up some lines which were > 80 characters, added a definition
> for aeabi_cdcmpeq again and applied the attached after *doing* a full
> bootstrap and test run on arm-none-linux-gnueabihf along with a test run on
> arm-none-eabi.

Thanks a lot! I guess I should've mentioned I've tested it on
arm-rtems411. I'm not sure why it didn't throw me any errors, though,
but I'm glad it's finally commited and working.

Again, thanks a lot and sorry for the inconvenience.

-- 

Martin Galvan

Software Engineer

Taller Technologies Argentina

San Lorenzo 47, 3rd Floor, Office 5

Córdoba, Argentina

Phone: 54 351 4217888 / +54 351 4218211

Re: Re: Fwd: [PING 2][PATCH] libgcc: Add CFI directives to the soft floating point support code for ARM

2015-05-11 Thread Martin Galvan 
On Mon, May 11, 2015 at 4:45 AM, Ramana Radhakrishnan 
 wrote:
> sorry about the slow response, I was travelling for a bit and missed your
> emails. Trying your patch out gives me failures possibly because my mail
> client munged it when it received this inline.
>
> Can you please rebase if necessary, test and send it again as an attachment?

I checked it again and it seems to be a whitespace issue.
I re-generated the patch and this one seems to apply just fine; try it out
again.

---
libgcc/config/arm/ieee754-df.S | 177 +---
libgcc/config/arm/ieee754-sf.S | 101 ++--
libgcc/config/arm/lib1funcs.S  |  10 ++
3 files changed, 261 insertions(+), 27 deletions(-)

diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index f75630b..d1f9066 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -33,8 +33,12 @@
  * Only the default rounding mode is intended for best performances.
  * Exceptions aren't supported yet, but that can be added quite easily
  * if necessary without impacting performances.
+ *
+ * In the CFI related comments, 'previousOffset' refers to the previous offset
+ * from sp used to compute the CFA.
  */

+.cfi_sections .debug_frame

 #ifndef __ARMEB__
 #define xl r0
@@ -53,11 +57,13 @@

 ARM_FUNC_START negdf2
 ARM_FUNC_ALIAS aeabi_dneg negdf2
+CFI_START_FUNCTION

 @ flip sign bit
 eor xh, xh, #0x8000
 RET

+CFI_END_FUNCTION
 FUNC_END aeabi_dneg
 FUNC_END negdf2

@@ -66,6 +72,7 @@ ARM_FUNC_ALIAS aeabi_dneg negdf2
 #ifdef L_arm_addsubdf3

 ARM_FUNC_START aeabi_drsub
+CFI_START_FUNCTION

 eor xh, xh, #0x8000 @ flip sign bit of first arg
 b   1f
@@ -81,7 +88,11 @@ ARM_FUNC_ALIAS aeabi_dsub subdf3
 ARM_FUNC_START adddf3
 ARM_FUNC_ALIAS aeabi_dadd adddf3

-1:  do_push {r4, r5, lr}
+1:  do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp to sp + 8
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8

 @ Look for zeroes, equal values, INF, or NAN.
 shift1  lsl, r4, xh, #1
@@ -148,6 +159,11 @@ ARM_FUNC_ALIAS aeabi_dadd adddf3
 @ Since this is not common case, rescale them off line.
 teq r4, r5
 beq LSYM(Lad_d)
+
+@ CFI note: we're lucky that the branches to Lad_* that appear after this 
function
+@ have a CFI state that's exactly the same as the one we're in at this
+@ point. Otherwise the CFI would change to a different state after the branch,
+@ which would be disastrous for backtracing.
 LSYM(Lad_x):

 @ Compensate for the exponent overlapping the mantissa MSB added later
@@ -413,6 +429,7 @@ LSYM(Lad_i):
 orrne   xh, xh, #0x0008 @ quiet NAN
 RETLDM  "r4, r5"

+CFI_END_FUNCTION
 FUNC_END aeabi_dsub
 FUNC_END subdf3
 FUNC_END aeabi_dadd
@@ -420,12 +437,19 @@ LSYM(Lad_i):

 ARM_FUNC_START floatunsidf
 ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
+CFI_START_FUNCTION

 teq r0, #0
 do_it   eq, t
 moveq   r1, #0
 RETc(eq)
-do_push {r4, r5, lr}
+
+do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
 mov r4, #0x400  @ initial exponent
 add r4, r4, #(52-1 - 1)
 mov r5, #0  @ sign bit is 0
@@ -435,17 +459,25 @@ ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
 mov xh, #0
 b   LSYM(Lad_l)

+CFI_END_FUNCTION
 FUNC_END aeabi_ui2d
 FUNC_END floatunsidf

 ARM_FUNC_START floatsidf
 ARM_FUNC_ALIAS aeabi_i2d floatsidf
+CFI_START_FUNCTION

 teq r0, #0
 do_it   eq, t
 moveq   r1, #0
 RETc(eq)
-do_push {r4, r5, lr}
+
+do_push {r4, r5, lr}@ sp -= 12
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
 mov r4, #0x400  @ initial exponent
 add r4, r4, #(52-1 - 1)
 andsr5, r0, #0x8000 @ sign bit in r5
@@ -457,11 +489,13 @@ ARM_FUNC_ALIAS aeabi_i2d floatsidf
 mov xh, #0
 b   LSYM(Lad_l)

+CFI_END_FUNCTION
 FUNC_END aeabi_i2d
 FUNC_END floatsidf

 ARM_FUNC_START extendsfdf2
 ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
+CFI_START_FUNCTION

 movsr2, r0, lsl #1  @ toss sign bit
 mov xh, r2, asr #3  @ stretch exponent
@@ -480,34 +514,54 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2

 @ value was denormalized.  We can normalize it now.
 do_push {r4, r5, lr}
+.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+.cfi_rel_offset r4, 0   @ Registers are saved from sp + 0 to sp + 8.
+.cfi_rel_offset r5, 4
+.cfi_rel_offset lr, 8
+
 mov r4, #0x380  @ setup corresponding exponent
 and r5, xh, #0x8