gEDA-user: Hardware Design ansd SystemC.
Hello, Let me introduce myself : Guillaume FORTAINE, French engineer in informatics. I would want to build a start up to sell mobile phones ( OEM Level ). I am currently in discussions with investors. We are currently searching people with a strong background in Hardware Design and SystemC. Our business model is in its early stage, but we would be interested into a break oppposite to the legacy one of our competitors who are nearly all ARM based. Our choice is to use the PowerPC architecture : all the challenge is here, that's why we need people with a strong background... This is a very big project. We would want to sign a contract with people ready for at least a one year full-time contract. We look forward to your answer, Best Regards, Guillaume ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
John Griessen wrote: Dan McMahill wrote: Does this need to be a feature? I'm not an expert in PCB layout tools but it seems worthy I think it is important but I'm not sure when I'll have time. I wonder if maybe just a "nopaste" flag for pins/pads is enough. If we could show it as a layer and add a rectangle, I think it would be less error prone. Checking for such rare things as an added rectangle on soldermask or paste could be like: show only solderpaste layer, select all, see count. so actually, I ended up looking this instead of sleeping like I should have been doing. I have added, but not yet committed, support for a pad having a "nopaste" flag. It does what it sounds like. This would let you create a fiducial element. I added a bit to the drc code that just gives you a warning and a count when you find "nopaste" pads. So you'll be told that you don't have drc violations but you may get a line like: warning: 4 pads have the no paste flag set. Any further comments from anyone before I check this in? Allowing the user to prevent a solderpaste stencil opening is important for fiducials but it also provides a mechanism for a user screw up and miss it easily which is why I wanted to at least provide the count. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Trouble with Component Editing
Adrian Nania wrote: A whole pile of problems I am fighting with could be avoided on Component Editing level if the active red end of a pin could be forced to stay _only_ on a 100 mils grid (or whatever the default choice). I need to be able to move the inactive white end on the grid I will choose (for symbols with round body for example) but if the red active end “slips” from 100 mils grid, the resulting mess is useless. Could somebody implement a “checkbox” like option “force active end on 100 mils” or “automatically realign all red ends”? Adrian, Try 'snap grid spacing'. 'o shift-s' in keys. I've never seen Gschem get off the grid if you rigorously use this when creating symbols. You want your pins to be defaulted to a .300 spacing. pt ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: aroma hotplate info
DJ Delorie wrote: I did an experiment with my hotplate to see how evenly it heated up (not very). I had a lousy hotplate too. I bandsawed off the edges, sanded off the teflon, and screwed it to a 1/2" surplus aluminum plate. Seems fairly even now. I thought it'd be a good idea to have a nice flat plate too, until I realized that circuit boards warp when you heat 'em up. DJ, did your test account for warp somehow? Older hotplates tended to have more metal. They noticeably lacked cords or working thermostats when I browsed the Salvation Army. Newer plates tend to have a much lighter swage joint between the element and the plate. Some hotplates are no longer die-cast, instead they're pressed and have a swage holding the element on the bottom. These formed 'plates are the least flat and the least even heating. Get the cheapest hotplate that has a continuous, thick joint between the element and the plate, and add a slab of metal, copper would be nice but rather vain. Phil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
John Griessen wrote: Dan McMahill wrote: Does this need to be a feature? I'm not an expert in PCB layout tools but it seems worthy I think it is important but I'm not sure when I'll have time. I wonder if maybe just a "nopaste" flag for pins/pads is enough. If we could show it as a layer and add a rectangle, I think it would be less error prone. Checking for such rare things as an added rectangle on soldermask or paste could be like: show only solderpaste layer, select all, see count. Having the paste patterns shown explicitly and having a way to explicitly create a paste pattern would be the general way to do it. Same thing for the solder mask. There have been lots of times where I just wanted a rectangle cleared of solder resist. that is not tied to a part. PCB really should be able to cleanly deal with layers that are not copper. Joe T As far as one side only fiducial workarounds, how about these: Make opposed, offset L lines in a copper layer so their edges are on intersecting X and Y axes. Etching results might make the edges eaten back from a perfect line through them all, but you could still use them as fiducials by aiming for the middle of the gap. This approximates a fiducial of alternating squares of black and clear. Another is a zero length line to get a circle of copper layer. Same as a zero diameter via, but on one side only. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: aroma hotplate info
You might try putting an iron skillet on your hotplate as a heat diffuser. It will take some extra time to heat up, but should be much more even (also useful for making candy on an electric range). Used ones should be available for a lot less than $20. -Jeff ps, I've been reading this list for a awhile, odd that my first post contains info from a cooking show. On 11/3/06, DJ Delorie <[EMAIL PROTECTED]> wrote: I did an experiment with my hotplate to see how evenly it heated up (not very). Results here: http://www.delorie.com/pcb/hotplate/ It includes a video of the paste melting so you know what to look for, not that it's subtle or anything. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Phone: 269-804-2071 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
On 11/3/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: What do you mean "on grid"? gschem has a grid set at 100 gschem-units. For a connection to be made pins have to have the active end on the grid. Your schematic is on grid. Did you load the netlist file prior to running the optimize command? Your schematic, PCB and netlist file look correct and they worked for me. I did the following: 1. File->Load Layout 2. File->Load netlist File 3. Pressed the 'O' key (optimize rats nest). (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thermal overries mask of neighboring via's and holes
Jeff VR wrote: As I was putting the finishing touches on my board and connecting my mounting holes to the GND plane I noticed what seems to me to be an oddity. I had a neighboring via that was appropriately clearing the GND plane polygon and meeting the DRC clearances. When I added the thermal to the mounting hole one of the thermal fingers went into the mask of the via. I think I'm using the right terminology? This happened again with a pin of one of my connectors. I didn't get an warnings after o about shorts between the Net and GND? Should I create an example schematic? I'm using version 20050609. I realize this is an older version but I'm in a hurry to get my board done before doing a clean install from the CVS trunk or latest release. This bug was fixed with the polygon clipping code added recently. Only the current CVS code has this bug fixed. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
Dan McMahill wrote: Does this need to be a feature? I'm not an expert in PCB layout tools but it seems worthy I think it is important but I'm not sure when I'll have time. I wonder if maybe just a "nopaste" flag for pins/pads is enough. If we could show it as a layer and add a rectangle, I think it would be less error prone. Checking for such rare things as an added rectangle on soldermask or paste could be like: show only solderpaste layer, select all, see count. As far as one side only fiducial workarounds, how about these: Make opposed, offset L lines in a copper layer so their edges are on intersecting X and Y axes. Etching results might make the edges eaten back from a perfect line through them all, but you could still use them as fiducials by aiming for the middle of the gap. This approximates a fiducial of alternating squares of black and clear. Another is a zero length line to get a circle of copper layer. Same as a zero diameter via, but on one side only. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
What do you mean "on grid"? I don't get that. I'm sending a very simple example. Exporting it to PCB will get no connections between the connectors. Thank you. 2006/11/3, John Luciani <[EMAIL PROTECTED]>: On 11/3/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: > Hi there, > > I've made an schematic with a "pin bar" that has "JUMPER10" as footprint. > But when I export it to PCB none of the pins on it get connected. > The rest of my circuit is ok, but the "JUMPER10" components goes > disconnected in PCB. > In the schematic are the connection ends of the pin bars on grid? Are the pin numbers consistent between the schematic symbol and the PCB footprint? You may want to post a *small* schematic and pcb file that demonstrates the problem. For the schematic make sure you use embedded symbols. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user jumper.sch Description: Binary data jump Description: Binary data jmp.pcb Description: Binary data jmp.net Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
Jeff VR wrote: >Is you soldermask clear enough? I'm not sure. I haven't ordered my boards yet. My assembler requires the fiducial to not have the soldermask so the vision equipment is sure to get an accurate reading. you should not have paste or soldermask over the fiducial. >Does this need to be a feature? I'm not an expert in PCB layout tools but given the importance of a good fiducial it seems worthy of some development time. I think it is important but I'm not sure when I'll have time. I wonder if maybe just a "nopaste" flag for pins/pads is enough. The soldermask opening is already supported. If a 'nopaste' flag is allowed I wonder if running drc should give you a count of how many pads have 'nopaste'. You'd hate to blow a stencil because you accidentally turned off the solderpaste on 17 pads on a 240 pin fpga... -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Thermal overries mask of neighboring via's and holes
As I was putting the finishing touches on my board and connecting my mounting holes to the GND plane I noticed what seems to me to be an oddity. I had a neighboring via that was appropriately clearing the GND plane polygon and meeting the DRC clearances. When I added the thermal to the mounting hole one of the thermal fingers went into the mask of the via. I think I'm using the right terminology? This happened again with a pin of one of my connectors. I didn't get an warnings after o about shorts between the Net and GND? Should I create an example schematic? I'm using version 20050609. I realize this is an older version but I'm in a hurry to get my board done before doing a clean install from the CVS trunk or latest release. Thanks, Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
>Is you soldermask clear enough? I'm not sure. I haven't ordered my boards yet. My assembler requires the fiducial to not have the soldermask so the vision equipment is sure to get an accurate reading. >Does this need to be a feature? I'm not an expert in PCB layout tools but given the importance of a good fiducial it seems worthy of some development time. Thanks, Jeff John Griessen wrote: I just tried making a rectangle of solder mask -- that's out. Jeff VR wrote: is their a way to get PCB to not put paste on a pad so I can go back to having a fiducial on one side of the board? This is in the manual: Pad [rX1 rY1 rX2 rY2 Thickness Clearance Mask "Name" "Number" SFlags] Pad (rX1 rY1 rX2 rY2 Thickness Clearance Mask "Name" "Number" NFlags) Pad (aX1 aY1 aX2 aY2 Thickness "Name" "Number" NFlags) Pad (aX1 aY1 aX2 aY2 Thickness "Name" NFlags) © rX1 rY1 rX2 rY2 Coordinates of the endpoints of the pad, relative to the element’s mark. Note that the copper extends beyond these coordinates by half the thickness. To make a square or round pad, specify the same coordinate twice. aX1 aY1 aX2 aY2 Same, but absolute coordinates of the endpoints of the pad. Thickness width of the pad. Clearance add to thickness to get clearance width. Mask width of solder mask opening. Name name of pin Number number of pin SFlags symbolic or numerical flags NFlags numerical flags only Can you look at your element file for the fiducial and change the mask flag and see what happens? This would give solder mask no opening, so fiducial covered with and also fiducial no stencil opening, so not pasted on... Is you soldermask clear enough? Does this need to be a feature? John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
I just tried making a rectangle of solder mask -- that's out. Jeff VR wrote: is their a way to get PCB to not put paste on a pad so I can go back to having a fiducial on one side of the board? This is in the manual: Pad [rX1 rY1 rX2 rY2 Thickness Clearance Mask "Name" "Number" SFlags] Pad (rX1 rY1 rX2 rY2 Thickness Clearance Mask "Name" "Number" NFlags) Pad (aX1 aY1 aX2 aY2 Thickness "Name" "Number" NFlags) Pad (aX1 aY1 aX2 aY2 Thickness "Name" NFlags) © rX1 rY1 rX2 rY2 Coordinates of the endpoints of the pad, relative to the elements mark. Note that the copper extends beyond these coordinates by half the thickness. To make a square or round pad, specify the same coordinate twice. aX1 aY1 aX2 aY2 Same, but absolute coordinates of the endpoints of the pad. Thickness width of the pad. Clearance add to thickness to get clearance width. Mask width of solder mask opening. Name name of pin Number number of pin SFlags symbolic or numerical flags NFlags numerical flags only Can you look at your element file for the fiducial and change the mask flag and see what happens? This would give solder mask no opening, so fiducial covered with and also fiducial no stencil opening, so not pasted on... Is you soldermask clear enough? Does this need to be a feature? John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Trouble with Component Editing
A way to deal with that is set the grid at 50 or 25, keep the ends on grid dots that correspond to 100 mils. MOve one end only by clicking on the end. Move the whole segment by clicking on its middle. John G Adrian Nania wrote: I need to be able to move the inactive white end on the grid I will choose (for symbols with round body for example) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Trouble with Component Editing
Title: Trouble with Component Editing A whole pile of problems I am fighting with could be avoided on Component Editing level if the active red end of a pin could be forced to stay _only_ on a 100 mils grid (or whatever the default choice). I need to be able to move the inactive white end on the grid I will choose (for symbols with round body for example) but if the red active end “slips” from 100 mils grid, the resulting mess is useless. Could somebody implement a “checkbox” like option “force active end on 100 mils” or “automatically realign all red ends”? Thanks, Adrian Nania ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
> I started out by using one of the fiducials you guys have listed > with a pad as a sub-element. However when I started reviewing my > PCB with my assembler rep he noticed that their would be a hole in > the stencil causing solder paste to be applied to the fiducial. I > changed to the pin with zero size hole and the paste is naturally > gone. However now I have fiducials on both sides with a big hole in > my GND plane because of the clearance to the GND polygon. So, is > their a way to get PCB to not put paste on a pad so I can go back to > having a fiducial on one side of the board? At the moment, we don't have any way of adjusting the paste size. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: FPGAs, SDSL, Ronjas...
Karel Kulhavy <[EMAIL PROTECTED]> wrote: > You need to do the reverseengineering and declassifying work. What if they > refuse to give out the docs, he? What docs? Do you really think that any ISP actually knows anything about the protocols, packet formats, etc. of their equipment? The answer is no, they just buy equipment and operate it, but they have NO technical knowledge or docs. Now the bad guys who refuse to give out the docs are the DSLAM manufacturers, and yes, I've been reverse-engineering them, quite successfully so far I might add. The gadget that I'm now drawing in gschem (the OSDCU) will be another great aid in this reverse engineering work when it's built. The good thing is that thanks to the new G.shdsl standard there will be no new proprietary SDSL/2B1Q flavors to reverse-engineer, just the existing legacy ones. The G.shdsl spec (the ETSI version, same technical content formatted differently) can be downloaded freely from the ETSI website, and chipsets are available from several vendors that provide a complete implementation. Don't like the closed source firmware of those chipsets? The spec is completely open, so feel free to make your own implementation from discrete components. The only reason I'm not enjoying G.shdsl and mess with legacy SDSL instead is that there are so many existing deployed SDSL/2B1Q lines that it'll take a global apocalypse to take them all out of service so they can be replaced with something else. But the key point is that it's all legacy stuff, so there is no one out there to invent new different flavors just to break my open source hardware. > The business grade services offered here are prohibitively expensive here. Well, then I'm fortunate enough to live in a place where I can afford a real business Internet service, because I would never be able to live without it -- I could never live with an ISP doing the kind of evil things to me you've been talking about in this whole thread. > You can put tripods with analogue Ronja retranslation and solar battery > between the cows and horses. Yeah, and the cost of buying or renting the land for those towers, plus the towers themselves, would be a lot more than a T3. Thanks, but I'll take the T3 instead if I ever have that kind of money. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: gEDA user with problems
Thanks guys for your responses. I will update my small HOWTO.
Carlos is telling us:
[snip]
>Nevertheless I tried this with CVS version, and the auto numbering when
>copying components seems to work for me
In that case, looks like a good idea to install all the time the latest
CVS version? The default Ubuntu version doesn't look too old.
[snip]
>Yeah, source-library has nothing to do with this. What exactly are you
>trying to accomplish by defining a "working path"?
This definitely is my mistake. I have seen
"${HOME}/projects/my_schematics" and automatically I assumed this must
be related to the place where I am keeping my projects. Something like
the default PATH gEDA is looking for when I want to open a project. I do
have different disks (partitions) mounted under $HOME:
/home/backups
/home/projects
...
Adrian
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Re: gEDA-user: OT: FPGAs, SDSL, Ronjas...
Karel Kulhavy <[EMAIL PROTECTED]> wrote: > Who is Michael Sokolov? Me. > "Chernobyl" must be a Russian word for wormwood It is. > A star is physically an atomic reactor. In the old days when they wrote the > text they didn't have a word for "atomic reactor", so they probably used an > existing word describing an object with the same internal physical function. The internal physical function is not the same. Fission and fusion are two very different nuclear reactions. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: aroma hotplate info
I did an experiment with my hotplate to see how evenly it heated up (not very). Results here: http://www.delorie.com/pcb/hotplate/ It includes a video of the paste melting so you know what to look for, not that it's subtle or anything. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA user with problems
El jue, 02-11-2006 a las 22:12 -0500, Ales Hvezda escribió: [snip] > >Could somebody show me what I am doing wrong? I am using Ubuntu Edgy > >with gEDA default package. > >1) I am trying to activate the auto numbering for components placement. > >I modified /etc/gEDA/system-gschemrc to: > >... > >(load (string-append gedadatarc "/scheme/auto-uref.scm")) > >(add-hook! add-component-hook auto-uref) > >(add-hook! copy-component-hook auto-uref) > >... > >And I can not see any auto numbering. > > I commented in those lines, and on my machine I get auto numbering > when I add components. I did not see any auto numbering when I copied > components though. Did something change to break this? Carlos? None I can remember. Nevertheless I tried this with CVS version, and the auto numbering when copying components seems to work for me Regards, Carlos ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
I started out by using one of the fiducials you guys have listed with a pad as a sub-element. However when I started reviewing my PCB with my assembler rep he noticed that their would be a hole in the stencil causing solder paste to be applied to the fiducial. I changed to the pin with zero size hole and the paste is naturally gone. However now I have fiducials on both sides with a big hole in my GND plane because of the clearance to the GND polygon. So, is their a way to get PCB to not put paste on a pad so I can go back to having a fiducial on one side of the board? Thanks, Jeff On 9/11/06, Phil Taylor <[EMAIL PROTECTED]> wrote: > standard libraries? Has anyone posted fiducials that I could use as a > starting reference? > > Thanks a lot for your assistance guys. > Jeff Jeff, Here are three fiducial footprints. First is a top-layer pad only. Second is a 50 mil pad with a 100 mil clearance circle and a 100 mil soldermask opening. Third is the same as second but with a 175mil clearance circle. This is the one I see the most on other peoples' pcbs. The 2nd and 3rd version appear on all layers. Please let me know if they work out for you. phil _ Element[0x0 "FIDUCIAL__pad-50-100-100.fp" "" "" 0 0 0 0 0 100 0x0] ( Pad[0 0 0 0 5000 5000 1 "" "1" 0x000] ) _ Element[0x0 "FIDUCIAL__pin-50-100-100.fp" "" "" 0 0 0 0 0 100 0x0] ( Pin[0 0 5000 5000 1 0 "" "1" 0x001] ) _ Element[0x0 "FIDUCIAL__pin-50-175-100.fp" "" "" 0 0 0 0 0 100 0x0] ( Pin[0 0 5000 12500 1 0 "" "1" 0x001] ) Element[0x0 "FIDUCIAL__pad-50-100-100.fp" "" "" 0 0 0 0 0 100 0x0] ( Pad[0 0 0 0 5000 5000 1 "" "1" 0x000] ) Element[0x0 "FIDUCIAL__pin-50-100-100.fp" "" "" 0 0 0 0 0 100 0x0] ( Pin[0 0 5000 5000 1 0 "" "1" 0x001] ) Element[0x0 "FIDUCIAL__pin-50-175-100.fp" "" "" 0 0 0 0 0 100 0x0] ( Pin[0 0 5000 12500 1 0 "" "1" 0x001] ) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: slotting problem
El jue, 02-11-2006 a las 22:17 -0500, Ales Hvezda escribió: > [snip] > >None of these work for me. I'm not sure how to use the Edit/Slot... > >function - it doesn't even seem to change the slot attribute value > >(select component, choose Edit/Slot..., change value of slot in dialog). > >The dialog box changes the slot attribute value but doesn't update the > >pins. > > That's bizarre. Can anybody else reproduce this behavior? > On my box, I select the component, pick Edit/Slot..., type in the > new slot number (2 for a 7474-1), hit okay, and boom, I get the pins > to change. Same on mine, unless you use the single attribute editor. Using it, the pin numbers are not updated. Regards, Carlos ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Peter Clifton wrote: > The user setting the footprint attribute would auto-complete with a drop-down list of the available footprints This would be useful. The insertion of proper footprint names in gattrib is currently the slowest part (for me anyway) of going from gschem to PCB. Another thought was even to (optionally) bring up the PCB footprint window with a GUI preview. (Suitably library'fied if possible to avoid code duplication) This would be useful. Phil Taylor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: no pins in JUMPER10
On 11/3/06, Giorgenes Gelatti <[EMAIL PROTECTED]> wrote: Hi there, I've made an schematic with a "pin bar" that has "JUMPER10" as footprint. But when I export it to PCB none of the pins on it get connected. The rest of my circuit is ok, but the "JUMPER10" components goes disconnected in PCB. In the schematic are the connection ends of the pin bars on grid? Are the pin numbers consistent between the schematic symbol and the PCB footprint? You may want to post a *small* schematic and pcb file that demonstrates the problem. For the schematic make sure you use embedded symbols. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: no pins in JUMPER10
Hi there, I've made an schematic with a "pin bar" that has "JUMPER10" as footprint. But when I export it to PCB none of the pins on it get connected. The rest of my circuit is ok, but the "JUMPER10" components goes disconnected in PCB. Any advice? Thank you guys. []'s ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Fri, 2006-11-03 at 09:57 +, Peter Baxendale wrote: > > >The parser starts at the end, moving towards the start of the string and > > >strips off lower case characters until it encounters any non-lowercase > > >character, then it stops. Thus Rp4 will be a valid element name. This > > >has been documented in the manual for at least 5 years now since I first > > >wrote that code. From the pcb manual: > > > > It might be useful to put this information in gEDA/gaf's attribute > > guide under refdes as well. Filed bug to remind us: > > Yes, thanks, that's a good idea. It's at the schematic entry stage when > you're choosing refdes values, so it would be handy to mention it there, > even though strictly it's a pcb issue, not gEDA/gaf. Sorry I missed the > pcb manual bit - I could have saved myself and others some time and also > some noise on this list if I'd seen it. Whilst this statement may be controversial, I'm inclined to believe that anything you have to dig deep into a manual to discover isn't obvious enough in the program :). There are of course exceptions, as no-one expects a complicated EDA package to be learnt solely through feeling your way around the gui.. it simply isn't productive to do so. OTOH, this is how beginners learn, and was exactly how I started. I like to see what people trip over in real life. Even if there is an "answer" in a manual somewhere, perhaps there is a better way. Amusing aside: a few times I found myself poking at the source to see if I could implement a feature / behaviour in PCB / gschem, only to find it was there already and I just didn't know how to activate it! Now, the source-code is my manual! I had a great computer science teacher at A-Level... when you took a program to her for testing, rather than inputting the proper numbers (which as a developer, you do), she would randomly press all the keyboard keys until something broke. A great lesson in input validation! Peter B and I were looking at the possibility of introducing some plugable input validation / auto-complete modules into the gschem attribute editing system. The down side of course, is these must be configured (by default if you will) to understand what attributes are necessary, and what is legal. One idea was "footprint" (assuming your config states that validation and auto-complete for this attribute should be for "PCB", not some other layout package). The user setting the footprint attribute would auto-complete with a drop-down list of the available footprints - obviously requires a knowledge of how / where PCB finds its footprint lists, or a library interface to this functionality in PCB. Another thought was even to (optionally) bring up the PCB footprint window with a GUI preview. (Suitably library'fied if possible to avoid code duplication) I already have too much work backed up to get on with this right now, but if people feed back that this might be useful, it will go higher on the todo pile. (Right after finishing the DBus support in PCB and making xgsch2pcb place nice with it). Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: gEDA user with problems
On Thu, 02 Nov 2006 22:05:03 -0500, Ales Hvezda wrote: > This isn't correct. The source-library rc keyword and associated > path is only used when searching for underlying hierarchical schematic > sheets in gschem and gnetlist. Ouups. Somehow this got mangled in my mind... Digging back in the archives of the list reminds me, that I actually asked in march 2006 how to set the path for the footprints. Back then the answer was "it is hard coded into source". Did this change since then? ---<(kaimartin)>--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> >The parser starts at the end, moving towards the start of the string and > >strips off lower case characters until it encounters any non-lowercase > >character, then it stops. Thus Rp4 will be a valid element name. This > >has been documented in the manual for at least 5 years now since I first > >wrote that code. From the pcb manual: > > It might be useful to put this information in gEDA/gaf's attribute > guide under refdes as well. Filed bug to remind us: Yes, thanks, that's a good idea. It's at the schematic entry stage when you're choosing refdes values, so it would be handy to mention it there, even though strictly it's a pcb issue, not gEDA/gaf. Sorry I missed the pcb manual bit - I could have saved myself and others some time and also some noise on this list if I'd seen it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: slotting problem
> That's bizarre. Can anybody else reproduce this behavior? > On my box, I select the component, pick Edit/Slot..., type in the > new slot number (2 for a 7474-1), hit okay, and boom, I get the pins > to change. Weird. I just tried it again to make sure I wasn't going crazy. Here's what I did: run gschem click on "add component" select 7400-1.sym click in main window close add component window click on the 7400 select Edit menu, slot... (Edit slot number dialogue appears) change slot=1 to slot=2, click OK The pin numbers don't change and if I edit attributes the slot number hasn't been changed either. A bit more investigation shows that this only applies to newly added components. That is, if I save the file and exit gschem, then run it again, Edit/slot... now works on the 7400 I added before, but if I add another one it doesn't work on that one. Maybe it's my version? 20061020 built from sources. Or can I screw this up with something in my gschemrc or gafrc file? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: FPGAs, SDSL, Ronjas...
On Thu, Nov 02, 2006 at 01:27:35PM -0500, Dave McGuire wrote: > On Nov 2, 2006, at 4:35 PM, Michael Sokolov wrote: > >>When the ISP detects this, > > > >Do you think that ISPs have nothing better to do than go into the low > >level debug features of their DSLAMs, look at individual packets in > >hex > >etc. to detect that I started using a different implementation of > >their > >line management protocol? > > Further, very few ISPs actually employ anyone with half a clue > anymore anyway. Trivial matters such as making DNS entries is beyond > most ISPs' staff these days. > > This must be a sign of the apocalypse. I am agreeing with Michael > Sokolov. Why do you think it's a sign of the apocalypse? Who is Michael Sokolov? I can't find any entry for Michael Sokolov on Wikipedia. The Apocalypse may have already began, because the star called Wormwood already spread it's portion of death. "Chernobyl" must be a Russian word for wormwood (in Czech language, which is a slavic language too, there is a plant called "Pelynek cernobyl", which means "Wormwood the black weed"). A star is physically an atomic reactor. In the old days when they wrote the text they didn't have a word for "atomic reactor", so they probably used an existing word describing an object with the same internal physical function. But who cares about some apocalypse here apocalypse there? I currently care about my amplifier to have fast enough edge reaction, clean clipping and not oscillate. When people manage to destroy the civilization, the effect for me will be there will be lots of free abandoned metal all around from which I would build Ronja's for free :) CL< > > >As for the relic Copper Mountain DSLAMs, I've just bought one on eBay > >and am now waiting for the UPS man. > > Those "relics" are deployed by the dozen all over the country. I > am currently responsible for two of them myself. Be prepared...the > user interface is...erm, obtuse. > >-Dave > > -- > Dave McGuire > Cape Coral, FL > > > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: FPGAs, SDSL, Ronjas...
On Thu, Nov 02, 2006 at 04:35:48PM +, Michael Sokolov wrote: > Karel Kulhavy <[EMAIL PROTECTED]> wrote: > > > When the ISP detects this, > > Do you think that ISPs have nothing better to do than go into the low > level debug features of their DSLAMs, look at individual packets in hex > etc. to detect that I started using a different implementation of their > line management protocol? > > > he can change the standard > > Well, we have a precedent already: @#$%^&* Verizon has decided to > decommission their own nice solid Enterprise DSL network (built with > Copper Mountain DSLAMs) and reduce to reselling crappy Covad service. > Covad uses Nokia DSLAMs. They are now connecting all new customers > through Covad even where they have previously had their own DSLAMs. > I don't know what'll happen to the existing customers on the old CM > network, but I won't be surprised if one nice day they force them to > switch. Doesn't matter for me though as my SDSL line is already of the > Nokia/Covad flavor since the last physical relocation of the facilities. > (I don't know if it's because they had already started their diabolical > plan then or because this rural location has never had Enterprise DSL to > begin with.) > > As for the relic Copper Mountain DSLAMs, I've just bought one on eBay > and am now waiting for the UPS man. > > > and then you have > > to do the work once more again. > > Which is where the FPGA saves the day again. That's what field- > programmable is all about: change the hardware with vi and make. You need to do the reverseengineering and declassifying work. What if they refuse to give out the docs, he? > > > Or he puts "only original modem from the > > ISP is allowed" into the contract. > > They probably do already, but how are they going to enforce it? The > worst they can do is not provide me with tech support for a modem of my > own design, but that's rather obvious. They won't disconnect me -- as > long as I pay the bill they don't give a damn about anything else. I'm > perfectly free to experiment with unsupported hw/sw/fw at my own risk. > > > Or what if the ISP starts to telling you what you can do and what you can't? > > For example, my ISP Cablecom Switzerland says in the contract: [...] > > If my ISP were like that, I wouldn't be their customer! Although of > course not all business customers are the same and I can't expect > exactly the same treatment as their T3, OC12 etc. customers, it still IS > a business service, and restrictions like you describe are unheard of on > mission-critical business Internet services -- at least the kind of > business Internet services that I would ever subscribe to. The business grade services offered here are prohibitively expensive here. > > > What is more reliably is getting rid of the abominable ISP and taking the > > whole > > infrastructure into your hands. All you need is my device called Ronja > > [...] > > Of course you don't get an Internet connection with this, but if you find > > more neightbour of friends you can make a LAN > > Rather useless for me as there's nothing but horses and cows in a 20 km > radius of my facility. I'm rather amazed that we have a Covad DSLAM You can put tripods with analogue Ronja retranslation and solar battery between the cows and horses. With WiFi, it wouldn't work because the packetloss increases with amount of hops. With Ronja the packetloss is so low that even a chain of 1000 Ronja's is not a problem (well instead of 10^-9 you get 10^-6 BER). CL< > here. Are Americans now spoiled to the point that even horses and cows > can't live without high speed Internet any more? > > > and then connect with some > > professional-grade connection. > > Aha! You still need the professional-grade connection! That's what my > SDSL is -- professional-grade connection, non-profit organisation > budget-appropriate. > > Of course I would never do a project like this for a consumer service > like ADSL or DOCSIS -- but _S_DSL is a different story. > > > Do something else instead :) > > Let's just agree that we have different interests in life, and leave it > at that. > > MS, > who wants to get back to drawing OSDCU schematics > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: furnace controller I/O port again
On 11/2/06, Dave McGuire <[EMAIL PROTECTED]> wrote: On Nov 2, 2006, at 8:15 PM, Bob Paddock wrote: >> I'll look into it. The thing about op amps is that they're cheap and >> tiny. > > Which frequently gets people into trouble when they try to use > Op-Amps as Comparators: ... > TI: > Op Amps and Comparators - Don't Confuse Them > > Operational amplifiers (op amps) and comparators look similar; they > even have very similar schematic symbols. > This leads a lot of designers to think they are interchangeable. > There is a strong temptation to use a spare section > of a multiple op amp package as a comparator to save money. This > application note will explain why designers should not do this. > > http://encon.fke.utm.my/nikd/latest/sloa067.pdf > Download .pdf (sloa067.pdf, 150 Kbytes)" Not to butt in, but...wow, that is a VERY informative article...Thanks for sending that URL! -Dave I think the article is overstating things a little bit. Sure, op-amps make lousy, slow comparators. But commercially successful op-amps aren't going to burn up if you let the output go to a rail! Some high-spec opamps may have limitations, such as high current in the input stage if you exceed a certain differential voltage, but these limitations should be called out in the datasheet. And expensive, exotic amps aren't the ones being pressed into comparator duty. Regards, Mark [EMAIL PROTECTED] -- You think that it is a secret, but it never has been one. - fortune cookie ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: m32c expansion board works!
I added some pictures of the board swamped with logic probe clips (22 clips) as I debugged the bus timing. http://www.delorie.com/pcb/m3a/ Turns out the CP2200 is too slow to run the m32c at full speed (30 MHz); the m32c can only add 3 wait states (115nS vs 140nS needed). The RAM is too slow for zero wait states by design (15nS vs 20nS needed); the rd/wr pulses are only a half clock wide, not a full clock. So, I programmed the m32c to run at half the crystal speed (15MHz), the RAM at 0 ws (33nS) and the cp2200 at 2 ws (165nS). It seems to be happy that way. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
