gEDA-user: connecting symbols that look nothing like their footprint
Hi all, I'm at the stage in my circuit design where I need to start worrying about converting my schematic to a PCB. I was playing with PCB earlier today and I found the official PCB documentation to be very, very helpful - I wish the gschem docs were as good (the gschem wiki seems a little scattered to me, but maybe I just can't figure out how to navigate it efficiently). Anyways, in my searches I haven't found anything relating to my particular question. I have a MOSFET in my circuit, so naturally I added the appropriate symbol from the gschem symbol library (I think it was mosfet with diode 1). This has the oddity of having the pin numbers be G, D and S instead of actual numbers... But I can rename them to numbers or rename the footprint to those; my real problem has to do with the fact that my FET's package is SO8. 3 pins are source, 4 are drain and 1 is gate. How to I convey to gschem that the single source and drain symbol pins should actually be connected to multiple physical pins? This issue has also come up with parts that have many ground connections, such as the ADXL321 accelerometer; it would be logical for the symbol to have 1 ground pin connected to many physical pins, but until I ran up against this problem with the FET, I just lived with making the symbol look like the package. Note: I understand how I can have a symbol such as an op-amp which hides the power and ground pins; I just don't know how to connect a single symbol pin to multiple physical pins. I thought about using the net attribute, but then I think all instances of my symbol would end up connected together? Sorry for being so long-winded, I was trying to be thorough. I'd appreciate any help you can give me in figuring this out. Thanks, Ryan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
[.] my real problem has to do with the fact that my FET's package is SO8. 3 pins are source, 4 are drain and 1 is gate. How to I convey to gschem that the single source and drain symbol pins should actually be connected to multiple physical pins? Redraw the symbol to incorporate multiple pins. Name them s1, s2, s3, d1, d2, d3, d4, and g. Then draw your PCB footprint to match the symbol. By the way, this is what you do in ViewDraw, Orcad, or any other commerical package. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
On 11/17/06, Meador, Ryan D [EMAIL PROTECTED] wrote:
This issue has also come up with parts that have
many ground connections, such as the ADXL321 accelerometer; it would be
logical for the symbol to have 1 ground pin connected to many physical pins,
but until I ran up against this problem with the FET, I just lived with
making the symbol look like the package.
Note: I understand how I can have a
symbol such as an op-amp which hides the power and ground pins; I just don't
know how to connect a single symbol pin to multiple physical pins. I thought
about using the net attribute, but then I think all instances of my symbol
would end up connected together?
When you are troubleshooting your circuit it is useful to know where
all the physical
pins are connected. If you start eliminating pins from your schematic symbols
you will lose that information. You will not known whether a pin was
Vdd, GND, Vss.
It gets worse for components that operate with multiple isolated grounds (like
isolation amplifiers and isolated DC-DC converters).
Avoid using symbols that hide the power and grounds. You may want to run
a dual-supply amplifier off a single power supply which means connecting Vee to
GND. You may want to connect two isolated DC-DC converters together to get a
positive and negative output which means connecting the output return of one
converter to the output of the other converter. If the nets are embedded you
will not be able to do this.
You can make a symbol with just power and ground connections. If
multiple symbols
have the same refdes they will be treated as a single part.
I have included a short schematic (below) that shows how I like to do power
and connections.
(* jcl *)
--
http://www.luciani.org
--- cut here
v 20050313 1
C 54400 66800 1 0 0 EMBEDDEDcapacitor.sym
[
P 54600 67300 54600 67100 1 0 0
{
T 54650 67500 5 8 0 1 0 0 1
pinnumber=1
T 54650 67500 5 8 0 0 0 0 1
pinseq=1
}
P 54600 66800 54600 67000 1 0 0
{
T 54650 66900 5 8 0 1 0 0 1
pinnumber=2
T 54650 66900 5 8 0 0 0 0 1
pinseq=2
}
L 54800 67100 54400 67100 3 0 0 0 -1 -1
L 54800 67000 54400 67000 3 0 0 0 -1 -1
T 55000 67200 5 10 0 0 0 0 1
device=CAPACITOR
T 54400 66800 8 10 0 1 0 0 1
pins=2
T 54400 66800 8 10 0 1 0 0 1
class=DISCRETE
]
{
T 54700 67200 5 10 1 1 0 0 1
refdes=C?
T 54700 66900 5 10 1 1 0 2 1
value=?
}
C 66800 65400 1 0 0 EMBEDDEDcapacitor.sym
[
P 67000 65900 67000 65700 1 0 0
{
T 67050 66100 5 8 0 1 0 0 1
pinnumber=1
T 67050 66100 5 8 0 0 0 0 1
pinseq=1
}
P 67000 65400 67000 65600 1 0 0
{
T 67050 65500 5 8 0 1 0 0 1
pinnumber=2
T 67050 65500 5 8 0 0 0 0 1
pinseq=2
}
L 67200 65700 66800 65700 3 0 0 0 -1 -1
L 67200 65600 66800 65600 3 0 0 0 -1 -1
T 67400 65800 5 10 0 0 0 0 1
device=CAPACITOR
T 66800 65400 8 10 0 1 0 0 1
pins=2
T 66800 65400 8 10 0 1 0 0 1
class=DISCRETE
]
{
T 67100 65800 5 10 1 1 0 0 1
refdes=C1
T 67100 65500 5 10 1 1 0 2 1
value=0.1uF
}
C 68000 65500 1 0 0 EMBEDDED74x1G14.sym
[
L 68300 65700 68300 66300 3 0 0 0 -1 -1
L 68300 66300 68800 66000 3 0 0 0 -1 -1
L 68800 66000 68300 65700 3 0 0 0 -1 -1
V 68850 66000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 68000 66000 68300 66000 1 0 0
{
T 68200 66050 5 8 1 1 0 6 1
pinnumber=2
T 68200 65950 5 8 0 1 0 8 1
pinseq=1
T 68350 66000 9 8 0 1 0 0 1
pinlabel=A
T 68350 66000 5 8 0 1 0 2 1
pintype=in
}
P 69200 66000 68900 66000 1 0 0
{
T 69000 66050 5 8 1 1 0 0 1
pinnumber=4
T 69000 65950 5 8 0 1 0 2 1
pinseq=2
T 68750 66000 9 8 0 1 0 6 1
pinlabel=Y
T 68750 66000 5 8 0 1 0 8 1
pintype=out
}
T 68300 66900 5 10 0 0 0 0 1
slot=1
T 68300 66700 5 10 0 0 0 0 1
numslots=1
T 68300 66500 5 10 0 0 0 0 1
device=74x1G14
L 68390 66060 68390 65860 3 0 0 0 -1 -1
L 68390 65860 68450 65900 3 0 0 0 -1 -1
L 68390 66060 68450 66100 3 0 0 0 -1 -1
L 68390 65860 68330 65820 3 0 0 0 -1 -1
L 68450 65900 68450 66100 3 0 0 0 -1 -1
L 68450 66100 68520 66140 3 0 0 0 -1 -1
T 68300 68700 5 10 0 0 0 0 1
pins=5
T 68300 69100 5 10 0 0 0 0 1
description=single inverting Schmitt-trigger
T 68300 69500 5 10 0 0 0 0 1
footprint=SC70-65P-210L1-5N__LTC_SC6-Package
]
{
T 68600 66200 5 10 1 1 0 0 1
refdes=U1
}
C 66500 65300 1 0 0 EMBEDDED74x1G14_pwr.sym
[
P 66600 65900 66600 65800 5 0 0
{
T 66600 65775 5 6 1 1 0 5 1
pinlabel=Vcc
T 66625 65825 5 6 1 1 0 0 1
pinnumber=5
}
P 66600 65400 66600 65500 5 0 0
{
T 66600 65525 5 6 1 1 0 3 1
pinlabel=GND
T 66625 65475 5 6 1 1 0 2 1
pinnumber=3
}
]
{
T 66575 65825 5 6 1 1 0 6 1
refdes=U1
}
N 68000 66000 67900 66000 4
N 67900 66000 67900 65900 4
C 66800 66100 1 0 0 EMBEDDED+5V.sym
[
P 67000 66100 67000 66150 1 0 0
{
T 67050 66150 5 6 0 1 0 0 1
pinnumber=1
T 67050 66150 5 6 0 0 0 0 1
pinseq=1
}
V 67000 66200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 67000 66275 9 8 1 0 0 3 1
+5V
T 67100 66100 8 8 0 0 0 0 1
net=+5V:1
]
C 66900 65000 1 0 0 EMBEDDEDgnd.sym
[
P 67000 65150 67000 65200 1 0 1
{
T 67058 65161 5 4 0 1 0 0 1
pinnumber=1
T 67058 65161 5 4 0 0 0 0 1
pinseq=1
}
L 66900 65150 67100 65150 3 0 0 0 -1 -1
L 66900 65150 67000 65050 3 0 0 0 -1 -1
L 67000 65050 67100 65150 3 0 0 0
Re: gEDA-user: connecting symbols that look nothing like their footprint
Meador, Ryan D wrote:
my real problem has to do with the fact that my FET's package is SO8.
3 pins are source, 4 are drain and 1 is gate. How to I convey to gschem that
the single source and drain symbol pins should actually be connected to
multiple physical pins?
The secret is connecting symbols that look nothing like their footprint
is NOT the problem we need to solve
I saw two replies already with concepts for you to think about, and here's
another. To do verbatim what you ask, you convey that to gschem by creating a
symbol to match your situation, and attaching a footprint property with the name
of a matching footprint you will make and put in your local pcb footprint
element library. Your symbol has a list of pairs, (plus more, but the pair of
values are the key ones), of names and numbers of pins. The below scripts use
the bash command shell -- adjust to your situation...
djboxsym and jgboxsym, (gedasymbols.org), are ways to create a symbol box from a
list of the form:
rmfet.symdef
==
# rmfet symbol creation file
[labels]
rmfet
Ecosensory.com
refdes=Q?
! copryright=2006 Meador, Ryan D
! author=Meador, Ryan D
! uselicense=unlimited
! distlicense=GPL
! device=rmfet
! description=fet
! footprint=rmfet.fp
[left]
1 S
2 S
3 G
4 G
[right]
5 D
6 D
7 D
[top]
[bottom]
=
then run:
djboxsym rmfet.symdef rmfet.sym
and edit rmfet.sym in gschem to tweak the appearance,
then put it in your dir like mine called
~/EEProjects/now/circuitboards/gschem-cibolo/ic-gull-wing
that is listed in a file
~/.gEDA/gafrc
containing lines like:
(component-library
${HOME}/EEProjects/now/circuitboards/gschem-cibolo/ic-gull-wing)
and restart gschem or just the library chooser
and place that new symbol.
Next to do with pcb,
add a working dir file:
gafrc
with a line like:
lib-newlib = /home/john/EEProjects/now/circuitboards/footprints_pcb
(Where your new footprints will go)
Now make a footprint with rows of pads with DJ's dual in line pad layer outer
footprint generator (see gedasymbols.org)
if you got the layout just right, but the number order wrong use the n key in
pcb to change the pad numbers,
or just regenerate the footprint again with a different numbering alignment --
the default is likely the way your package is.
John Griessen
I've written this in on swoop with no proofing, so... let's turn it into a FAQ
or guide, huh?
___
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Re: gEDA-user: LED in reverse
Karel Kulhavy wrote: Do you know at which voltage a typical red LED breaks down in reverse? 100V? [jg]usual is 10, 15, 20 Volts onlyfor the ones from 1979 in a hemisphere on cylinder plastic molding What happens when the diode is charged slowly with a current source of say 0.5mA until it breaks down and it's internal capacitance discharges by avalanche? Will it blink or stay dark in the process? [jg]flashes once, then dead... John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LED in reverse
Karel Kulhavy wrote: Do you know at which voltage a typical red LED breaks down in reverse? 100V? No, more like 5v or so. LEDs are not designed for high reverse breakdown voltages. What happens when the diode is charged slowly with a current source of say 0.5mA until it breaks down and it's internal capacitance discharges by avalanche? Will it blink or stay dark in the process? If you are talking about a current applied in the reverse direction it won't light up at all. I haven't looked at the very bright LEDs that have been marketed recently, but in general I would say that most LEDs make lousy capacitors and won't store much charge at all. Joe T Wikipedia says an avalanche reaches maximum in picoseconds. If the avalanche shines, does the light generated reach maximum in picoseconds as well? CL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LED in reverse
On 11/17/06, joeft [EMAIL PROTECTED] wrote: If you are talking about a current applied in the reverse direction it won't light up at all. I haven't looked at the very bright LEDs that have been marketed recently, but in general I would say that most LEDs make lousy capacitors and won't store much charge at all. Actually, diodes and LEDs have been used for varacitors for some time now, especially in homebrew RF equipment. They work quite well for this application. However, because they're not built for use as varacitors, they're not *tested* to see how much capacitance they offer. Consequently, they can have very wide tolerances. -- Samuel A. Falvo II ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hello list
Darryl Gibson wrote: But, I would really, really like my resistors, and diodes standing up, not laying down. Darryl here are three vertical footprints. I've used them before. I just cleaned them up a little. Let the list know if they work for you. These foots are named withing the Element tag. --phil Element[0x R-0W25-vertical.fp R? 172500 127500 -5500 4550 0 100 0x] ( Pin[-3900 0 7000 2000 8200 2900 1 0x01] Pin[3900 0 7000 2000 8200 2900 2 0x01] ElementLine [-3900 -4050 3700 -4050 1000] ElementLine [-3900 4050 3700 4050 1000] ElementArc [3900 0 4050 4050 90 180 1000] ElementArc [-3900 0 4050 4050 270 180 1000] ) Element[0x R-0W5-vertical.fp R? 143000 84000 -7500 5100 0 100 0x] ( Pin [-5200 0 7800 2000 9000 3600 1 0x001] Pin [5200 0 7800 2000 9000 3600 2 0x001] ElementLine [-5200 -4400 5200 -4400 1000] ElementLine [-5200 4400 5200 4400 1000] ElementArc [-5200 0 4400 4400 270 180 1000] ElementArc [5200 0 4400 4400 90 180 1000] ) Element[0x DIO__DO-41-vertical.fp D? 172500 127500 -9900 6050 0 100 0x] ( Pin[-6200 0 9500 2000 10700 4200 1 0x0101] Pin[6200 0 9500 2000 10700 4200 2 0x01] ElementLine [-11450 -5300 6200 -5300 1000] ElementLine [-11450 5300 6200 5300 1000] ElementLine [-11450 -5300 -11450 5300 1000] ElementArc [6200 0 5300 5300 90 180 1000] ) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hello list
[EMAIL PROTECTED] wrote: Darryl Gibson wrote: But, I would really, really like my resistors, and diodes standing up, not laying down. Darryl here are three vertical footprints. I've used them before. I just cleaned them up a little. Let the list know if they work for you. These foots are named withing the Element tag. --phil Phil and DJ, Thanks for the footprints, I'm filing them away for future reference. I'm under time constraints to get this project done. So I'm cheating, and using RCY100 for the resistors. When I'm finished with this project, I'll delve into learning how to make my own footprints. -- Darryl Gibson N2DIY RLU X 182668/379552 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
Thank you for your quick replies. Unfortunately, I don't think I adequately conveyed my question... your answers didn't tell me anything I don't already know. Please pardon me for not quoting them, here, as between the 3 I received so far, it would be a lot of text. I'm aware it is bad practice to hide power and ground pins (I hate symbols with hidden pins!) I'm aware of the option to redraw the symbol to look like the package, but the symbol creation guidelines suggest laying out symbols to be logical rather than reflect the actual look of the device. I've previously used AutoTrax and MultiSim (only the latter to produce a PCB) and never run into this issue - MultiSim's library is extensive enough so that I never had to create my own device. I find it difficult to believe that there is no mechanism in place to accomplish what I want - if that's true, I may just have to implement it. Allow me to once again try to state my problem. Both the FET and gyro I referenced in my initial email have multiple pins with the same purpose. This is different than having multiple but seperate power and ground connections (for an op-amp, for example). The SO8 package of the FET contains only 1 FET. It uses pins 1 through 3 for the source and 5-8 for the drain so it can handle more current than a single lead on that size package normally could. I'm not hiding any pins or forcing them to be connected - they actually are connected inside the device. The standard FET symbol still applies perfectly, as the device has only 3 connections despite having 8 pins. I think this is a bit clearer - is the only option for me to redraw the symbol to have 8 pins and then connect the ones that should be connected on the schematic? Thanks again, Ryan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
Have you tried just naming the pins all the same? The autorouter might not do the right thing, but DRC shouldn't complain. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LED in reverse
Samuel A. Falvo II wrote: On 11/17/06, joeft [EMAIL PROTECTED] wrote: If you are talking about a current applied in the reverse direction it won't light up at all. I haven't looked at the very bright LEDs that have been marketed recently, but in general I would say that most LEDs make lousy capacitors and won't store much charge at all. Actually, diodes and LEDs have been used for varacitors for some time now, especially in homebrew RF equipment. They work quite well for this application. However, because they're not built for use as varacitors, they're not *tested* to see how much capacitance they offer. Consequently, they can have very wide tolerances. Don't forget that diodes intended for use as varactors typically have a substantially different doping profile when compared to diodes intended for use as rectifiers. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: LED in reverse
Karel Kulhavy wrote: Do you know at which voltage a typical red LED breaks down in reverse? 100V? Nope, 5v, and some are as low as 3v. What happens when the diode is charged slowly with a current source of say 0.5mA until it breaks down and it's internal capacitance discharges by avalanche? Will it blink or stay dark in the process? Avalanche is a function of voltage, not current. A diode won't conduct significant current until the max. Vr is exceeded. Wikipedia says an avalanche reaches maximum in picoseconds. If the avalanche shines, does the light generated reach maximum in picoseconds as well? Yep, things will happen in a hurry, whether it emits any light, I don't know. Take a look at this spec. sheet, you can see max Vr is 5v, and max Ir, is 10 microamps. http://www.ledsupply.com/l2-0-r5th20-1.php -- Darryl Gibson N2DIY RLU X 182668/379552 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
Meador, Ryan D wrote: laying out symbols to be logical rather than reflect the actual look of the device. is the only option for me to redraw the symbol to have 8 pins and then connect the ones that should be connected on the schematic? You can redo the symbol so it looks the same, but yes, to get a layout netlist that requires to hook up all D (drain) pins before saying it is complete will require 8 pins in the symbol. To get what you want, you can make some of them invisible though. The pin number to name pair is needed in the netlist to get a layout that has all D pins connected, and that is the mechanism. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
Meador, Ryan D wrote: Thank you for your quick replies. I put an example of how I did two transistors in one package. DJ's preview drew the lines 10X thicker than they show up in gschem... not sure what is off...I'm using very recent cvs of both gschem and pcb... http://www.gedasymbols.org/user/john_griessen/symbols/ pnp_npn_slot1.sym pnp_npn_slot2.sym These have a one pin to one pad correspondence -- I just mention them since they show a way to handle these with fractional package symbols, but not the usual slot look. John Griessen PS There are some other symbols in my dir also. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
I put an example of how I did two transistors in one package. DJ's preview drew the lines 10X thicker than they show up in gschem... not sure what is off...I'm using very recent cvs of both gschem and pcb... I'll try to find time to look into that over the weekend. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hello list
Darryl Gibson wrote: I'm under time constraints to get this project done. So I'm cheating, and using RCY100 for the resistors. uh ... what's rcy100? Phil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Wishes, bugs and misunderstandings
Some time ago I promised to turn my notes during my first geda projects into bug reports and feature requests and send them to this mailing list. Some of the issues may be resolved, some may be misunderstandings by a newbie and some may be known but need too much work. I hope you don't smack me if I bring them up again. Here is the deal: The list of notes has grown to quite some size. I will present five notes at a time just to disperse them a bit. If you think a particular topic is worth the effort, I'll integrate it into the ToTo list in the wiki. So please give your opinion if the particular issue is valid or just a newbies misunderstanding. 1) gsch2pcb should look at $HOME/.pcb/preferenes for layer names and layer groups of the pcb file it produces. 2) Feature request: gschem and pcb both don't seem to present a list of recently loaded files in the file menu. This would come handy for work on more than one project at a time. 3) Similar functions in gschem and pcb should be called by the same key accelerators. I still find myself pressing [n] in pcb if I want to draw a track, or do an [u] in gschem for a quick undo. I know, there are different philosophies for the keys. Why not have the best of both worlds and add the respective accelerators to the already installed set? 3a) I miss the sort of standard accelerators [ctrl-c], [ctrl-v], [ctrl-z], [ctrl-shift-z], [ctrl-s], [ctrl-f] and [ctrl-a] 3b) Please add a key accelerator for the grid size dialog. 3c) German keyboards have the z and the y key exchanged. Thus the two letter accelerators that involve these keys tend to be not quite as convenient as on an american keyboard. 3d) Feature request: Please use the built-in key customization of GTK2. With pcb this already works while the application runs, but gets reset on restart. 4) Feature request gschem: Please show the current grid size in the status bar. 5) gschem: Put the name of the current page should in the window title bar rather than in the status bar. The status bar space may contain more volatile information. Any comments? ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: strange lines at the end of gerber files
On monday the first gerbers made with pcb from the current iso image will go to the fab. I appreciate, that the layer commands have been reworked. No more identical layer names, no need to apply my renaming sed script :-) While looking at the gerbers, I notice that there is an additional layer at the end of files called *group*.gbr. Layer name is the same as further up in the file _C1. There is a LPC command in the next line. And the last line of the file is crowded by a host of G commands without X or Y parameters. Example: -8-- G54D25*%LNGROUP0_C1*% %LPC*% G54D37*G54D36*G54D37*G54D38*G54D13*G54D38*G54D13*G54D38*G54D37*G54D13*G54D38*G54D36*G54D19*G54D39*G54D19*G54D39*G54D19*G54D39*G54D19*G54D39*G54D19*G54D39*G54D19*G54D11*G54D19*G54D11*G54D19*G54D39*G54D19*M02* 8 What is the significance of these lines? gerbv didn't seem to care if I removed them. Can I or should I remove them before sending the gerbers to the fab? ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
