Re: gEDA-user: Which are the biggest looking gEDA warts?
Dan McMahill wrote: Andy Peters wrote: On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote: On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote: No back-annotation. This is VERY important to me. As part of general cleanup after finishing a layout, I renumber all of the reference designators in geographical order. This gives technicians a fighting chance to find parts on a cluttered board. I'll just comment that it would be quite easy to implement this. doh! I just looked and realized I _had_ already implemented this The only thing I had not done was test it out and create a regression test. So, any volunteers? In pcb, :Renumber(), then use the pcb_backannotate script. Try pcb_backannotate --help to get you going. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Which are the biggest looking gEDA warts?
Dan McMahill wrote: Dan McMahill wrote: Andy Peters wrote: On Feb 25, 2007, at 4:53 PM, Ben Jackson wrote: On Sun, Feb 25, 2007 at 05:07:59PM -0600, John Griessen wrote: No back-annotation. This is VERY important to me. As part of general cleanup after finishing a layout, I renumber all of the reference designators in geographical order. This gives technicians a fighting chance to find parts on a cluttered board. I'll just comment that it would be quite easy to implement this. doh! I just looked and realized I _had_ already implemented this The only thing I had not done was test it out and create a regression test. So, any volunteers? In pcb, :Renumber(), then use the pcb_backannotate script. Try pcb_backannotate --help to get you going. -Dan oh, one more thing. Since pcb_backannotate had not been fully tested, it is distributed (geda-utils/scripts/pcb_backannotate) but it is not installed. I was waiting to add it to the install list until it had received some testing. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gnetlist -gdrc2 output
Hello, I'm at the stage of processing my design through gnetlist so I can track down all the errors. I'm having a little trouble with the output generated by a call like: gnetlist -v -g drc2 pedio_5i20Aconn.sch pedio_5i20Bconn.sch ... (lots more .sch files) ... -o drc_output.txt drc_stdout.txt 2drc_stderr.txt The problem is that I see reported errors, but it is difficult to work out where the error was caused; that is, in which schematic. For example: Checking slots... ERROR: Multislotted reference U? has no slot attribute defined. It would be very useful if the schematic on which the U? element appears was printed. The program where this should happen is get-drc2.scm. Having only programmed a little lisp about 7 years ago, I don't feel too much like getting stuck into this file. What do other geda users do about error checking? Has anyone else had this problem? Seb James ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist -gdrc2 output
On 2/26/07, Seb James [EMAIL PROTECTED] wrote: Checking slots... ERROR: Multislotted reference U? has no slot attribute defined. It would be very useful if the schematic on which the U? element appears was printed. The program where this should happen is get-drc2.scm. Having only programmed a little lisp about 7 years ago, I don't feel too much like getting stuck into this file. You could try processing one schematic at a time. A real quick way to find refdes set to U? would be to use grep. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist -gdrc2 output
Seb James wrote: I tried that, but it seems that the component doesn't have an explicit refdes of U?. I suppose that somewhere there is a component which is missing the refdes altogether. If you search all your output files, ( -o drc_output.txt drc_stdout.txt 2drc_stderr.txt), for the same words as went to ERROR: Multislotted reference U? has no slot attribute defined. you'll get near the problem. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC problem at close pads
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png Could you post (or send me privately) the .pcb file? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: DRC: Line with insufficient clearance inside polygon
Hi, the DRC tells me Line with insufficient clearance inside polygon. If I do Ctrl+R on the line in question, the clearance is correctly shown as 5.91mils (actually 0.15mm). 0.15mm is also my configured DRC clearance. Might that just be a rounding error which I can ignore? regards, David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: nets in symbols
Hi again,
I defined a new symbol, for the Mesa Electronics 7I33 daughter board.
This has 104 pins, of which about half connect to ground.
The start of the symbol file is appended to the end of this email, and I
attached the complete symbol file.
If you look at the first 15 lines or so, you'll see I defined a GND net and a
+5V net for two subsets of the pins.
So far so good...
Problem 1
--
However, gnetlist -g drc2 . is telling me that these pins are of unknown
type, which is true - I didn't set the type.
How would I set the type for these nets? All the examples I have seen of
setting the pintype attribute have related to a single, visible pin, rather
than a declaration for a set of pins like this:
net=GND:2,4,6
The symbol creation guide (http://geda.seul.org/wiki/geda:scg) tells you how
to set the power pins of a NAND gate, but I can't see that the pintypes of
the power pins for that symbol are set.
Problem 2
--
I am placing this symbol in a design which is split into two regions, with
opto-isolators connecting them. This means I have two ground nets, and I also
have two 5V nets.
Instead of using the nets GND and +5V, I have gnd_left and gnd_right and
+5v_left and +5v_right.
But... the nets in my symbol are GND and +5V. What is the best way to redefine
these nets? Should I manually add the 50 or so ground/power pins to my
symbol, so that I can wire each ground pin to either gnd_left or gnd_right in
my schematic? Or is there another way of setting what the GND net in my
symbol actually connects to? Can I redefine the nets for those pins after I
placed the symbol in my schematic?
with regards,
Seb James
7I33.sym is attached, the start is appended here:
v 20060123 1
B 500 300 2500 17700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
{
T 1300 18300 5 10 0 0 0 0 1
devicename=7I33
T 1300 18600 5 10 0 0 0 0 1
footprint=7I33_Socket
T 1300 18970 5 10 0 0 0 0 1
net=GND:2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50
T 1300 19270 5 10 0 0 0 0 1
net=GND:51,54,60,62,66,72,74,78,84,86,90,96,98,100,102,103
T 1300 19570 5 10 0 0 0 0 1
net=+5V:57,69,81,93,101,104
T 1300 19870 5 10 0 0 0 0 1
documentation=http://www.mesanet.com/pdf/motion/7i33man.pdf
T 500 100 5 10 1 1 0 0 1
description=Mesa Electronics 7I33 Servo Daughter Board.
T 1300 20170 5 10 0 0 0 0 1
device=MESA7I33
T 1300 20470 5 10 0 0 0 0 1
numslots=0
}
T 2700 18100 8 10 1 1 0 0 1
refdes=U?
P 3300 8000 3000 8000 1 0 0
{
T 2900 8000 5 10 1 1 0 6 1
pinlabel=QB1
T 3400 8000 5 10 1 1 0 6 1
pinnumber=1
T 2900 8200 5 10 0 0 0 6 1
pintype=out
T 3400 8200 5 10 0 1 0 6 1
pinseq=1
}
etc. etc...
v 20060123 1
B 500 300 2500 17700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
{
T 1300 18300 5 10 0 0 0 0 1
devicename=7I33
T 1300 18600 5 10 0 0 0 0 1
footprint=7I33_Socket
T 1300 18970 5 10 0 0 0 0 1
net=GND:2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50
T 1300 18970 5 10 0 0 0 0 1
pintype=pwr:2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50
T 1300 19270 5 10 0 0 0 0 1
net=GND:51,54,60,62,66,72,74,78,84,86,90,96,98,100,102,103
T 1300 19270 5 10 0 0 0 0 1
pintype=pwr:51,54,60,62,66,72,74,78,84,86,90,96,98,100,102,103
T 1300 19570 5 10 0 0 0 0 1
net=+5V:57,69,81,93,101,104
T 1300 19570 5 10 0 0 0 0 1
pintype=pwr:57,69,81,93,101,104
T 1300 19870 5 10 0 0 0 0 1
documentation=http://www.mesanet.com/pdf/motion/7i33man.pdf
T 500 100 5 10 1 1 0 0 1
description=Mesa Electronics 7I33 Servo Daughter Board.
T 1300 20170 5 10 0 0 0 0 1
device=MESA7I33
T 1300 20470 5 10 0 0 0 0 1
numslots=0
}
T 2700 18100 8 10 1 1 0 0 1
refdes=U?
P 3300 8000 3000 8000 1 0 0
{
T 2900 8000 5 10 1 1 0 6 1
pinlabel=QB1
T 3400 8000 5 10 1 1 0 6 1
pinnumber=1
T 2900 8200 5 10 0 0 0 6 1
pintype=out
T 3400 8200 5 10 0 1 0 6 1
pinseq=1
}
P 3300 8400 3000 8400 1 0 0
{
T 2900 8400 5 10 1 1 0 6 1
pinlabel=QA1
T 3400 8400 5 10 1 1 0 6 1
pinnumber=3
T 2900 8600 5 10 0 0 0 6 1
pintype=out
T 3400 8600 5 10 0 1 0 6 1
pinseq=3
}
P 3300 10700 3000 10700 1 0 0
{
T 2900 10700 5 10 1 1 0 6 1
pinlabel=QB0
T 3400 10700 5 10 1 1 0 6 1
pinnumber=5
T 2900 10900 5 10 0 0 0 6 1
pintype=out
T 3400 10900 5 10 0 1 0 6 1
pinseq=5
}
P 3300 11100 3000 11100 1 0 0
{
T 2900 11100 5 10 1 1 0 6 1
pinlabel=QA0
T 3400 11100 5 10 1 1 0 6 1
pinnumber=7
T 2900 11300 5 10 0 0 0 6 1
pintype=out
T 3400 11300 5 10 0 1 0 6 1
pinseq=7
}
P 3300 7600 3000 7600 1 0 0
{
T 2900 7600 5 10 1 1 0 6 1
pinlabel=IDX1
T 3400 7600 5 10 1 1 0 6 1
pinnumber=9
T 2900 7800 5 10 0 0 0 6 1
pintype=out
T 3400 7800 5 10 0 1 0 6 1
pinseq=9
}
P 3300 10300 3000 10300 1 0 0
{
T 2900 10300 5 10 1 1 0 6 1
pinlabel=IDX0
T 3400 10300 5 10 1 1 0 6 1
pinnumber=11
T 2900 10500 5 10 0 0 0 6 1
pintype=out
T 3400 10500 5 10 0 1 0 6 1
pinseq=11
}
P 3300 2400 3000 2400 1 0 0
{
T 2900 2400 5 10 1 1 0 6 1
pinlabel=QB3
T 3400 2400 5 10 1 1 0 6 1
pinnumber=25
T 2900 2600 5 10 0 0 0 6 1
pintype=out
T 3400 2600 5 10 0 1 0 6 1
pinseq=25
}
P 3300 2800 3000 2800 1 0 0
{
T 2900 2800 5
Re: gEDA-user: nets in symbols
On Monday 26 February 2007 16:06, Seb James wrote: Hi again, I defined a new symbol, for the Mesa Electronics 7I33 daughter board. This has 104 pins, of which about half connect to ground. The start of the symbol file is appended to the end of this email, and I attached the complete symbol file. If you look at the first 15 lines or so, you'll see I defined a GND net and a +5V net for two subsets of the pins. So far so good... Problem 1 -- However, gnetlist -g drc2 . is telling me that these pins are of unknown type, which is true - I didn't set the type. How would I set the type for these nets? All the examples I have seen of setting the pintype attribute have related to a single, visible pin, rather than a declaration for a set of pins like this: net=GND:2,4,6 The symbol creation guide (http://geda.seul.org/wiki/geda:scg) tells you how to set the power pins of a NAND gate, but I can't see that the pintypes of the power pins for that symbol are set. Relating to my problem 1, I found this message: http://osdir.com/ml/gmane.comp.cad.geda.user/2006-03/msg00267.html Which relates to this pintype of hidden power pins problem. A patch was posted and applied, so I think I need to use a more recent version of gschem/gnetlist with my design. I'm currently using 20060123 as that is the version which is easiest to install on Gentoo Linux. Seb ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC: Line with insufficient clearance inside polygon
DJ == DJ Delorie [EMAIL PROTECTED] writes: the DRC tells me Line with insufficient clearance inside polygon. If I do Ctrl+R on the line in question, the clearance is correctly shown as 5.91mils (actually 0.15mm). 0.15mm is also my configured DRC clearance. Look for tiny traces under the pads. Hide the pins/pads layer to see them. Yes, I had also problem with tiny traces under pads. But still every line in my degsign that crossed a polygon showed a DRC error, which points to another issue? Now I already increased the of all those lines. Just wanted to reproduce the pior error, but after decreasing line clearence, the error doesn't occure any more. Maybe increasing/decreasing clearence made rounded results fall towards a wider clearence? Yes that seems to be the case. For new lines the error still occurs, see the cyan-colored line hi-lighted by the DRC: http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem2.png After increasing and decreasing clearence (pressing k then K), object-report shows the clearance to be 5.92 mil instead of the prior 5.91 mil. Well, now my design has only one (strange?) DRC error left. thanks for your help, regards, David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC problem at close pads
DJ == DJ Delorie [EMAIL PROTECTED] writes: http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png Could you post (or send me privately) the .pcb file? Here is a simplified file that only contains the problematic footprint. Quite possibly this is just a problem with the footprint? After all this was hand-coded in M4... regards, David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 bugboard.pcb Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: DRC: Element Z50 has 5 silk lines which are too thin
Hi, just another strange DRC error. This is caused by the oldlib-generated footprint SMT_DIODE 15 8: Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09 min drill 1.00, min annular ring 15.75 Element Z50 has 5 silk lines which are too thin near location (1942.91,1350.39) Found 1 design rule error I thought PCB would just increase too thin silk lines when exporting gerber files. At least it does so for fonts... David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dinotrace (Re: Which are the biggest looking gEDA warts?)
About dinotrace How 'bout Stuart's big build CD? Good idea. I just added it to the ToDo list. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dinotrace (Re: Which are the biggest looking gEDA warts?)
Hi Dan and all, On Monday 26 February 2007 17:20, Stephen Williams wrote: Is it wrapped up into any Linux packages? Can you convince Werner to include it in his set of tools that he packages for SuSE? How 'bout Stuart's big build CD? Really, in the Linux world, dinotrace seems to be a well kept secret:-) I'll take a look at it. Regards Werner ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Installer suddenly dying on Mandriva 2007.0
Al Hooton wrote: This is on a vanilla install of Mandriva 2007.0. I have looked through the list archives, the INSTALL information and googled around, but I'm stuck. Hopefully somebody here has the answer as to why the installer just suddenly gives up near the beginning of things. I downloaded the gEDA installer ISO about a week ago and burned it to CD (yes, I just noticed there is a new installer ISO that went up in the last couple of days, but before I try it I'd like to know if the following is a known problem or not). When it gets to the point of determining that it needs to install readline it asks me for the root password, waits a couple of seconds, then the installer just disappears. Here's what I get with both --log and --verbose on the installer command line: installer log This is the log window which will display the spew generated by the installation process gEDA Installer -- version 20061214, Copyright (C) 2004 -- 2006 Stuart D. Brorson. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details: http://www.gnu.org/licenses/gpl.html You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. First check if I am running as root. whoami al Checking for various required programs . . . which gcc /usr/bin/gcc which make /usr/bin/make which gtk-config which: no gtk-config in (/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/usr/games:/usr/lib/qt3//bin:/home/al/bin:/usr/lib/qt3//bin) gtk-config is missing on this machine. We'll tell the user about that in a minute. which pkg-config /usr/bin/pkg-config pkg-config version 0.20 found. pkg-config version found on this system is good. Great! find /usr/include /usr/local/include -name 'readline.h' -print | grep 'include/readline/readline.h' We need to install readline.h on this machine. We'll do that in a minute. which gettext /bin/gettext which autopoint which: no autopoint in (/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/usr/games:/usr/lib/qt3//bin:/home/al/bin:/usr/lib/qt3//bin) We need to install autopoint -- a component of the gettext system -- on this machine. We'll do that in a minute. which gdlib-config which: no gdlib-config in (/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/usr/games:/usr/lib/qt3//bin:/home/al/bin:/usr/lib/qt3//bin) We need to install gdlib-config on this machine. We'll do that in a minute. which guile /usr/bin/guile which guile-config which: no guile-config in (/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/usr/games:/usr/lib/qt3//bin:/home/al/bin:/usr/lib/qt3//bin) We need to install guile-config on this machine. We'll do that in a minute. which wx-config which: no wx-config in (/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/usr/games:/usr/lib/qt3//bin:/home/al/bin:/usr/lib/qt3//bin) We need to install wx-config on this machine. We'll do that in a minute. which wish /usr/bin/wish tclsh version 8.4 found. tclsh version found on this system is good. Great! Preparing to install the readline headers. . . . Now start process of building and installing readline.h. I need root in order to execute this command. --- Starting expect session --- Sending su Timeout waiting for password prompt Spew received up to now: Password: /installer log That's it -- the installer just stops. Anybody know what's happening? Thanks! -Al ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user I've had this same problem with the 20061214 installer, and with the previous 2 releases. Haven't tried Stuart's latest release yet. I run this on SuSe 9.3. My solution was to manually install readline and the other system packages needed. You can run the installer as root but this is not recommended according to the installer documentation. It tends to break things later in the install process.. Joe T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: new boards!
Just showed up today... http://www.delorie.com/house/furnace/pcb2/ First observations: pcb-pool's drills (m32c board) were off center a bit, coming close to touching the edges of the copper. Advanced Circuit's drills seem to be much more accurately aligned. I put 1 2 3 4 on each layer, it turns out this makes it easy to verify the stackup (see photo), which is of course correct. As far as I can tell, all the thermals, teardrops, and clipped polygons turned out perfect. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new boards!
DJ Delorie wrote: Just showed up today... The teardrops look nice, DJ. What are the 3 long pads that appear next to some of the 20 pin and 32 pin footprints (on the top)? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new boards!
The teardrops look nice, DJ. Thanks! I've had traces detach from pins during rework, I'm hoping that the teardrops avoid the hard inside corners that sometimes lead to failure. Plus they're pretty :-) What are the 3 long pads that appear next to some of the 20 pin and 32 pin footprints (on the top)? 20MHz resonators for the five microcontrollers. Panasonic EFO-BM2005E5, about 72 cents each. Here's a photo on my r8c board: http://www.delorie.com/pcb/r8c-1b-adapter/bottom.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Master Parts List
I am putting together a master parts list table for my component database. I am trying to determine a good format for component part numbers. Are there any industry standards for this type of information? IPC documentation? I was thinking of starting with some of the IPC-7351 component category tags and adding in the missing component types. The categories CAP, RES, IND, DIO, LED, BAT, etc. would work. To add sub-categories I would add suffixes. For example a 330pf 1% X7R ceramic cap in an 0805 package could be CAP_X7R-331-102-0805 A few other caps --- CAP_NPO, CAP_AE (aluminum electrolytic) Cap arrays --- CAPCAV, CAPCAX, CAPCAF For ICs maybe IC_AMP, IC_LDO, IC_74LVC138, etc. Some sort of package suffix convention is needed. I am looking for some detailed information that is public. Thanks. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: nets in symbols
On Mon, 26 Feb 2007 16:06:57 + Seb James [EMAIL PROTECTED] wrote: Problem 2 -- I am placing this symbol in a design which is split into two regions, with opto-isolators connecting them. This means I have two ground nets, and I also have two 5V nets. Instead of using the nets GND and +5V, I have gnd_left and gnd_right and +5v_left and +5v_right. But... the nets in my symbol are GND and +5V. What is the best way to redefine these nets? Should I manually add the 50 or so ground/power pins to my symbol, so that I can wire each ground pin to either gnd_left or gnd_right in my schematic? Or is there another way of setting what the GND net in my symbol actually connects to? Can I redefine the nets for those pins after I placed the symbol in my schematic? This is why I don't use 'hidden' nets, they get in the way when using multiple gnd/vcc. I group all the vcc and gnd together by expected application, and add a line in the schmatic. All the pins are the same length so a line is easy draw. But if an other application comes up, I have all my different nets available. Also, Looking at your symbol, it might be nice to split your symbol by application. ie one symbol for each isolated half. Just give them the same refdes and all is well. I attached my 4part example. Look at power and ADC. they show what I did. I used djboxsym.pl[1] to make my symbols. [1] http://www.gedasymbols.org/user/dj_delorie/tools/djboxsym.html -Lares pgpqF0sMpkmy6.pgp Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: nets in symbols
Gah! Attaching .sym's help. -Lares ATMega640-1280-2560_ADC.sym Description: Binary data ATMega640-1280-2560_IO1.sym Description: Binary data ATMega640-1280-2560_IO2.sym Description: Binary data ATMega640-1280-2560_pwr.sym Description: Binary data pgp0b6ysaTX1h.pgp Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC problem at close pads
David Kuehling wrote: DJ == DJ Delorie [EMAIL PROTECTED] writes: http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png Could you post (or send me privately) the .pcb file? Here is a simplified file that only contains the problematic footprint. Quite possibly this is just a problem with the footprint? After all this was hand-coded in M4... I'd be more likely to suspect the footprint if after all it was hand drawn instead of generated programattically... Ok, here's the deal. It is a bug in pcb. Square (or rectangular) pads are checked by growing one of them in X and Y on all 4 sides by the minimum space. This of course means that the corners grew by sqrt(2) more and thats why you got a failures. I'll try to cook up a patch tonight. I took a quick look at that footprint and it is similar but not quite the same as the TQFN_40_6_EP in the ~geda library. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC: Element Z50 has 5 silk lines which are too thin
David Kuehling wrote: Hi, just another strange DRC error. This is caused by the oldlib-generated footprint SMT_DIODE 15 8: Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09 min drill 1.00, min annular ring 15.75 Element Z50 has 5 silk lines which are too thin near location (1942.91,1350.39) Found 1 design rule error I thought PCB would just increase too thin silk lines when exporting gerber files. At least it does so for fonts... It does not and I would object to it increasing too thin silk lines automatically. Perhaps doing that causes silk on a pad for example. My take is silk lines that are too narrow are real DRC violations. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: nets in symbols
Marc Moreau wrote: On Mon, 26 Feb 2007 16:06:57 + Seb James [EMAIL PROTECTED] wrote: Instead of using the nets GND and +5V, I have gnd_left and gnd_right and +5v_left and +5v_right. Can I redefine the nets for those pins after I placed the symbol in my schematic? Looking at your symbol, it might be nice to split your symbol by application. ie one symbol for each isolated half. Just give them the same refdes and all is well. [jg]making a separate symbol for just the power and ground is another ,(least effort), way to handle this -- then copy that symbol and give one group U1, U2, U3 and connect to a net with attrib netname=+5v_left and connect another group to a net with attrib netname=+5v_right. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB question
OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the packages directory in the current workig directory. No?! -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the packages directory in the current workig directory. No?! Note that a local directory *overrides* the global one, as pcb only supports one library at a time (er, one each of m4 and newlib). In my gsch2pcb project file, I do something like this: elements-dir footprints For PCB, you set the lib-newlib variable (settings in gtk, Xdefaults in lesstif). Xdefaults example: Pcb.lib-newlib: /envy/dj/geda/gedasymbols/www/user/dj_delorie/footprints ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
On Mon, Feb 26, 2007 at 07:59:02PM -0500, DJ Delorie wrote: Note that a local directory *overrides* the global one, as pcb only supports one library at a time (er, one each of m4 and newlib). Agh can I add that as a wart? I don't remember this happening to me, but it might explain why adding a local directory of newlib increased my use of m4! -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
Agh can I add that as a wart? Yup :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: PCB question
DJ Delorie wrote: OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the packages directory in the current workig directory. No?! Note that a local directory *overrides* the global one, as pcb only supports one library at a time (er, one each of m4 and newlib). In my gsch2pcb project file, I do something like this: elements-dir footprints For PCB, you set the lib-newlib variable (settings in gtk, Xdefaults in lesstif). Xdefaults example: Pcb.lib-newlib: /envy/dj/geda/gedasymbols/www/user/dj_delorie/footprints I'm puzzled by this response. Under File-Preferences in the Library tab there is an entry box for Element directories that asks for a colon separated list of directories. Where does this list get stored? Where is this settings file for the gtk hid? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: PCB question
I'm puzzled by this response. Under File-Preferences in the
Library tab there is an entry box for Element directories that
asks for a colon separated list of directories. Where does this
list get stored?
These are the times I like it when I'm wrong. Both gtk and lesstif
allow colon-separated lists, to provide for multiple newlib
directories. However, it does seem to override the default library.
Where is this settings file for the gtk hid?
IIRC gtk uses the standard gconf stuff.
Note that PCB (any hid) attempts to load settings from
$prefix/share/pcb/settings, ~/.pcb/settings, and ./pcb.settings.
You can use :SaveSettings() to save them:
SaveSettings()
SaveSettings(local)
Saves settings.
If you pass no arguments, the settings are stored in
@code{$HOME/.pcb/settings}. If you pass the word @code{local} they're
saved in @code{./pcb.settings}.
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Re: gEDA-user: PCB question
DJ Delorie wrote: OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the packages directory in the current workig directory. No?! When you say it will automatically search what is the it? If you're talking the library browser in pcb, I think it won't. If you're talking about gsch2pcb I think it will. Note that a local directory *overrides* the global one, as pcb only supports one library at a time (er, one each of m4 and newlib). Thats not really true. Only 1 for m4, but for newlib, you just use a : separated path (; for windows due to paths like c:\) just like a unix search path. In my gsch2pcb project file, I do something like this: elements-dir footprints I'm pretty certain that you can include multiple elements-dir lines in your project file and gsch2pcb will search through them all. At least thats what it looks like in the code. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC problem at close pads
Dan McMahill wrote:
David Kuehling wrote:
DJ == DJ Delorie [EMAIL PROTECTED] writes:
http://user.cs.tu-berlin.de/~dvdkhlng/clearance-problem.png
Could you post (or send me privately) the .pcb file?
Here is a simplified file that only contains the problematic footprint.
Quite possibly this is just a problem with the footprint? After all
this was hand-coded in M4...
I'd be more likely to suspect the footprint if after all it was hand
drawn instead of generated programattically...
Ok, here's the deal. It is a bug in pcb. Square (or rectangular) pads
are checked by growing one of them in X and Y on all 4 sides by the
minimum space. This of course means that the corners grew by sqrt(2)
more and thats why you got a failures. I'll try to cook up a patch
tonight.
could you try out the attached patch? I'd appreciate it if you tried it
out on some corner cases where the spacing should just barely pass or
just barely fail both on pads on a single row and on those corners.
I think it seems ok, but until there is some sort of regression
testsuite in place I'm nervious about that part of the code
-Dan
Index: src/find.c
===
RCS file: /cvsroot/pcb/pcb/src/find.c,v
retrieving revision 1.59
diff -u -2 -r1.59 find.c
--- src/find.c 5 Nov 2006 01:27:13 - 1.59
+++ src/find.c 27 Feb 2007 01:41:06 -
@@ -432,4 +432,15 @@
BoxType b1, b2;
+ /* Here we are trying to find out if two rectangles have at least
+ * Bloat space between them. Note that this takes more care than
+ * simply blowing out one of the rectangles by Bloat on all sides.
+ * That only works if the shortest line between the two original
+ * rectangles is perpendicular to the sids of the rectangles.
+ *
+ */
+
+ /* Step #1 find out if the shortest line is perpendicular to
+ * the closest edge
+ */
b1.X1 = MIN (p1-Point1.X, p1-Point2.X) - (p1-Thickness + 1) / 2;
b1.Y1 = MIN (p1-Point1.Y, p1-Point2.Y) - (p1-Thickness + 1) / 2;
@@ -437,17 +448,64 @@
b1.Y2 = MAX (p1-Point1.Y, p1-Point2.Y) + (p1-Thickness + 1) / 2;
- b2.X1 =
-MIN (p2-Point1.X,
- p2-Point2.X) - MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
- b2.Y1 =
-MIN (p2-Point1.Y,
- p2-Point2.Y) - MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
- b2.X2 =
-MAX (p2-Point1.X,
- p2-Point2.X) + MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
- b2.Y2 =
-MAX (p2-Point1.Y,
- p2-Point2.Y) + MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
- return BoxBoxIntersection (b1, b2);
+ b2.X1 = MIN (p2-Point1.X, p2-Point2.X) - (p2-Thickness + 1) / 2;
+ b2.Y1 = MIN (p2-Point1.Y, p2-Point2.Y) - (p2-Thickness + 1) / 2;
+ b2.X2 = MAX (p2-Point1.X, p2-Point2.X) + (p2-Thickness + 1) / 2;
+ b2.Y2 = MAX (p2-Point1.Y, p2-Point2.Y) + (p2-Thickness + 1) / 2;
+
+ if ( (b2.X1 = b1.X2 b2.X2 = b1.X1) ||
+ (b2.Y1 = b1.Y2 b2.Y2 = b1.Y1) )
+ {
+ b2.X1 =
+ MIN (p2-Point1.X,
+p2-Point2.X) - MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
+ b2.Y1 =
+ MIN (p2-Point1.Y,
+p2-Point2.Y) - MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
+ b2.X2 =
+ MAX (p2-Point1.X,
+p2-Point2.X) + MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
+ b2.Y2 =
+ MAX (p2-Point1.Y,
+p2-Point2.Y) + MAX ((p2-Thickness + 1) / 2 + Bloat, 0);
+ return BoxBoxIntersection (b1, b2);
+ }
+ else
+ {
+ /* the shortest line is between two corners */
+ double x1, x2, y1, y2, d;
+
+ if (b2.X2 b1.X1)
+ {
+ /* b2 is to the left of b1 */
+ x1 = (double) b1.X1;
+ x2 = (double) b2.X2;
+ }
+ else
+ {
+ /* b2 is to the right of b1 */
+ x1 = (double) b1.X2;
+ x2 = (double) b2.X1;
+ }
+
+ if (b2.Y2 b1.Y1)
+ {
+ /* b2 is above b1 */
+ y1 = (double) b1.Y1;
+ y2 = (double) b2.Y2;
+ }
+ else
+ {
+ /* b2 is below b1 */
+ y1 = (double) b1.Y2;
+ y2 = (double) b2.Y1;
+ }
+
+ /* use floating point math to avoid overflows here */
+ if ( (x1 - x2)*(x1 - x2) + (y1 - y2)*(y1 - y2) ((double)
Bloat)*((double) Bloat) )
+ return TRUE;
+ else
+ return FALSE;
+ }
+
}
if (TEST_FLAG (SQUAREFLAG, p1))
@@ -455,5 +513,5 @@
return LinePadIntersect ((LineTypePtr) p1, p2);
}
-
+
static inline Boolean
PV_TOUCH_PV (PinTypePtr PV1, PinTypePtr PV2)
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gEDA-user: Re: PCB question
DJ Delorie wrote:
I'm puzzled by this response. Under File-Preferences in the
Library tab there is an entry box for Element directories that
asks for a colon separated list of directories. Where does this
list get stored?
These are the times I like it when I'm wrong. Both gtk and lesstif
allow colon-separated lists, to provide for multiple newlib
directories. However, it does seem to override the default library.
Where is this settings file for the gtk hid?
IIRC gtk uses the standard gconf stuff.
Note that PCB (any hid) attempts to load settings from
$prefix/share/pcb/settings, ~/.pcb/settings, and ./pcb.settings.
You can use :SaveSettings() to save them:
SaveSettings()
SaveSettings(local)
Saves settings.
If you pass no arguments, the settings are stored in
@code{$HOME/.pcb/settings}. If you pass the word @code{local} they're
saved in @code{./pcb.settings}.
OK, wart alert. I go into preferences and I expect to see the
current search path there. It's blank. OK, so I put in a search
path and do what the text in the box says to do, and it doesn't
work. Nothing changes.
So I do a :SaveSettings() and uncomment the lib-newlib setting
and suddenly the packages library directory works perfectly and
according to all the hints I found about a ./packages directory.
I'll file bug reports for these.
--
Steve WilliamsThe woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep.
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Re: gEDA-user: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)
[snip] OK, wart alert. I go into preferences and I expect to see the [snip] I'll file bug reports for these. Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. Just a reminder that there are really only three ways to get misfeatures fixed (listed from the most effective to the most expensive): 1) Submit a patch for the misfeature to the appropriate patch tracker. For gEDA/gaf: http://sourceforge.net/tracker/?group_id=161080atid=818428 For PCB: http://sourceforge.net/tracker/?group_id=73743atid=538813 In the last code sprint, the gEDA/gaf developers cleared out almost all of the outstanding patches. Nothing gets my full attention more than a report with a patch attached. Really. 2) File a bug report in the appropriate bug tracker and maybe one of the developers will feel motivated or a desire to fix it at some point. For gEDA/gaf: http://sourceforge.net/tracker/?group_id=161080atid=818426 For PCB: http://sourceforge.net/tracker/?group_id=73743atid=538811 If you do not file a report and just whine on the mailing lists, I can pretty much guarantee it (your post, your whine, and/or maybe even you) will be ignored. Sorry, but developer bandwidth is limited and certainly not infinite. :-( 3) Hire a developer. I'm sure there are several developers here who are willing to fix your favorite pet peeve. But this, of course, won't be cheap, as everybody's free time is extremely valuable. -Ales broken record player -- Ales Hvezda ahvezdaATgeda.seul.org http://geda.seul.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)
Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. We appreciate all the feedback, with the understanding that we can only get to a tiny percentage of it at a time, as there's only a few of us, and we only do this as a hobby. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)
DJ Delorie wrote: Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. We appreciate all the feedback, with the understanding that we can only get to a tiny percentage of it at a time, as there's only a few of us, and we only do this as a hobby. I'll tell you what. I'll pay you to fix your bugs if you pay me to fix mine. Deal? :-) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)
I'll tell you what. I'll pay you to fix your bugs if you pay me to fix mine. Deal? :-) Fixing my own bugs is usually at the top of *my* todo list. But my comment... We appreciate all the feedback, ... applies to more than just bug fixes. We also appreciate feedback about design choices, usability, documentation, future direction, enhancements, etc. We just can't do it all at once :-P ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)
Stephen Williams wrote: DJ Delorie wrote: Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. We appreciate all the feedback, with the understanding that we can only get to a tiny percentage of it at a time, as there's only a few of us, and we only do this as a hobby. I'll tell you what. I'll pay you to fix your bugs if you pay me to fix mine. Deal? :-) now is it a coincidence that this came just a day or two after I filed an icarus bug report ;) Seriously, I also appreciate bug reports and suggestions for improvement as long as people realize that there are relatively few of us working on these tools and it is largely hobby work. I have way more ideas for things I'd like to see in gEDA/gaf and also PCB than I have time to implement. One thing which came up today is I'd love to see a framework for as much automated testing of pcb as possible be put into place. I know Carlos has done some for the drc2 backend for gnetlist. I'd also like to see a more general framework in place for testing parts of gEDA/gaf. If such a system ever gets put into place I could envision it being very useful to have some volunteers take all bug reports and turn them into regression tests that show the failure. I'm just not quite sure how to implement all this though... To give an example of where this could be useful, there was the drc bug that came up today with pads on the corner of a QFN package. So it would be most useful to have some automated tests that probe the limits of the drc checker. Another is that there are some patches on sf right now for allowing more or less arbitrary rotations of objects in pcb. A cursory glance shows that the submitter is thinking of many of right issues in making this actually work. It would be most useful if there were a framework for really systematically testing it though. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
