Re: gEDA-user: pcb program
On Thu, 2007-03-08 at 10:53 +, Seb James wrote: Hello, I have moved on from the schematic capture part of my project to laying out the board. I'm using pcb 20070208. I've noticed a couple of odd things so far. One is that if I create a rats nest, then sometimes, pcb decides to just fill the whole screen with the colour of the rats nest. I can switch off the rats nest layer, but can't get a proper rats nest in this case. Could that have anything to do with the size of my board? I set it to 50 inches by 30 inches so that I could auto disperse all the components to get started - planning to shrink it down later to a more sensible size. This problem is occurring a lot. A screenshot is here: http://www.esfnet.co.uk/pcb_screenshot_after_erase_rats.png This is going to be problematic. I'm already starting to need the rats nest to help me lay the components out. This isn't too much of an issue right now, as I am in the process of manually moving my components to sensible regions of the board. However, I'm seeing some odd behaviour related to selecting components, then being unable to de-select them. Am I seeing any known bugs here? regards, Seb James ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Free Dog gathering tonight in Reading, MA!
On Thu, 8 Mar 2007 07:45:43 -0500 (EST) Stuart Brorson [EMAIL PROTECTED] wrote: -- Free Dog Gathering Announcement [cut] The meeting will be an open and informal working session. Bring your laptop *and* wireless card! Some items on the agenda are: * Google's Summer of Code. I'm interested in being a Student for this program. Do we have a tentative list of projects we would like to get done? -Marc pgpdeJUK8Dgje.pgp Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
This problem is occurring a lot. A screenshot is here: http://www.esfnet.co.uk/pcb_screenshot_after_erase_rats.png This is going to be problematic. I'm already starting to need the rats nest to help me lay the components out. Could you try rebuilding with --with-gui=lesstif? That will help narrow down the location of the bug. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Element for a Molex 71661-2068?
Dan McMahill wrote: Ben Jackson wrote: Is this to meet a pick place requirement that was in the datasheet, or is the Mark arbitrary? The mark is not used by pcb when generating the pick and place file. The center of the part that goes in the XY file is the common centroid of all the pins/pads. What do you think of a different mark for the calculated centroid? A + mark in a different color instead of the x origin mark? I'd use it to sometimes put origin marks near the centroid if it was there. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Several PCB versions on 1 system
ST de Feber wrote: I am still working with an older version of PCB. Is it possible to install and run another one besides it ? grtz ST Sure. See http://www.gedasymbols.org/user/john_griessen/tools/two-pcbs-installed.html John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
Seb James wrote: I'm using pcb 20070208. I've noticed a couple of odd things so far. One is that if I create a rats nest, then sometimes, pcb decides to just fill the whole screen with the colour of the rats nest. This is going to be problematic. I'm already starting to need the rats nest to help me lay the components out. This isn't too much of an issue right now, as I am in the process of manually moving my components to sensible regions of the board. However, I'm seeing some odd behaviour related to selecting components, then being unable to de-select them. Am I seeing any known bugs here? Not known to me. Sounds like your installation is bad. Can you do a make clean, then make configure and see if anything is missing that it wants, then try reinstalling all the dependencies to fix any corrupted installations and check the md5sum against the md5sum of the package you got... --with-lesstif-gui ? default? John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Free Dog gathering tonight in Reading, MA!
Marc -- I'm happy to hear of your interest! Several wish lists have been posted to geda-user. We will also discuss the logistics tonight. My questions for you is: Where are you located geographically? Google's SoC requires every student to have a mentor (basically a supervisor and paper-pusher), and I think that mentor needs to be located in the same place as you. Depending upon where you are located, we might already have a gEDA developer close to you. Alternately, do you have a university professor who would like to mentor you in this program? Stuart On Thu, 8 Mar 2007, Marc Moreau wrote: On Thu, 8 Mar 2007 07:45:43 -0500 (EST) Stuart Brorson [EMAIL PROTECTED] wrote: -- Free Dog Gathering Announcement [cut] The meeting will be an open and informal working session. Bring your laptop *and* wireless card! Some items on the agenda are: * Google's Summer of Code. I'm interested in being a Student for this program. Do we have a tentative list of projects we would like to get done? -Marc ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: What's your way of syncing CPLD design and gschem symbols???
Hi! How do you keep your Xilinx CPLD design in sync w/ your gschem symbol files? I mean, after you have drawn all your schematics and build up the essentials of your CPLD design (esp. the pins must exist :)), when doing the PCB artwork shuffling the CPLD pins can give a really improved PCB layout ... But the problem for me was to keep the symbol in sync w/ the Xilinx Fitter report, so to do the work auto- matically I hacked a Perl script (~6kB) last year, but before adding some required upgrades improvements to the script I just wanted to ask how you do the sync job! For those not familiar with the Xilinx report files I added a example Xilinx pin-out report for a small Xilinx device (sorry for the attachment!) Files with this structure are converted to symbols. BTW: How do split up large ICs in multiple (different) symbols? For example: One symbol for power, clk and JTAG and one symbol for the rest of the design. - cl Pin List Pin Num Pin Type Assigned Signal 1 I/O clko1 2 I/O rst 3 I/O rotenc_b 4 I/O hid_irq 5 I/O/GCK1 clki1 6 I/O/GCK2 clki2 7 I/O/GCK3 pclk 8 I/O PGND 9 I/O PGND 10 GND GND 11 I/O q_in0 12 I/O q_in1 13 I/O PGND 14 I/O tp5 15 TDI TDI 16 TMS TMS 17 TCK TCK 18 I/O tp4 19 I/O tp3 20 I/O tp2 21 VCCINT VCC 22 I/O tp6 23 GND GND 24 I/O rotenc_pb 25 I/O rotenc_a 26 I/O lcd_cp 27 I/O tp7 28 I/O pb_b 29 I/O tp1 30 TDO TDO 31 GND GND 32 VCCIO VCC 33 I/O q_in2 34 I/O tp0 35 I/O clko2 36 I/O pb_c 37 I/O lcd_sd 38 I/O l_q_in 39 I/O/GSR sclk 40 I/O/GTS2 pb_a 41 VCCINT VCC 42 I/O/GTS1 pb_d 43 I/O queue_irq 44 I/O q_in3 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Free Dog gathering tonight in Reading, MA!
On Thu, 8 Mar 2007 10:55:23 -0500 (EST) Stuart Brorson [EMAIL PROTECTED] wrote: Marc -- I'm happy to hear of your interest! Several wish lists have been posted to geda-user. We will also discuss the logistics tonight. My questions for you is: Where are you located geographically? Google's SoC requires every student to have a mentor (basically a supervisor and paper-pusher), and I think that mentor needs to be located in the same place as you. Depending upon where you are located, we might already have a gEDA developer close to you. Alternately, do you have a university professor who would like to mentor you in this program? Stuart I'm in Lethbridge, Alberta, Canada[1]. About 3hrs North of Great Falls, Montana, USA. I'm sure I can scrounge up a prof to supervise me if necessary. [1] http://maps.google.ca/maps?f=qhl=enq=Lethbridge+AB+Canadalayer=ie=UTF8z=12om=1iwloc=addr -Marc pgph1tsMUfnaM.pgp Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: What's your way of syncing CPLD design and gschem symbols???
Hi! How do you keep your Xilinx CPLD design in sync w/ your gschem symbol files? I mean, after you have drawn all your schematics and build up the essentials of your CPLD design (esp. the pins must exist :)), when doing the PCB artwork shuffling the CPLD pins can give a really improved PCB layout ... But the problem for me was to keep the symbol in sync w/ the Xilinx Fitter report, so to do the work auto- matically I hacked a Perl script (~6kB) last year, but before adding some required upgrades improvements to the script I just wanted to ask how you do the sync job! For those not familiar with the Xilinx report files I added a example Xilinx pin-out report for a small Xilinx device (sorry for the attachment!) Files with this structure are converted to symbols. BTW: How do split up large ICs in multiple (different) symbols? For example: One symbol for power, clk and JTAG and one symbol for the rest of the design. I would create the symbols and give them the same refdes ... don't know if this is the correct way to make it work! - cl Pin List Pin Num Pin Type Assigned Signal 1 I/O clko1 2 I/O rst 3 I/O rotenc_b 4 I/O hid_irq 5 I/O/GCK1 clki1 6 I/O/GCK2 clki2 7 I/O/GCK3 pclk 8 I/O PGND 9 I/O PGND 10 GND GND 11 I/O q_in0 12 I/O q_in1 13 I/O PGND 14 I/O tp5 15 TDI TDI 16 TMS TMS 17 TCK TCK 18 I/O tp4 19 I/O tp3 20 I/O tp2 21 VCCINT VCC 22 I/O tp6 23 GND GND 24 I/O rotenc_pb 25 I/O rotenc_a 26 I/O lcd_cp 27 I/O tp7 28 I/O pb_b 29 I/O tp1 30 TDO TDO 31 GND GND 32 VCCIO VCC 33 I/O q_in2 34 I/O tp0 35 I/O clko2 36 I/O pb_c 37 I/O lcd_sd 38 I/O l_q_in 39 I/O/GSR sclk 40 I/O/GTS2 pb_a 41 VCCINT VCC 42 I/O/GTS1 pb_d 43 I/O queue_irq 44 I/O q_in3 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
Hi! Sorry for posting the same message two times! Please, ignore this one and answer only to the second message. - cl ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
On Thu, Mar 08, 2007 at 10:53:25AM +, Seb James wrote: I'm using pcb 20070208. I've noticed a couple of odd things so far. One is that if I create a rats nest, then sometimes, pcb decides to just fill the whole screen with the colour of the rats nest. That happened to me recently as well. I was working on something very simple. I didn't see it on earlier boards. Maybe it's a new bug? -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
BTW: How do split up large ICs in multiple (different) symbols? For example: One symbol for power, clk and JTAG and one symbol for the rest of the design. I would create the symbols and give them the same refdes ... don't know if this is the correct way to make it work! This is the correct (and common) way of dealing with large packages. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
On Mar 8, 2007, at 9:35 AM, Christoph LECHNER wrote: Hi! How do you keep your Xilinx CPLD design in sync w/ your gschem symbol files? I mean, after you have drawn all your schematics and build up the essentials of your CPLD design (esp. the pins must exist :)), when doing the PCB artwork shuffling the CPLD pins can give a really improved PCB layout ... But the problem for me was to keep the symbol in sync w/ the Xilinx Fitter report, so to do the work auto- matically I hacked a Perl script (~6kB) last year, but before adding some required upgrades improvements to the script I just wanted to ask how you do the sync job! For those not familiar with the Xilinx report files I added a example Xilinx pin-out report for a small Xilinx device (sorry for the attachment!) Files with this structure are converted to symbols. It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It gets even more complicated when schematic net names don't match the CPLD design pin names, or when you connect the same schematic net to two FPGA pins (like when doing external clock feedback). This isn't really a problem for small CPLDs but it's a right royal PITA with large FPGAs. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gch2pcb problem
Thanks for your helpful replies. The problem turned out to be with a particular footprint that I had used for my test points (SIL 1). For some reason, it didn't like that footprint, but when I changed it to SIP1, it worked fine! Thanks again, Doug On 3/7/07, Doug Glidden [EMAIL PROTECTED] wrote: Hey, I'm having a problem with the gsch2pcb utility. In trying to convert my schematic (http://mrperson.org/mortimer/schematic.tar.gz), I have found that the m4 process seems to get stuck somewhere along the way. It simply consumes more and more memory until it's finally killed by the kernel for taking up too much memory. Netlist creation works fine, but when it tries to create the PCB file it gets hung up. When I run the gnetlist command indepently with -v, it appears to finish going through all of the components, but then it just hangs after the last one. Anyone ever seen this problem before? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
Andy Peters schrieb: It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It gets even more complicated when schematic net names don't match the CPLD design pin names, or when you connect the same schematic net to two FPGA pins (like when doing external clock feedback). This isn't really a problem for small CPLDs but it's a right royal PITA with large FPGAs. Fortunately I only use XC9572XL CPLDs for most of my designs :) And as you already wrote there's no problem with the net names, as they map 1:1 between the VHDL source and the schematic symbol. - cl ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
Actually, one thing I have dreamed about is incorporating a method into gnetlist to read a .ucf (Xilinx) or .pin (Altera) file to get pin-outs for a large FPGA. Then, you'd just stick a big box (or bunch of boxes) onto your schematic representing the device. The box would have a bunch of named pins, but no pin nos. You'd wire nets to the pins as usual. Then you'd stick somethign like a .include directive onto the same page. The .include directive would point to the .pin file, and be bound somehow to the big FPGA box (maybe by sharing refdes). Then, gnetlist would find the .include, open the corresponding .pin file, and use it to stick the device's pins into teh output netlist. This scheme makes design easy, but is bad for service, since the pins are not annotated onto teh schematic. It would require the service guy to have a set of schematics and printouts of the .pin files to work from. Maybe not such a big deal. FWIW, Steve -- one of the Free Doggers here in Boston -- will talk about his FPGA flow at our gathering tonight. I anticipate he will have some interesting ideas about how to handle the pin issue. Stuart On Thu, 8 Mar 2007, Andy Peters wrote: On Mar 8, 2007, at 9:35 AM, Christoph LECHNER wrote: Hi! How do you keep your Xilinx CPLD design in sync w/ your gschem symbol files? I mean, after you have drawn all your schematics and build up the essentials of your CPLD design (esp. the pins must exist :)), when doing the PCB artwork shuffling the CPLD pins can give a really improved PCB layout ... But the problem for me was to keep the symbol in sync w/ the Xilinx Fitter report, so to do the work auto- matically I hacked a Perl script (~6kB) last year, but before adding some required upgrades improvements to the script I just wanted to ask how you do the sync job! For those not familiar with the Xilinx report files I added a example Xilinx pin-out report for a small Xilinx device (sorry for the attachment!) Files with this structure are converted to symbols. It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It gets even more complicated when schematic net names don't match the CPLD design pin names, or when you connect the same schematic net to two FPGA pins (like when doing external clock feedback). This isn't really a problem for small CPLDs but it's a right royal PITA with large FPGAs. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
On Thu, 2007-03-08 at 10:00 -0800, Ben Jackson wrote: On Thu, Mar 08, 2007 at 10:53:25AM +, Seb James wrote: I'm using pcb 20070208. I've noticed a couple of odd things so far. One is that if I create a rats nest, then sometimes, pcb decides to just fill the whole screen with the colour of the rats nest. That happened to me recently as well. I was working on something very simple. I didn't see it on earlier boards. Maybe it's a new bug? My board is quite busy - about 2800 rats nest lines. I'll have a look at the code. I tried the lesstif gui, but that crashed even when I tried to optimise the rats nest, so no workaround there. It looks to me like it is the pcb code, rather than a problem with my installation - it compiled just fine, no trouble with dependencies. Would there be any interest in maintaining a stable version of pcb - no new features, just bug fixes? Seb ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
Andy Peters schrieb: It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It's true that ripping off everything exept the pairing Pin Names - Pin Numbers from the gschem symbol is a snap compared to building/ updating a symbol from the Fitter report. But how would you make sure that the user of gschem doesn't put an input pin at an reserved location, i.e. a JTAG or PWR pin. The timing issues following from forcing the Xilinx tool to use a user-defined pin-out are non-trivial IMHO, at least for CPLDs. So I guess it would be better regarding timing issues to run Xilinx ISE (or another vendor's tool) first and then go to gschem and create/update the symbol. But nevertheless, I'm looking forward to the new FPGA flow ... The (at the moment) missing link between logic design tools and gschem is a big show-stopper for the gEDA suite, I guess. - cl ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
On Mar 8, 2007, at 2:47 PM, Christoph Lechner wrote: Andy Peters schrieb: It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc). It's true that ripping off everything exept the pairing Pin Names - Pin Numbers from the gschem symbol is a snap compared to building/ updating a symbol from the Fitter report. But how would you make sure that the user of gschem doesn't put an input pin at an reserved location, i.e. a JTAG or PWR pin. I guess we're talking about creating symbols that are CPLD-design specific, so that pin names will change with the design. This is as opposed to creating generic symbols, as noted in my other e-mail in this thread. Generic symbols have the vendor-assigned pin name which includes information about pin type, such as differential pairs, global/regional clocks, config pins, etc. To answer the question. One of two ways: a) Have Yet Another Attribute attached to the symbol pins that would throw up an error if a user attempted to attach a regular signal wire to one of the reserved pins. b) Assume that the gschem user is not an idiot, and is actually looking at the vendor-provided pinout tables while deciding which pins to assign. I just got through doing this last week for a 100- pin VQFP Xilinx FPGA. This might be the simplest approach. I had the schematic and layout windows up and a printout of the pinout diagram, and assigned pins based on how it routed while also noting the pin type. Of course, what would be cool is if after this all completed, it would back-annotate to the .ucf. A guy can dream ... The timing issues following from forcing the Xilinx tool to use a user-defined pin-out are non-trivial IMHO, at least for CPLDs. So I guess it would be better regarding timing issues to run Xilinx ISE (or another vendor's tool) first and then go to gschem and create/update the symbol. For older architectures, it was definitely a requirement that you let the tools assign the pins. But in my recent designs, using CoolRunner CPLDs and Spartan IIE and 3E and Acex FPGAs, I assign pins as needed by the layout, and I've never had problems meeting timing, nor have I had fitting issues. The XC3000 and 95xx parts are dead! The (at the moment) missing link between logic design tools and gschem is a big show-stopper for the gEDA suite, I guess. Commercial tools charge big bucks for this missing link, and it's still not ideal. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???
On Mar 8, 2007, at 5:20 PM, Andy Peters wrote: The timing issues following from forcing the Xilinx tool to use a user-defined pin-out are non-trivial IMHO, at least for CPLDs. So I guess it would be better regarding timing issues to run Xilinx ISE (or another vendor's tool) first and then go to gschem and create/update the symbol. For older architectures, it was definitely a requirement that you let the tools assign the pins. But in my recent designs, using CoolRunner CPLDs and Spartan IIE and 3E and Acex FPGAs, I assign pins as needed by the layout, and I've never had problems meeting timing, nor have I had fitting issues. The XC3000 and 95xx parts are dead! Really? That's interesting. My XC9500s are working just fine. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)
Gabriel Paubert wrote: On Thu, Mar 08, 2007 at 12:39:42PM -0600, John Griessen wrote: OK then, still on the pragmatic tack, why not use silk for a centroid calculation? Find the most extreme corners of (silk OR pins OR pads). What does OR mean in that context? The bounding box? I was thinking of the centerline of the silk layer package outline. I strongly suspect that, for example, pick and place machines want the same centroid for SOT23 with 5 or 6 pins, [jg]Ideally there's a point defined in the part datasheet that is good for picking it up from with a vacuum tip, but in its absence, we can pragmatically calculate a workable point. It maybe different from the exact center of the flat spot on top of a molded package. It will be close though, so picking the part up at its tape and reel centroid will only be off maybe... 5% of the distance across a package... So the first part-placing run will probably place all the parts without a total miss and collision with nearby parts. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
I noticed the problem is occuring during an extremely high zoom in. pcb used to have code to clip the zoomed lines to the screen in order to prevent integer overflow. With the advent of hid that was removed and now zooming in runs the risk of overflow with its unlimited zoom capability. It's very severe with rats because all rats seem to be being drawn, even those that should not be visible at all - thus virtually all of them are overflowing. First recommendation is don't zoom in so close with rats on. Second thing is we should fix the drawing so that it only draws the visible rats. I thought it already did that. Third is it's time to put proper clipping into the hid drawing routines. Interesting polygons are the only structures being properly clipped at the moment. The polygon clipping is slow when the polygons have many thousands of verticies. I'll be improving this situation this spring by (a) reducing a circle's vertice count to 20 from 36 (this is still more than many commercial packages). (b) cacheing the diced polygons used for rendering and (c) Modifying the file format to store the clipped polygon data so that file loading is fast if the clip information is saved. h. TV dinner still cooling? Check out Tonight's Picks on Yahoo! TV. http://tv.yahoo.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pictures of symbols
Is there an easy command line way to generate an image (png or
whatever) from a gschem symbol file? I'd like to catalogue my
symbols for other users and a little picture would be nice.
I've also asked for a command line print this schematic option, and
Ales is working on it (or at least, it's on his to-do list).
If you have an X server available you can do it now:
gschem -o output.ps -s print.scm -p $i
where print.scm can be found at ${prefix}/share/gEDA/scheme
If you don't have an X server, then you can use Xvfb.
If you oppose Xvfb, then then answer is no, you can't print a schematic
from the command line. If it is possible (and I find the time) to add
this functionality to gschlas, then I'll add it.
-Ales
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Re: gEDA-user: scons
[snip] I would argue that this is not true at all. You still need to write portable code. In my mind, the biggest thing autotools bring are a) a consistent way to configure and build and b) some framework to help figure out if required dependencies exist and c) a framework for running tests to deal with differences in OS that you can't avoid by just writing more portable code. And I like the autotools since they also add: d) the functionality to create source distribution tarballs with minimal amounts of pain (make dist) and e) the ability to automatically run various tests while building above mentioned source tarballs (make distcheck). Speaking of which, I am fixing make check in gnetlist to work with make distcheck and now it will be impossible to create a new version of gnetlist without the regression tests passing. -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: freedog pictures
Just a couple of photos from tonight's meeting... http://www.delorie.com/photos/20070308-freedog/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
With the advent of hid that was removed and now zooming in runs the risk of overflow with its unlimited zoom capability. Third is it's time to put proper clipping into the hid drawing routines. I've re-added basic line clipping to both GUIs. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: VMPlayer Image
I'm interested in it. Have you found a host, is it available now? Thanks, Janos Jeff VR wrote: Well, based on the discussion I think there is definitely some interest and it's worth providing. I haven't made huge strides to make the image smaller but compressed it's around 830MB. I've got a couple hosting options I'm looking into with sufficient bandwidth. It should be available in a couple of days. Jeff VR ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: freedog pictures
Yo DJ, The furnace controller board looks nice. Appears that the rj45 is in the wrong spot ?? Also, there is this intriguing board with a db-9, to-220 and some totally elegant T-shaped trace ... what is it? Cool! Phil DJ Delorie wrote: Just a couple of photos from tonight's meeting... http://www.delorie.com/photos/20070308-freedog/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: freedog pictures
On 3/9/07, DJ Delorie [EMAIL PROTECTED] wrote: Just a couple of photos from tonight's meeting... http://www.delorie.com/photos/20070308-freedog/ The thumbnails are too small to see anything, and the large version take long time to load. Could you add a size in-between for us who just want to see what is going on and not measure the width of the PCB-tracks :-) Looks like a nice place, by the way. Kind regards, Svenn ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
