Re: gEDA-user: Page contents browser
On Fri, 2007-04-06 at 00:22 -0400, evan foss wrote: That is so cool. I can't wait to see it with say tabs. Thanks. I just posted another example - with an idea of how buses might be represented. (This takes buses further than their current, graphical existence) What views / information could / should be presented in this browser? (Are there any other types of object we need to see listed? - I know I missed buses - should these come under nets? I might suggest that it also have the ability to search for a given object or value in the tree. Like a filter, or a search. This is possible. What would be really really cool but very hard would be to add a search with connection or relative location to another. I'm not sure exactly what you mean by this, but if it is along the lines of searching for a resistor connected to this object, that could be useful. I'm not sure how the user would specify the search though. I would also add further subcategories because I can see that getting very cluttered. For a large digital design it would be nice to group all the 0.1uF caps. It gets difficult to solve all cases. Grouping by component, e.g. collecting all components using resistor-2.sym, or capacitor-1.sym, could be a start. I'm not sure about automatically grouping things by part number, or value. Grouping could be customisable by plug-in, but it would be much more complex to implement. Is this useful to real users - or just as a test of libgeda hooking? (This will determine how much effort is put into polishing it) I would use it but I would like to be able to turn it off when dealing with subcircuit blocks. I never get that complex. Turn off what- the grouping? Should sub-circuits expand hierarchically in the browser? (My instinct is no for now. I agree that would lead to a real mess and defeat the purpose of having subcircuits. They exist so you can just deal with larger blocks. The 3D-Cad package I occasionally use can expand sub-components. I'm not sure how well it would work with schematics though - and its certainly simpler to code without the expansion. Thanks for the comments, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Hierarchical (nested) buses
Hi, A screen shot showing possible bus-nesting is at: http://www2.eng.cam.ac.uk/~pcjc2/geda/hierarchical_bus_example.png http://www2.eng.cam.ac.uk/~pcjc2/geda/hierarchical_bus_example2.png I've been calling this hierarchical buses, but actually this is more nesting. The hierarchy bit will come when you can have bus pins plumbing these buses straight into a sub-circuit or symbol. The second example shows breaking into a bus by path, such as address_bus/A0. I'm thinking more along the lines of hierarchical naming, than netname naming here: Putting signals A, B and C in a bus called foo, for example, makes the hierarchical net-names: foo/A foo/B foo/C A bus-ripper attached to foo might have an attribute ripout=A, to get A. Now imagine C is actually a bus representing a LVDS pair (say): C/plus C/minus If you wanted, you could rip C/minus from the outer bus foo, directly, with a bus-ripper with ripout=C/minus. This would be an alternative to splitting out bus C with ripout=C, then splitting from that with ripout=minus. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Page contents browser
I love the page content browser! On Apr 6, 2007, at 8:30 AM, Peter Clifton wrote: What views / information could / should be presented in this browser? (Are there any other types of object we need to see listed? - I know I missed buses - should these come under nets? I might suggest that it also have the ability to search for a given object or value in the tree. Like a filter, or a search. This is possible. If you click on an object in the browser can it center the part in the display? Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Page contents browser
On 4/6/07, Steven Michalske [EMAIL PROTECTED] wrote: I love the page content browser! On Apr 6, 2007, at 8:30 AM, Peter Clifton wrote: What views / information could / should be presented in this browser? (Are there any other types of object we need to see listed? - I know I missed buses - should these come under nets? I might suggest that it also have the ability to search for a given object or value in the tree. Like a filter, or a search. This is possible. If you click on an object in the browser can it center the part in the display? Steve The search feature can listen on a socket or fifo. Then pcb can be modified to automatically search, so when I click on a part or net it highlights it in gschem. Regards, Mark [EMAIL PROTECTED] -- Most of the time, for most of the world, no matter how hard people work at it, nothing of any significance happens. -- Weinberg's Law ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Page contents browser
On 4/6/07, Peter Clifton [EMAIL PROTECTED] wrote: On Fri, 2007-04-06 at 00:22 -0400, evan foss wrote: That is so cool. I can't wait to see it with say tabs. Thanks. I just posted another example - with an idea of how buses might be represented. (This takes buses further than their current, graphical existence) Well you could have a sub group with the buses name containing all the buses nets. What views / information could / should be presented in this browser? (Are there any other types of object we need to see listed? - I know I missed buses - should these come under nets? I might suggest that it also have the ability to search for a given object or value in the tree. Like a filter, or a search. This is possible. What would be really really cool but very hard would be to add a search with connection or relative location to another. I'm not sure exactly what you mean by this, but if it is along the lines of searching for a resistor connected to this object, that could be useful. I'm not sure how the user would specify the search though. You know I don't remember what I meant now that I think about it. (it was 1AM when I wrote that. Sorry) I would also add further subcategories because I can see that getting very cluttered. For a large digital design it would be nice to group all the 0.1uF caps. It gets difficult to solve all cases. Grouping by component, e.g. collecting all components using resistor-2.sym, or capacitor-1.sym, could be a start. I'm not sure about automatically grouping things by part number, or value. Grouping could be customisable by plug-in, but it would be much more complex to implement. You are probably correct. Is this useful to real users - or just as a test of libgeda hooking? (This will determine how much effort is put into polishing it) I would use it but I would like to be able to turn it off when dealing with subcircuit blocks. I never get that complex. Turn off what- the grouping? No, the whole window you added. Should sub-circuits expand hierarchically in the browser? (My instinct is no for now. I agree that would lead to a real mess and defeat the purpose of having subcircuits. They exist so you can just deal with larger blocks. The 3D-Cad package I occasionally use can expand sub-components. I'm not sure how well it would work with schematics though - and its certainly simpler to code without the expansion. I suspect that like all other things in software you will write it, use it and realize that some minor things bug you enough to warrant changing them. Thinking a head is never a complete substitute for user feed back. What cad package do you use? Thanks for the comments, Thanks for listening. -- http://www.coe.neu.edu/~efoss/ http://evanfoss.googlepages.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Page contents browser
The 3D-Cad package I occasionally use can expand sub-components. I'm not sure how well it would work with schematics though - and its certainly simpler to code without the expansion. I suspect that like all other things in software you will write it, use it and realize that some minor things bug you enough to warrant changing them. Thinking a head is never a complete substitute for user feed back. What cad package do you use? I use ProEngineer, from PTC. Its quite nice. I'd not expect to see any of these new dialogs in gschem any time soon - they are a development work in progress - I just wanted some feedback on the idea. Thanks, Peter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Efficient Memories
On 5 Apr 2007, at 11:22:18 AM, Stephen Williams wrote: [EMAIL PROTECTED] wrote: I've made a BMP image format creating module for fun. I maintain a 640x480 24-bits per pixel buffer and then write the data out to a file. At first I used a reg array, but came to find that each element of such a structure is expressed in vvp assembly as distinct reg. This made the vvp assembly 32 MB and unrunnable. Now independent of all the above, I'm surprised that 32Meg makes a vvp file unrunnable. I can believe slow to load, but unless you are very memory constrained, it shouldn't be that much slower then in older snapshots before exploded arrays. Try vvp -v foo.vvp to get a bit more detail what might be going on. Here are the results from (1) Large reg (byte) array : reg [7:0] data [0:sizeImage-1]; // sizeImage = 640*480*3 bytes (2) Large reg vector: reg [sizeImage*8-1:0] data; (1) (a) Running iverilog produces in 11.6 seconds the file a.out, which is 35 MB: Using language generation: IEEE1364-2001+Extensions,specify,xtypes PARSING INPUT LOCATING TOP-LEVEL MODULES test ... done, 0.02 seconds. ELABORATING DESIGN ... done, 0.68 seconds. RUNNING FUNCTORS -F cprop ... -F nodangle ... ... 1 iterations deleted 0 dangling signals and 0 events. (count=0) ... done, 0.01 seconds. CODE GENERATION -t dll ... invoking target_design ... done, 11.6 seconds. STATISTICS lex_string: add_count=44 hit_count=123 (1) (b) Running vvp -v a.out takes 1.22 hours to compile and 15.3 seconds to run (fill all locations and write file). Compiling VVP ... Compile cleanup... ... Linking ... Removing symbol tables ...0 functors 0 table 0 bufif 0 resolv 0 variable ... 901 opcodes (16384 bytes) ... 921630 nets ...0 memories ...5 scopes ... 4404.64 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Running ... ... 15.3602 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Event counts: (event pool = 0) 20007 thread schedule events 0 propagation events 0 assign events 0 other events (2) (a) Running iverilog produces in 0.03 seconds the file a.out, which is 32 KB: Using language generation: IEEE1364-2001+Extensions,specify,xtypes PARSING INPUT LOCATING TOP-LEVEL MODULES test ... done, 0.01 seconds. ELABORATING DESIGN ... done, 0.01 seconds. RUNNING FUNCTORS -F cprop ... -F nodangle ... ... 1 iterations deleted 0 dangling signals and 0 events. (count=0) ... done, 0 seconds. CODE GENERATION -t dll ... invoking target_design ... done, 0.03 seconds. STATISTICS lex_string: add_count=47 hit_count=123 (1) (b) Running vvp -v a.out takes 0.02812 seconds to compile and 11.7084 seconds seconds to run (fill all locations and write file). Compiling VVP ... Compile cleanup... ... Linking ... Removing symbol tables ...0 functors 0 table 0 bufif 0 resolv 0 variable ... 907 opcodes (16384 bytes) ... 33 nets ...0 memories ...5 scopes ... 0.02812 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Running ... ... 11.7084 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Event counts: (event pool = 0) 20007 thread schedule events 0 propagation events 0 assign events 0 other events In other words, exploding the arrays has a significantly bad impact on performance. As comparison: import time time1=time.time(); a = range(1024*768*3*8); print time.time() - time1 gives: 1.99313998222 seconds and: time1 = time.time() for i in xrange(1024*768*3*8): a[i] = 0; print time.time() - time1 gives: 13.961877107620239 seconds. Why not go ahead and compile vvp assembly? What makes python faster? Thanks for your time. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Slots and tragesym
Could someone please explain how to use slot= slotdef= in tragesym for symbols with multiple identical components in a symbol/chip? Thanks super in advance, Craig Niederberger ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Efficient Memories
On Fri, Apr 06, 2007 at 05:57:32PM -0400, [EMAIL PROTECTED] wrote: Here are the results from (1) Large reg (byte) array : reg [7:0] data [0:sizeImage-1];// sizeImage = 640*480*3 bytes (2) Large reg vector: reg [sizeImage*8-1:0] data; In the spirit of, the implementor must cheat, but not get caught, it sounds like iverilog should detect the absence of continuous assignments and rever to an addressed model for the memory. A less general solution would be to infer addressable RAMs from templates as other synthesis tools do. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slots and tragesym
Craig, from the 7400-1.sym numslots=4 slotdef=1:1,2,3 slotdef=2:4,5,6 slotdef=3:9,10,8 slotdef=4:12,13,11 slot=1 This tells us that this symbol has 4 slots. The pins for slot 1 are 1, 2 and 3 and for slot 2 they are 4, 5 and 6. The graphical pins themselves have an attribute pinseq=3. This tells us that that particular pin has its pin number replaced with the third pin number in the desired slotdef. for example, slotdef=4:12,13,11 the third pin is pin 11 When you select the symbol after it is dropped into a schematic you may set at the schematic level a slot attribute. For example slot=2. Best Wishes, Steve Meier Craig Niederberger wrote: Could someone please explain how to use slot= slotdef= in tragesym for symbols with multiple identical components in a symbol/chip? Thanks super in advance, Craig Niederberger ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slots and tragesym
Thanks super, Steve. I'm dense. I can't seem to get tragesym to work for multiple slots. Here's a snippet... numslots=4 #slot=1 #slotdef=1:1,2,3 #slotdef=2:7,6,5 #slotdef=3:8,9,10 #slotdef=4:14,13,12 #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, i/o, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the Vcc or GND name # label represents the pinlabel. # negation lines can be added with _Q_ # if you want to add a _ or \ use \_ and \\ as escape sequences #- #pinnr seq typestyle posit. net label #- 11outlinerout 21inlinelin- 31inlinelin+ 4pwrlinetV 52inlinelin+ 62inlinelin- 72outlinerout 83outlinerout 93inlinelin- 103inlinelin+ 11pwrnonebGNDGND 124inlinelin+ 134inlinelin- 144outlinerout What I am doing wrong? Many thanks, Craig On 4/6/07, Steve Meier [EMAIL PROTECTED] wrote: Craig, from the 7400-1.sym numslots=4 slotdef=1:1,2,3 slotdef=2:4,5,6 slotdef=3:9,10,8 slotdef=4:12,13,11 slot=1 This tells us that this symbol has 4 slots. The pins for slot 1 are 1, 2 and 3 and for slot 2 they are 4, 5 and 6. The graphical pins themselves have an attribute pinseq=3. This tells us that that particular pin has its pin number replaced with the third pin number in the desired slotdef. for example, slotdef=4:12,13,11 the third pin is pin 11 When you select the symbol after it is dropped into a schematic you may set at the schematic level a slot attribute. For example slot=2. Best Wishes, Steve Meier Craig Niederberger wrote: Could someone please explain how to use slot= slotdef= in tragesym for symbols with multiple identical components in a symbol/chip? Thanks super in advance, Craig Niederberger ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slots and tragesym
The comment markers in front of your slotdefs slot=1 slotdef=1:1,2,3 slotdef=2:7,6,5 slotdef=3:8,9,10 slotdef=4:14,13,12 On Apr 6, 2007, at 7:57 PM, Craig Niederberger wrote: Thanks super, Steve. I'm dense. I can't seem to get tragesym to work for multiple slots. Here's a snippet... numslots=4 #slot=1 #slotdef=1:1,2,3 #slotdef=2:7,6,5 #slotdef=3:8,9,10 #slotdef=4:14,13,12 #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, i/o, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the Vcc or GND name # label represents the pinlabel. # negation lines can be added with _Q_ # if you want to add a _ or \ use \_ and \\ as escape sequences #- #pinnr seq typestyle posit. net label #- 11outlinerout 21inlinelin- 31inlinelin+ 4pwrlinetV 52inlinelin+ 62inlinelin- 72outlinerout 83outlinerout 93inlinelin- 103inlinelin+ 11pwrnonebGNDGND 124inlinelin+ 134inlinelin- 144outlinerout What I am doing wrong? Many thanks, Craig On 4/6/07, Steve Meier [EMAIL PROTECTED] wrote: Craig, from the 7400-1.sym numslots=4 slotdef=1:1,2,3 slotdef=2:4,5,6 slotdef=3:9,10,8 slotdef=4:12,13,11 slot=1 This tells us that this symbol has 4 slots. The pins for slot 1 are 1, 2 and 3 and for slot 2 they are 4, 5 and 6. The graphical pins themselves have an attribute pinseq=3. This tells us that that particular pin has its pin number replaced with the third pin number in the desired slotdef. for example, slotdef=4:12,13,11 the third pin is pin 11 When you select the symbol after it is dropped into a schematic you may set at the schematic level a slot attribute. For example slot=2. Best Wishes, Steve Meier Craig Niederberger wrote: Could someone please explain how to use slot= slotdef= in tragesym for symbols with multiple identical components in a symbol/chip? Thanks super in advance, Craig Niederberger -- -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slots and tragesym
In the immortal words of Homer Simpson, Doh. Thanks super, Steven and Steve. For those who might encounter this on a search for tragesym and slot (as I), here's the correct snippet--N.B. seq refers to a repeated pin, not a cluster of pins, and none out all of the invisible pins: numslots=4 slot=1 slotdef=1:1,2,3 slotdef=2:7,6,5 slotdef=3:8,9,10 slotdef=4:14,13,12 [pins] #... #- #pinnr seq typestyle posit. net label #- 11outlinerout 22inlinelin- 33inlinelin+ 44pwrlinetV 53innonelin+ 62innonelin- 71outnonerout 81outnonerout 92innonelin- 103innonelin+ 115pwrnonebGNDGND 123innonelin+ 132innonelin- 141outnonerout CN On 4/6/07, Steven Michalske [EMAIL PROTECTED] wrote: The comment markers in front of your slotdefs slot=1 slotdef=1:1,2,3 slotdef=2:7,6,5 slotdef=3:8,9,10 slotdef=4:14,13,12 On Apr 6, 2007, at 7:57 PM, Craig Niederberger wrote: Thanks super, Steve. I'm dense. I can't seem to get tragesym to work for multiple slots. Here's a snippet... numslots=4 #slot=1 #slotdef=1:1,2,3 #slotdef=2:7,6,5 #slotdef=3:8,9,10 #slotdef=4:14,13,12 #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, i/o, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the Vcc or GND name # label represents the pinlabel. # negation lines can be added with _Q_ # if you want to add a _ or \ use \_ and \\ as escape sequences #- #pinnr seq typestyle posit. net label #- 11outlinerout 21inlinelin- 31inlinelin+ 4pwrlinetV 52inlinelin+ 62inlinelin- 72outlinerout 83outlinerout 93inlinelin- 103inlinelin+ 11pwrnonebGNDGND 124inlinelin+ 134inlinelin- 144outlinerout What I am doing wrong? Many thanks, Craig On 4/6/07, Steve Meier [EMAIL PROTECTED] wrote: Craig, from the 7400-1.sym numslots=4 slotdef=1:1,2,3 slotdef=2:4,5,6 slotdef=3:9,10,8 slotdef=4:12,13,11 slot=1 This tells us that this symbol has 4 slots. The pins for slot 1 are 1, 2 and 3 and for slot 2 they are 4, 5 and 6. The graphical pins themselves have an attribute pinseq=3. This tells us that that particular pin has its pin number replaced with the third pin number in the desired slotdef. for example, slotdef=4:12,13,11 the third pin is pin 11 When you select the symbol after it is dropped into a schematic you may set at the schematic level a slot attribute. For example slot=2. Best Wishes, Steve Meier Craig Niederberger wrote: Could someone please explain how to use slot= slotdef= in tragesym for symbols with multiple identical components in a symbol/chip? Thanks super in advance, Craig Niederberger ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TwoStageAmp example
On Thursday 05 April 2007 10:19, John Doty wrote: It really needs to be built into the device models. Much of the point of a SPICE NOISE analysis is to be sure you haven't left out an important noise source in your pencil and paper noise analysis. Verilog-AMS supports that, so eventually gnucap will have it. Whether it is built into any particular model depends on whoever wrote the model. Gnucap models need not be specific to gnucap. There will be several mechanisms for using different kinds of models, including spice C models and Verilog-AMS. Eventually there will be more depending on demand and resources. They are all plugins, and all look the same to the core. Well ... they will have wrappers that make them all look the same to the core. I expect that Verilog-AMS models will be more efficient than Spice models. Most likely they will have identical user interfaces. Most new models are coming out in Verilog-AMS, not Spice, particularly the detailed ones with noise. Of course, explicit noisy sources could be handy too, for noisy inputs, power supplies, etc. It's really the same, because it is defined in Verilog-AMS. I was describing what you can do in gnucap now. In the tricky cases it's not a simple matter of display. The simulator output needs a fair amount of post processing. Tools like AWK, C, and Mathematica come in handy, here. There is a real need for a good postprocessor. I expect to see some improvements to the ones we have soon, but it will be a while longer until we see a real postprocessor program. Ideally, the whole thing would be written in an interpreted language that lets you bring out the interpreter so you can write your own manipulations. Python, Ruby, TCL-TK, R .. are all possibilities. Probably the best choice of these is Python, because there are libraries available for most of what is needed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slots and tragesym
And the last entry for those who might be searching tragesym and slot, *only include one* of the multiple components, eg numslots=4 slot=1 slotdef=1:1,2,3 slotdef=2:7,6,5 slotdef=3:8,9,10 slotdef=4:14,13,12 [pins] # ... #- #pinnr seq typestyle posit. net label #- 11outlinerout 22inlinelin- 33inlinelin+ 44pwrlinetV 115pwrnonebGNDGND CN On 4/6/07, Craig Niederberger [EMAIL PROTECTED] wrote: In the immortal words of Homer Simpson, Doh. Thanks super, Steven and Steve. For those who might encounter this on a search for tragesym and slot (as I), here's the correct snippet--N.B. seq refers to a repeated pin, not a cluster of pins, and none out all of the invisible pins: numslots=4 slot=1 slotdef=1:1,2,3 slotdef=2:7,6,5 slotdef=3:8,9,10 slotdef=4:14,13,12 [pins] #... #- #pinnr seq typestyle posit. net label #- 11outlinerout 22inlinelin- 33inlinelin+ 44pwrlinetV 53innonelin+ 62innonelin- 71outnonerout 81outnonerout 92innonelin- 103innonelin+ 115pwrnonebGNDGND 123innonelin+ 132innonelin- 141outnonerout CN On 4/6/07, Steven Michalske [EMAIL PROTECTED] wrote: The comment markers in front of your slotdefs slot=1 slotdef=1:1,2,3 slotdef=2:7,6,5 slotdef=3:8,9,10 slotdef=4:14,13,12 On Apr 6, 2007, at 7:57 PM, Craig Niederberger wrote: Thanks super, Steve. I'm dense. I can't seem to get tragesym to work for multiple slots. Here's a snippet... numslots=4 #slot=1 #slotdef=1:1,2,3 #slotdef=2:7,6,5 #slotdef=3:8,9,10 #slotdef=4:14,13,12 #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, i/o, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the Vcc or GND name # label represents the pinlabel. # negation lines can be added with _Q_ # if you want to add a _ or \ use \_ and \\ as escape sequences #- #pinnr seq typestyle posit. net label #- 11outlinerout 21inlinelin- 31inlinelin+ 4pwrlinetV 52inlinelin+ 62inlinelin- 72outlinerout 83outlinerout 93inlinelin- 103inlinelin+ 11pwrnonebGNDGND 124inlinelin+ 134inlinelin- 144outlinerout What I am doing wrong? Many thanks, Craig On 4/6/07, Steve Meier [EMAIL PROTECTED] wrote: Craig, from the 7400-1.sym numslots=4 slotdef=1:1,2,3 slotdef=2:4,5,6 slotdef=3:9,10,8 slotdef=4:12,13,11 slot=1 This tells us that this symbol has 4 slots. The pins for slot 1 are 1, 2 and 3 and for slot 2 they are 4, 5 and 6. The graphical pins themselves have an attribute pinseq=3. This tells us that that particular pin has its pin number replaced with the third pin number in the desired slotdef. for example, slotdef=4:12,13,11 the third pin is pin 11 When you select the symbol after it is dropped into a schematic you may set at the schematic level a slot attribute. For example slot=2. Best Wishes, Steve Meier Craig Niederberger wrote: Could someone please explain how to use slot= slotdef= in tragesym for symbols with multiple identical components in a symbol/chip? Thanks super in advance, Craig Niederberger ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org
