Re: gEDA-user: PCB and AM_MAINTAINER_MODE
On Wednesday 18 February 2009 01:37:13 DJ Delorie wrote: Pleas read README.cvs I still think that removing AM_MAINTAINER_MODE from gaf's autoconf was a very good decision. Peter -- Peter Brett Electronic Systems Engineer Integral Informatics Ltd signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
Hello, thanks for looking into it! I'll try the newest git head later today. Please note that I have constructed some tast cases too and attached them to the bug tickets. On Tue, 17 Feb 2009 20:02:42 + Peter Clifton pc...@cam.ac.uk wrote: On Mon, 2009-02-16 at 14:58 +0100, Denis Grelich wrote: Sorry, forgot to actually attach the screenshot and the example ;) That's pretty broken looking.. I think the first hint of trouble is exemplified by PCB's failure to clear this the 360 degree arc from the polygon. I've distilled a test-case from your example (attached). I wonder if (as a workaround) you'd get better results from two half-arcs, rather than one arc which touches its-self. When I get chance I'll try to fix the case for the self-intersecting arc. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Wed, 2009-02-18 at 09:32 +0100, Denis Grelich wrote: Hello, thanks for looking into it! I'll try the newest git head later today. Please note that I have constructed some tast cases too and attached them to the bug tickets. Ok, thanks.. I've taken a look. Some are fixed, some remain. I'm noticing really crappy grid-snap behaviour in the PCB+GL branch at the moment, especially on your test-case design. Did you test if any of that grief happen in the non PCB+GL code? The PCB+GL branch also contains some grid-snap improvements which weren't perfect, so never yet got pushed to git HEAD. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Wed, 2009-02-18 at 09:32 +0100, Denis Grelich wrote: Hello, thanks for looking into it! I'll try the newest git head later today. Please note that I have constructed some tast cases too and attached them to the bug tickets. Btw.. how did the fullpoly flag get set on some polygons in your design? That flag breaks connectivity checking, and makes the PCB+GL branch hit slow rendering paths. (Could speed it up, just haven't yet). There is a GUI option Settings-New polygons are full ones, but it doesn't seem to be hooked up - certainly not on the PCB+GL build, and I don't remember disabling it. I've attached a small example of how the connectivity scanning is broken with fullpoly. Press f to highlight connections from each via in turn, and see the damage. Also, note that PCB ignores the resurrected piece of the polygon in many cases, such as pressing f on it. The code I was writing to allow full polygon pours is intended to allow the equivalent of fullpoly whilst allowing proper connectivity scanning. You'd just have to switch off island removal, and you get the same behaviour. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) full_poly_connectivity.pcb Description: application/pcb-layout ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
I have set the fullpoly flag manually, which wasn't a big deal since I had to do a lot of manual work in the file (especially when it comes to arcs -- I was even thinking about writing a patch to be able to work with arcs sensibly with the GUI, maybe I'll still look into it even though the board is finished.) Without fullpoly, I wouldn't get the plane filled with GND, but only some small isle. On Wed, 18 Feb 2009 12:55:32 + Peter Clifton pc...@cam.ac.uk wrote: On Wed, 2009-02-18 at 09:32 +0100, Denis Grelich wrote: Hello, thanks for looking into it! I'll try the newest git head later today. Please note that I have constructed some tast cases too and attached them to the bug tickets. Btw.. how did the fullpoly flag get set on some polygons in your design? That flag breaks connectivity checking, and makes the PCB+GL branch hit slow rendering paths. (Could speed it up, just haven't yet). There is a GUI option Settings-New polygons are full ones, but it doesn't seem to be hooked up - certainly not on the PCB+GL build, and I don't remember disabling it. I've attached a small example of how the connectivity scanning is broken with fullpoly. Press f to highlight connections from each via in turn, and see the damage. Also, note that PCB ignores the resurrected piece of the polygon in many cases, such as pressing f on it. The code I was writing to allow full polygon pours is intended to allow the equivalent of fullpoly whilst allowing proper connectivity scanning. You'd just have to switch off island removal, and you get the same behaviour. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Wed, 18 Feb 2009 12:50:11 + Peter Clifton pc...@cam.ac.uk wrote: I'm noticing really crappy grid-snap behaviour in the PCB+GL branch at the moment, especially on your test-case design. Did you test if any of that grief happen in the non PCB+GL code? The PCB+GL branch also contains some grid-snap improvements which weren't perfect, so never yet got pushed to git HEAD. Yes, I worked with both an older pcb version and the PCB+GL branch, and they both seemed to show pretty much the same behaviour. I didn't really notice the grid-snap deficiencies, since I was working without grid snapping (or with a grid of 0.01mm) most of the time anyway, because of the many arcs. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Wed, 2009-02-18 at 15:18 +0100, Denis Grelich wrote: I have set the fullpoly flag manually, which wasn't a big deal since I had to do a lot of manual work in the file (especially when it comes to arcs -- I was even thinking about writing a patch to be able to work with arcs sensibly with the GUI, maybe I'll still look into it even though the board is finished.) Without fullpoly, I wouldn't get the plane filled with GND, but only some small isle. Seemed to work for me just now when I tried it. You just loose some islanded sections. The code is supposed to keep the largest piece of the polygon. Sometimes this works fine. other times.. you want to re-connect the islanded pieces, so it becomes a pain to have to redraw them. You'll just have to beware of the connectivity checking failures with fullpoly for now. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Another distilled polygon test-case [WAS: Re: GL pcb bugs and a question re the log/library window, gerber outline output]
Changing the clearance on this line breaks the polygon where the thermal'd via cuts the contour. Uses fullpoly on the polygon to show the broken fragment(s) which otherwise don't get rendered. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another distilled polygon test-case [WAS: Re: GL pcb bugs and a question re the log/library window, gerber outline output]
On Wed, 2009-02-18 at 15:05 +, Peter Clifton wrote: Changing the clearance on this line breaks the polygon where the thermal'd via cuts the contour. Uses fullpoly on the polygon to show the broken fragment(s) which otherwise don't get rendered. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) change_line_breaks_poly.pcb Description: application/pcb-layout ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Wed, 18 Feb 2009 00:21:08 + Peter Clifton pc...@cam.ac.uk wrote: On Tue, 2009-02-17 at 11:29 +0100, Denis Grelich wrote: On Mon, 16 Feb 2009 12:34:15 -0800 Ben Jackson b...@ben.com wrote: On Mon, Feb 16, 2009 at 02:56:44PM +0100, Denis Grelich wrote: First there's a problem with polygon clearance. I think that might be a GL display bug. There was a thread about that recently. Try exporting your layout to PostScript and view that (you can convert with ps2pdf and use acroread if you want). If the planes look fine there, they will look fine in the gerbers. I've tried it with an older version of PCB (20081128) and there I have pretty much the same behaviour. The exported gerber files yield those artifacts as well, so I guess it's an issue with the polygon clearance code, not just a rendering issue. Try again now.(with git HEAD, or the GL branch if you re-fetch it) I've just commited what I believe to be a fix for the problem. The artifacts seem to be gone, the crashes too. I still get the disappearing polygon, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Wed, 2009-02-18 at 21:11 +0100, Denis Grelich wrote: On Wed, 18 Feb 2009 00:21:08 + The artifacts seem to be gone, the crashes too. I still get the disappearing polygon, though. Yes, that is slightly odd. See the last test-case I posted for a simpler example of the breakage. I've not had chance to figure out what is wrong though. Possibly something in the contour intersection routine*. * /me makes locating that bug sound far simpler than it is likely to be. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Digilent USB-JTAG and Lattice
I have been using the Digilent USB-JTAG cable to program Xilinx devices and now am working with some Lattice CPLDs in a new project. Does anyone know of some JTAG programming software that will recognize the Digilent USB-JTAG cable and allow me to program Lattice parts? Eric Winsor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Digilent USB-JTAG and Lattice
On Wed, Feb 18, 2009 at 5:59 PM, Eric Winsor e...@winsor.us wrote: I have been using the Digilent USB-JTAG cable to program Xilinx devices and now am working with some Lattice CPLDs in a new project. Does anyone know of some JTAG programming software that will recognize the Digilent USB-JTAG cable and allow me to program Lattice parts? Ask the UR JTAG people http://urjtag.org/ Eric Winsor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- http://www.coe.neu.edu/~efoss/ http://evanfoss.googlepages.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Digilent USB-JTAG and Lattice
Eric Winsor wrote: I have been using the Digilent USB-JTAG cable to program Xilinx devices and now am working with some Lattice CPLDs in a new project. Does anyone know of some JTAG programming software that will recognize the Digilent USB-JTAG cable and allow me to program Lattice parts? AFIK, no software in the world supports the Digilent USB-JTAG cable except for Digilent's Adept suite. Digilent doesn't make their protocols available for others to use, and since this cable uses a variation of the Cypress FX2 8051+USB 2.0 interface it's difficult to reverse engineer. A few years back, there was one fellow on comp.sys.fpga who claimed to have an open-source tool that would talk to the Digilent cable, but after trying it I wasn't able to get it to work. Subsequent attempts to contact the original author were unsuccessful. Maybe you would have better luck - find it here: http://sourceforge.net/projects/xilprg I believe that Digilent's Adept suite can 'play' SVF files, so if your Lattice tools can generate a JTAG SVF file, you may be able to load that into Adept. FWIW, Xilinx's Impact can be do this, so it's not unheard of. Let me know how it goes... Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
