gEDA-user: PCB: simple FreeType fonts implementation
This subject has been discussed many times on this list. Recently, I tested ideas from http://archives.seul.org/geda/user/Jan-2009/msg00869.html and this resulted in a patchset 2684726 at https://sourceforge.net/tracker/index.php?func=detailaid=2684726group_id=73743atid=538813 Of course, this is of very limited use, but somebody may be interested. General features First patches introduce multiple fonts per board; every text has a pointer to it's font; the font for a new text is selected in the text input window; I also added a field for the font scale. Then different text layouts are introduced. Texts may be vertical or horizontal; the layout also may be `reverse': for horizontal layouts this means right-to-left; for vertical --- donwside-up. (http://ineiev.users.sourceforge.net/pcb/graph/layout.png) (the figure shows an optimistic case for a horizontal font turned vertically: in general, the letters are not adjusted horizontally). A new font type added, based on FreeType2 library. TTF and Type1 fonts seem to work, PCF don't (most probably, I load them incorrectly). The glyphs are loaded and rendered in DrawTextLowLevel() function; perhaps some caching could improve performance, but this is a _simple_ implementation. Kerning should work for horizontal layouts (http://ineiev.users.sourceforge.net/pcb/graph/kerning.png) FreeType does not support kerning for vertical layouts, and actually I have no idea if the implementation may be used for such scripts. Glyphs rendering At first I rendered them with `vertical' lines, like this: (http://ineiev.users.sourceforge.net/pcb/graph/fill.png) This was the most simple way, though small characters become unreadable too soon. Then I learnt FreeType glyphs had outline structures and drew them with lines: (http://ineiev.users.sourceforge.net/pcb/graph/outline.png) The next way was to join outlines with fills: (http://ineiev.users.sourceforge.net/pcb/graph/full.png) The `vertical' lines don't fill the outlines very good, some small spaces remain; probably, something should be adjusted. At last, I tried to do it with polygons: (http://ineiev.users.sourceforge.net/pcb/graph/poly.png) I don't do it clearly, because some contours need to be added, other subtracted, and it is not evident to me how to do it in real time. Besides that, I think lines look more realistic, because the polygons are not restricted with design rules; the lines are. Cyrillic texts The latest example demostrated a Cyrillic font; the implementation matches this script quite well; some fonts lacked `ж' glyph; no other inconveniences. Polytonic Greek (http://ineiev.users.sourceforge.net/pcb/graph/grdjvu.png) There may be some problems: first, the implementation does not support combining characters, so there may be difficulties when entering accented letters; I entered them via Gnome character map application. Also, once I could not pull `μ' glyph from a font, though it was present; probably something wrong with that font mapping. Devanagari (http://ineiev.users.sourceforge.net/pcb/graph/devanagari.png) The consonants are not joined into ligatures (this was expected); however, it puts viramam where it makes sence; it even adds vowels (much better than I expected). `i short' is put in a wrong place: I actually wrote an incorrect sequence to force it hang where it should, e.g. -ko(i)va- instead of -kovi-. Afro-Asiatic scripts (http://ineiev.users.sourceforge.net/pcb/graph/ar.png) I really can't tell how usable it is for tfel-ot-thgir scripts; I reproduced a word, I don't know how correctly. I checked reverse checkbox in the text input window and dragged the letters from Gnome character map. Some letters take several places in the map; my font accepted one of them and rejected the rest. Some notes on usage To load a font, use LoadFreetype action, like this: LoadFreetype(some_font.pfb); it will be added to the font list of the current board. Every font in the list has use counter, it will be embedded when saving the board if some texts use it. Different rendering options (outlines, fill, polygons) are switched with defines in src/ft2font.c Final remarks Once I thought whether it would be better to use pango instead of freetype; it would solve problems with combining character, but it has the next disadvantages: first, it is a stronger dependence; second, it renders to bitmaps only, whereas having vectored outlines is important when the characters grow small. As I mentioned, these patches can hardly be used in practice, because I had to change PCB file format, so mainstream PCB won't read the files saved by the patched program. Regards, Ineiev ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: simple FreeType fonts implementation
On Thu, 2009-03-12 at 12:32 +0300, Ineiev wrote: Final remarks Once I thought whether it would be better to use pango instead of freetype; I was just thinking this as you were talking about scripts. it would solve problems with combining character, Don't even bother trying to re-invent all the I18N stuff pango implements. It is _really_ complex, and I don't want to see PCB attempt ot repeat it. We simply don't have the base of expertise to maintain it, or get every corner case right. but it has the next disadvantages: first, it is a stronger dependence; Personally, I don't care. It isn't so bad, and modern linux desktops will have it. Anything using GTK anywhere will have it. (And we can make it work with Lesstif too, so there is no problem there). second, it renders to bitmaps only, whereas having vectored outlines is important when the characters grow small. Untrue. You have to supply a function for drawing glyphs, or drawing trapezoids and rectangles IIRC. Pango does work with vector outlines, you just need an appropriate back-end. As I mentioned, these patches can hardly be used in practice, because I had to change PCB file format, so mainstream PCB won't read the files saved by the patched program. Still, an impressive start, and we can only move forwards with features like this when people start experimenting with these things. I expect we could start using Freetype2 / Pango without changing the file-format, just you'd not be able to adjust any of the font / layout settings from the defaults. For backwards compat with fonts.. I know of people who've written custom Freetype backends which allow them to feed legacy font data into Freetype. (Alternatively we could convert the usual PCB font into a format it understands). If you want me to help with polygons, let me know. Depending on how you're creating them, you could add new contours for the holes directly in the linked list (might need to set a direction flag, or ensure the contour is in the right order). You could create a contour with the higher level routines for including points, then create a contour and subtract it from the main outline. This should be more robust. A lower level, direct to data-structure approach would probably be faster (avoiding the boolean routines), but only works if the rules of Freetype's polygon contours match any invariants we expect of them, such as non-intersecting contours. I agree the lined versions have a certain charm to them, and that we'd need to be able to enforce DRC rules for min width on polygon versions. I can't think how to do that immediately. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: datasheet
Hello, Sorry, I am looking for the datasheet of an IC ECG9099. Because I did not find it on the internet, I am just asking if you have any idea where I could find it !! Thank -- --- == Patrick DUPRÉ | | Department of Chemistry| |Phone: (44)-(0)-1904-434384 The University of York | |Fax: (44)-(0)-1904-432516 Heslington | | York YO10 5DD United Kingdom | |email: pd...@york.ac.uk == ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cannot find gdk-pixbuf, building gaf from source
On Mon, Mar 9, 2009 at 5:08 PM, Shakthi Kannan wrote: The package to be installed is gtk2-devel on Fedora 10. It provides gdk-pixbuf-2.0.pc. FYI: to ease your life, create an rpm from the source tarball based on fedora's spec. # yum install yum-utils @fedora-packager # yumdownloader --source pcb --enablerepo=rawhide as simple user $ rpmdev-setuptree $ rpm -ivh pcb-XYZ.rpm $ kate rpmbuild/SPECS/pcb.spec update the %source tag with respect to your tarball archive. rpmbuild -ba rpmbuild/SPECS/pcb.spec if you need development packages in order to build pcb, rpmbuild will tell you. Afterwards you will have a nice little rpm for pcb. If there is something wrong with the pcb's SPEC file, file a bug. I'll get it fixed on rawhide. cheers, Chitlesh PS: I'm looking for co-maintainer of pcb or other FEL apps :) I have more than 60 packages under my name. Chitlesh ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: datasheet
NTE/ECG/Philips sells chips that are pin for pin replacements for a lot of things. The thing is that the part number they use frequently don't match what anyone else uses. I looked up your part number in a reference book from 1996 and got this Dual M/S J-K Flip-Flop 5MHz I have the pin out too if you need it. I know that it is DTL but you might be able to replace it with a TTL chip from the 7400 series. My reference only goes 1 way from everyone else stuff to ECG. Honestly until I got this message I was going to recycle the stupid book. I guess I have too keep it now. I have the pinout if you want it but not the data sheet. What I guess we should be asking is could you use a TTL chip say 7400 series as a replacement or would the fan in/out be an issue. On Thu, Mar 12, 2009 at 2:25 PM, Patrick Dupre pd...@york.ac.uk wrote: Hello, Sorry, I am looking for the datasheet of an IC ECG9099. Because I did not find it on the internet, I am just asking if you have any idea where I could find it !! Thank -- --- == Patrick DUPRÉ | | Department of Chemistry | | Phone: (44)-(0)-1904-434384 The University of York | | Fax: (44)-(0)-1904-432516 Heslington | | York YO10 5DD United Kingdom | | email: pd...@york.ac.uk == ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- http://www.coe.neu.edu/~efoss/ http://evanfoss.googlepages.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: datasheet
I looked up the NTE number NTE9099 and the best I could find was a scanned in copy of a later/earlier version of my book. http://www.datasheetarchive.com/pdf-datasheets/Datasheets-115/DSAP001035.pdf The version in my book has an actual schematic of the flip/flops laid out in the chip which looks prettier in my opinion. On Thu, Mar 12, 2009 at 3:27 PM, evan foss evanf...@gmail.com wrote: NTE/ECG/Philips sells chips that are pin for pin replacements for a lot of things. The thing is that the part number they use frequently don't match what anyone else uses. I looked up your part number in a reference book from 1996 and got this Dual M/S J-K Flip-Flop 5MHz I have the pin out too if you need it. I know that it is DTL but you might be able to replace it with a TTL chip from the 7400 series. My reference only goes 1 way from everyone else stuff to ECG. Honestly until I got this message I was going to recycle the stupid book. I guess I have too keep it now. I have the pinout if you want it but not the data sheet. What I guess we should be asking is could you use a TTL chip say 7400 series as a replacement or would the fan in/out be an issue. On Thu, Mar 12, 2009 at 2:25 PM, Patrick Dupre pd...@york.ac.uk wrote: Hello, Sorry, I am looking for the datasheet of an IC ECG9099. Because I did not find it on the internet, I am just asking if you have any idea where I could find it !! Thank -- --- == Patrick DUPRÉ | | Department of Chemistry | | Phone: (44)-(0)-1904-434384 The University of York | | Fax: (44)-(0)-1904-432516 Heslington | | York YO10 5DD United Kingdom | | email: pd...@york.ac.uk == ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- http://www.coe.neu.edu/~efoss/ http://evanfoss.googlepages.com/ -- http://www.coe.neu.edu/~efoss/ http://evanfoss.googlepages.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: datasheet
Hello, Thank you very much for the information. Yes I would be interested by the pinout. It is probably different from the TTL. By the way, I already try to replace a DTL by a TTL after pin modification, but the chip warms up and seems to oscilate. Any, with the pinout, I can first check it is faulty. Best Regards. NTE/ECG/Philips sells chips that are pin for pin replacements for a lot of things. The thing is that the part number they use frequently don't match what anyone else uses. I looked up your part number in a reference book from 1996 and got this Dual M/S J-K Flip-Flop 5MHz I have the pin out too if you need it. I know that it is DTL but you might be able to replace it with a TTL chip from the 7400 series. My reference only goes 1 way from everyone else stuff to ECG. Honestly until I got this message I was going to recycle the stupid book. I guess I have too keep it now. I have the pinout if you want it but not the data sheet. What I guess we should be asking is could you use a TTL chip say 7400 series as a replacement or would the fan in/out be an issue. On Thu, Mar 12, 2009 at 2:25 PM, Patrick Dupre pd...@york.ac.uk wrote: Hello, Sorry, I am looking for the datasheet of an IC ECG9099. Because I did not find it on the internet, I am just asking if you have any idea where I could find it !! Thank -- --- == Patrick DUPRÉ | | Department of Chemistry | | Phone: (44)-(0)-1904-434384 The University of York | | Fax: (44)-(0)-1904-432516 Heslington | | York YO10 5DD United Kingdom | | email: pd...@york.ac.uk == ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- --- == Patrick DUPRÃ | | Department of Chemistry| |Phone: (44)-(0)-1904-434384 The University of York | |Fax: (44)-(0)-1904-432516 Heslington | | York YO10 5DD United Kingdom | |email: pd...@york.ac.uk == ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Meaning of --with-x and --without-gui for pcb
Am Sonntag, den 01.03.2009, 15:09 -0500 schrieb DJ Delorie: And maybe about xrender: Is this an option for GTK and/or motif/openmotif/lesstif GUI. We use this to do translucent solder masks in the GUIs. Nice for Motif GUI. For pcb 20081128 and GTK GUI I can not see an effect if xrender is enabled. ste...@amd64-x2 ~ $ ldd /usr/bin/pcb linux-vdso.so.1 = (0x7fff0f5ff000) libdl.so.2 = /lib/libdl.so.2 (0x7f6a0715) libm.so.6 = /lib/libm.so.6 (0x7f6a06ecf000) libdbus-1.so.3 = /usr/lib/libdbus-1.so.3 (0x7f6a06c92000) libXrender.so.1 = /usr/lib/libXrender.so.1 (0x7f6a07446000) libgtk-x11-2.0.so.0 = /usr/lib/libgtk-x11-2.0.so.0 (0x7f6a066e7000) libgdk-x11-2.0.so.0 = /usr/lib/libgdk-x11-2.0.so.0 (0x7f6a0645) libatk-1.0.so.0 = /usr/lib/libatk-1.0.so.0 (0x7f6a0623) libgdk_pixbuf-2.0.so.0 = /usr/lib/libgdk_pixbuf-2.0.so.0 (0x7f6a06017000) libpangocairo-1.0.so.0 = /usr/lib/libpangocairo-1.0.so.0 (0x7f6a05e0c000) libpango-1.0.so.0 = /usr/lib/libpango-1.0.so.0 (0x7f6a05bc7000) libcairo.so.2 = /usr/lib/libcairo.so.2 (0x7f6a0595e000) libgobject-2.0.so.0 = /usr/lib/libgobject-2.0.so.0 (0x7f6a0571b000) libgmodule-2.0.so.0 = /usr/lib/libgmodule-2.0.so.0 (0x7f6a05517000) libglib-2.0.so.0 = /usr/lib/libglib-2.0.so.0 (0x7f6a0523c000) libjpeg.so.62 = /usr/lib/libjpeg.so.62 (0x7f6a0501a000) libpng12.so.0 = /usr/lib/libpng12.so.0 (0x7f6a04df5000) libz.so.1 = /lib/libz.so.1 (0x7f6a04ce1000) libgd.so.2 = /usr/lib/libgd.so.2 (0x7f6a04aa3000) libc.so.6 = /lib/libc.so.6 (0x7f6a0475b000) /lib64/ld-linux-x86-64.so.2 (0x7f6a07354000) libX11.so.6 = /usr/lib/libX11.so.6 (0x7f6a04452000) libXcomposite.so.1 = /usr/lib/libXcomposite.so.1 (0x7f6a0435) libXdamage.so.1 = /usr/lib/libXdamage.so.1 (0x7f6a0424e000) libXfixes.so.3 = /usr/lib/libXfixes.so.3 (0x7f6a04149000) libfontconfig.so.1 = /usr/lib/libfontconfig.so.1 (0x7f6a03f19000) libXext.so.6 = /usr/lib/libXext.so.6 (0x7f6a03e08000) libXi.so.6 = /usr/lib/libXi.so.6 (0x7f6a03bff000) libXrandr.so.2 = /usr/lib/libXrandr.so.2 (0x7f6a039f7000) libXcursor.so.1 = /usr/lib/libXcursor.so.1 (0x7f6a037ed000) libpangoft2-1.0.so.0 = /usr/lib/libpangoft2-1.0.so.0 (0x7f6a035c1000) libfreetype.so.6 = /usr/lib/libfreetype.so.6 (0x7f6a03331000) libpixman-1.so.0 = /usr/lib/libpixman-1.so.0 (0x7f6a03104000) libXau.so.6 = /usr/lib/libXau.so.6 (0x7f6a03001000) libXdmcp.so.6 = /usr/lib/libXdmcp.so.6 (0x7f6a02efc000) libexpat.so.1 = /usr/lib/libexpat.so.1 (0x7f6a02cd8000) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How to plot in batch mode (ngspice)
Hello, I've discovered gEDA and ngspice and it's fantastic although there is a big road to do. I'm making a work in my university about EDA tools in Linux. My question: Is there a way to plot a graphic (with a .plot directive in the netlist file) after run a simulation in batch mode? Thanks in advance -- View this message in context: http://www.nabble.com/How-to-plot-in-batch-mode-%28ngspice%29-tp22486892p22486892.html Sent from the gEDA - User mailing list archive at Nabble.com. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: iverilog synthesis
Would somebody point me in the right direction for learning more about synthesis with Icarus Verilog? I'm happy to read the source, but synth.cc doesn't seem like the right place to start. Specifically, I am curious to learn if anybody has used Icarus Verilog to target a custom ASIC design. I am fascinated by the concept of doing something like this, and would like to learn if and how it could be done. At the highest level, I can appreciate using Icarus Verilog for an FPGA target, where one somehow tells iverilog about the capabilites of a CLB/slice and, based on that information, iverilog would know how to fill in the LUT and how to configure the flop, but I am very curious to learn how one might tell iverilog about some set of primitives (possibly as primitive as NAND, NOR, NOT, and D-flip-flop) and it would somehow be able to synthesize a netlist for wiring those together to match the verilog model. But aside from the philosophical discussion of how one does this sort of thing, I don't even know were to start to read some documentation about how one might target, for instance, a specific FPGA. I have seen a few references on this list to folks writing their own backend target -- where did they go to learn what they needed to know? So I am also curious about the nuts bolts and don't know where to turn. Thanks for any pointers you might care to toss at me... --wpd --wpd ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: iverilog synthesis
Hello, Patrick, I just starts re-targeting iverilog to some of our own FPGA fabrics. I am still learning the iverilog codes. But, ff you are worrying about generating netlist for your structure, iverilog has provided an interface called ivl for you to manipulate logic gates and computing units like adders, subtracters and more. You can learn the concept of ivl by reading ivl_target.h and t-dll.h. Usually, what you need to do is compiling you netlist generation codes into a shared object or DLL for windows platform. iverilog will call target_design() of your .so and you can call many ivl_* routines to gather necessary information within target_design() and write out your own netlist. The codes in sub-directory tgt-fpga and other tgt-* are also good references for you. Hope they can help you. Best regards. Yujie Wen Patrick Doyle 写道: Would somebody point me in the right direction for learning more about synthesis with Icarus Verilog? I'm happy to read the source, but synth.cc doesn't seem like the right place to start. Specifically, I am curious to learn if anybody has used Icarus Verilog to target a custom ASIC design. I am fascinated by the concept of doing something like this, and would like to learn if and how it could be done. At the highest level, I can appreciate using Icarus Verilog for an FPGA target, where one somehow tells iverilog about the capabilites of a CLB/slice and, based on that information, iverilog would know how to fill in the LUT and how to configure the flop, but I am very curious to learn how one might tell iverilog about some set of primitives (possibly as primitive as NAND, NOR, NOT, and D-flip-flop) and it would somehow be able to synthesize a netlist for wiring those together to match the verilog model. But aside from the philosophical discussion of how one does this sort of thing, I don't even know were to start to read some documentation about how one might target, for instance, a specific FPGA. I have seen a few references on this list to folks writing their own backend target -- where did they go to learn what they needed to know? So I am also curious about the nuts bolts and don't know where to turn. Thanks for any pointers you might care to toss at me... --wpd --wpd ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB: connect line to rectangle
Hello, I have some lines that are ground that I am trying to connect to rectangles. If I try to do that, there is space erased on the rectangle surrounding the lines. How do I avoid this and make the connection? Advice greatly appreciated. Thanks, Frank -- Transistor Toaster transistortoas...@fastmail.fm -- http://www.fastmail.fm - Same, same, but different... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: connect line to rectangle
Use the 'j' key on the line to join them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gsch2pcb use pcb library preferences patch
Thanks for the comments. I have made suggested changes. I have tried
using g_strsplit and found it to takes more lines of code and uses
more memory. I prefer the changes to be walking-style instead of
g_strsplit due to fewer lines, less allocated memory, and it will be
easier to make it accept escape characters or other tweaks. I made a
function to add libraries that replaces the strtok code and can be
used if more libraries need to be added.
-Josh Jordan
--- On Wed, 3/11/09, Peter Clifton pc...@cam.ac.uk wrote:
From: Peter Clifton pc...@cam.ac.uk
Subject: Re: gEDA-user: gsch2pcb use pcb library preferences patch
To: gEDA user mailing list geda-user@moria.seul.org
Date: Wednesday, March 11, 2009, 12:38 PM
On Tue, 2009-03-10 at 17:47 -0700, Josh Jordan wrote:
This patch lets gsch2pcb open up ~/.pcb/preferences and read the
library-newlib = paths and add them to the list of places to get
footprints. The patch is directly for gsch2pcb.c
If you could send patches readdy for applying, that would be great.
I'm
noting that we don't actually want:
+ printf(going into new code\n);
+ printf(coming out of new code\n);
or any other of the live debugging printf patched into gsch2pcb.
I think the general idea of the patch is fine. We have various plans
to
completely re-write how gsch2pcb works at some point (making it defer
operations to PCB), but in the absence of solid progress on that
front,
I don't see how improving the exsting gsch2pcb hurts anything.
+ if (g_str_has_prefix(buf, library-newlib =
))
+ {
+ pref_paths = buf+17;
Code like this is very dangerous from a maintenance point of view.
You could use:
pref_paths = buf + strlen (library-newlib = );
(Bonus points for storing that string in a variable or #define). Smart
compilers ought to be able to optimise out the strlen call of a
static
string, and if not.. we're not exactly on a time-critical path here.
+ while(*++tmp != ':' *tmp !=
0); //push np up to next : or end of string
This breaks portability to Win32, where we use ; as a path
separator.
I presume you want to change the np in the comment to tmp?
You'll notice that the last context after your diff is:
#define PCB_PATH_DELIMETER :
This suggests that we already had a portability problem there. In any
case, you should put your changes after that define, and use it rather
than hard-coding the delimiter.
I doubt any of our existing code gracefully handles : or ; in
filenames, so I'm not going to gripe that yours doesn't allow any
escaping of those characters to treat them as part of the file-names.
Given that you're not handling escaping (which might require you to
walk
the string manually), g_strsplit() might be a neater way to dice up
the
path. (It would be more easy to visually inspect for correctness than
traditional pointer arithmetic based string walking.)
I note that you're not using similar code to that existing in gsch2pcb
to parse the path string (just after your changes). That code uses
strtok, however the man page for that routine suggests it should be
avoided for various reasons. (IE.. don't use it in your new code).
A patch to make both code blocks use the same method (whatever that
is)
would be welcome. I'll also note that they could probably be
refactored
to share that common code (once you've stripped off the
library-newlib
= prefix (using pointer arithmetic).
Stylistic points.. Your code's indenting doesn't seem to match the
existing gsch2pcb code (or the typical convention used in the rest of
the main gEDA code-base). Additionally, the gEDA code base does not
generally use // comments. Instead, use /* . */ blocks.
I hope these comments are useful, and help you improve the patches
further. it is always nice to have new people working on gEDA / PCB,
and
this is certainly an area which hasn't seen a lot of active
maintenance
for a while now.
Best regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
___
geda-user mailing list
[1]geda-u...@moria.seul.org
[2]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
References
1. file://localhost/mc/compose?to=geda-u...@moria.seul.org
2. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
--- gsch2pcb_orig.c 2009-03-13 00:37:48.0 -0400
+++ gsch2pcb.c 2009-03-13 00:36:39.0 -0400
@@ -1229,6 +1229,32 @@
return 1;
}
+#define PCB_PATH_DELIMETER :
+static void
+add_library_paths(gchar *paths)
+ {
+ gchar
