Re: gEDA-user: PCB patches (was: [PATCH 1/7] PCB localization)
Hi,
On 5/26/10, Jared Casper jaredcas...@gmail.com wrote:
So since the only way to contribute to PCB seems to be to continually
spam the list with patches, here's three patches to fix bugs in the
bug tracker. Comments welcome.
Here are two more patches dealing with issues similar to
0001-Fix-pr2976245-refdes-labels-in-new-layout-can-t-be-m.patch
0001 makes PCB reinserts the text into the tree when the length may be changed;
0002 aligns the default symbols on solder side (t.pcb is a test case).
If any of the devs have any
suggestions for how I can better contribute to PCB, I'd be glad to
hear it.
I second.
Cheers,
Ineiev
From b7af7773d5edb9110c96f538e9b050c582d4bd56 Mon Sep 17 00:00:00 2001
From: Ineiev ine...@users.berlios.de
Date: Sat, 7 Mar 2009 08:12:21 +0300
Subject: [PATCH] misfix a bug of edit text action
re-insert the text object into the rtree when it's size may change
HOW TO REPRODUCE
Put a short text (o); change it's name (N in default GTK shortcuts)
to something much longer (longlonglonglong text);
(1) zoom in at the end of the text; the text disappears
(2) click at the end of the text; the text is not selected/deselected
---
src/change.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/change.c b/src/change.c
index 4d42bc3..70bec00 100644
--- a/src/change.c
+++ b/src/change.c
@@ -1066,10 +1066,12 @@ ChangeTextName (LayerTypePtr Layer, TextTypePtr Text)
return (NULL);
EraseText (Layer, Text);
RestoreToPolygon (PCB-Data, TEXT_TYPE, Layer, Text);
+ r_delete_entry (Layer-text_tree, (BoxTypePtr) Text);
Text-TextString = NewName;
/* calculate size of the bounding box */
SetTextBoundingBox (PCB-Font, Text);
+ r_insert_entry (Layer-text_tree, (BoxTypePtr) Text, 0);
ClearFromPolygon (PCB-Data, TEXT_TYPE, Layer, Text);
DrawText (Layer, Text, 0);
return (old);
--
1.6.0.4
From 90ea11d2c6aef91906a123d2da13dd29dc2c9ab2 Mon Sep 17 00:00:00 2001
From: Ineiev ine...@users.berlios.de
Date: Sat, 28 Feb 2009 11:41:20 +0300
Subject: [PATCH] misfix default symbol on solder
the symbol was shifted
HOW TO REPRODUCE
Remove a symbol from the font embedded in a PCB file;
put a text using undefined symbol in the solder layer;
rotate it
In the unpatched version the default symbol is shifted relatively
to the text; in the patched it is aligned correctly
---
src/draw.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/draw.c b/src/draw.c
index d06813d..98d2e05 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -1594,6 +1594,14 @@ DrawTextLowLevel (TextTypePtr Text, int min_line_width)
RotateBoxLowLevel (defaultsymbol, 0, 0, Text-Direction);
+ if (TEST_FLAG (ONSOLDERFLAG, Text))
+ {
+ defaultsymbol.X1 = SWAP_SIGN_X (defaultsymbol.X1);
+ defaultsymbol.Y1 = SWAP_SIGN_Y (defaultsymbol.Y1);
+ defaultsymbol.X2 = SWAP_SIGN_X (defaultsymbol.X2);
+ defaultsymbol.Y2 = SWAP_SIGN_Y (defaultsymbol.Y2);
+ }
+
/* add offset and draw box */
defaultsymbol.X1 += Text-X;
defaultsymbol.Y1 += Text-Y;
--
1.6.0.4
t.pcb
Description: Binary data
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Re: gEDA-user: PCB patches (was: [PATCH 1/7] PCB localization)
On Wed, May 26, 2010 at 11:49 PM, Ineiev ine...@gmail.com wrote: On 5/26/10, Jared Casper jaredcas...@gmail.com wrote: So since the only way to contribute to PCB seems to be to continually spam the list with patches, here's three patches to fix bugs in the bug tracker. Comments welcome. Here are two more patches dealing with issues similar to 0001-Fix-pr2976245-refdes-labels-in-new-layout-can-t-be-m.patch If it makes it any easier. All five of these patches can be pulled from: git://github.com/jaredcasper/pcb.git Jared ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
I wrote: I started working on stuff in the PCB source, and found that it uses a typedef called 'Boolean' rather than the c99 bool type. Please find three patches that transition PCB over to using the c99 bool ... Ineiev wrote: What are the advantages? is current implementation broken for some platform, modern or future? Advantages: * Compiler is able to perform optimisations specific to the bool type. * Additional type safety. * Code becomes less obfuscated (in my mind it's similar to typedef'ing an int to be Int) and so more approachable by new hackers. * Crucially for me, any code in PCB used outside PCB's source doesn't have to have this additional Boolean type cluttering the place up. I wrote: The PCB build scripts tell the compiler to use the 'gnu99' standard (C99 with GNU extensions) Ineiev wrote: I believe it does not in general case, and current sources do build with c89 compilers as far as I know. On closer inspection, the build scripts in PCB don't specifically require C99. I was looking at the arguments it was feeding to the compiler. What I said earlier in this thread about adding AC_HEADER_STDBOOL still applies. (Also note that C99 introduced the ubiquitous '//' inline comment into the C standard.) Cheers, Rob signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB patches (was: [PATCH 1/7] PCB localization)
Jared Casper wrote: If it makes it any easier. All five of these patches can be pulled from: git://github.com/jaredcasper/pcb.git Thank you. _I_ shall. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
Yo, I wrote: Advantages: * Compiler is able to perform optimisations specific to the bool type. ineiev wrote: Yes, it is. I don't think the gain will be noticeable, though. PCB data are mostly ints, and pointers, and floats, and doubles. The point is that there's this patch sitting here that does it. I've done the conversion work so no-one else has to. No matter how small a performance increase it gives, it can be implemented quite cheaply now. I wrote: * Crucially for me, any code in PCB used outside PCB's source doesn't have to have this additional Boolean type cluttering the place up. ineiev wrote: Will Boolean conflict with your sources? are not you going to use other PCB types? I'm working on making a PCB library that exposes PCB's element file parsing and writing. Having a library who's headers define the type Boolean is completely superfluous. If another library writer takes the same attitude as you (seem) to be taking and it's included in the same program as this PCB library, then these typedefs will conflict. Why have a library provide a Boolean type when there's already a perfectly good bool type ready for everyone to use? Why should this wheel be re-invented in PCB's sources? On closer inspection, the build scripts in PCB don't specifically require C99. I was looking at the arguments it was feeding to the compiler. What I said earlier in this thread about adding AC_HEADER_STDBOOL still applies. Your patches don't implement it. No, I never said they did. Here's what I said about this earlier in this thread: if this does actually come up as an issue then I suggest we conditionally enable the typedef using the autoconf AC_HEADER_STDBOOL macro and some cpp guff The key word being if. If and when the issue arises, then we fix it. You'll also note that my patch doesn't include any things to make sure that it compiles on a VAX ;) If and when someone has an issue compiling it on a VAX, then it gets fixed, not before! (Also note that C99 introduced the ubiquitous '//' inline comment into the C standard.) True. oh, please don't replace all C-style comments with C++-style ones in PCB! it will be a real pain for some people on the list to rebase their local patch sets against new master HEAD. You've misunderstood. I was pointing out that this _C99_ feature is already in use in the PCB source code, not that it should be changed to be compliant with C89 (my bet is that exceptionally few PCB builders use a C89 compiler). What are the advantages of keeping this Boolean typedef? Cheers, Rob signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Source file not found
I am just transitioning from gschem to pcb for a robot controller board I am making. It spans several sheets, and has never successfully been exported by gsch2pcb. One of the error messages is cannot find file ROV_2010_analog.sch. This is one of the sheets in the overall motherboard, and is included in the project file. I even copied the file name and cut-n-pasted it into the project file to make sure that all the spelling and capitalization was correct. Then I did a text search through each schematic file and found only one occurrence of ROV_2010_ananlog.sch in any of the schematic files, and that was part of an 'input' symbol and was listed as 'source'. Do I need to have a source file name for every input and output symbol? Or is it not necessary if both schematics are read in at the same time as part of one project? If I have to add them to each input and output symbol, using gattrib won't help much because it does not create a column for data elements that are never called out in that schematic. Also, I clearly do not understand about the name:number convention on the net reference. Should I change the name for every type of signal, and only use numbers when I have a data bus or very similar signals? Or should I use one name for the entire sheet and number each output in sequence? If so, does the name have to be equal to the schematic's file name? I have not yet succeeded getting all the symbols translated to footprints, so I have not yet seen the results of the input/output pairs on the rats list to see if I got it to work or not. Any help getting that fixed BEFORE I start trying to move all the components and layout the traces would be greatly appreciated! Mike ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Still confused on using PCB to make footprints
I was trying to make footprints for the screw terminals I am using in my current project. They are on 5 mm spacing, not inches, so I was hesitant to start with a different footprint and try to change it for fear of getting the units mixed up and creating a mess. So I switched PCB to mm with 0.5mm grid spacing. I had no trouble laying out a silkscreen outline, and little trouble adding vias for the three through holes. But then I could not figure out how to change the vias to pins to assign them numbers and or names. And I am still confused on how to make sure that the pins in a footprint I make will match up with the correct nets from the schematic symbol pins. I looked through every drop down menu several times, and checked the key mapping info. I am sure that there is a tutorial somewhere that helps with this, but the only ones I have read seem to skip over the pin creation and naming, and verifying that they associate with the correct pins on the symbol. Could someone explain to me how to create a footprint in PCB with pins and assign names/numbers to them? And what information is needed to get gscht2pcb to correctly assign nets to pads? Is there any way to test a symbol - gsch2pcb - footprint translation without making a whole schematic? And is there a better tutorial on making footprints with PCB for gschem symbols that I should have been reading instead (and if so, where can I find it)? I managed to gerrymander a 2 row header perl script in inches into making the mm spaced single row of holes for the screw terminals using Luciani's perl scripts, but I was doubtful until they finally worked. Mike ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Still confused on using PCB to make footprints
Could someone explain to me how to create a footprint in PCB with pins and assign names/numbers to them? And what information is needed to get gscht2pcb to correctly assign nets to pads? http://www.delorie.com/pcb/docs/gs/ The second Your first board has that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On 5/27/10 5:50 AM, Robert Spanton wrote: Advantages: * Compiler is able to perform optimisations specific to the bool type. I have it here but don't feel like digging through it, and it seems like it's fresh in your mind so I'll ask...Is there anything in C99 that'd allow for packing bools into a byte or word value, a-la Pascal's packed array of boolean? (Also note that C99 introduced the ubiquitous '//' inline comment into the C standard.) *barf* I've never liked C++-style comments. Just my opinion, worth every penny you pay for it. ;) -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Source file not found
On May 27, 2010, at 10:51 AM, Mike Bushroe wrote: Then I did a text search through each schematic file and found only one occurrence of ROV_2010_ananlog.sch in any of the schematic files, and that was part of an 'input' symbol and was listed as 'source'. That doesn't make any sense to the netlister. You use source= when you have made a symbol that represents an entire hierarcical subcircuit, with all its inputs and outputs. Then you associate source= attributes with the symbol so that the netlister can find the schematics associated with that subcircuit. You also have to tell the netlister where to find such schematics in gafrc. The whole input/output symbol thing can be very confusing until you understand how the netlister works. If you're not using hierarchy, I recommend avoiding those symbols and just attaching netname= attributes to nets. All nets with the same name will be connected together. I sometimes use busses to visually indicate global connectivity. If you want to use some sort of IO symbol to connect nets together on different sheets at the same level, use the net= attribute. Look at gnd-1.sym to see how that works. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On Thu, 2010-05-27 at 13:23 -0400, Dave McGuire wrote: I have it here but don't feel like digging through it, and it seems like it's fresh in your mind so I'll ask...Is there anything in C99 that'd allow for packing bools into a byte or word value, a-la Pascal's packed array of boolean? I think that won't give you a performance win on many targets. bool should be the thing that's fastest to access on the given machine, and accessing single bits will often involve more than one instruction I think. Rob p.s. What's going on with the reply-to header on this list? Why does it seem random whether it's set to geda-u...@... or the sender's email? signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On 5/27/10 12:51 PM, Robert Spanton wrote: The key word being if. If and when the issue arises, then we fix it. You'll also note that my patch doesn't include any things to make sure that it compiles on a VAX ;) If and when someone has an issue compiling it on a VAX, then it gets fixed, not before! In that case, I'll get started on my GL-accelerated Unibus fraembuffer idea! ;) -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On 5/27/10 1:28 PM, Robert Spanton wrote: On Thu, 2010-05-27 at 13:23 -0400, Dave McGuire wrote: I have it here but don't feel like digging through it, and it seems like it's fresh in your mind so I'll ask...Is there anything in C99 that'd allow for packing bools into a byte or word value, a-la Pascal's packed array of boolean? I think that won't give you a performance win on many targets. Of course not...not everything has (for example) 8051's bit-addressable space. I was just curious. :) bool should be the thing that's fastest to access on the given machine, and accessing single bits will often involve more than one instruction I think. Absolutely. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On Thu, 2010-05-27 at 17:51 +0100, Robert Spanton wrote: Yo, I wrote: Advantages: * Compiler is able to perform optimisations specific to the bool type. ineiev wrote: Yes, it is. I don't think the gain will be noticeable, though. PCB data are mostly ints, and pointers, and floats, and doubles. The point is that there's this patch sitting here that does it. I've done the conversion work so no-one else has to. No matter how small a performance increase it gives, it can be implemented quite cheaply now. You forget all the development work which has not yet been merged, which will now be presented with huge (and unnecessary) conflicts. It is not cheap, nor easy due to the existing patch sets and branches out there. (I'm the author of several large ones, so I would be affected there). If you had an automated script for performing the conversions, it might mitigate that. I'm not against de-crufting some of PCB's types (I'm personally not a fan of the foo and fooPtr typedef idiom), but I'm less likely to push for this kind of change than real substantive code improvements. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
Dave McGuire wrote: I have it here but don't feel like digging through it, and it seems like it's fresh in your mind so I'll ask...Is there anything in C99 that'd allow for packing bools into a byte or word value, a-la Pascal's packed array of boolean? What you are looking for is a bit-vector - it is possible to name every bit in it like components in a structure. It's a standard but rarely used datatype in C. Armin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Still confused on using PCB to make footprints
Thanks DJ. The first part of that looks familiar. I guess I never read down far enough to get the footprint creation. I now realize that my problem was that the menu did not indicate that converting the buffer to an element converted vias to pins. I had no idea at all how the pin numbers were assigned. Is there a way to change the pin numbers if you create the vias in the wrong order? Or do you have to cut the element back to the buffer, break the element back to pieces, and manually move the vias around to get the pin numbers in the right places? And also how do you add names to the pins? I know that the gschem symbols have a pin number, a pin sequence number, and a pin label (John Doty is probably snarling already at how heavy this makes the symbols :)). Which governs the association of symbol pin to footprint pin? The pin number, or the pin name/label? And what does the pin sequence number do? Does adding a pin label override the pin numbers if they disagree? Hopefully at this point, most of these questions are for future learning. I _think_ I have the schematics ready to populate the board. The last big hold out, and what was going to be my first plea for help, was CONN8 finding the RJ45 footprint, then not finding it. In the process of documenting all the relevant files, I found that my RJ45.fp footprint was actually the html code for the page that gave the link to the footprint file! It found the file, but failed to make a footprint of it. Now that I have that solved, I should be able to get all elements to load tonight. Mike ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Still confused on using PCB to make footprints
Is there a way to change the pin numbers if you create the vias in the wrong order? The easiest way is to use a text editor. And also how do you add names to the pins? gsch2pcb and pcb's File-Import do that automatically, based on the pin names in the schematic. Which governs the association of symbol pin to footprint pin? The pin number, or the pin name/label? Pin number. And what does the pin sequence number do? It determines the order in which the pins are printed in the netlist. Not really useful for PCB, but useful for simulation models. Does adding a pin label override the pin numbers if they disagree? No. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Still confused on using PCB to make footprints
On May 27, 2010, at 2:13 PM, DJ Delorie wrote: And what does the pin sequence number do? It determines the order in which the pins are printed in the netlist. Not really useful for PCB, but useful for simulation models. Also needed for slotting. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On Thu, 2010-05-27 at 18:45 +0100, Peter Clifton wrote:
You forget all the development work which has not yet been merged, which
will now be presented with huge (and unnecessary) conflicts.
I didn't know that it was a significant amount. Now I do :)
If you had an automated script for performing the conversions, it might
mitigate that.
Sure. Find it attached.
Sequence of application:
1. Apply stdbool-include.patch to add the stdbool.h include and
remove the typedef.
2. Run rename-bool.sh with the pcb source as the working dir. This
replaces switches all .c and .h files over to using bool, true,
and false. It then goes to work on the .y and .l files. My sed
fu is weak, so it only does the replacement in the top and
bottom sections of those files. There is not much to change in
the middle sections, and step 3 sorts it out.
3. Apply parse_y.y-finish-bool-conv.patch -- This does the
remaining (small amount) of conversion required.
The reason I haven't extended the script to work on the middle sections
of the .y and .l files is that I don't think the amount of work involved
in parsing them is necessary. If someone does have some huge changes
queued to the .y or .l files (and I suspect they don't) then we can work
that out.
Cheers,
Rob
From 1fe097f0ad591332b8bb3804630a9db607c91bdf Mon Sep 17 00:00:00 2001
From: Robert Spanton rspan...@zepler.net
Date: Thu, 27 May 2010 21:26:25 +0100
Subject: [PATCH 1/3] Remove Boolean typedef and include stdbool.h
---
src/global.h |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/src/global.h b/src/global.h
index 1082dd1..d099d42 100644
--- a/src/global.h
+++ b/src/global.h
@@ -49,6 +49,7 @@
#include math.h
#include ctype.h
#include sys/types.h
+#include stdbool.h
/* Forward declarations for structures the HIDs need. */
typedef struct BoxType BoxType, *BoxTypePtr;
@@ -68,7 +69,6 @@ typedef int BDimension; /* big dimension */
#ifndef XtSpecificationRelease
typedef unsigned int Cardinal;
-typedef char Boolean;
/*typedef unsigned int Pixel;*/
typedef char *String;
typedef short Position;
@@ -76,9 +76,6 @@ typedef short Dimension;
#endif
typedef unsigned char BYTE;
-#define True 1
-#define False 0
-
/* Nobody should know about the internals of this except the macros in
macros.h that access it. This structure must be simple-assignable
for now. */
--
1.7.0.1
From 9d74f050560b51d30de4fbcb8704a95c2745c8df Mon Sep 17 00:00:00 2001
From: Robert Spanton rspan...@zepler.net
Date: Thu, 27 May 2010 21:30:43 +0100
Subject: [PATCH 3/3] Convert parse_y.y True and False over to C99 true and false.
---
src/parse_y.y | 42 +-
1 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/parse_y.y b/src/parse_y.y
index 22265f6..aad3baf 100644
--- a/src/parse_y.y
+++ b/src/parse_y.y
@@ -151,7 +151,7 @@ parsepcb
YYABORT;
}
for (i = 0; i MAX_LAYER + 2; i++)
- LayerFlag[i] = False;
+ LayerFlag[i] = false;
yyFont = yyPCB-Font;
yyData = yyPCB-Data;
yyData-pcb = (void *)yyPCB;
@@ -196,8 +196,8 @@ parsepcb
| { PreLoadElementPCB ();
layer_group_string = NULL; }
element
- { LayerFlag[0] = True;
- LayerFlag[1] = True;
+ { LayerFlag[0] = true;
+ LayerFlag[1] = true;
yyData-LayerN = 2;
PostLoadElementPCB ();
}
@@ -216,7 +216,7 @@ parsedata
YYABORT;
}
for (i = 0; i MAX_LAYER + 2; i++)
- LayerFlag[i] = False;
+ LayerFlag[i] = false;
yyData-LayerN = 0;
}
pcbdata
@@ -238,13 +238,13 @@ parsefont
Message(illegal fileformat\n);
YYABORT;
}
-yyFont-Valid = False;
+yyFont-Valid = false;
for (i = 0; i = MAX_FONTPOSITION; i++)
- yyFont-Symbol[i].Valid = False;
+ yyFont-Symbol[i].Valid = false;
}
symbols
{
-yyFont-Valid = True;
+yyFont-Valid = true;
SetFontInfo(yyFont);
}
;
@@ -363,9 +363,9 @@ pcbgridnew
yyPCB-GridOffsetX = $4*100;
yyPCB-GridOffsetY = $5*100;
if ($6)
- Settings.DrawGrid = True;
+ Settings.DrawGrid = true;
else
- Settings.DrawGrid = False;
+ Settings.DrawGrid = false;
}
;
@@ -376,9 +376,9 @@ pcb2grid
yyPCB-GridOffsetX = $4*100;
yyPCB-GridOffsetY = $5*100;
if ($6)
- Settings.DrawGrid = True;
+ Settings.DrawGrid = true;
else
- Settings.DrawGrid = False;
+ Settings.DrawGrid = false;
}
;
pcbhigrid
@@ -388,9 +388,9 @@ pcbhigrid
yyPCB-GridOffsetX = $4;
yyPCB-GridOffsetY = $5;
if ($6)
- Settings.DrawGrid = True;
+ Settings.DrawGrid = true;
else
- Settings.DrawGrid = False;
+ Settings.DrawGrid = false;
}
;
@@ -861,7 +861,7 @@ layer
/* memory for name is already allocated */
Layer-Name = $4;
-LayerFlag[$3-1] = True;
+LayerFlag[$3-1] = true;
if (yyData-LayerN + 2
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On 5/27/10 4:07 PM, Armin Faltl wrote: I have it here but don't feel like digging through it, and it seems like it's fresh in your mind so I'll ask...Is there anything in C99 that'd allow for packing bools into a byte or word value, a-la Pascal's packed array of boolean? What you are looking for is a bit-vector - it is possible to name every bit in it like components in a structure. It's a standard but rarely used datatype in C. I believe KR called them bit fields, but yes, I'm aware of that. What I was talking about, though, was declaring bool variables and have the compiler do the packing and unpacking, and have the actual bit positions opaque to the programmer. It was more an academic question than anything else. Being primarily an embedded systems developer, my brain is well-trained to look for ways to minimize data structure size. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
On Thu, 2010-05-27 at 21:48 +0100, Robert Spanton wrote:
2. Run rename-bool.sh with the pcb source as the working dir. This
replaces switches all .c and .h files over to using bool, true,
and false. It then goes to work on the .y and .l files. My sed
fu is weak, so it only does the replacement in the top and
bottom sections of those files. There is not much to change in
the middle sections, and step 3 sorts it out.
I forgot to mention that this script can be used with git filter-branch.
If one has some existing commits that haven't been pushed, one can
convert them over to bool like so:
git filter-branch --tree-filter rename-bool.sh HEAD...${HASH}
Replacing ${HASH} with the hash of the most recent commit shared with
the main repository. This *should* remove merge conflicts to do with
bool.
Cheers,
Rob
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Re: gEDA-user: Source file not found
John, Thanks for the clarification. I checked and I have created a unique 'name':'number' for each net attribute, and matched input to output names. If a net is formed for each unique name:number, and all inputs and outputs with that unique name are combined together, then that was exactly what I was looking for. I briefly tried the up/down hierarchy, but clearly did not understand what it was doing, so I went back to just using input and output symbols and giving each connection a unique name. Mike ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Adding options for manufacturer
Dear, I'm new in PCB, and PCB manual suggested use vendor file to specify set of sizes for a PCB manufacturers. But I'd like to know how change defaults of individual layers gerbers as: top layer: mirror; units: mm, etc. and produce it? Too I'd like to know how to add options to drills files: supress LZ, presicion, absolute, etc.? Thank you for reply! Jose ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Source file not found
Mike Bushroe wrote: If a net is formed for each unique name:number, and all inputs and outputs with that unique name are combined together, then I believe it's more a symbol pinnumber to pinlabel correspondence that matches up symbol pin to subschematic refdes name same as pin label. There's no number on a IO port symbol in a subschematic. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Source file not found
On May 27, 2010, at 6:01 PM, John Griessen wrote: I believe it's more a symbol pinnumber to pinlabel correspondence that matches up symbol pin to subschematic refdes name same as pin label. There's no number on a IO port symbol in a subschematic. You're thinking hierarchy, but Mike's not using hierarchy. He's trying to use symbols to connect pages at top level. Not the most natural thing to do in the gEDA paradigm, but gEDA is flexible... John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Still confused on using PCB to make footprints
Thanks and DJ and John. Now I finally begin to feel comfortable with creating footprints in PCB. But I am still finding another problem with getting the whole pile to translate. I have made or downloaded several custom symbols and footprints. But not matter how many times I insert a gafrc into /gaf or /myproject, it still fails to help gsch2pcb find the custom footprints. For awhile, I was getting an error message saying possible unbalanced parenthesis, but that has gone away, even though I have not changed the parenthesis in either gafrc file. Only the project file seems to actually register when I use the double verbose mode, but even though the element-library is correctly mentioned, it is not searched when looking for footprints. Here is the gafrc in the /gaf directory: (component-library /media/TOSHIBA/gaf/symbols) (element-library /media/TOSHIBA/gaf/footprints) (element-library /media/TOSHIBA/gaf/packages) And here is the one from the project directory (component-library /media/TOSHIBA/gaf/symbols) (element-library /media/TOSHIBA/gaf/footprints) (element-library /media/TOSHIBA/gaf/packages) These are currently setup to run off my USB drive so that I can work off a KNOPPIX disk at work that has gschem and pcb, but the same files ar eon my home drive, with /media/TOSHIBA replaced with /home/mike. The project file is: component-library /media/TOSHIBA/gaf/symbols element-library /media/TOSHIBA/gaf/packages schematics ATMega164P_motherboard.sch ROV_2010_analog.sch ROV_2010_power.sch ROV_2010_Hydraulics.sch ROV_2010_I2C.sch ROV_2010_subprocesser.sch ROV_2010_camera.sch output -name ROV-2010_motherboard When processed, the verbose output is : Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ATMega164P_motherboard.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_analog.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_power.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_Hydraulics.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_I2C.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_subprocesser.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_camera.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ATMega164P_motherboard.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_analog.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_power.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_Hydraulics.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_I2C.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_subprocesser.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_camera.sch] Using the m4 processor for pcb footprints Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ATMega164P_motherboard.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_analog.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_power.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_Hydraulics.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_I2C.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_subprocesser.sch] Loading schematic [/media/TOSHIBA/gaf/ROV_2010/motherboard/ROV_2010_camera.sch] Reading project file: project component-library /media/TOSHIBA/gaf/symbols element-library /media/TOSHIBA/gaf/packages schematics ATMega164P_motherboard.sch ROV_2010_analog.sch ROV_2010_power.sch ROV_2010_Hydraulics.sch ROV_2010_I2C.sch ROV_2010_subprocesser.sch ROV_2010_camera.sch output -name ROV-2010_motherboard Processing PCBLIBPATH=/usr/share/pcb/pcblib-newlib:/usr/share/pcb/newlib Adding /usr/share/pcb/pcblib-newlib to the newlib search path Adding /usr/share/pcb/newlib to the newlib search path Running command: gnetlist -g pcbpins -o ATMega164P_motherboard.cmd ATMega164P_motherboard.sch ROV_2010_analog.sch ROV_2010_power.sch ROV_2010_Hydraulics.sch ROV_2010_I2C.sch ROV_2010_subprocesser.sch ROV_2010_camera.sch Running command: gnetlist -g PCB -o ATMega164P_motherboard.net ATMega164P_motherboard.sch ROV_2010_analog.sch ROV_2010_power.sch ROV_2010_Hydraulics.sch ROV_2010_I2C.sch ROV_2010_subprocesser.sch ROV_2010_camera.sch Default m4-pcbdir: /usr/share/pcb/m4 gnet-gsch2pcb-tmp.scm override file: (define m4-pcbdir /usr/share/pcb/m4) (define gsch2pcb:use-m4 #t) Running command: gnetlist -g gsch2pcb -o ATMega164P_motherboard.pcb -m gnet-gsch2pcb-tmp.scm
Re: gEDA-user: Still confused on using PCB to make footprints
Here's one of my project files (for gsch2pcb): -- laminator.prj -- m4-pcbdir /envy/dj/geda/share/pcb/m4 elements-dir /envy/dj/geda/gedasymbols/www/user/dj_delorie/footprints elements-dir ./footprints schematics laminator.sch output-name laminator -- -- However, if PCB can find your footprints in the library window, try using the new importer (File-Import Schematics). If you have more than one toplevel *.sch you'll need to read the docs on the Import() action to see how to add the names, but it uses PCB's internal library path instead of gsc2pcb's paths. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PolyStitch plugin
I needed to do some logos, so everyone gets a logo tool :-) PolyStitch is a PCB plugin to fix the output of pstoedit's pcbfill output, when you have text with holes in it (like the letter d). Pstoedit makes two polygons, one for the outside and one for the hole, but what you really want in PCB is one polygon, so that the hole is not filled. This plugin, used when the crosshair is over the inner polygon, stitches the two polygons together such that the area inside the inner polygon becomes outside the resulting polygon. Basically, it cuts the shape at the narrowest spot and stitches the point lists together. It can also be used to cut holes in a ground plane, by drawing the hole as a separate polygon then stitching it to the plane's polygon. Plugin source: http://www.delorie.com/pcb/polystitch.c Sample board: http://www.delorie.com/pcb/polystitch.pcb Undo is not supported (sorry). DJ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PolyStitch plugin
On Fri, May 28, 2010 at 12:33 AM, DJ Delorie d...@delorie.com wrote: I needed to do some logos, so everyone gets a logo tool :-) PolyStitch is a PCB plugin to fix the output of pstoedit's pcbfill output, when you have text with holes in it (like the letter d). Pstoedit makes two polygons, one for the outside and one for the hole, but what you really want in PCB is one polygon, so that the hole is not filled. Have you tried the -ssp option to pstoedit? This does the right thing, when it doesn't segfault. Regards, Mark markra...@gmail -- Mark Rages, Engineer Midwest Telecine LLC markra...@midwesttelecine.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PolyStitch plugin
Have you tried the -ssp option to pstoedit? This does the right thing, when it doesn't segfault. Predictably, it seg faulted on me. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Patches: Use c99 bool instead of manual typedef.
Hello,
Robert Spanton rspan...@zepler.net wrote:
The key word being if. If and when the issue arises, then we fix it.
In other words, you are willing to break it and won't fix.
2. Run rename-bool.sh with the pcb source as the working dir. This
replaces switches all .c and .h files over to using bool, true,
and false. It then goes to work on the .y and .l files. My sed
fu is weak, so it only does the replacement in the top and
bottom sections of those files. There is not much to change in
the middle sections, and step 3 sorts it out.
I forgot to mention that this script can be used with git filter-branch.
If one has some existing commits that haven't been pushed, one can
convert them over to bool like so:
git filter-branch --tree-filter rename-bool.sh HEAD...${HASH}
Replacing ${HASH} with the hash of the most recent commit shared with
the main repository. This *should* remove merge conflicts to do with
bool.
Why not apply it to your local branch instead of PCB master?
Best wishes,
Ineiev
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