Re: gEDA-user: Icarus verilog Synthesis
I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. For FPGA work, I am unaware of any engine that can synthesize those constructs. If you read through the XST manual from Xilinx (just for an example), I am pretty sure they tell you what can and cannot be synthesized. The commands you just listed work well for test benches or other verification code (and simulation too) but are probably not appropriate for fpga level design. Maybe VLSI is different - but I have no experience with that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Unusual uses of gEDA...
My latest project has five PCBs designed in gEDA/PCB. One of those oddball projects that uses PCB layout but no gschem or gnetlist. No netlist at all, in fact. http://www.evilmadscientist.com/go/eggbot A tricky part of this was the mask keepout on two of the boards-- I ended up drawing a separate layer for mask, and using it instead of the standard mask gerber. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unusual uses of gEDA...
Windell H. Oskay wrote: http://www.evilmadscientist.com/go/eggbot me likes! :-) ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unusual uses of gEDA...
On 09/10/2010 06:24 AM, Windell H. Oskay wrote: http://www.evilmadscientist.com/go/eggbot A tricky part of this was the mask keepout on two of the boards-- I ended up drawing a separate layer for mask, and using it instead of the standard mask gerber. The black on white rules and logo look great Windell. I like the idea of an engraver for it -- then it could do promotional doo-dads and trophies for club events... I don't see any big unprinted areas where your custom mask is though, what triggered that need? Was the printing done as white soldermask and black silk layer? On FR-4, acrylic? The board material looks almost clear. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unusual uses of gEDA...
On Sep 10, 2010, at 8:28 AM, John Griessen wrote: The black on white rules and logo look great Windell. I like the idea of an engraver for it -- then it could do promotional doo-dads and trophies for club events... The engraver is pretty neat-- it can make, for example, etched glass christmas ornaments. Here's one that we made at MakerFaire Detroit: [1]http://www.flickr.com/photos/lenore-m/4856324866/in/photostream/ The photo shows a dull-silver-painted glass ornament, engraved down to etched glass, and lit from within by a multicolor LED. I'm not sure that it's precise enough for trophies, but I bet there will be a lot of ornaments sent to gramma. :) I don't see any big unprinted areas In this photo, you can see a big square on the lower left piece and a big rectangle on the second piece from the top: [2]http://www.flickr.com/photos/oskay/4970320961/ If you look closely, you'll see that those two areas are not black ink but are silver colored: those are large mask-free areas that are HASL finished. The motors screw down to those two locations-- one fixed, the other slotted so that it can go to different positions . Without the mask, there's a good metal-to-metal thermal connection between the motor and the top copper. Those two boards have a copper flood going all the way to 20 mil from the board edges, which acts as a surprisingly effective heat sink for the motors. Was the printing done as white soldermask and black silk layer? On FR-4, acrylic? The board material looks almost clear. Yes, it's white mask and black silk on 100 mil FR-4. There's actually printing on both sides, so you'd see some of that if it were clear. The white mask is quite opaque. You can see the board edges somewhat in this photo, where the FR-4 has its usual translucency: [3]http://www.flickr.com/photos/oskay/4970933180/in/photostream/ We did some of our mechanical prototyping in 3 mm laser-cut acrylic. It's almost shocking how much stronger the FR-4 is. References 1. http://www.flickr.com/photos/lenore-m/4856324866/in/photostream/ 2. http://www.flickr.com/photos/oskay/4970320961/ 3. http://www.flickr.com/photos/oskay/4970933180/in/photostream/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unusual uses of gEDA...
On 09/10/2010 11:45 AM, Windell H. Oskay wrote: The engraver is pretty neat-- it can make, for example, etched glass christmas ornaments. Here's one that we made at MakerFaire Detroit: [1]http://www.flickr.com/photos/lenore-m/4856324866/in/photostream/ The photo shows a dull-silver-painted glass ornament, engraved down to etched glass, and lit from within by a multicolor LED. I'm not sure that it's precise enough for trophies, but I bet there will be a lot of ornaments sent to gramma. :) So, if the engraver vibration is too fuzzy, how about adding force feedback control and a rotary tool? The force feedback would let you hold up the weight of the rotary tool, and probably help pickup and touch down at the same spots too. Does the eibot board have some spare inputs for feedback? John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unusual uses of gEDA...
On Sep 10, 2010, at 10:10 AM, John Griessen wrote: So, if the engraver vibration is too fuzzy, how about adding force feedback control and a rotary tool? The force feedback would let you hold up the weight of the rotary tool, and probably help pickup and touch down at the same spots too. Does the eibot board have some spare inputs for feedback? Interesting idea. We have used rotary tools with success, but they cost *a lot more,* and they're bulky and weigh a lot-- a little challenging for our motors without careful balance. The nicest results were with an air-powered dental drill. Adding force feedback would be possible, but also adds cost. Probably the best way to improve precision is just to increase the stiffness of the flexure hinge, meaning that there's less motion in undesirable degrees of freedom. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, Sep 10, 2010 at 01:00:34AM +0100, Peter Clifton wrote:
Gah, you perhaps saw my comments on geda-dev about that. I've got half a
mind to bulk rename as appropriat:
max_layer - max_copper_layer
OR- max_group
They happen to be the same number, but the context is different and it
makes a lot of code confusing.
There are actually max_copper_layer + 2 layers, with the last two being
the silk layers. It sits wrong with me to see:
for (i = 0; i max_layer + 2; i++) {
Layer[i]...
}
I think max_copper_layer + 2 is slightly less perverse.
It's a PITA to find and read the geda-dev archives, and given the relatively
low volume, I don't usually bother. So I missed your comments.
Having said that, I'd do you one step further, and move /all/ the layers into
their own list structure. Each layer would have flags set to indicate if it
was a copper, silk, keepout or virtual (ie, ratsnest) layer. They would also
be tagged as being always on top or always on bottom, in the case of silk
layers that we don't want ending up inside the board.
The layer-selector widget would then be little more than a pretty layer on
top of that structure.
A common theme in pcb is that limitations in the file format and our
data structures, show up as ugly hacks in the GUI code.
Point me some examples and I'll probably agree, but I can't think of any
immediately.
Well, the fact there are exactly two silk layers, both selected in the same
way (depending on which side of the board is being viewed), and a ratsnest
layer, all of which require switch blocks throughout the layer-selector GUI
code. Also, there are weird variables like SilkActive and RatsActive that
implicitly depend on each other, and the layer array.
There have been plenty of places where the core's assumption of
rendering requirements / ordering have bitten me with the GL branches
though. It is tricky to fix them as you can't always tell how changes
will affect other exporters / GUIs.
(You may notice I've started in a few places pulling common drawing code
into a common_* prefix under the hid/ folder). My aim was to set it up
such that the GUIs could take or leave various bits of the common
rendering code as their authors desire.
To do this, we would have to use a single renderer, no? For example, have
OpenGL do the viewport drawing in all of Gtk, LessTIF, (Windows?), etc?
Not so easy as that, as there will necessarily be toolkit specific
requirements for setting up a rendering context, and possibly even
different strategies for managing redraw.
Yuck. I'll keep this in mind while doing any restructuring.
Andrew
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Re: gEDA-user: next PCB release - 1.99za vs 4.0
Having said that, I'd do you one step further, and move /all/ the layers into their own list structure. Each layer would have flags set to indicate if it was a copper, silk, keepout or virtual (ie, ratsnest) layer. They would also be tagged as being always on top or always on bottom, in the case of silk layers that we don't want ending up inside the board. Yup, that's on the long-term plan. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote: PS.. have you tried any of the GL stuff? http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-3.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-4.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-5.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-6.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-7.png Wow! I tried out the GL branch and was impressed by how fast and responsive it was. Also, that clicking and selecting objects worked properly (the Gdk stuff is /awful/ at this.) But I had not played with 3D.. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 11:03 -0700, Andrew Poelstra wrote: It's a PITA to find and read the geda-dev archives, and given the relatively low volume, I don't usually bother. So I missed your comments. If you're developing, ask Ales to get you signed up to geda-dev. As you say, it is pretty low volume. Having said that, I'd do you one step further, and move /all/ the layers into their own list structure. Each layer would have flags set to indicate if it was a copper, silk, keepout or virtual (ie, ratsnest) layer. They would also be tagged as being always on top or always on bottom, in the case of silk layers that we don't want ending up inside the board. Yes, indeed.. magic silk (and other) layers should probably go and die. It was sorely tempting to do that earlier. For now, I've pushed a patch which makes it a little clearer what the intent is when iterating over layers / groups. I wanted to come up with a better name that max_copper_layers, but I guess that can change when we actually put some non-copper layers in place. max_normal_layers? (Or just max_layers once again, when we've made all layers equal). Perhaps it would be good to use a new name though.. to avoid silent breakage on old plugins which assume the old semantics though. Whatever we do, it is still useful to be able to designate component / solder side groups (or have some means to define physical stack-up) so that pads can be rendered on the right layers ;) Point me some examples and I'll probably agree, but I can't think of any immediately. Well, the fact there are exactly two silk layers, both selected in the same way (depending on which side of the board is being viewed), and a ratsnest layer, all of which require switch blocks throughout the layer-selector GUI code. Also, there are weird variables like SilkActive and RatsActive that implicitly depend on each other, and the layer array. Ok, I've got you... and you are correct ;) -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 11:05 -0700, Andrew Poelstra wrote: On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote: PS.. have you tried any of the GL stuff? http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-3.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-4.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-5.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-6.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-7.png Wow! I tried out the GL branch and was impressed by how fast and responsive it was. Also, that clicking and selecting objects worked properly (the Gdk stuff is /awful/ at this.) Major refactoring is wanted there IMO. I've not pushed my changes as yet because there are still shortcomings. The code to snap the mouse-pointer onto the grid is completely different code to that which performs actions.. so you could snap to the center of a via, and (say), have the mouse-click perform on some object which was _not_ snapped to. I figured the GUI / core's mouse-snap code should determine which object got the snap, and pass that on to the action code, rather than having it re-figure-out which object to manipulate based on the mouse coordinates. PS. if I didn't say already, it is the before_pours branch you probably want. master is fun for polygons... go try that ;), but it isn't what I would call compatible semantics to old files. You'll have to place something conducting, such as a joined trace, or a thermal to make the pieces of polygon appear though, but it does proper island removal. But I had not played with 3D.. You see the strange circle / ellipse under the layer buttons. Drag that around like a track-ball. If you have a board which has an outline or route layer which is complete (no little gaps), it will render the solder-mask layers to match that outline for added visualisation goodness. I just wish the code wasn't quite so crufty in places ;) -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote: PS.. have you tried any of the GL stuff? http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-3.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-4.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-5.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-6.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-7.png Wow. These screenshots are incredible. Please excuse my naive question, but is this something that the rest of us can expect to see in PCB someday? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Whatever we do, it is still useful to be able to designate component / solder side groups (or have some means to define physical stack-up) so that pads can be rendered on the right layers ;) I figure we need each layer to specify: * type (copper, silk, mask, anti-copper, keepout, etc) - probably a set of values: base type plus flags for anti etc - maybe a sequence number for layering, like anti-silk over silk rectangles, etc. * layer class (top, bottom, inner) * OR specific layer (0..N based on the stackup) So a footprint could specify clearance on all inners, or copper on just the inner under the traces, etc. So a (top,silk) solid rectangle, above that a (top,silk,anti) text, gives us black text on a white area... But I figure the top/inner/bottom class is what we need for importing footprints. They'd be layered by class, not number, so they can adapt to whatever number of layers the board has. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote: I figure we need each layer to specify: * type (copper, silk, mask, anti-copper, keepout, etc) There are no types, there are only properties. The conductors may not be copper. I've even worked with a board that had two different conductive materials on the same physical layer. The support layers are also not always FR4. The board I noted above had different numbers of layers in different places, and the support layers weren't all the same material and thickness. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, Sep 10, 2010 at 01:42:21PM -0600, John Doty wrote: On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote: I figure we need each layer to specify: * type (copper, silk, mask, anti-copper, keepout, etc) There are no types, there are only properties. I disagree. Replace the word copper with conductor and you will see what I mean. If you have two different conductive materials, with different properties, then yes, the layer needs to have property information. Even so, I don't think it's as as high a priority as layer unification. The conductors may not be copper. I've even worked with a board that had two different conductive materials on the same physical layer. Then perhaps the material used should be a property of the traces, not a property of the layer. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
The conductors may not be copper. I've even worked with a board that had two different conductive materials on the same physical layer. Interesting case. Let's suppose that you have conductors -- say niobium and copper -- on the same physical layer. Does that have implications for PCB? I'm not certain that I see any. I'd imagine that you ultimately need to generate separate gerber files for the two separate conductors. That means putting them on separate layers in PCB (or, I suppose, major architecture changes). If that was an inner layer, you could lay it out as two separate inner layers and that would work, so far as I can see. If the two conductors are both on the top outer layer, I believe that you could use the same strategy, defining both to be in the same component side layer group. Am I missing something? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Windell H. Oskay wrote: Wow. These screenshots are incredible. Please excuse my naive question, but is this something that the rest of us can expect to see in PCB someday? I tried to use the 3D view for regular work a few moths ago (medium density, 4-layer, analog layout). Turns out, it makes routing/placing more confusing than pure 2D vertical view. It is difficult to tell the distance of objects on different layers. After all, the physical screen is 2D an the layout problem is almost 2D. IMHO, the big advantage of Peters GL version is transparency. Plus, a few extra features. For example, snap to the middle of pads rather than to the end of the paths the pad is build from. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
I tried to use the 3D view for regular work a few moths ago (medium density, 4-layer, analog layout). Turns out, it makes routing/placing more confusing than pure 2D vertical view. It is difficult to tell the distance of objects on different layers. After all, the physical screen is 2D an the layout problem is almost 2D. I'd certainly advocate 2D routing and placement. I do see two key reasons to include this function, though. 3D seems like a *very* useful addition for inspection and review prior to taping out. (I already like the transparency in gerbv.) Second, it makes for excellent screenshots which can attract new users to gEDA. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 15:01 -0400, DJ Delorie wrote: Whatever we do, it is still useful to be able to designate component / solder side groups (or have some means to define physical stack-up) so that pads can be rendered on the right layers ;) I figure we need each layer to specify: * type (copper, silk, mask, anti-copper, keepout, etc) ___^___ Just how useful is anti-copper? Is it mitigated by allowing holes in polygons? I do have some code (not sure what state it is in) which implements anti-polygons within a given layer. It was my first stab at figuring out a way to allow user-specified holes in polygons. I have been rebasing that branch against current changes just in case it would ever be of any use, but I had basically consigned as an idea that went nowhere. - probably a set of values: base type plus flags for anti etc - maybe a sequence number for layering, like anti-silk over silk rectangles, etc. Presumably anti- layers would have be be composited into a single output layer by for various exporters? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
If we have a real stackup, the 3-D view lets you verify it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 16:23 -0400, Windell H. Oskay wrote: The conductors may not be copper. I've even worked with a board that had two different conductive materials on the same physical layer. Interesting case. Let's suppose that you have conductors -- say niobium and copper -- on the same physical layer. Does that have implications for PCB? I'm not certain that I see any. I'd imagine that you ultimately need to generate separate gerber files for the two separate conductors. That means putting them on separate layers in PCB (or, I suppose, major architecture changes). If that was an inner layer, you could lay it out as two separate inner layers and that would work, so far as I can see. With PCB as is.. you would probably use layer-groups to separate the distinct sub-layers. I don't tend to use them, so I couldn't swear to how the gerbers come out - but I'm certain it would not be hard to make it produce separate gerbers if necessary (you might just need to un-group the layers). If the two conductors are both on the top outer layer, I believe that you could use the same strategy, defining both to be in the same component side layer group. Am I missing something? Yep... I should read the full email before starting to reply ;) Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 22:48 +0200, Kai-Martin Knaak wrote: Windell H. Oskay wrote: Wow. These screenshots are incredible. Please excuse my naive question, but is this something that the rest of us can expect to see in PCB someday? I tried to use the 3D view for regular work a few moths ago (medium density, 4-layer, analog layout). Turns out, it makes routing/placing more confusing than pure 2D vertical view. It is difficult to tell the distance of objects on different layers. After all, the physical screen is 2D an the layout problem is almost 2D. Indeed.. I would have never imagined anyone trying to do actual layout / routing in a non-head-up orientation. I find somehow the 2.5D / 3D view is just enough to get the brain to imagine what the finished board will look like, and that helps me sometimes. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Just how useful is anti-copper? Is it mitigated by allowing holes in polygons? I don't know, but if we're going to have anti-layers, might as well have them for everything. I imagine making a SMPS power supply, you'd want to start with a polygon and cut thin slices off between regions, to get the maximum copper you can, for example... Presumably anti- layers would have be be composited into a single output layer by for various exporters? Yes. We'd have to figure out a sensible well-defined way to merge layers of the same type in the same group. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 14:16 -0400, Windell H. Oskay wrote: On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote: PS.. have you tried any of the GL stuff? http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-3.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-4.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-5.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-6.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-7.png Wow. These screenshots are incredible. Thanks! Please excuse my naive question, but is this something that the rest of us can expect to see in PCB someday? Some day.. eventually. It is a slow work in progress to get the code clean enough to push into git HEAD. In the mean time, the branch is before_pours in this repository: git://repo.or.cz/geda-pcb/pcjc2.git I've been working slowly to get the OpenGL stuff to co-exist with a standard GDK build, but for the moment that isn't finished. Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
With PCB as is.. you would probably use layer-groups to separate the distinct sub-layers. I don't tend to use them, so I couldn't swear to how the gerbers come out - but I'm certain it would not be hard to make it produce separate gerbers if necessary (you might just need to un-group the layers). One of my other long-term wishlist items is to put a real scriptable CAM engine in, so you could do things like spit out copper layers in this group by attribute FOO. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, Sep 10, 2010 at 10:49:45PM +0100, Peter Clifton wrote: Presumably anti- layers would have be be composited into a single output layer by for various exporters? What if the anti-layer isn't even a real layer - just an option while editing a layer, to draw vacuum. For example, if we redesigned the layer-selector, we could cram icons into a 4x4 grid for each layer: ++-+ | active | visible | ++-+ | locked | vacuum | +--+ I know there is opposition to making the layer-selector take up any more space than it does, but I think we could make these 8x8 or 10x10 icons and still remain space-conservative. I don't like the idea of layer groups, and I certainly don't think we should do something that (pretty much) requires them to work. So having anti-layers sounds wrong to me. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
What if the anti-layer isn't even a real layer - just an option while editing a layer, to draw vacuum. If you use the line tool to cut up a polygon, how do you edit that cut later? And I think we need anti-layers to handle some soldermask and paste issues anyway. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 22:48 +0200, Kai-Martin Knaak wrote: Windell H. Oskay wrote: Wow. These screenshots are incredible. Please excuse my naive question, but is this something that the rest of us can expect to see in PCB someday? I tried to use the 3D view for regular work a few moths ago (medium density, 4-layer, analog layout). Turns out, it makes routing/placing more confusing than pure 2D vertical view. It is difficult to tell the distance of objects on different layers. After all, the physical screen is 2D an the layout problem is almost 2D. Indeed.. I would have never imagined anyone trying to do actual layout / routing in a non-head-up orientation. I find somehow the 2.5D / 3D view is just enough to get the brain to imagine what the finished board will look like, and that helps -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, Sep 10, 2010 at 06:11:05PM -0400, DJ Delorie wrote: What if the anti-layer isn't even a real layer - just an option while editing a layer, to draw vacuum. If you use the line tool to cut up a polygon, how do you edit that cut later? When the edit mode is set to 'vacuum', the anti-traces would be visible, perhaps in a semi-transparent or outlined way. And I think we need anti-layers to handle some soldermask and paste issues anyway. I think that anti-layers can be implemented as a subset of existing layers, rather than as layers in their own right. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Fri, 2010-09-10 at 18:11 -0400, DJ Delorie wrote: If you use the line tool to cut up a polygon, how do you edit that cut later? If the cut was in fact an anti-line, just a clearance created, then it would remain editable - although I'm not sure quite how you'd render it. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: layers for pcb
On 09/10/2010 05:20 PM, Peter Clifton wrote: On Fri, 2010-09-10 at 18:11 -0400, DJ Delorie wrote: If you use the line tool to cut up a polygon, how do you edit that cut later? If the cut was in fact an anti-line, just a clearance created, then it would remain editable - although I'm not sure quite how you'd render it. Whatever you call it, for the case of generated clearance gaps, a layer of shapes that cut and make disappear other layers gets generated according to an attribute attached to the trace object on a layer. When you think of the algorithm for doing it, sets of objects just pop into existence because you need them as an intermediate to processing to get to the end result. The thing we are now calling layer group seems what Andrew wants to call a layer. Then you'd still have intermediates and what to call them? Anti-layer isn't my favorite. I'd call some of the intermediates cut-sets or cut-layers. Layer group as a name doesn't bother me. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: layers for pcb
On Fri, 2010-09-10 at 17:41 -0500, John Griessen wrote: On 09/10/2010 05:20 PM, Peter Clifton wrote: The thing we are now calling layer group seems what Andrew wants to call a layer. Then you'd still have intermediates and what to call them? I think layer groups as a way of partitioning different tracks / zones on the board is more limited than tagging with attributes. I realise there are a lot of Unix fans here, so this analogy isn't perfect to make my point.. but think unix group based permissions vs. ACLs. Either system can do what you want, but with groups / layer groups, you end up needing to create a lot of them (for PCB, layers within a group), and management of them can get a little out of control. From a technical point of view.. using lots of layer groups is also bad for performance, (not sure how much you'd notice though), since the r-trees of objects are stored per layer, and search complexity would seem to go up with unfavourably with increasing numbers of sub-groups. Anti-layer isn't my favorite. I'd call some of the intermediates cut-sets or cut-layers. Layer group as a name doesn't bother me. The composition / z-order rules will be important to define and get right whatever we do, be it with anti-objects, or cutting layers. Do the anti-objects / layers clear every type of object? (Polys / Lines / Pads?), or do they only act on (say) polygons? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
