Re: gEDA-user: new footprint guidelines
Rick Collins wrote: At most you might want to verify that the data in the XYRS file matches the Gerber files for a small number of representative parts. Why do you think you need to verify the results by reverse engineering the code??? That is the stuff I am talking about over thinking the problem. All you need to do is look at the output. Looking at the output is a precondition to verifying anything. You tell me, that I shouldn't look at the input. But it's one of the iron rules of computation: garbage in - garbage out Having to verify the output on each and every design is rediculous. It's like a marksman determining his hold-off on every target by trial. This is not very common nowadays because the bear wins. E.g., where is the centroid of a 3-leged part? Is it: a) the center of the bounding box of the pads b) the center of the bounding box of the pad centers c) the center of gravity of the pad centers (each weight 1) d) the center of gravity of the pad areas e) (0, 0) in the footprint definition file (or a designated vector inthere) ... When you find out what PCB does, a through e, what will that tell you? It will tell me, whether what PCB does, conforms to the standard or has a chance to conform to the standard with correct libraries. If you don't know what the standard is, how will you know if your design is correct? If there is a standard and I don't know it, it's my fault - and of course I will never know until the assembly house told me, that I screwed up. Maybe for the series you do, the cost is negligible. At my present state of business €250 for the setup compared to €950 for assembling 30 boards is a considerable cost factor. If I can get rid of this or reduce it to €50 because the assemblers knows they can trust my data, this is a huge competitive advantage. Maybe the savings generated by this discussion here never hit my wallet. But I'm not writing for me alone, as I use others work for free. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
Rick Collins wrote: I'm guessing here, but pick and place machine have to orientate the part very fast, so it is important that they pick the component from a principal axis of inertia. It is not always easy to determine where the axis lies when the component is asymmetric, which is frequent with power components. For another example, look a DPAK or D2PAK components (SOT404, SOT428, etc). I'm not even sure that they option a) would work, but it might be a good default, provided you can override it. Pick and place machine operators don't want you to tell them how to pick a part. All they want from you is to tell them where on the board to put it. That is why the XYRS file uses the centroid and not the center of mass. I know that and was on the verge of replying the same. All I want is to make sure that I'll provide a correct description of the geometry. And now it's time for more reading and less writing. Thanks again for sending me the standard. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem sym files
Karl Hammar wrote: +1 for nc since ICs have pins that are labeled that way. Would the DRC just ignore it, or would the DRC complain if it was connected to anything? +1 ... Since nc is just a piece of copper attached to the (plastic/ceramic) package, why should drc complain? A nc pin would be like pas, but gives no error if unconnected. The documentation of the Renesas TinyH8 states: ... Do not connect anything to the nc-pins. They might be used as test pins under certain conditions or used for damping purposes, which you don't know. I would also like to see a pwr_src pin type which would be the output of the voltage regulator (or source). That way the DRC would warn you if you shorted two power sources together or if you forgot to hook one of your power input pins to the power plane (and only connected it to a capacitor instead). +1 +1 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: multiple monitors
John Griessen wrote: That's a nice idea. I'd also like a feature where besides just panning, you could define views that stay around. They'd show as zones on the whole design view, and selecting them would open the pcb work view window on that area of interest. A way to do a UI for that might be to pan when you click outside one of the defined views, zoom to a defined view when you click inside it, and mov ethe defined view when you click and drag on it. My mechanical cad demo has a similiar feature: 5 buttons that will store views: - middle click on one of them stores your current view - left click makes the stored view active You have to remember what was where, but a thumbnail of the whole board with a red frame in it can be realized. I implemented this, because mechanical constructions sometimes have 2 small areas of interest with long parallel lines connecting them - but I find it generally handy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: multiple monitors
On 10/04/2010 10:59 AM, Armin Faltl wrote: John Griessen wrote: That's a nice idea. I'd also like a feature where besides just panning, you could define views that stay around. They'd show as zones on the whole design view, My mechanical cad demo has a similiar feature: 5 buttons that will store views: - middle click on one of them stores your current view - left click makes the stored view active Sounds good, and pragmatically programmable Armin :-) What kind of CAD demo? John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem sym files
Since nc is just a piece of copper attached to the (plastic/ceramic) package, why should drc complain? A nc pin would be like pas, but gives no error if unconnected. The documentation of the Renesas TinyH8 states: ... Do not connect anything to the nc-pins. They might be used as test pins under certain conditions or used for damping purposes, which you don't ,know. This would imply that a 'nc' should prohibit any connections to it whatsoever, so there is no chance of a connection, and that another type: 'don't care' or 'ignore' or 'unknown' or 'x' should be made that will not give an error if unconnected, but will also not give an error IF connected. I would also like to see a pwr_src pin type which would be the output of the voltage regulator (or source). That way the DRC would warn you if you shorted two power sources together or if you forgot to hook one of your power input pins to the power plane (and only connected it to a capacitor instead). +1 +1 Very useful. Andrew Miner ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem sym files
I have seen this handled in other CAD packages not by making the pin an NC in the symbol, but by having a feature in the schematic where the pin can be No Connected so that it is not flagged as an error if it has no wire. Or course, it makes some sense to have a special type of NC in a symbol if the data sheet says to not connect it. I have seen those. They often don't even tell you why. I think typically it is a factory use pin and they don't want any noise pickup. Grounding it would upset the operation of the chip so it just needs to float with as little copper as feasible. So either you should not be able to connect a wire to it (just make it a graphic pin and not a real pin) or flag an error if a connection is made. Rick At 12:24 PM 10/4/2010, you wrote: Since nc is just a piece of copper attached to the (plastic/ceramic) package, why should drc complain? A nc pin would be like pas, but gives no error if unconnected. The documentation of the Renesas TinyH8 states: ... Do not connect anything to the nc-pins. They might be used as test pins under certain conditions or used for damping purposes, which you don't ,know. This would imply that a 'nc' should prohibit any connections to it whatsoever, so there is no chance of a connection, and that another type: 'don't care' or 'ignore' or 'unknown' or 'x' should be made that will not give an error if unconnected, but will also not give an error IF connected. I would also like to see a pwr_src pin type which would be the output of the voltage regulator (or source). That way the DRC would warn you if you shorted two power sources together or if you forgot to hook one of your power input pins to the power plane (and only connected it to a capacitor instead). +1 +1 Very useful. Andrew Miner ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Problem whit footprint.
Hi, im new on geda, and have installed the latest version. There are changes or problems when i try make a footprint and call it from xgschem2pcb?? Only one footprint (only one pin) do not appear when i touch the button update layout in xgschem2. Thanks!! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB layers questions
I'm having trouble with layers in pcb and can't find any relevant info either on the web or in reading back through several hundred archived messages, so I figured I'd just ask. I'm using version 20080202 (because that's what's in the repo I use.) When I try to add a new layer, it refuses unless I add the layer into or above one of the three component-associated or solder-associated layers. (component, gnd-comp, vcc-comp; solder, gnd-solder, vcc-solder) Once I do that, it associates my new layer with either component or solder, even if I go to 'groups' and click on a different group number: it reverts to the layer in which it was originally created as soon as I close the prefs window. Aside from that, I also don't know how to get pcb to produce gerbers from new layers that I add. If I delete gnd-comp and add a new layer called 'outline' -- which it sticks under 'component' and associates with that group, as above -- it doesn't produce a gerber for my new layer, separate from the 'component' gerber. What I'd *like*, is a fab notes layer to which I can add text, including board dimensions, and an outline layer that contains nothing but the board outline, in addition to top, bottom, silk top, silk bottom, since my pcb production system requires both of these. Any suggestions/online resources for help? Thanks John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB layers questions
I'm using version 20080202 (because that's what's in the repo I use.) When I try to add a new layer, it refuses unless I add the layer into or above one of the three component-associated or solder-associated layers. (component, gnd-comp, vcc-comp; solder, gnd-solder, vcc-solder) Once I do that, it associates my new layer with either component or solder, even if I go to 'groups' and click on a different group number: it reverts to the layer in which it was originally created as soon as I close the prefs window. I can't reproduce this with the latest release, but you're doing the right thing... Aside from that, I also don't know how to get pcb to produce gerbers from new layers that I add. If I delete gnd-comp and add a new layer called 'outline' -- which it sticks under 'component' and associates with that group, as above -- it doesn't produce a gerber for my new layer, separate from the 'component' gerber. You need to make the new layers their own group - pcb produces one gerber per *group* not per *layer*. What I'd *like*, is a fab notes layer to which I can add text, including board dimensions, and an outline layer that contains nothing but the board outline, in addition to top, bottom, silk top, silk bottom, since my pcb production system requires both of these. Common request. Don't have one yet, sorry. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB layers questions
jb...@frii.com wrote: I'm using version 20080202 (because that's what's in the repo I use.) What repo? When I try to add a new layer, it refuses unless I add the layer into or above one of the three component-associated or solder-associated layers. (component, gnd-comp, vcc-comp; solder, gnd-solder, vcc-solder) Once I do that, it associates my new layer with either component or solder, even if I go to 'groups' and click on a different group number: it reverts to the layer in which it was originally created as soon as I close the prefs window. Although your version of pcb is pretty old, this is likely not the only cause. Back, when this version was shiny and new, I never experienced the kind of problem you described. Maybe there is some Aside from that, I also don't know how to get pcb to produce gerbers from new layers that I add. If I delete gnd-comp and add a new layer called 'outline' -- which it sticks under 'component' and associates with that group, as above -- it doesn't produce a gerber for my new layer, separate from the 'component' gerber. Given, that the new layer is in the component group, this is the expected behavior. The export produces a separate gerber file for every layer group. What I'd *like*, is a fab notes layer to which I can add text, including board dimensions, and an outline layer that contains nothing but the board outline, in addition to top, bottom, silk top, silk bottom, since my pcb production system requires both of these. Note, every layer except silk and outline will contain the holes and pins in the gerbers. This is a consequence of the current concept: All layers are copper, except for special magic ones. A switch to a more generallayer concept is one of the long term goals ... Any suggestions/online resources for help? a) Edit the default layer stack in $HOME/.pcb/preferences with a text editor. The relevant lines start with groups = and layer-name- . Excerpt from my preferences: / groups = 1,2,3,c:4,5,6,s:7:8 route-styles = Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600 library-newlib = ~/geda/footprints:$PWD color-file = /home/kmk/.pcb/colors/kmk layer-name-1 = top layer-name-2 = top.-poly. layer-name-3 = top.-GND layer-name-4 = bottom layer-name-5 = bot-polyg. layer-name-6 = bot.-GND layer-name-7 = comment layer-name-8 = outline \- b) Download the current source with git and compile the application yourself to /usr/local/bin . The developers tend to refrain from using bleeding edge libraries. So you might well get away with the *.dev packages from your 2008 repo. Hope, this helps, ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20100929 released
On 4/10/2010 01:11, DJ Delorie wrote: Excellent! If you could put update the readme and built script for windows high on the priority list, it will save us much headache in the future. One way would be to directly add my script to the pcb sources. I would trim it down for building only pcb and its dependencies. Another way would be just to point the user/developer to the minipack project at http://code.google.com/p/minipack, and ask him to follow the documentation there. Which do you prefer? Cesar ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20100929 released
I prefer replacing the scripts already in pcb, to avoid confusion. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
