Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread gedau
On Mon, Apr 11, 2011 at 10:58:51AM +0530, Abhijit Kshirsagar wrote:
 1. Agree! I'd find this much more intuitive and easy to work with. The
 layers option will be a big help...

+1

I also like the ieda of dropping component/solder side, replacing it 
with whatever else that suggests one side and the other side.

 2. What would go to the outline layer? The gerber files have outlines
 for each layer right?

If your board is not rectangular, the outline layer would tell the fab 
house what shape to mill. It's sort of a hack as you draw something 
that looks copper but PCB supposed to handle it differently because the 
_name_ of the layer is outline.

Regards,

Tibor


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Stephan Boettcher
Peter Clifton pc...@cam.ac.uk writes:

 On Sun, 2011-04-10 at 19:42 -0400, DJ Delorie wrote:
 I'm pondering a minor change in pcb's defaults to give us a more
 useful default stackup.  How's this?
 
   LAYERNAME (1, top),
   LAYERNAME (2, ground),
   LAYERNAME (3, signal2),
   LAYERNAME (4, signal3),
   LAYERNAME (5, power),
   LAYERNAME (6, bottom),
   LAYERNAME (7, outline),
   LAYERNAME (8, spare),

 I'm very keen to see this change.

 The PCB+GL renderer (for example), needs layers (actually layer group
 numbers) in the correct physical order to be able to figure out how to
 render 3D views. Our current default stack is totally useless for that.

I'd very much like to not have any exporters/renderers requiring the
layers to be in physical order, since I tend to move the final order
around a lot.  My layer order is defined in the README that goes to the
board house, and little text numbers in the layers.

A layer attribute that tells Ben-mode and PCB+GL how to render the stack
may be the way to go.  

Is it really the layer order, or the group order that PCB+GL or Ben-mode
uses?

-- 
Stephan 


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread DJ Delorie


 Is it really the layer order, or the group order that PCB+GL or
 Ben-mode uses?

PCB draws in group order, not layer order.

So you can order the drawing layers as you wish, as long as the group
order is set to your stacking order.


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread DJ Delorie

 I basically agree, but why stop here and not add a Z coordinate to
 each layer?

You deleted the answer to that:

 Note that this would be an interim change until we get around to
 either a new-board-wizard or new-means-load-template.


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Gabriel Paubert
On Mon, Apr 11, 2011 at 03:20:11AM -0400, DJ Delorie wrote:
 
  I basically agree, but why stop here and not add a Z coordinate to
  each layer?
 
 You deleted the answer to that:
 
  Note that this would be an interim change until we get around to
  either a new-board-wizard or new-means-load-template.

Well, I did not really understand that paragraph. Anyeay, fine with me,
although I don't really see the interest of an interim step.

Regards,
Gabriel


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread DJ Delorie

 Well, I did not really understand that paragraph. Anyeay, fine with me,
 although I don't really see the interest of an interim step.

I.e none of us have time right now to completely rewrite how layers
work

This was a fairly quick change which should make the current PCB more
obviously usable to new users by pre-exposing some of the newer
features and setting things up to resemble reality closer.


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
 $ firefox symbol.svg

 renders a familiar looking symbol on my debian linux machine.

 So, are you thinking of making a translation in and out of gschem for all the 
 attributes
 a full symbol needs?  Embedding the attribs in the SVG?

 Then being able to morph the visual shape of a symbol with well developed 
 tools
 as inkscape and import into scribus for making a book out of it?

 That might go over well.  Using SVG as the internal format for gschem symbols 
 and pcb
 footprints might not go over so well as the current formats are more compact.

 John

Yes it's copy/paste from OrCad, dont hate me ;-)

So my short term goal is to come up with SVG semantics for symbols 
footprints that fill the following criteria;

1. Render sensibly in an un-modified browser .
2. Allow import/export to a few common EDA packages, I'm sure you know
the roll call.

Obviously switching the internal file format is a huge effort and I
wouldn't presume to suggest that at this point.


Andrew


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Ethan Swint

On 04/10/2011 04:55 PM, Andrew Seddon wrote:

I am exploring the idea of using the Scalable Vector Graphics standard
as an EDA format.

https://github.com/seddona/svgparts

Would be interested in your thoughts, there's a little more
explanation on my blog.

You might want to check out Fritzing (fritzing.org).  It targets 
non-EEs, but they have all of their graphics in SVG.




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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
 The idea of basing future formats on SVG has been thought of, floated,
 and discussed before now. I don't recall whether any conclusions were
 reached. I personally have mixed feelings, but am leaning towards the
 the thought that it is a good idea - but with a healthy dose of
 uneasiness about it as well.

 When I designed path support in gschem, I deliberately made the path
 syntax compatible / identical to SVG paths in case we went down this
 route at a later stage, and that so more complex paths could be drawn in
 a graphics program, then copy+pasted from an SVG file.

 libgeda only saves (and guarantees to load) simple line and bezier curve
 based paths, but an implementation detail (due to code re-use from
 librsvg), it can actually read any legal SVG path in its path primitive.
 When saving, it always converts that out to simple lines and beziers.


 I'm not as convinced of the idea for PCB layouts / footprints. I'm just
 not certain the drawing model is constrained enough. to match real world
 geometry demands.

 The main niggle is that SVG is more expressive than a generic PCB layer.
 Things like colours and gradient fills are just not meaningful in
 copper. That means we need to act intelligently if something adds those.
 Supporting complex geometry primitives which SVG would bring also means
 internal processing in PCB might get more difficult.

 --
 Peter Clifton

Yes I see some work was done into an XML file format before, will try
and dig up the SVG discussion. I cant see any real technical benefit
to gEDA in using SVG to be honest.

The benefit is the warm fuzzy feeling your average hardware
developer/pcb designer would get when they double click on the file
and a nice representation opens up in the browser. My premise is that
this alone would increase adoption of the format and any tools which
use it. There are also knock on benefits in terms of communicating
design intent to production houses etc.

The hard part is going to be constraining and augmenting SVG so as to
produce a dialect which can;

1. Be translated to common EDA formats with relatively simple algorithms
2. Display nicely on standard SVG viewers
3. Be easily to manipulate by tools working natively in the format
(this is probably implicit in 1 though)

Keen to hear why this idea sucks!
---
Andrew


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
 $ firefox symbol.svg

 renders a familiar looking symbol on my debian linux machine.

 So, are you thinking of making a translation in and out of gschem for all the 
 attributes
 a full symbol needs?  Embedding the attribs in the SVG?

 Then being able to morph the visual shape of a symbol with well developed 
 tools
 as inkscape and import into scribus for making a book out of it?

 That might go over well.  Using SVG as the internal format for gschem symbols 
 and pcb
 footprints might not go over so well as the current formats are more compact.

 John

Yes it's copy/paste from OrCad, dont hate me ;-)

So my short term goal is to come up with SVG semantics for symbols 
footprints that fill the following criteria;

1. Render sensibly in an un-modified browser .
2. Allow import/export to a few common EDA packages, I'm sure you know
the roll call.

Obviously switching the internal file format is a huge effort and I
wouldn't presume to suggest that at this point.


Andrew


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gEDA-user: Fwd: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
 The idea of basing future formats on SVG has been thought of, floated,
 and discussed before now. I don't recall whether any conclusions were
 reached. I personally have mixed feelings, but am leaning towards the
 the thought that it is a good idea - but with a healthy dose of
 uneasiness about it as well.

 When I designed path support in gschem, I deliberately made the path
 syntax compatible / identical to SVG paths in case we went down this
 route at a later stage, and that so more complex paths could be drawn in
 a graphics program, then copy+pasted from an SVG file.

 libgeda only saves (and guarantees to load) simple line and bezier curve
 based paths, but an implementation detail (due to code re-use from
 librsvg), it can actually read any legal SVG path in its path primitive.
 When saving, it always converts that out to simple lines and beziers.


 I'm not as convinced of the idea for PCB layouts / footprints. I'm just
 not certain the drawing model is constrained enough. to match real world
 geometry demands.

 The main niggle is that SVG is more expressive than a generic PCB layer.
 Things like colours and gradient fills are just not meaningful in
 copper. That means we need to act intelligently if something adds those.
 Supporting complex geometry primitives which SVG would bring also means
 internal processing in PCB might get more difficult.

 --
 Peter Clifton

Yes I see some work was done into an XML file format before, will try
and dig up the SVG discussion. I cant see any real technical benefit
to gEDA in using SVG to be honest.

The benefit is the warm fuzzy feeling your average hardware
developer/pcb designer would get when they double click on the file
and a nice representation opens up in the browser. My premise is that
this alone would increase adoption of the format and any tools which
use it. There are also knock on benefits in terms of communicating
design intent to production houses etc.

The hard part is going to be constraining and augmenting SVG so as to
produce a dialect which can;

1. Be translated to common EDA formats with relatively simple algorithms
2. Display nicely on standard SVG viewers
3. Be easily to manipulate by tools working natively in the format
(this is probably implicit in 1 though)

Keen to hear why this idea sucks!
---
Andrew


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 13:05 +0100, Andrew Seddon wrote:

 1. Be translated to common EDA formats with relatively simple algorithms
 2. Display nicely on standard SVG viewers
 3. Be easily to manipulate by tools working natively in the format
 (this is probably implicit in 1 though)
 
 Keen to hear why this idea sucks!

It doesn't.

Some challenges to be met though.

If you make schematics == SVG files, you need to ensure that opening and
saving from an SVG editor (e.g. Inkscape) won't break the data within.

Gschem currently uses special primitives to mark connectivity - nets,
pins, buses etc.. I'm not quite clear how that can be mapped to SVG in a
way which doesn't loose that information when edited outside of the EDA
tool.

Perhaps 2x way is too much to hope for though.. and we can just rely on
the fact our files will render as an SVG. XCircuit does this with
postscript files.

Btw - I have a branch lurking about which emits SVG onto the clipboard
when copy+pasting within gschem. That lets you paste from gschem
straight into Inkscape. The net and pin end-cues aren't quite right with
it though.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA

2011-04-11 Thread Andrew Seddon
You might want to check out Fritzing (fritzing.org).  It targets
 non-EEs, but they have all of their graphics in SVG.

Great link, I havent seen this project before. They have some usefull
info on SVG in this context, particularly the use of
http://www.cheetahtemplate.org/ .

A lot of their issues stem from trying to import SVG's made by generic
drawing packages.

I'm more interested in keeping the editing to domain specific tools
but allow viewing in general purpose packages.

p.s sorry for the double post earlier, I do some funky email routing
and got confused!


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
Yeah I think allowing a file to be saved by a general purpose tool
will be really tricky, as we'd have to account for everything that
might happen. Inkscape does weird stuff to SVG's even if you just open
and save straight away.

I dont really think that mode of operation is super useful anyway. I
cant imagine wanting to edit a pcb/schematic in Inkscape any time
soon, though it would be nice for say drawing a logo or something. I'd
say that kind of support would be a longer term goal.

I suppose my sole purpose for SVG right now is the warm fuzzy feeling
of viewing in a browser :-)



On Mon, Apr 11, 2011 at 2:07 PM, Peter Clifton pc...@cam.ac.uk wrote:
 On Mon, 2011-04-11 at 13:05 +0100, Andrew Seddon wrote:

 1. Be translated to common EDA formats with relatively simple algorithms
 2. Display nicely on standard SVG viewers
 3. Be easily to manipulate by tools working natively in the format
 (this is probably implicit in 1 though)

 Keen to hear why this idea sucks!

 It doesn't.

 Some challenges to be met though.

 If you make schematics == SVG files, you need to ensure that opening and
 saving from an SVG editor (e.g. Inkscape) won't break the data within.

 Gschem currently uses special primitives to mark connectivity - nets,
 pins, buses etc.. I'm not quite clear how that can be mapped to SVG in a
 way which doesn't loose that information when edited outside of the EDA
 tool.

 Perhaps 2x way is too much to hope for though.. and we can just rely on
 the fact our files will render as an SVG. XCircuit does this with
 postscript files.

 Btw - I have a branch lurking about which emits SVG onto the clipboard
 when copy+pasting within gschem. That lets you paste from gschem
 straight into Inkscape. The net and pin end-cues aren't quite right with
 it though.

 --
 Peter Clifton

 Electrical Engineering Division,
 Engineering Department,
 University of Cambridge,
 9, JJ Thomson Avenue,
 Cambridge
 CB3 0FA

 Tel: +44 (0)7729 980173 - (No signal in the lab!)
 Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Stefan Salewski
On Sun, 2011-04-10 at 21:55 +0100, Andrew Seddon wrote:
 I am exploring the idea of using the Scalable Vector Graphics standard
 as an EDA format.
 
 https://github.com/seddona/svgparts
 
 Would be interested in your thoughts, there's a little more
 explanation on my blog.
 

What would be the benefit of SVG?

Arbitrary symbol sizes? We can scale our current symbols already, but a
schematic with very many different symbol sizes will look strange.
Indeed limited scaling may be fine, ie. scaling our 900 units long
resistor to 800 or 1000 units length -- but pins should always end on a
100 grid multiple. (no that is not really needed to connect nets, but
for ordered look.)  

Currently SVG export should be a trivial task due to cairo -- similar to
PS and PDF export.

Filled SVG paths are fine, we have it, still without editing support.

Do we need other fancy graphics? I do not think so. Schematics design is
not really art work.

If we really want full SVG, we may consider a Schematic Mode for
Inkscape. But Inkscape is really a large, complex tool.

If it is possible to embedd all the elelectronics stuff like
attributes, net connection, slots, ... in SVG file, then it may be OK.
But the effort -- it is similar to a complete rewrite of gschem. And a
rewrite -- again C and guile and GTK?

PS:
We may consider using inkscapes svg icon set for geda/pcb. Inkspape is
GPL, so it should be OK. You may look at files 

/usr/share/inkscape/icons/icons.svg
/usr/share/inkscape/icons/tango_icons.svg

Very nice icon set, I intend using it for my plain ruby gschem clone.

Best regards,

Stefan Salewski




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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
 On Sun, 2011-04-10 at 21:55 +0100, Andrew Seddon wrote:
 I am exploring the idea of using the Scalable Vector Graphics standard
 as an EDA format.

 https://github.com/seddona/svgparts

 Would be interested in your thoughts, there's a little more
 explanation on my blog.


 What would be the benefit of SVG?

 Arbitrary symbol sizes? We can scale our current symbols already, but a
 schematic with very many different symbol sizes will look strange.
 Indeed limited scaling may be fine, ie. scaling our 900 units long
 resistor to 800 or 1000 units length -- but pins should always end on a
 100 grid multiple. (no that is not really needed to connect nets, but
 for ordered look.)

 Currently SVG export should be a trivial task due to cairo -- similar to
 PS and PDF export.

 Filled SVG paths are fine, we have it, still without editing support.

 Do we need other fancy graphics? I do not think so. Schematics design is
 not really art work.

 If we really want full SVG, we may consider a Schematic Mode for
 Inkscape. But Inkscape is really a large, complex tool.

 If it is possible to embedd all the elelectronics stuff like
 attributes, net connection, slots, ... in SVG file, then it may be OK.
 But the effort -- it is similar to a complete rewrite of gschem. And a
 rewrite -- again C and guile and GTK?

 PS:
 We may consider using inkscapes svg icon set for geda/pcb. Inkspape is
 GPL, so it should be OK. You may look at files

 /usr/share/inkscape/icons/icons.svg
 /usr/share/inkscape/icons/tango_icons.svg

 Very nice icon set, I intend using it for my plain ruby gschem clone.

 Best regards,

 Stefan Salewski




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So I think it might help to limit the scope of my intent initially to
library parts. I'd like to create a truly vendor neutral, widely
supported EDA library format, and the only way I see to do that is to
piggy back on a format much larger than anything the EDA industry
could ever create in isolation.

I'm actually thinking more of a direct convert from the gEDA library
files so as to maintain design intent, rather than ripping from the
graphics layer.


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Stephan Boettcher
Peter Clifton pc...@cam.ac.uk writes:

 On Mon, 2011-04-11 at 13:05 +0100, Andrew Seddon wrote:

 1. Be translated to common EDA formats with relatively simple algorithms
 2. Display nicely on standard SVG viewers
 3. Be easily to manipulate by tools working natively in the format
 (this is probably implicit in 1 though)
 
 Keen to hear why this idea sucks!

 It doesn't.

 Some challenges to be met though.

 If you make schematics == SVG files, you need to ensure that opening and
 saving from an SVG editor (e.g. Inkscape) won't break the data within.

 Gschem currently uses special primitives to mark connectivity - nets,
 pins, buses etc.. I'm not quite clear how that can be mapped to SVG in a
 way which doesn't loose that information when edited outside of the EDA
 tool.

Does SVG/Inkscape support layers? It sure does. I recently looked at an
svg export from gerbv, and I found it pretty useless.  I found one
object inside, and when I ungrouped that object I found all the little
pieces, but not grouped into layers.  And no transparency.

A schematic could require nets and pins to be in special layers.  When
Inkscape messes with the file, as long as the layers are preseved the
connectivity should survive.  All non-schematic layers are graphics.

So it should be easy to map the semantics of gschem to an svg subset,
allow gschem to export to such a format.  On open/import, the schematic
is extracted from those layers/groups that have a meaning, all the rest
is preserved as graphics, maybe with limited edit sorrut, like move and
delete.

If this shall become the primary format, I'd first insist on really good
native scripting support, since external schematics scripting on svg is
no fun.

-- 
Stephan


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread John Griessen

On 04/11/2011 02:11 AM, Gabriel Paubert wrote:

consider layers with the same
Z coordinate as a layer group


OK, that could be used for stackup, and also farther along,
Z is a general axis designator, so would become Z position
in the stackup, so your group number attrib
should be some other name than Z.  Why not add it?  Because DJ is doing a
minor change and has no time budget for a sweeping overhaul.

John


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA

2011-04-11 Thread John Griessen

On 04/11/2011 08:08 AM, Andrew Seddon wrote:

I'm more interested in keeping the editing to domain specific tools
but allow viewing in general purpose packages.


Sounds good.

On 04/11/2011 08:18 AM, Andrew Seddon wrote:
 I suppose my sole purpose for SVG right now is the warm fuzzy feeling
 of viewing in a browser:-)

Another benefit is compact file size for publishing and documentation  purposes.

On 04/11/2011 08:43 AM, Andrew Seddon wrote:
 I'd like to create a truly vendor neutral, widely
 supported EDA library format

A key part of that goal is specifying what are legal shapes, so vendors create
shapes we can use directly, instead of having to approximate them just to load 
them
into PCB, Fritzing, Kicad for example.  In other words, no bezier curve trace 
bends
unless your tool can handle them.  No bezier curve bends in footprints.

John


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gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Kovacs Levente
I'm currently designing a power amplifier for the HF (3-30MHz) radio
band.

I am selecting capacitors for the low pass harmonic filter bank at the output.
My question is what kind of capacitors should I use? I apply not more then
100V of say 30MHz maximum.

My best bet is to use X7R capacitors with as much DC voltage rating as I can
get. I don't know if there's any connection between the DC and AC losses.


Thanks,
Levente

-- 
Kovacs Levente leventel...@gmail.com
Voice: +36705071002




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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Uwe Bonnes
 Kovacs == Kovacs Levente leventel...@gmail.com writes:

Kovacs I'm currently designing a power amplifier for the HF (3-30MHz)
Kovacs radio band.

Kovacs I am selecting capacitors for the low pass harmonic filter bank
Kovacs at the output.  My question is what kind of capacitors should I
Kovacs use? I apply not more then 100V of say 30MHz maximum.

Kovacs My best bet is to use X7R capacitors with as much DC voltage
Kovacs rating as I can get. I don't know if there's any connection
Kovacs between the DC and AC losses.


What value do you need? Try NP0/COG type, even if substantial more
expensive. I guess the X ceramic will introduce more harmonics than it will
filter out...
-- 
Uwe Bonnesb...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
- Tel. 06151 162516  Fax. 06151 164321 --


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Andy Fierman
Uwe is spot on.

The capacitance vs. voltage of the X7R dielectric is not very good.
NP0/COG are usually specified for precision timing and filter
applications.

NP0/COG also have a much lower temperature coefficient.

Andy.


On 11 April 2011 15:58, Uwe Bonnes
b...@elektron.ikp.physik.tu-darmstadt.de wrote:
 Kovacs == Kovacs Levente leventel...@gmail.com writes:

    Kovacs I'm currently designing a power amplifier for the HF (3-30MHz)
    Kovacs radio band.

    Kovacs I am selecting capacitors for the low pass harmonic filter bank
    Kovacs at the output.  My question is what kind of capacitors should I
    Kovacs use? I apply not more then 100V of say 30MHz maximum.

    Kovacs My best bet is to use X7R capacitors with as much DC voltage
    Kovacs rating as I can get. I don't know if there's any connection
    Kovacs between the DC and AC losses.


 What value do you need? Try NP0/COG type, even if substantial more
 expensive. I guess the X ceramic will introduce more harmonics than it will
 filter out...
 --
 Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de

 Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
 - Tel. 06151 162516  Fax. 06151 164321 --


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Kovacs Levente
On Mon, 11 Apr 2011 16:58:37 +0200
Uwe Bonnes
b...@elektron.ikp.physik.tu-darmstadt.de
wrote:

 What value do you need? Try NP0/COG type, even if substantial more

120pf ... 1.5nF

 expensive. I guess the X ceramic will introduce more harmonics than
 it will filter out...

Thanx for the hint.

-- 
Kovacs Levente leventel...@gmail.com
Voice: +36705071002




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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Steven Michalske
This is what I see as a benefit. If you go to a vendor's website you
will find one or two EDA footprint and symbol files.  But nothing that
was a bell ringer for commonality.  It would be nice to have a
universal starting point.

There is EDIF but I see EDIF as not being so useful, i think they
tried to do too many things, and failed to get them all correct. As
one file format to rule them all.

I rather see svg symbol format, svg footprint format, and svg format.

Steve


On Mon, Apr 11, 2011 at 9:43 PM, Andrew Seddon and...@seddon.me wrote:
 On Sun, 2011-04-10 at 21:55 +0100, Andrew Seddon wrote:
 I am exploring the idea of using the Scalable Vector Graphics standard
 as an EDA format.

 https://github.com/seddona/svgparts

 Would be interested in your thoughts, there's a little more
 explanation on my blog.


 What would be the benefit of SVG?

 Arbitrary symbol sizes? We can scale our current symbols already, but a
 schematic with very many different symbol sizes will look strange.
 Indeed limited scaling may be fine, ie. scaling our 900 units long
 resistor to 800 or 1000 units length -- but pins should always end on a
 100 grid multiple. (no that is not really needed to connect nets, but
 for ordered look.)

 Currently SVG export should be a trivial task due to cairo -- similar to
 PS and PDF export.

 Filled SVG paths are fine, we have it, still without editing support.

 Do we need other fancy graphics? I do not think so. Schematics design is
 not really art work.

 If we really want full SVG, we may consider a Schematic Mode for
 Inkscape. But Inkscape is really a large, complex tool.

 If it is possible to embedd all the elelectronics stuff like
 attributes, net connection, slots, ... in SVG file, then it may be OK.
 But the effort -- it is similar to a complete rewrite of gschem. And a
 rewrite -- again C and guile and GTK?

 PS:
 We may consider using inkscapes svg icon set for geda/pcb. Inkspape is
 GPL, so it should be OK. You may look at files

 /usr/share/inkscape/icons/icons.svg
 /usr/share/inkscape/icons/tango_icons.svg

 Very nice icon set, I intend using it for my plain ruby gschem clone.

 Best regards,

 Stefan Salewski




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 So I think it might help to limit the scope of my intent initially to
 library parts. I'd like to create a truly vendor neutral, widely
 supported EDA library format, and the only way I see to do that is to
 piggy back on a format much larger than anything the EDA industry
 could ever create in isolation.

 I'm actually thinking more of a direct convert from the gEDA library
 files so as to maintain design intent, rather than ripping from the
 graphics layer.


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Steven Michalske
http://www.avx.com/SpiApps/default.asp

Some cool capacitor tools, like spicap3

Steve

On Mon, Apr 11, 2011 at 11:19 PM, Kovacs Levente leventel...@gmail.com wrote:
 On Mon, 11 Apr 2011 16:58:37 +0200
 Uwe Bonnes
 b...@elektron.ikp.physik.tu-darmstadt.de
 wrote:

 What value do you need? Try NP0/COG type, even if substantial more

 120pf ... 1.5nF

 expensive. I guess the X ceramic will introduce more harmonics than
 it will filter out...

 Thanx for the hint.

 --
 Kovacs Levente leventel...@gmail.com
 Voice: +36705071002




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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 08:18 +0200, Stephan Boettcher wrote:
 Peter Clifton pc...@cam.ac.uk writes:

 Is it really the layer order, or the group order that PCB+GL or Ben-mode
 uses?

The group numbering - and I don't see any reason why we can't stipulate
that is the rendering sequence.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread DJ Delorie

 The group numbering - and I don't see any reason why we can't stipulate
 that is the rendering sequence.

I think we decided that a while back.  The group order *is* the
stacking order.

Now we just need to figure out how to enforce it :-)


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread John Doty

On Apr 11, 2011, at 9:19 AM, Kovacs Levente wrote:

 On Mon, 11 Apr 2011 16:58:37 +0200
 Uwe Bonnes
 b...@elektron.ikp.physik.tu-darmstadt.de
 wrote:
 
 What value do you need? Try NP0/COG type, even if substantial more
 
 120pf ... 1.5nF

Another possibility in that range is plastic film dielectrics rather than 
ceramic.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com




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Re: gEDA-user: OT?: Altium (Protel) Relocates From Sydney Australia to Shanghai China

2011-04-11 Thread Evan Foss
Yea, I second the last part of the. If you have a large library of
parts done in a particular tool you will have to redraft all of them.
That is not good.

On Sun, Apr 10, 2011 at 12:19 AM,  ge...@igor2.repo.hu wrote:
 On Sat, Apr 09, 2011 at 10:51:00AM -0400, Bob Paddock wrote:

 snip

 The developers always wanted to know the fastest way to do something
 and had no interest in learning the best way to do something.

 Lately I had the chance to work together with professional software
 developers from multiple different western countries, and I have to tell
 you it is not china-specific. I think it's a generic big-company problem
 that you will see all around the world.

 Those developers work for money, not for joy, so fastest way is the only
 way for them, especially combined with the pressure from the management
 to deliver at deadline _and_ save cost (do it with less developers).


 In the end the company did ship Cellphones that some how did work.  Is
 that all that maters?  I hope not...
 Is this one company representative of all development in China?  I hope 
 not...

 because of the above, in that big-copmpany environment it's very common
 to use duct tape all around. If there is a requirement and some well
 defined method that will be used to tes if the requirement is met at the
 end, you can be almost sure the developer will implement something that
 will work only for that one test case and will ignore the general idea
 behind th erequirement or the test case. This how sleep(1) kind of
 fixes end up in network code.

 I don't say it's because those developers are stupid or even
 inexperienced. It's more like the whole company culture. If you want to
 make things properly in such an environment, it will take more time and
 the feedback will not be cool, you made some really robust, reusable
 code but next time please spend less on the golden knobs and
 concentrate on the task. Thus the best developers either leave after a
 while (either to other company or promoted to management) or they will
 start following the lazy methods knowing that it's not good, but i have
 no choice.

 Hopefully  this will drive a lot more interest to gEDA and PCB.

 Honestly, I doubt. At the end once the user got used to whichever tool,
 he won't switch easily even if quality starts to go down.

 Regards,

 Tibor


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-- 
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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread John Doty

On Apr 11, 2011, at 9:55 AM, John Doty wrote:

 
 On Apr 11, 2011, at 9:19 AM, Kovacs Levente wrote:
 
 On Mon, 11 Apr 2011 16:58:37 +0200
 Uwe Bonnes
 b...@elektron.ikp.physik.tu-darmstadt.de
 wrote:
 
 What value do you need? Try NP0/COG type, even if substantial more
 
 120pf ... 1.5nF
 
 Another possibility in that range is plastic film dielectrics rather than 
 ceramic.

Oh, and one more issue. AC is much more stressful on a capacitor than DC. It's 
best to choose a capacitor with an AC voltage rating. If you can't, a common 
rule of thumb is to choose one with a DC voltage rating 3 times the AC RMS.

Classically, this has been an application for mica capacitors, but they're 
relatively rare these days.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com




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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread John Doty
And one more note.

On Apr 11, 2011, at 9:09 AM, Andy Fierman wrote:

 The capacitance vs. voltage of the X7R dielectric is not very good.
 NP0/COG are usually specified for precision timing and filter
 applications.
 
 NP0/COG also have a much lower temperature coefficient.

NPO/C0G is a temperature coefficient spec. Usually, a low temperature 
coefficient ceramic will also have low dielectric hysteresis. However, I have 
encountered exceptions. It's preferable to use capacitors where the 
manufacturer's data sheet gives a limit on hysteresis. A common spec for a 
good capacitor is 0.1% hysteresis.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com




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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Uwe Bonnes
 Kovacs == Kovacs Levente leventel...@gmail.com writes:

Kovacs On Mon, 11 Apr 2011 16:58:37 +0200 Uwe Bonnes
Kovacs b...@elektron.ikp.physik.tu-darmstadt.de wrote:

 What value do you need? Try NP0/COG type, even if substantial more

Kovacs 120pf ... 1.5nF

In this range you will easily find better types than X7R...
-- 
Uwe Bonnesb...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
- Tel. 06151 162516  Fax. 06151 164321 --


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Stefan Salewski
On Mon, 2011-04-11 at 23:18 +0800, Steven Michalske wrote:
 This is what I see as a benefit. If you go to a vendor's website you
 will find one or two EDA footprint and symbol files.  But nothing that
 was a bell ringer for commonality.  It would be nice to have a
 universal starting point.
 
 There is EDIF but I see EDIF as not being so useful, i think they
 tried to do too many things, and failed to get them all correct. As
 one file format to rule them all.
 
 I rather see svg symbol format, svg footprint format, and svg format.
 
 Steve

For svg footprints we have two problems: We always have to convert it to
old gerber format before sending to manufacturer. (Or to another format
which manufacturers support, I think no one currently supports svg.) And
if we scale footprints, we should not to forget to scale our (real word)
components with the same factor. Of course, would be fine: If our case
is too small for our device, just scale the whole thing down. :-)




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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Steven Michalske
On Tue, Apr 12, 2011 at 12:28 AM, Stefan Salewski m...@ssalewski.de wrote:
 On Mon, 2011-04-11 at 23:18 +0800, Steven Michalske wrote:
 This is what I see as a benefit. If you go to a vendor's website you
 will find one or two EDA footprint and symbol files.  But nothing that
 was a bell ringer for commonality.  It would be nice to have a
 universal starting point.

 There is EDIF but I see EDIF as not being so useful, i think they
 tried to do too many things, and failed to get them all correct. As
 one file format to rule them all.

 I rather see svg symbol format, svg footprint format, and svg format.

 Steve

 For svg footprints we have two problems: We always have to convert it to
 old gerber format before sending to manufacturer. (Or to another format
 which manufacturers support, I think no one currently supports svg.) And
 if we scale footprints, we should not to forget to scale our (real word)
 components with the same factor. Of course, would be fine: If our case
 is too small for our device, just scale the whole thing down. :-)



Same exists for out current footprints,  they need to be converted to
gerbers via pcb.

basically

svg - converter - pcb fp format - pcb - gerber
--or--
pcb fp - svg
--or--
vendor x - converter - svg - converter - pcb fp

It would be nice to scale the solder masks and the solder paste
layers.  for process dependencies.

Steve


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Steven Michalske
On Mon, Apr 11, 2011 at 11:35 PM, DJ Delorie d...@delorie.com wrote:


 Now we just need to figure out how to enforce it :-)

With a stick!


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Re: gEDA-user: OT?: Altium (Protel) Relocates From Sydney Australia to Shanghai China

2011-04-11 Thread Andrew Seddon
On Mon, Apr 11, 2011 at 4:57 PM, Evan Foss evanf...@gmail.com wrote:
 Yea, I second the last part of the. If you have a large library of
 parts done in a particular tool you will have to redraft all of them.
 That is not good.

 On Sun, Apr 10, 2011 at 12:19 AM,  ge...@igor2.repo.hu wrote:
 On Sat, Apr 09, 2011 at 10:51:00AM -0400, Bob Paddock wrote:

 snip

 The developers always wanted to know the fastest way to do something
 and had no interest in learning the best way to do something.

 Lately I had the chance to work together with professional software
 developers from multiple different western countries, and I have to tell
 you it is not china-specific. I think it's a generic big-company problem
 that you will see all around the world.

 Those developers work for money, not for joy, so fastest way is the only
 way for them, especially combined with the pressure from the management
 to deliver at deadline _and_ save cost (do it with less developers).


 In the end the company did ship Cellphones that some how did work.  Is
 that all that maters?  I hope not...
 Is this one company representative of all development in China?  I hope 
 not...

 because of the above, in that big-copmpany environment it's very common
 to use duct tape all around. If there is a requirement and some well
 defined method that will be used to tes if the requirement is met at the
 end, you can be almost sure the developer will implement something that
 will work only for that one test case and will ignore the general idea
 behind th erequirement or the test case. This how sleep(1) kind of
 fixes end up in network code.

 I don't say it's because those developers are stupid or even
 inexperienced. It's more like the whole company culture. If you want to
 make things properly in such an environment, it will take more time and
 the feedback will not be cool, you made some really robust, reusable
 code but next time please spend less on the golden knobs and
 concentrate on the task. Thus the best developers either leave after a
 while (either to other company or promoted to management) or they will
 start following the lazy methods knowing that it's not good, but i have
 no choice.

 Hopefully  this will drive a lot more interest to gEDA and PCB.

 Honestly, I doubt. At the end once the user got used to whichever tool,
 he won't switch easily even if quality starts to go down.

 Regards,

 Tibor


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 http://evanfoss.googlepages.com/


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Altium have some great ideas but their execution is dire. They also
spread themselves very thin by trying to encapsulate the whole
embedded dev (Processor/FPGA) process into one tool, personally I
think this was a huge mistake.

As they've been loosing money for the last 10 years I cant say the
move to China is shocking but I cant see it helping their execution
woes. They're also hampered by a massive legacy code base in Delphi
which essentially has no eco-system any more.


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
I think EDIF pretty much died, no party had a vested interest in
making it work and the standard is a bloated mess.

SVG represents a real opportunity to piggy back on the much more
dominant force of the interwebs.

On Mon, Apr 11, 2011 at 4:18 PM, Steven Michalske smichal...@gmail.com wrote:
 This is what I see as a benefit. If you go to a vendor's website you
 will find one or two EDA footprint and symbol files.  But nothing that
 was a bell ringer for commonality.  It would be nice to have a
 universal starting point.

 There is EDIF but I see EDIF as not being so useful, i think they
 tried to do too many things, and failed to get them all correct. As
 one file format to rule them all.

 I rather see svg symbol format, svg footprint format, and svg format.

 Steve


 On Mon, Apr 11, 2011 at 9:43 PM, Andrew Seddon and...@seddon.me wrote:
 On Sun, 2011-04-10 at 21:55 +0100, Andrew Seddon wrote:
 I am exploring the idea of using the Scalable Vector Graphics standard
 as an EDA format.

 https://github.com/seddona/svgparts

 Would be interested in your thoughts, there's a little more
 explanation on my blog.


 What would be the benefit of SVG?

 Arbitrary symbol sizes? We can scale our current symbols already, but a
 schematic with very many different symbol sizes will look strange.
 Indeed limited scaling may be fine, ie. scaling our 900 units long
 resistor to 800 or 1000 units length -- but pins should always end on a
 100 grid multiple. (no that is not really needed to connect nets, but
 for ordered look.)

 Currently SVG export should be a trivial task due to cairo -- similar to
 PS and PDF export.

 Filled SVG paths are fine, we have it, still without editing support.

 Do we need other fancy graphics? I do not think so. Schematics design is
 not really art work.

 If we really want full SVG, we may consider a Schematic Mode for
 Inkscape. But Inkscape is really a large, complex tool.

 If it is possible to embedd all the elelectronics stuff like
 attributes, net connection, slots, ... in SVG file, then it may be OK.
 But the effort -- it is similar to a complete rewrite of gschem. And a
 rewrite -- again C and guile and GTK?

 PS:
 We may consider using inkscapes svg icon set for geda/pcb. Inkspape is
 GPL, so it should be OK. You may look at files

 /usr/share/inkscape/icons/icons.svg
 /usr/share/inkscape/icons/tango_icons.svg

 Very nice icon set, I intend using it for my plain ruby gschem clone.

 Best regards,

 Stefan Salewski




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 So I think it might help to limit the scope of my intent initially to
 library parts. I'd like to create a truly vendor neutral, widely
 supported EDA library format, and the only way I see to do that is to
 piggy back on a format much larger than anything the EDA industry
 could ever create in isolation.

 I'm actually thinking more of a direct convert from the gEDA library
 files so as to maintain design intent, rather than ripping from the
 graphics layer.


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread Ben Jackson
On Mon, Apr 11, 2011 at 04:55:15PM +0200, Kovacs Levente wrote:
 
 I am selecting capacitors for the low pass harmonic filter bank at the output.
 My question is what kind of capacitors should I use? I apply not more then
 100V of say 30MHz maximum.

The classic cap in this application is silver mica.  High voltage
capacity, super tolerance compared to other types (to 0.25%! but commonly
1% or 2%).  The only ones I have are enormous bulky things with dot
style marking.  A quick search on Mouser turns up only SMT ones...

 My best bet is to use X7R capacitors with as much DC voltage rating as I can
 get. I don't know if there's any connection between the DC and AC losses.

Not X7R.

-- 
Ben Jackson AD7GD
b...@ben.com
http://www.ben.com/


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 18:14 +0100, Andrew Seddon wrote:
 I think EDIF pretty much died, no party had a vested interest in
 making it work and the standard is a bloated mess.
 
 SVG represents a real opportunity to piggy back on the much more
 dominant force of the interwebs.

TBH, I've not seen SVG anywhere on the main-stream internet. Linux
desktops use SVG a lot for desktop graphics, but it really isn't as
prevalent as it should be.

What excuse is there for OpenOffice / LibreOffice being so appallingly
bad at working with SVG files?

Why can't we paste them right into TeX, LaTeX or whatever? They are all
open source, yet this open format is not supported.

Whilst SVG is an obvious open vector standard to support - not a lot of
things actually work well with it sadly.

I was pleasantly surprised to see FreeCAD saves out SVG for its CAD
exports - but I would have expected (and half preferred) PDF. I'm
getting used to the amazing ease with which tools like Inkscape can open
PS and PDF files, then edit them as vector graphics.



-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 18:14 +0100, Andrew Seddon wrote:
 I think EDIF pretty much died, no party had a vested interest in
 making it work and the standard is a bloated mess.
 
 SVG represents a real opportunity to piggy back on the much more
 dominant force of the interwebs.

TBH, I've not seen SVG anywhere on the main-stream internet. Linux
desktops use SVG a lot for desktop graphics, but it really isn't as
prevalent as it should be.

What excuse is there for OpenOffice / LibreOffice being so appallingly
bad at working with SVG files?

Why can't we paste them right into TeX, LaTeX or whatever? They are all
open source, yet this open format is not supported.

Whilst SVG is an obvious open vector standard to support - not a lot of
things actually work well with it sadly.

I was pleasantly surprised to see FreeCAD saves out SVG for its CAD
exports - but I would have expected (and half preferred) PDF. I'm
getting used to the amazing ease with which tools like Inkscape can open
PS and PDF files, then edit them as vector graphics.



-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Kai-Martin Knaak
Peter Clifton wrote:

 TBH, I've not seen SVG anywhere on the main-stream internet.

Wikipedia prefers SVG for anything that is not a photograph. The servers
render SVG graphics to PNG as needed before handing it out to the browser.


 Linux
 desktops use SVG a lot for desktop graphics, but it really isn't as
 prevalent as it should be.

Microsoft and Apple do not like 


 What excuse is there for OpenOffice / LibreOffice being so appallingly
 bad at working with SVG files?

Actually, SVG import is among the first features of libreoffice beyond 
openoffice:
http://www.libreoffice.org/download/new-features-and-fixes/


 Why can't we paste them right into TeX, LaTeX or whatever? They are all
 open source, yet this open format is not supported.

IMHO, latex development reached a state of virtual feature freeze before
SVG became a viable alternative.


 Whilst SVG is an obvious open vector standard to support - not a lot of
 things actually work well with it sadly.

The number one open source vector drawing application, inkscape uses SVG
as its native file format. This alone would be reason enough to seriously
consider SVG as an import/export file format.

---)kaimartin(---
-- 
Kai-Martin Knaak  tel: +49-511-762-2895
Universität Hannover, Inst. für Quantenoptik  fax: +49-511-762-2211 
Welfengarten 1, 30167 Hannover   http://www.iqo.uni-hannover.de
GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get



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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Andrew Seddon
 TBH, I've not seen SVG anywhere on the main-stream internet. Linux
 desktops use SVG a lot for desktop graphics, but it really isn't as
 prevalent as it should be.

The latest version of every major Desktop/Mobile browser's support is
good enough for what we want to do. Support across the web (as in
random people arriving at your site) is approaching 50%. Lots of AJAX
web apps now use SVG for charting etc.

It's a done deal, SVG is the standard for 2D vector graphics for the
next x years.

@Kai, Chrome actually renders SVG inside an image tag to my delight!

Anyway I'm going to stop talking about this and go and write some code now! haha

@Peter, not sure if you got my email but definitely up for meeting,
let me know when's good for you.

Andrew


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Larry Doolittle
On Mon, Apr 11, 2011 at 08:55:12PM +0200, Kai-Martin Knaak wrote:
 Peter Clifton wrote:
 
  TBH, I've not seen SVG anywhere on the main-stream internet.
 
 Wikipedia prefers SVG for anything that is not a photograph. The servers
 render SVG graphics to PNG as needed before handing it out to the browser.
 
 
  Linux
  desktops use SVG a lot for desktop graphics, but it really isn't as
  prevalent as it should be.
 
 Microsoft and Apple do not like 
 
 
  What excuse is there for OpenOffice / LibreOffice being so appallingly
  bad at working with SVG files?
 
 Actually, SVG import is among the first features of libreoffice beyond 
 openoffice:
 http://www.libreoffice.org/download/new-features-and-fixes/
 
 
  Why can't we paste them right into TeX, LaTeX or whatever? They are all
  open source, yet this open format is not supported.
 
 IMHO, latex development reached a state of virtual feature freeze before
 SVG became a viable alternative.

Surely you can convert SVG to EPS, which TeX/LaTeX happily embed.

Looks like UniConvertor/sK1 is the usual Free tool to script that
conversion.  Would it make any sense to leverage that software base,
and add Gerber or native gEDA/PCB to its list of import and export filters?

http://sk1project.org/modules.php?name=Productsproduct=uniconvertor

  - Larry


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Stefan Salewski
On Mon, 2011-04-11 at 07:50 -0400, Ethan Swint wrote:
 On 04/10/2011 04:55 PM, Andrew Seddon wrote:
  I am exploring the idea of using the Scalable Vector Graphics standard
  as an EDA format.
 
  https://github.com/seddona/svgparts
 
  Would be interested in your thoughts, there's a little more
  explanation on my blog.
 
 You might want to check out Fritzing (fritzing.org).  It targets 
 non-EEs, but they have all of their graphics in SVG.
 

The have a paper

http://www.svgopen.org/2009/papers/33-SVG_in_Fritzing_a_Case_Study/



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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Krzysztof Kościuszkiewicz
On Sun, Apr 10, 2011 at 11:22:54PM +0200, Markus Traidl wrote:

Actually I would like to use only the net attribute. There I could
assign net=3V3 instead of net=3V3:1.

You might have missed a recent discussion on the topic:
http://archives.seul.org/geda/user/Mar-2011/msg00074.html
-- 
Krzysztof Kościuszkiewicz
Simplicity is the ultimate sophistication -- Leonardo da Vinci


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 20:55 +0200, Kai-Martin Knaak wrote:
 Peter Clifton wrote:

  What excuse is there for OpenOffice / LibreOffice being so appallingly
  bad at working with SVG files?
 
 Actually, SVG import is among the first features of libreoffice beyond 
 openoffice:
 http://www.libreoffice.org/download/new-features-and-fixes/

The last time I tried it, support wasn't very good. Things might have
changed though, so I guess it is worth me trying again.


 The number one open source vector drawing application, inkscape uses SVG
 as its native file format. This alone would be reason enough to seriously
 consider SVG as an import/export file format.

Heck, I know Windows users who love Inkscape. I don't think there is
anything available which is remotely comparable which doesn't cost
serious money. Inkscape is awesomeness.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 20:12 +0100, Andrew Seddon wrote:
  TBH, I've not seen SVG anywhere on the main-stream internet. Linux
  desktops use SVG a lot for desktop graphics, but it really isn't as
  prevalent as it should be.
 
 The latest version of every major Desktop/Mobile browser's support is
 good enough for what we want to do. Support across the web (as in
 random people arriving at your site) is approaching 50%. Lots of AJAX
 web apps now use SVG for charting etc.
 
 It's a done deal, SVG is the standard for 2D vector graphics for the
 next x years.
 
 @Kai, Chrome actually renders SVG inside an image tag to my delight!
 
 Anyway I'm going to stop talking about this and go and write some code now! 
 haha
 
 @Peter, not sure if you got my email but definitely up for meeting,
 let me know when's good for you.

I got it, but haven't had a chance to think about when might suit. If
there is any time you're going to be around in Cambridge anyway, please
let me know.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 12:37 -0700, Larry Doolittle wrote:

 Surely you can convert SVG to EPS, which TeX/LaTeX happily embed.
 
 Looks like UniConvertor/sK1 is the usual Free tool to script that
 conversion.  Would it make any sense to leverage that software base,
 and add Gerber or native gEDA/PCB to its list of import and export filters?
 
 http://sk1project.org/modules.php?name=Productsproduct=uniconvertor

I use pdfLaTeX with LyX almost exclusively now, so my workflow is
Inkscape - PDF - LyX - pdfLaTeX.

I've come across sK1 and UniConverter before. I tried to use it to
generate EMF files for pasting into OpenOffice (from gschem's
clipboard). I can't recall what it failed to convert properly, but it
was something ;).

Each converter I tried to get into OpenOffice messed something up.
Usually it was related to text handling.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Krzysztof Kościuszkiewicz
On Sun, Apr 10, 2011 at 11:22:54PM +0200, Markus Traidl wrote:
 
 Actually I would like to use only the net attribute. There I could
 assign net=3V3 instead of net=3V3:1.
 
 I know that the :1 is that the gnetlist tool knows that the 3V3 is
 connected to pin 1.
 
 But in case of a One-Pin-Symbol the gnetlist tool could assume that
 the only net should be assigned to the only pin.

This has been asked for several times and I don't see a reason why this should
not be allowed for single pin symbols and only for pin number 1.

The patches are attached - please test and report any potential breakage.

-- 
Krzysztof Kościuszkiewicz
Simplicity is the ultimate sophistication -- Leonardo da Vinci
From 336dbb62f859a19c5078504828c8298a11d47210 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Krzysztof=20Ko=C5=9Bciuszkiewicz?= k.kosciuszkiew...@gmail.com
Date: Mon, 11 Apr 2011 23:03:12 +0200
Subject: [PATCH 1/3] gnetlist: refactor s_netattrib_net_search

Replace two loops with one by using o_attrib_search_object_attribs_by_name.
Factor out inside of the loop to a separate function,
netname_if_matching_wanted_pin.
---
 gnetlist/src/s_netattrib.c |   94 
 1 files changed, 34 insertions(+), 60 deletions(-)

diff --git a/gnetlist/src/s_netattrib.c b/gnetlist/src/s_netattrib.c
index 957735c..c8052f9 100644
--- a/gnetlist/src/s_netattrib.c
+++ b/gnetlist/src/s_netattrib.c
@@ -213,84 +213,58 @@ s_netattrib_handle (TOPLEVEL * pr_current, OBJECT * o_current,
   }
 }
 
+static char* netname_if_matching_wanted_pin (OBJECT *o_current,
+ char   *net_attr,
+ const char *wanted_pin)
+{
+  char *char_ptr = strchr (net_attr, ':');
+
+  if (char_ptr != NULL) {
+/* found a colon separating netname and list of pins */
+char *net_name = s_netattrib_extract_netname (net_attr);
+char *start_of_pinlist = char_ptr + 1;
+char *current_pin = strtok (start_of_pinlist, DELIMITERS);
+
+while (current_pin) {
+  if (strcmp (current_pin, wanted_pin) == 0)
+return net_name;
+  current_pin = strtok (NULL, DELIMITERS);
+}
+
+g_free (net_name);
+return NULL;
+  } else {
+fprintf (stderr, Got an invalid net= attrib [net=%s]\n
+ Missing : in net= attrib\n, net_attr);
+return NULL;
+  }
+}
+
 char *s_netattrib_net_search (OBJECT * o_current, char *wanted_pin)
 {
   char *value = NULL;
-  char *char_ptr = NULL;
   char *net_name = NULL;
-  char *current_pin = NULL;
-  char *start_of_pinlist = NULL;
-  char *return_value = NULL;
   int counter;
 
   if (o_current == NULL ||
   o_current-complex == NULL)
 return NULL;
 
-  /* for now just look inside the component */
-  for (counter = 0; ;) {
-value = o_attrib_search_inherited_attribs_by_name (o_current,
-   net, counter);
+  for (counter = 0; ; ++counter) {
+value = o_attrib_search_object_attribs_by_name (o_current,
+net, counter);
 if (value == NULL)
   break;
 
-counter++;
-
-char_ptr = strchr (value, ':');
-if (char_ptr == NULL) {
-  fprintf (stderr, Got an invalid net= attrib [net=%s]\n
-   Missing : in net= attrib\n, value);
-  g_free (value);
-  return NULL;
-}
-
-net_name = s_netattrib_extract_netname (value);
-
-start_of_pinlist = char_ptr + 1;
-current_pin = strtok (start_of_pinlist, DELIMITERS);
-while (current_pin  !return_value) {
-  if (strcmp (current_pin, wanted_pin) == 0) {
-return_value = net_name;
-  }
-  current_pin = strtok (NULL, DELIMITERS);
-}
+net_name = netname_if_matching_wanted_pin (o_current, value, wanted_pin);
 
 g_free (value);
-  }
-
-  /* now look outside the component */
-  for (counter = 0; ;) {
-value = o_attrib_search_attached_attribs_by_name (o_current,
-  net, counter);
-if (value == NULL)
-  break;
-
-counter++;
 
-char_ptr = strchr (value, ':');
-if (char_ptr == NULL) {
-  fprintf (stderr, Got an invalid net= attrib [net=%s]\n
-   Missing : in net= attrib\n, value);
-  g_free (value);
-  return NULL;
-}
-
-net_name = s_netattrib_extract_netname (value);
-
-start_of_pinlist = char_ptr + 1;
-current_pin = strtok (start_of_pinlist, DELIMITERS);
-while (current_pin) {
-  if (strcmp (current_pin, wanted_pin) == 0) {
-g_free (return_value);
-return net_name;
-  }
-  current_pin = strtok (NULL, DELIMITERS);
-}
-
-g_free (value);
+if (net_name != NULL)
+  return net_name;
   }
 
-  return return_value;
+  return NULL;
 }
 
 char *s_netattrib_return_netname(TOPLEVEL * pr_current, OBJECT * o_current,
-- 
1.7.4.1

From 68eeaa6103d851371b1264f24eab10a126fa97ad Mon Sep 17 00:00:00 2001
From: 

Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Larry Doolittle
On Mon, Apr 11, 2011 at 10:43:08PM +0100, Peter Clifton wrote:
 On Mon, 2011-04-11 at 12:37 -0700, Larry Doolittle wrote:
  Surely you can convert SVG to EPS, which TeX/LaTeX happily embed.
  http://sk1project.org/modules.php?name=Productsproduct=uniconvertor
 I use pdfLaTeX with LyX almost exclusively now, so my workflow is
 Inkscape - PDF - LyX - pdfLaTeX.

I didn't mention PDF, but that's relevant for the pdf(la)tex
variants that your flow uses, and sK1/UniConvertor has a PDF
output filter.

Inkscape is nice, but doesn't feel right for embedding in a Makefile.
I haven't tried UniConvertor for this purpose.

   - Larry


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Vanessa Ezekowitz
On Mon, 11 Apr 2011 02:45:18 +0200
Kai-Martin Knaak k...@lilalaser.de wrote:

 DJ Delorie wrote:
 
  
  I'm pondering a minor change in pcb's defaults to give us a more
  useful default stackup.  How's this?
  
LAYERNAME (1, top),
LAYERNAME (2, ground),
LAYERNAME (3, signal2),
LAYERNAME (4, signal3),
LAYERNAME (5, power),
LAYERNAME (6, bottom),
LAYERNAME (7, outline),
LAYERNAME (8, spare),
  
  This encompasses a few changes:
  
  1. Default to six-layer stackup.  You can ignore the signalN or
 power/ground layers for smaller boards.  This covers nearly all PCB
 users (2/4/6 layers), and the rest can edit the stackup as usual.

I like KMK's idea; I'd suggest his proposed switches establish the following:

 I like to have a comment layer just below the outline layer. In 
 this layer I put internal notes. 
[...]
 Make the default layer stack depend on options: 
 --2layer

1, Top
2, Bottom
3, Outline
4, Notes

 --4layer

1, Top
2, Signal 2
3, Signal 3
4, Bottom
5, Outline
6, Notes

(This is similar to the stackup I usually use, except with different names).

 --6layer

As DJ suggested originally, with Notes on layer 8.

-- 
There are some things in life worth obsessing over.  Most
things aren't, and when you learn that, life improves.
http://starbase.globalpc.net/~ezekowitz
Vanessa Ezekowitz vanessaezekow...@gmail.com


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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Peter Clifton
On Mon, 2011-04-11 at 23:59 +0200, Krzysztof Kościuszkiewicz wrote:
 On Sun, Apr 10, 2011 at 11:22:54PM +0200, Markus Traidl wrote:
  
  Actually I would like to use only the net attribute. There I could
  assign net=3V3 instead of net=3V3:1.
  
  I know that the :1 is that the gnetlist tool knows that the 3V3 is
  connected to pin 1.
  
  But in case of a One-Pin-Symbol the gnetlist tool could assume that
  the only net should be assigned to the only pin.
 
 This has been asked for several times and I don't see a reason why this should
 not be allowed for single pin symbols and only for pin number 1.
 
 The patches are attached - please test and report any potential breakage.

I would advise a note of caution. In general, I don't like it when tools
start special casing things like this.. it just feels wrong.

This is a FAQ though..

The problem is that one can completely validly override nets for pins
which don't exist in the symbol. (E.g. hidden power pins).

People are proposing we add a new special case, which says if the user
omits the :1, assume a :1 suffix when interpreting this particular
attribute. If (and only if) the symbol has one single pin.

What about the cases where this is a mistake? The net= attribute was
supposed to refer to some implicit power pin - not the device's one
symbolic pin, but the user forgot the suffix.

Our power symbols already fell like a bit of a kludge as there is no
physical pin or component which ends up in the netlist file.

(Why should we have to give that power symbol's pin ANY pinnumber
attribute? Why is pin 1 special?)

Does special casing pin 1 as the Missing ':?' case help teach users
how to use the net= attribute properly in the general case? I don't
think so.

_I_ think it adds to the confusion - as it would mean there are two
completely different syntax for the same attribute to be used in
different situations.

I don't want to see that special case code proliferate in gEDA. We have
enough already!


A far more satisfying solution in the long run would be to make the
symbols which annotate net naming (like the power and ground symbols,
off-page labels etc..) have an editable attribute associated with the
PIN which gets hooked up to the net which becomes named (or renamed).
(netname=) as if it were on the net its-self.

I realise this isn't currently possible, as we have no means to set or
override attributes on child objects of a complex (e.g. its pins).

Aside..

For some tools (Xilinx's schematic editor springs to mind), the net name
is a property of the net, and annotation markers you add are just
graphical sugar around a visualisation of the net's name attribute. I'm
not quite sure about whether power rail symbols transfer a name to nets
they are attached to.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)


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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Stefan Salewski
On Mon, 2011-04-11 at 23:25 +0100, Peter Clifton wrote:

 I would advise a note of caution.

What some people do not like is the visible :1 in schematics -- can we
simple suppress that output for symbols with only one pin and digit 1
after the :
That would be a not too dangerous patch, because it concerns only
graphical output.




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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Mark Rages
On Sun, Apr 10, 2011 at 6:42 PM, DJ Delorie d...@delorie.com wrote:

 I'm pondering a minor change in pcb's defaults to give us a more
 useful default stackup.  How's this?


My netlist enters pcb by way of gsch2pcb, which supplies its own
default stackup.  Can these be kept in sync somehow?

Regards,
Mark
markrages@gmail
-- 
Mark Rages, Engineer
Midwest Telecine LLC
markra...@midwesttelecine.com


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread gene glick

Kovacs Levente wrote:

I'm currently designing a power amplifier for the HF (3-30MHz) radio
band.

I am selecting capacitors for the low pass harmonic filter bank at the output.
My question is what kind of capacitors should I use? I apply not more then
100V of say 30MHz maximum.

My best bet is to use X7R capacitors with as much DC voltage rating as I can
get. I don't know if there's any connection between the DC and AC losses.


Thanks,
Levente



I also would recommend the plastic types.  Wima makes nice ones but 
there are others.


C0G/NP0 good too, as already pointed out.

gene


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Re: gEDA-user: OFF: capacitors for RF power amplifier

2011-04-11 Thread gene glick

quick link to Wima tech info:
http://www.wima.de/EN/technicalinformation.htm

One really nice thing about plastic film caps is that they fail open. 
Ceramic tends to fail short - which can sometimes ruin your day :)



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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Geoff Swan
I would advise a note of caution.

 What some people do not like is the visible :1 in schematics -- can
 we
 simple suppress that output for symbols with only one pin and digit
 1
 after the :
 That would be a not too dangerous patch, because it concerns only
 graphical output.

   +1
   Special case seems wrong. This would be a much nicer alternative.


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Re: gEDA-user: default pcb stackup change?

2011-04-11 Thread Kai-Martin Knaak
Mark Rages wrote:

 My netlist enters pcb by way of gsch2pcb, which supplies its own
 default stackup.  Can these be kept in sync somehow?

My current work-around is to call pcb without a filename but with 
multiple command line options to set the layer stack. After a save
with the desired name, gsch2pcb happily adopts this empty layout.
The scripting feature of pcb can be used to do this without GUI
interaction.

Here is a snippet from my create-project-script:
/-
# Create an empty layout
echo \
ChangeName(Layout) \
SaveTo(LayoutAs,$NAME.pcb) \
Quit() \
| pcb --listen \
 --fab-author \$AUTHOR\ \
 --groups 1,2,3,c:4,5,5,s:7:8 \
 --layer-name-1 top \
 --layer-name-2 top-polyg. \
 --layer-name-3 top-GND \
 --layer-name-4 bottom \
 --layer-name-5 bott.-poly. \
 --layer-name-6 bott.-GND \
 --layer-name-7 comment \
 --layer-name-8 outline \
 --bloat 600 \
 --shrink 1000 \
 --min-width 600 \
 --min-silk 600 \
 --min-drill 1500 \
 --min-ring 1000 \
 --route-styles \
Signal,1000,3600,2000,1000\
:Power,2500,6000,3500,1000\
:Fat,4000,6000,3500,1000\
:Skinny,600,2402,1181,600 \
 --default-PCB-width 60 \
 --default-PCB-height 60 \
 --grid-increment-mm 1.00 \
 --grid-increment-mil 20.00 \
 --size-increment-mm 0.20 \
 --size-increment-mil 10.00 \
 --line-increment-mm 0.10 \
 --line-increment-mil 8.00 \
 --clear-increment-mm 0.50 \
 --clear-increment-mil 2.00
\--

---)kaimartin(---
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Email: k...@familieknaak.de
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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Steven Michalske





On Apr 12, 2011, at 2:55 AM, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote:

 Peter Clifton wrote:
 
 TBH, I've not seen SVG anywhere on the main-stream internet.
 
 Wikipedia prefers SVG for anything that is not a photograph. The servers
 render SVG graphics to PNG as needed before handing it out to the browser.
 
 
 Linux
 desktops use SVG a lot for desktop graphics, but it really isn't as
 prevalent as it should be.
 
 Microsoft and Apple do not like 
 
 
Safari has supported SVG for a while now?  Why doesn't apple like SVG?



 What excuse is there for OpenOffice / LibreOffice being so appallingly
 bad at working with SVG files?
 
 Actually, SVG import is among the first features of libreoffice beyond 
 openoffice:
 http://www.libreoffice.org/download/new-features-and-fixes/
 
 
 Why can't we paste them right into TeX, LaTeX or whatever? They are all
 open source, yet this open format is not supported.
 
 IMHO, latex development reached a state of virtual feature freeze before
 SVG became a viable alternative.
 
 
 Whilst SVG is an obvious open vector standard to support - not a lot of
 things actually work well with it sadly.
 
 The number one open source vector drawing application, inkscape uses SVG
 as its native file format. This alone would be reason enough to seriously
 consider SVG as an import/export file format.
 
 ---)kaimartin(---
 -- 
 Kai-Martin Knaak  tel: +49-511-762-2895
 Universität Hannover, Inst. für Quantenoptik  fax: +49-511-762-2211
 Welfengarten 1, 30167 Hannover   http://www.iqo.uni-hannover.de
 GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get
 
 
 
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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Steven Michalske
Snip.

I agree that we should not special case it.  I would prefer varibles that 
refered to other attributes.

This example:  value = 3v3
net = $value:1

where the default scope is the local symbol and no lookups to higher scopes.

A resistor divider:

R1
   Value= 1000

R2
 Value = ${r1.value} / 2

See how I snuck in math!

This is flexible and is not special casing anything.   

Just imagining having a feedback resistor formula in a voltage regulator used 
to adding values for the two feedback resistors.

Steve


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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Mark Rages
On Mon, Apr 11, 2011 at 8:19 PM, Steven Michalske smichal...@gmail.com wrote:
 Snip.

 I agree that we should not special case it.  I would prefer varibles that 
 refered to other attributes.

 This example:  value = 3v3
 net = $value:1

 where the default scope is the local symbol and no lookups to higher scopes.

 A resistor divider:

 R1
   Value= 1000

 R2
     Value = ${r1.value} / 2

 See how I snuck in math!

 This is flexible and is not special casing anything.

 Just imagining having a feedback resistor formula in a voltage regulator used 
 to adding values for the two feedback resistors.

 Steve

I've often though it would be extremely handy to have spreadsheet-like
automatic calculations in gschem.

Regards,
Mark
markrages@gmail
-- 
Mark Rages, Engineer
Midwest Telecine LLC
markra...@midwesttelecine.com


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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread John Doty

On Apr 11, 2011, at 4:25 PM, Peter Clifton wrote:

 I would advise a note of caution. In general, I don't like it when tools
 start special casing things like this.. it just feels wrong.

I've long thought it a minor design flaw that indexed attributes attach the 
index to the value rather than the name. So, I would prefer net:1=Vcc, while 
preserving backward compatibility, of course.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com




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Re: gEDA-user: RFC using SVG with semantic markup as an EDA format

2011-04-11 Thread Kai-Martin Knaak
Steven Michalske wrote:

 Microsoft and Apple do not like 
 
 
 Safari has supported SVG for a while now?  Why doesn't apple like SVG?

Sorry, I got confused by Apples dislike of flash.

---)kaimartin(---
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Email: k...@familieknaak.de
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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Kai-Martin Knaak
Mark Rages wrote:

 I've often though it would be extremely handy to have spreadsheet-like
 automatic calculations in gschem.

You mean like specify the R1/R2 and R1 for the four resistors
of a differential opamp circuit? That would be cool!

---)kaimartin(---
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Email: k...@familieknaak.de
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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols

2011-04-11 Thread Mark Rages
On Mon, Apr 11, 2011 at 8:57 PM, Kai-Martin Knaak k...@lilalaser.de wrote:
 Mark Rages wrote:

 I've often though it would be extremely handy to have spreadsheet-like
 automatic calculations in gschem.

 You mean like specify the R1/R2 and R1 for the four resistors
 of a differential opamp circuit? That would be cool!


Yes, or the other way to keep notes up to date:  level here is
-20dBm, level after pad is -28 dBm, where the dB values would be
calculated from the circuit values.  Don't Repeat Yourself.

Also, I've never been much into simulation, preferring to think a bit
and write down equations instead.  I feel kind of silly evaluating
results on my HP calculator and then typing in the resulting circuit
values.  Seems like another place to make a cut/paste error (I'm
really good at those).

Regards,
Mark
markrages@gmail
-- 
Mark Rages, Engineer
Midwest Telecine LLC
markra...@midwesttelecine.com


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