Re: gEDA-user: pcb: Track routing strategies and tips
On Wed, May 11, 2011 at 02:26:43AM +0200, Kai-Martin Knaak wrote: Colin D Bennett wrote: Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. Put extra care into component placement. IMHO, placement is more critical to the design than routing. Indeed. I've been told y a professional (her job is to lay out PCB with expensive commercial tools) that she has never seen a good or even acceptable automatic placer. However she claims that automatic routers are now reasonably good, far from perfect, but the help. I have very similar problems in FPGAs: I often can only reach the performance I want when helping by fixing the location of the large blocks (mostly RAM and DSP). One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. Yep. This is a good default. It avoids road blocks by tracks on both sides. It's called Manhattan routing. It's a good starting point, but you should at least perform some via reduction run at some later stage. Do you ever use the pcb autorouter Rarely. Basically only for fun... or do you always route by hand? Mostly. Always in practice, but that's because my circuits are simple but almost invariably involve microstrip and/or coplanar line for the most important signals (and mechanical design of the enclosure is as critical as the PCB layout). I'm in the process of designing a much more complex board with FPGA, DDS and no real high frequency signal (highest frequency being the 400MHz DDS clock). But the layout is going to be done by the person mentioned above (using CadStar at the moment). BTW, there is no gschem-CadStar netlister, or did I miss it? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
I start off with schematics. People underestimate the need for a clear schematic. On the schematics, I tend to place components approximately where they will appear on the PCB. This gives me an idea of how traces are to be routed. I divide my schematics into virtual blocks - not actually marked on the schematic. For example one block would be a 3.3V buck powrer supply; another might be a 9DOF sensor area (mag/acc/gyro.) When it comes to a layout, I place major components first and attempt to fit the smaller blocks into the free space as long as traces are kept short. I rarely if ever use the autorouter, even on complex designs. No autorouter, no matter how good, can work as well as routing by hand, in my honest opinion. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Logos and graphics.. [WAS: Re: Where is pcb-20100929 for Win32 ?]
On Fri, 2011-05-06 at 10:00 -0700, Colin D Bennett wrote: Appears to be working well for me :) Allowing me to add some holes to polygons to sort out a logo on the silk screen - great! Did you draw a logo graphic in pcb itself using the polygon tool? I have really wanted to have decent logo graphics and beautifully typeset text on my boards, so I have created graphics and text in Inkscape, exported through pstoedit to pcb, but this has caused issues because pstoedit is generating some invalid polygons, which crashes most versions of pcb. I might be persuaded to take a look at fixing one or the other. I wrote a plugin a while back which takes the various forward / backwards orientated polygons spat out by pstoedit, then combines them to make PCB compatible polygons with holes. The tricky part was making it work with nested holes inside polygons inside a hole inside a polygon ;) Since a lot of core code has been updated since I wrote the script, I might have to fix it to work with current PCB, but I've attached it here in case it helps you get started. I've not seen PCB crash due to bad pstoedit polygons before though - if you have an example which is reproducible, please send it to me. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: strategies for 2-layer polygon planes? (chopped up polygons...)
On Tue, 2011-05-10 at 16:14 -0700, Colin D Bennett wrote: Now after a while of routing tracks, there were so many tracks that my ground plane polygons were chopped to bits and pcb started drawing only the left half of the polygon, for instance. This obviously created problems since nets that were already successfully routed got broken. If you're prepared to work with a non-standard version of PCB (producing files which won't look the same when loaded into standard PCB), I could take a poke at ensuring my pours branch is up to date and working. That handles planes by making them into pours, and performs on the fly island removal for non-connected pieces. The only difference is the polygon handling, and it out to be possible (with a small amount of code on my part) to morph the poured regions back into individual polygon shapes, That would produce a design compatible with git HEAD PCB again. (Admittedly the polygons produced would be pre-clipped exactly to your track routing, so it would be a last export step beyond which you'd not want to do further editing). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Logos and graphics.. [WAS: Re: Where is pcb-20100929 for Win32 ?]
On Wed, 2011-05-11 at 11:43 +0100, Peter Clifton wrote:
I've attached it here in case it helps you get started.
(Now attached!)
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
/* PolyCombine plug-in for PCB
Copyright (C) 2010 Peter Clifton pc...@cam.ac.uk
Licensed under the terms of the GNU General Public License, version 2.
Compile like this:
gcc -I$HOME/pcbsrc/git/src -I$HOME/pcbsrc/git -O2 -shared polycombine.c -o polycombine.so
The resulting polycombine.so goes in $HOME/.pcb/plugins/polycombine.so.
Usage: PolyCombine()
The selected polygons are combined together according to the ordering of their points.
*/
#include stdio.h
#include math.h
#include global.h
#include data.h
#include macro.h
#include create.h
#include remove.h
#include hid.h
#include error.h
#include rtree.h
#include polygon.h
#include polyarea.h
#include assert.h
#include strflags.h
#include find.h
#include misc.h
#include draw.h
static POLYAREA *
original_poly (PolygonType * p, bool *forward)
{
PLINE *contour = NULL;
POLYAREA *np = NULL;
Cardinal n;
Vector v;
int hole = 0;
*forward = true;
if ((np = poly_Create ()) == NULL)
return NULL;
/* first make initial polygon contour */
for (n = 0; n p-PointN; n++)
{
/* No current contour? Make a new one starting at point */
/* (or) Add point to existing contour */
v[0] = p-Points[n].X;
v[1] = p-Points[n].Y;
if (contour == NULL)
{
if ((contour = poly_NewContour (v)) == NULL)
return NULL;
}
else
{
poly_InclVertex (contour-head.prev, poly_CreateNode (v));
}
/* Is current point last in contour? If so process it. */
if (n == p-PointN - 1 ||
(hole p-HoleIndexN n == p-HoleIndex[hole] - 1))
{
poly_PreContour (contour, TRUE);
/* Log the direction in which the outer contour was specified */
if (hole == 0)
*forward = (contour-Flags.orient == PLF_DIR);
/* make sure it is a positive contour (outer) or negative (hole) */
if (contour-Flags.orient != (hole ? PLF_INV : PLF_DIR))
poly_InvContour (contour);
assert (contour-Flags.orient == (hole ? PLF_INV : PLF_DIR));
poly_InclContour (np, contour);
contour = NULL;
assert (poly_Valid (np));
hole++;
}
}
return np;
}
typedef struct poly_tree poly_tree;
struct poly_tree {
PolygonType *polygon;
bool forward;
POLYAREA *polyarea;
poly_tree *parent;
poly_tree *child;
poly_tree *prev;
poly_tree *next;
};
/* __
* ___|_ P6 | +P1 +P6
* | P1| || |
* | _ |_|| -P2 -P4 -P5
* | |P2 ||P5 | | |
* | | [] ||| | +P3
* | | P3 ||
* | |_||
* | |
* | ___|
* | |P4 | |
* | |___| |
* | |
* |_|
*
* As we encounter each polygon, it gets a record. We need to check
* whether it contains any of the polygons existing in our tree. If
* it does, it will become the parent of them. (Check breadth first).
*
* When processing, work top down (breadth first), although if the
* contours can be assumed not to overlap, we can drill down in this
* order: P1, P2, P3, P4, P5, P6.
*/
static bool
PolygonContainsPolygon (POLYAREA *outer, POLYAREA *inner)
{
// int contours_isect;
/* Should check outer contours don't intersect? */
// contours_isect = Touching (outer, inner);
/* Cheat and assume simple single contour polygons for now */
// return contours_isect ?
// 0 : poly_ContourInContour (outer-contours, inner-contours);
return poly_ContourInContour (outer-contours, inner-contours);
}
static poly_tree *
insert_node_recursive (poly_tree *start_point, poly_tree *to_insert)
{
poly_tree *cur_node, *next = NULL;
// bool to_insert_isects_cur_node; /* Intersection */
bool to_insert_contains_cur_node; /* Containment */
bool cur_node_contains_to_insert; /* Containment */
bool placed_to_insert = false;
poly_tree *return_root = start_point;
if (start_point == NULL)
{
// printf (start_point is NULL, so returning to_insert\n);
//to_insert-parent = !!; UNDEFINED
return to_insert;
}
/* Investigate the start point and its peers first */
for (cur_node = start_point; cur_node != NULL; cur_node = next)
{
next = cur_node-next;
// to_insert_isects_cur_node = IsPolygonInPolygon (to_insert-polygon, cur_node-polygon);
to_insert_contains_cur_node =
gEDA-user: Hiding individual layers of a layer-group
Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? cheers, Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote: Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? To achieve the visual clarity I guess you're looking for, switch to the pcb+gl branch and turn on thin draw polygons. Alternatively, thin draw polygons in git HEAD might still help you. The keyboard short-cut is Ctrl + Shift + P -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
On Wed, 11 May 2011 13:12:55 +0100 Peter Clifton pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote: Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? To achieve the visual clarity I guess you're looking for, switch to the pcb+gl branch and turn on thin draw polygons. Alternatively, thin draw polygons in git HEAD might still help you. The keyboard short-cut is Ctrl + Shift + P I do find that Thin Draw Polygons is helpful sometimes. However I also find many times that I would like to be able to show only specific layers (not whole layer groups). For instance, if I want to rip up all my ground plane polygons, I would like to be able to show only the ground plane layer (which is in the top layer's group) so that I can select all to select only the ground plane copper. Regards, Colin signature.asc Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
On Wed, 11 May 2011 13:12:55 +0100 Peter Clifton pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote: Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? To achieve the visual clarity I guess you're looking for, switch to the pcb+gl branch and turn on thin draw polygons. Alternatively, thin draw polygons in git HEAD might still help you. The keyboard short-cut is Ctrl + Shift + P Did I miss something or is Thin Draw Polygons (Ctrl+Shift+P) a feature that has been around at least for a couple of pcb releases? Does it differ from pcb+gl to mainline git HEAD? I have used both and it seems the same. Regards, Colin signature.asc Description: PGP signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
Colin D Bennett wrote: Does it differ from pcb+gl to mainline git HEAD? The pcb+gl version looks nicer :-) The polygon area is still rendered but very transparent. If this feature enters pcb-HEAD, there should be an option to really suppress polygon recalculation and maybe rendering, too. This is very useful when slow graphics meets complex layout. Think aged thinkpads, or that old desktop from 2001 in the barn. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb+gl
I've heard a lot about this pcb+gl and I like it... and it turns out I fetched my git a few days from the enabling of it, so I think I missed the bus for it... So, how do I enable it for the latest git? Is there a compile-time flag? Thanks, Tom ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: minipack-result -- gschem
Kai-Martin Knaak wrote: Unfortunately, the binaries fail when started with wine. They fail with different symptoms: This was via ssh. So this may have been an additional complication. From the local desktop I get different spew. I'll split the output of the different binaries to separate postings. gschem first: With wine, gschem.exe seems to miss a lib called libcanberra-gtk-module.dll . This lib was indeed not build by the script. Should it? I copied the result directory to a Virtualbox running winXP. In this setting, the same binary complains about missing boot-9.scm Here is the actual output: -minipack-gschem-with-winXP-in-Virtualbox-- C:\Programme\result\bingschem.exe ERROR: In procedure primitive-load-path: ERROR: Unable to find file ice-9/boot-9.scm in load path -minipack-gschem-with-wine kmk@bibo:/tmp$ wine /usr/local/src/pcb/pcb-for-windows/minipack/result/bin/gschem pidpeltier.sch Gtk-Message: Failed to load module canberra-gtk-module: `libcanberra-gtk-module.dll': Module not found wine: Unhandled page fault on read access to 0x at address 0xf7576110 (thread 0009), starting debugger... Unhandled exception: page fault on read access to 0x in 32-bit code (0xf7576110). Register dump: CS:0023 SS:002b DS:002b ES:002b FS:0063 GS:006b EIP:f7576110 ESP:0066fc18 EBP:0066fc38 EFLAGS:00010246( - 00 -RIZP1) EAX: EBX:7bc89444 ECX: EDX: ESI: EDI: Stack dump: 0x0066fc18: 7bc68b4d 0066fc48 0x0066fc28: 0002 7bc68b39 0066fe68 0x0066fc38: 0066fc68 6bfcf498 001eedc8 0x0066fc48: 66304430 0066fe68 00134a48 0001 0x0066fc58: 0066fc78 0066fe68 00134a48 0001 0x0066fc68: 0066fc78 6bfcf4b9 Backtrace: =1 0xf7576110 in libc.so.6 (+0x74110) (0x0066fc38) 2 0x6bfcf498 in libguile-17 (+0x4f498) (0x0066fc68) 3 0x6bfcf4b9 in libguile-17 (+0x4f4b9) (0x0066fc78) 4 0x66305913 in libgeda-38 (+0x5913) (0x0066fc88) 5 0x66306daa in libgeda-38 (+0x6daa) (0x0066fc98) 6 0x00408a02 in gschem (+0x8a02) (0x0066fcd8) 7 0x6bfad09a in libguile-17 (+0x2d09a) (0x0066fcf8) 8 0x6bf84af2 in libguile-17 (+0x4af2) (0x0066fd08) 9 0x6bfe84f2 in libguile-17 (+0x684f2) (0x0066fd88) 10 0x6bf84f26 in libguile-17 (+0x4f26) (0x0066fdd8) 11 0x6bf84fc1 in libguile-17 (+0x4fc1) (0x0066fe08) 12 0x6bfe6c5b in libguile-17 (+0x66c5b) (0x0066fe38) 13 0x6bfe6ca1 in libguile-17 (+0x66ca1) (0x0066fe58) 14 0x6bfad041 in libguile-17 (+0x2d041) (0x0066fe78) 15 0x004088bb in gschem (+0x88bb) (0x0066fea8) 16 0x004010a7 in gschem (+0x10a7) (0x0066fee8) 17 0x00401143 in gschem (+0x1143) (0x0066ff08) 18 0x7b8783a8 in kernel32 (+0x583a8) (0x0066ffe8) 0xf7576110: pcmpeqb 0x0(%esi),%mm0 Modules: Module Address Debug info Name (117 modules) PE23- 2aa000 Deferredlibpixman-1-0 PE40- 461000 Export gschem PE67- a6b000 Deferredlibgtk-win32-2.0-0 PE 61a0-61a34000 Deferredlibpng14-14 PE 61cc-61cda000 Deferredlibintl-8 PE 6294-6296b000 Deferredlibatk-1.0-0 PE 63a4-63a87000 Deferredlibgobject-2.0-0 PE 650c-6515 Deferredlibfreetype-6 PE 6534-65384000 Deferredlibgdk_pixbuf-2.0-0 PE 6558-655cd000 Deferredlibpango-1.0-0 PE 65c4-65c52000 Deferredlibgthread-2.0-0 PE 6600-660f1000 Deferredlibiconv-2 PE 6630-66336000 Export libgeda-38 PE 6660-5000 Deferredlibtiff-3 PE 685c-686cc000 Deferredlibglib-2.0-0 PE 6890-68949000 Deferredlibjpeg-7 PE 68a8-68ace000 Deferredlibgmp-3 PE 68dc-68e7 Deferredlibcairo-2 PE 6b28-6b29a000 Deferredlibpangowin32-1.0-0 PE 6bf8-6c03a000 Export libguile-17 PE 6c34-6c3f1000 Deferredlibgdk-win32-2.0-0 PE 6d48-6d494000 Deferredlibltdl-7 PE 6d4c-6d4d5000 Deferredlibpangocairo-1.0-0 PE 6d58-6d60a000 Deferredlibgio-2.0-0 PE 6dd0-6dd11000 Deferredlibgmodule-2.0-0 PE 6e8c-6e8df000 Deferredlibz PE 7104-71059000 Deferredlibgnurx-0 ELF 7b80-7b939000 Export kernel32elf \-PE 7b82-7b939000 \ kernel32 ELF 7bc0-7bca5000 Deferredntdllelf \-PE 7bc1-7bca5000 \ ntdll ELF 7bf0-7bf03000 Deferredwine-loader ELF 7dd4a000-7dd56000 Deferredlibnss_files.so.2 ELF 7dd56000-7dd6 Deferredlibnss_nis.so.2 ELF 7dd6-7dd77000
Re: gEDA-user: pcb+gl
Thomas Oldbury wrote: I've heard a lot about this pcb+gl and I like it... and it turns out I fetched my git a few days from the enabling of it, so I think I missed the bus for it... The single, largest impact of of pcb+gl is transparency. IIRC, this is only showing with rat lines at the current state of patches in PCB-head. Maybe, you got the bus but did not notice ;-) ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gschem
Kai-Martin Knaak wrote: -minipack-gschem-with-winXP-in-Virtualbox-- C:\Programme\result\bingschem.exe ERROR: In procedure primitive-load-path: ERROR: Unable to find file ice-9/boot-9.scm in load path I forgot to mention that the binary just dies after this. No GUI, no help lines when the option --help or /h is given. ---)kaiamrtin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gschem
On Wed, 11 May 2011 18:31:35 +0200, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Kai-Martin Knaak wrote: -minipack-gschem-with-winXP-in-Virtualbox-- C:\Programme\result\bingschem.exe ERROR: In procedure primitive-load-path: ERROR: Unable to find file ice-9/boot-9.scm in load path boot-9.scm is part of Guile (it's the master Scheme script needed to initialise the interpreter). Guile may not be installed correctly. Try running 'guile' and see if you get to a prompt. Peter -- Peter Brett pe...@peter-b.co.uk Remote Sensing Research Group Surrey Space Centre ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
On Wed, 11 May 2011 17:30:22 +0200 Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Colin D Bennett wrote: Does it differ from pcb+gl to mainline git HEAD? The pcb+gl version looks nicer :-) The polygon area is still rendered but very transparent. Ah, now that you mention it, I do remember noticing that before. It is a nice feature. In fact it was so natural that I forgot it existed. :-) Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: minipack result -- pcb
This is, how pcb.exe fares. When called by wine, the binary exits after about a second and a few error messages. see below. When called with the CMD tool of winXP in a Virtualbox, the GUI comes up fine. But there are glitches and a show stopper: * Zoom in does not work -- neither with the z key, nor with the mouse wheel. Panning with the right mouse seems to be fine, though. After I made the canvas smaller than the window, by fiddling with the sizes in preference, the z key did zoom. But it did so only to fit the window. No more zooming in. The mouse wheel still did nothing. * The radio buttons of the route style disappear, if the mouse leaves them to the left. They keep being visible, if the mouse cursor goes down. * the binary does not give the list of options when called with -h or with /h . There was no output on the CND line. minipack-pcb.exe-with-wine- kmk@bibo:/tmp$ wine /usr/local/src/pcb/pcb-for-windows/minipack/result/bin/pcb.exe (pcb.exe:26): GLib-WARNING **: Passing a non-NULL package to g_win32_get_package_installation_directory() is deprecated and it is ignored. Share installation path is Z:\usr\local\src\pcb\pcb-for-windows\minipack\result\share\pcb (pcb.exe:26): GLib-WARNING **: Passing a non-NULL package to g_win32_get_package_installation_directory() is deprecated and it is ignored. Gtk-Message: Failed to load module canberra-gtk-module: `libcanberra-gtk-module.dll': Module not found wine: Unhandled page fault on read access to 0x at address 0x7ec3a74a (thread 001b), starting debugger... kmk@bibo:/tmp$ ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gschem
Peter TB Brett wrote: boot-9.scm is part of Guile (it's the master Scheme script needed to initialise the interpreter). Guile may not be installed correctly. Try running 'guile' and see if you get to a prompt. I get the same result: C:\Programme\result\binguile.exe ERROR: In procedure primitive-load-path: ERROR: Unable to find file ice-9/boot-9.scm in load path ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
Nope... rat lines are solid. I checked thisversion out around 2nd May. On 11 May 2011 17:27, Kai-Martin Knaak [1]kn...@iqo.uni-hannover.de wrote: Thomas Oldbury wrote: I've heard a lot about this pcb+gl and I like it... and it turns out I fetched my git a few days from the enabling of it, so I think I missed the bus for it... The single, largest impact of of pcb+gl is transparency. IIRC, this is only showing with rat lines at the current state of patches in PCB-head. Maybe, you got the bus but did not notice ;-) ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover [2]http://www.iqo.uni-hannover.de GPG key: [3]http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list [4]geda-user@moria.seul.org [5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:kn...@iqo.uni-hannover.de 2. http://www.iqo.uni-hannover.de/ 3. http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get 4. mailto:geda-user@moria.seul.org 5. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
On Wed, May 11, 2011 at 04:51:21PM +0100, Thomas Oldbury wrote: I've heard a lot about this pcb+gl and I like it... and it turns out I fetched my git a few days from the enabling of it, so I think I missed the bus for it... So, how do I enable it for the latest git? Is there a compile-time flag? Thanks, Tom You might need to rerun ./configure; GL is now the default so you need to give it --disable-gl to suppress it. If it complains that you need to install the opengl libraries you know that you've got it :) -- Andrew Poelstra Email: asp11 at sfu.ca OR apoelstra at wpsoftware.net Web: http://www.wpsoftware.net/andrew/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gschem
On Wed, 11 May 2011 19:08:07 +0200, Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Peter TB Brett wrote: boot-9.scm is part of Guile (it's the master Scheme script needed to initialise the interpreter). Guile may not be installed correctly. Try running 'guile' and see if you get to a prompt. I get the same result: C:\Programme\result\binguile.exe ERROR: In procedure primitive-load-path: ERROR: Unable to find file ice-9/boot-9.scm in load path Okay, the problem is definitely with Guile rather than gschem. Please make sure that you have its paths set up correctly so that it can find its Scheme library. Peter -- Peter Brett pe...@peter-b.co.uk Remote Sensing Research Group Surrey Space Centre ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote: I've heard a lot about this pcb+gl and I like it... and it turns out I fetched my git a few days from the enabling of it, so I think I missed the bus for it... In git HEAD, there is some GL support. What I've always called pcb+gl is a feature branch I've been maintaining separately from the main PCB git repository. The aim is to merge it all to upstream git HEAD eventually!. To get the most speed and fancyness (including the more translucent thin-draw polygons), check out PCB from here: git clone git://repo.or.cz/geda-pcb/pcjc2.git git checkout -b pcb+gl_experimental origin/pcb+gl_experimental (If your card can cope with it, the pcb+gl_experimental branch has better rendering speed and a few extra bits and pieces). Otherwise, the default checkout should be the pcb+gl branch. As others have said, just run ./configure and GL should be enabled as the default. You might need to install your distro's libgtkglext-dev package before it will build. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
On Wed, 2011-05-11 at 07:16 -0700, Colin D Bennett wrote: On Wed, 11 May 2011 13:12:55 +0100 Peter Clifton pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote: Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? To achieve the visual clarity I guess you're looking for, switch to the pcb+gl branch and turn on thin draw polygons. Alternatively, thin draw polygons in git HEAD might still help you. The keyboard short-cut is Ctrl + Shift + P I do find that Thin Draw Polygons is helpful sometimes. However I also find many times that I would like to be able to show only specific layers (not whole layer groups). For instance, if I want to rip up all my ground plane polygons, I would like to be able to show only the ground plane layer (which is in the top layer's group) so that I can select all to select only the ground plane copper. How about some middle ground compromise - let it switch the layers off for the purposes of selection / rendering etc.., but still draw a faded (or de-saturated) version of their contents to aid not drawing geometry which would clash with other (hidden) sub-layers in the group. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Adding inner polygons to a plane
Sometimes, I want to add an inner polygon area to a plane in PCB. The area might be a power supply which only has to cover a small area; e.g. 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on top of the plane, there is no cut-out formed and I get shorts. To do what I want, I must cut a hole in the main polygon plane, then add my smaller polygon into it. This is very time consuming and changing the plane once created is very difficult. Is there a way to get PCB to support nested polygons? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote: Sometimes, I want to add an inner polygon area to a plane in PCB. The area might be a power supply which only has to cover a small area; e.g. 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on top of the plane, there is no cut-out formed and I get shorts. To do what I want, I must cut a hole in the main polygon plane, then add my smaller polygon into it. This is very time consuming and changing the plane once created is very difficult. Is there a way to get PCB to support nested polygons? Not easily. For many power plane cases, these polygons won't actually be truly nested, so it is impossible to infer which polygon the user wishes to clip the other. Perhaps it would be possible to support a flag on the smaller, clippiING polygon which makes it bully other polygons away from it, but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). This class of object would not be so much a pour, but behave more like a line or arc segment. I'm guessing we would still need to retain support for clipping it against pins, pads, lines and arcs. Shouldn't take that much code to make it happen (I already implemented a similar feature once before), I just need to hear that there is general consensus that it is a sensible thing to do. Often for the kind of inner layers you describe, you want some complex boolean logic operation to produce the final shape from various sources. Packages like Altium (which springs to mind), let you define a layer in terms of its _negative_, so you split up a power plane by defining the _boundary_ between the two (or more) regions. Perhaps the way is to go more like mech-CAD systems in defining geometry based upon a hierarchy of boolean operations. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: strategies for 2-layer polygon planes? (chopped up polygons...)
On Wed, 11 May 2011 02:16:03 +0200 Kai-Martin Knaak k...@lilalaser.de wrote: Colin D Bennett wrote: Does anyone have any strategies or tips for general design of ground planes in 2-layer PCBs? Do you do a ground flood, or do you remove all extra copper? I usually route everything, including ground connections with ordinary tracks. Then I select all ground connections and set their join flag with the setflag() action and draw a large polygon. Sometimes I need to draw additional rectangles because the dicer removed some parts. Sounds like a good way to do it. Thanks for the suggestion. Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
On Wed, 11 May 2011 02:26:43 +0200 Kai-Martin Knaak k...@lilalaser.de wrote: Colin D Bennett wrote: Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. Put extra care into component placement. IMHO, placement is more critical to the design than routing. I have heard this advice often. Do you ever study other people's PCB designs to learn from them? Sometimes I look with awe at computer motherboards ;-) I originally commented in my message at this point about how I found it interesting to examine computer motherboards (but decided to delete it). There is so much to those boards! Some of the vias are nearly microscopic (laser-drilled, I guess). One thing I recently discovered was the trace length matching in the SDRAM signals. Some beautiful PCB design. I've practiced my hot air rework skills with some old motherboards and studied their design while at the same time salvaging some nice connectors, inductors, etc. Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
On Tue, 10 May 2011 21:58:57 -0400
gene glick carzr...@optonline.net wrote:
Kai-Martin posted that placement is more important than routing. I'd
say they are equally important. The best layout guy in the world
can't fix a lousy placement. Bogus layout guys throw more layers at
the problem. So yeah, take the time to plan it out before routing.
One problem I have with placement is guessing how far apart to place
components. If I do the routing and then realize I could shrink the
board, it is really painful to do so since all the traces (lines) will
not scale or move usefully with the components. So basically if I move
a component I need to then re-route a significant part of all the traces
connected to it. (It would be fantastic if pcb could adjust traces
dynamically as components are moved.)
Does anyone have any tips on how to plan a layout for easy and clean
track routing? In particular for 2-layer boards.
No substitute for experience here. But, partitioning the design by
type may help : analog, digital, low-speed, high-speed. Try to think
beyond blindly connecting the parts. Sometimes swapping gates,
adding parts or other strategies become clear as you route. This is
a huge benefit when you route your own board. Layout guys just
connect the pieces together.
Rather than a strict two-step process of (1) schematic capture and
(2) PCB layout, I have recently found an iterative-design process loop
of do { edit_schematic(); edit_pcb(); } while (!satisfied); to be very
helpful, for instance when there is a choice of connector pinout or
microcontroller I/O pin usage. I often find that if I switch the MCU
I/O pins used for a connection it really cleans up part of the layout.
One strategy that I have seen and recently tried is to use the top
layer for all horizontal trace runs and the bottom layer for all
vertical trace runs, or vice-versa.
2-layer is tough. You also have to account for power and ground.
The parts themselves also crowd routing area. 2-layer is not
particularly suitable for high-speed anything. Seems good for power
supply design, and some audio work (I've seen a lot of audio ref
boards on 2 layer). You can make good designs with 2-layer, just is
more work. Cost difference to 4-layer is not bad.
At least for DorkbotPDX/pcb.laen.org, 4-layer is double the cost of
2-layer per unit area. However I guess you could do the board in a
smaller area with 4-layer so the final cost would actually be less than
double that of the 2-layer design.
Do you ever study other people's PCB designs to learn from them?
Yeah, a lot. You will find good and bad. There's a whole world of
opinion out there - and you know what they say about opinions :)
SI-LIST is a great place to exchange ideas on layout. Several
industry experts frequently post.
I am checking out SI-LIST now. Sounds interesting.
Regards,
Colin
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Re: gEDA-user: Adding inner polygons to a plane
On Wed, May 11, 2011 at 11:19 AM, Peter Clifton [1]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote: Sometimes, I want to add an inner polygon area to a plane in PCB. The � � area might be a power supply which only has to cover a small area; e.g. � � 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on � � top of the plane, there is no cut-out formed and I get shorts. To do � � what I want, I must cut a hole in the main polygon plane, then add my � � smaller polygon into it. This is very time consuming and changing the � � plane once created is very difficult. Is there a way to get PCB to � � support nested polygons? Not easily. For many power plane cases, these polygons won't actually be truly nested, so it is impossible to infer which polygon the user wishes to clip the other. Perhaps it would be possible to support a flag on the smaller, clippiING polygon which makes it bully other polygons away from it, but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). This class of object would not be so much a pour, but behave more like a line or arc segment. I'm guessing we would still need to retain support for clipping it against pins, pads, lines and arcs. Shouldn't take that much code to make it happen (I already implemented a similar feature once before), I just need to hear that there is general consensus that it is a sensible thing to do. I'm more in favor of anti-traces. They'd be equivalent to zero width traces, but still push polygon out of the way. Then you wouldn't need a nested polygon, just an anti-trace that goes around the border of the new region. References 1. mailto:pc...@cam.ac.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
One of the things I suggested for Peter's pours branch is to add another level of polygon-ness. To summarize, pours creates two layers of polygons - the layer the user creates, and the cut up polygons caused by traces, vias, etc. PCB's core sees the cut up polygons, not the user ones, so things like DRC and connectivity work properly. I suggested a layer of cut-lines between the user polys and the cut up pols, thus: Level 1: user-editable top-level polygons (whole polys) Level 2: user-editable traces which slice up polygons (sliced polys) Level 3: PCB PolygonType objects further cut up by polygon clearances etc (sliced cleared polys) (i.e. what you see in the gerbers) Level 4: output of polygon dicer (sliced, cleared, and diced polygons) (transient, used by exporters) In this example, the user would create one board-sized whole polygon, and suitable lines to slice it into the two power regions (3.3v and 1.8v) (sliced polys). These two sliced polys would then be further broken up by traces, vias, pins, etc, to make the final board. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
Colin D Bennett co...@gibibit.com writes: As a rather inexperienced PCB designer, I find that I have to throw away two or three layouts until I get one that is usable--and still not entirely satisfactory. I always end up with such a mess of traces that I know I need better organization and a method to the madness. But I am a newb with little knowledge so I fall back on trial-and-error. Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. My schematics usually look almost like the layout. The pins of the symbols are placed like on the package. People on this list argue that the schematic should document the function, not the physical implementation, but in my circuit the function is all inside the FPGA and the processor, while the details of the layout in low noise mixed signal or high-speed applications are very important, so I use the schematic entry as a first opportunity to preview the place and route. One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. This is a good for (slow) digital designs. These typically benefit from good functional schematics for review and documentation, so my physical style of schematics is not appropriate. OTOH, when it needs to fit on two layers, and the logic is not too complicated, a little physical planing on the schematic level may help later with the placement and save a few backannotation cycles for swapped pins and slots. Do you ever use the pcb autorouter or do you always route by hand? I never tried an autorouter. But for that kind of Manhattan routing I probably would try. Do you ever study other people's PCB designs to learn from them? I think you could find both good and bad examples: things to emulate and things to avoid yourself. Yes. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
I'm getting this problem when trying to run the last command: thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental origin/pcb+gl_experimental fatal: Not a git repository (or any of the parent directories): .git Any ideas? On 11 May 2011 18:41, Peter Clifton [1]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote: I've heard a lot about this pcb+gl and I like it... and it turns out I fetched my git a few days from the enabling of it, so I think I missed the bus for it... In git HEAD, there is some GL support. What I've always called pcb+gl is a feature branch I've been maintaining separately from the main PCB git repository. The aim is to merge it all to upstream git HEAD eventually!. To get the most speed and fancyness (including the more translucent thin-draw polygons), check out PCB from here: git clone git://[2]repo.or.cz/geda-pcb/pcjc2.git git checkout -b pcb+gl_experimental origin/pcb+gl_experimental (If your card can cope with it, the pcb+gl_experimental branch has better rendering speed and a few extra bits and pieces). Otherwise, the default checkout should be the pcb+gl branch. As others have said, just run ./configure and GL should be enabled as the default. You might need to install your distro's libgtkglext-dev package before it will build. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:pc...@cam.ac.uk 2. http://repo.or.cz/geda-pcb/pcjc2.git 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
Did the clone succeed? Did you cd into the cloned repo? On Wed, May 11, 2011 at 12:53 PM, Thomas Oldbury [1]toldb...@gmail.com wrote: � I'm getting this problem when trying to run the last command: � thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental � origin/pcb+gl_experimental � fatal: Not a git repository (or any of the parent directories): .git � Any ideas? � On 11 May 2011 18:41, Peter Clifton [1][2]pc...@cam.ac.uk wrote: � On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote: � I've heard a lot about this pcb+gl and I like it... and it turns out � I � � � fetched my git a few days from the enabling of it, so I think I � missed � � � the bus for it... � � In git HEAD, there is some GL support. What I've always called � � pcb+gl is a feature branch I've been maintaining separately from � � the � � main PCB git repository. � � The aim is to merge it all to upstream git HEAD eventually!. � � To get the most speed and fancyness (including the more translucent � � thin-draw polygons), check out PCB from here: � � git clone git://[2][3]repo.or.cz/geda-pcb/pcjc2.git � � git checkout -b pcb+gl_experimental origin/pcb+gl_experimental � � (If your card can cope with it, the pcb+gl_experimental branch has � � better rendering speed and a few extra bits and pieces). � � Otherwise, the default checkout should be the pcb+gl branch. � � As others have said, just run ./configure and GL should be enabled � � as � � the default. You might need to install your distro's libgtkglext-dev � � package before it will build. � � Best wishes, � � -- � � Peter Clifton � � Electrical Engineering Division, � � Engineering Department, � � University of Cambridge, � � 9, JJ Thomson Avenue, � � Cambridge � � CB3 0FA � � Tel: +44 (0)7729 980173 - (No signal in the lab!) � � Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) � � ___ � � geda-user mailing list � � [3][4]geda-user@moria.seul.org � � [4][5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References � 1. mailto:[6]pc...@cam.ac.uk � 2. [7]http://repo.or.cz/geda-pcb/pcjc2.git � 3. mailto:[8]geda-user@moria.seul.org � 4. [9]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [10]geda-user@moria.seul.org [11]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:toldb...@gmail.com 2. mailto:pc...@cam.ac.uk 3. http://repo.or.cz/geda-pcb/pcjc2.git 4. mailto:geda-user@moria.seul.org 5. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 6. mailto:pc...@cam.ac.uk 7. http://repo.or.cz/geda-pcb/pcjc2.git 8. mailto:geda-user@moria.seul.org 9. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 10. mailto:geda-user@moria.seul.org 11. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, 2011-05-11 at 15:17 -0400, DJ Delorie wrote: One of the things I suggested for Peter's pours branch is to add another level of polygon-ness. To summarize, pours creates two layers of polygons - the layer the user creates, and the cut up polygons caused by traces, vias, etc. PCB's core sees the cut up polygons, not the user ones, so things like DRC and connectivity work properly. I suggested a layer of cut-lines between the user polys and the cut up pols, thus: Level 1: user-editable top-level polygons (whole polys) Level 2: user-editable traces which slice up polygons (sliced polys) Level 2 is the missing layer, and yes - it would be really neat to have. I once had an anti-polygons branch, this would be more like anti-tracks. In general, we probably ought to support anti-anything. Level 3: PCB PolygonType objects further cut up by polygon clearances etc (sliced cleared polys) (i.e. what you see in the gerbers) Level 4: output of polygon dicer (sliced, cleared, and diced polygons) (transient, used by exporters) Dicer? How quaint ;) GL doesn't use it, PS export doesn't use it. In fact, only gerbv and PNG really need it I think. Actually, I suppose being fair - the GL render could use the dicer. It could also use its Bentley-Ottman rasteriser (stolen from cairo), which does effectively the same job, but much faster. For now, it turns out the easiest way to render polygons efficiently is with masking, then you only need to rasterise each contour (which doesn't have holes). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
On Wed, 2011-05-11 at 20:53 +0100, Thomas Oldbury wrote: I'm getting this problem when trying to run the last command: thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental origin/pcb+gl_experimental fatal: Not a git repository (or any of the parent directories): .git Any ideas? Sorry (Russell is right), I forgot to tell you to cd pcjc2 or whatever directory the repository cloned into. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
Ah, problem solved... needed to cd into the directory. On 11 May 2011 21:31, Russell Dill [1]russ.d...@asu.edu wrote: Did the clone succeed? Did you cd into the cloned repo? On Wed, May 11, 2011 at 12:53 PM, Thomas Oldbury [1][2]toldb...@gmail.com wrote:  I'm getting this problem when trying to run the last command:  thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental  origin/pcb+gl_experimental  fatal: Not a git repository (or any of the parent directories): .git  Any ideas?  On 11 May 2011 18:41, Peter Clifton [1][2][3]pc...@cam.ac.uk wrote:  On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote:  I've heard a lot about this pcb+gl and I like it... and it turns out  I    fetched my git a few days from the enabling of it, so I think I  missed    the bus for it...   In git HEAD, there is some GL support. What I've always called   pcb+gl is a feature branch I've been maintaining separately from   the   main PCB git repository.   The aim is to merge it all to upstream git HEAD eventually!.   To get the most speed and fancyness (including the more translucent   thin-draw polygons), check out PCB from here:   git clone git://[2][3][4]repo.or.cz/geda-pcb/pcjc2.git   git checkout -b pcb+gl_experimental origin/pcb+gl_experimental   (If your card can cope with it, the pcb+gl_experimental branch has   better rendering speed and a few extra bits and pieces).   Otherwise, the default checkout should be the pcb+gl branch.   As others have said, just run ./configure and GL should be enabled   as   the default. You might need to install your distro's libgtkglext-dev   package before it will build.   Best wishes,   --   Peter Clifton   Electrical Engineering Division,   Engineering Department,   University of Cambridge,   9, JJ Thomson Avenue,   Cambridge   CB3 0FA   Tel: +44 (0)7729 980173 - (No signal in the lab!)   Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)   ___   geda-user mailing list   [3][4][5]geda-user@moria.seul.org   [4][5][6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References  1. mailto:[6][7]pc...@cam.ac.uk  2. [7][8]http://repo.or.cz/geda-pcb/pcjc2.git  3. mailto:[8][9]geda-user@moria.seul.org  4. [9][10]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [10][11]geda-user@moria.seul.org [11][12]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:[13]toldb...@gmail.com 2. mailto:[14]pc...@cam.ac.uk 3. [15]http://repo.or.cz/geda-pcb/pcjc2.git 4. mailto:[16]geda-user@moria.seul.org 5. [17]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 6. mailto:[18]pc...@cam.ac.uk 7. [19]http://repo.or.cz/geda-pcb/pcjc2.git 8. mailto:[20]geda-user@moria.seul.org 9. [21]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 10. mailto:[22]geda-user@moria.seul.org 11. [23]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [24]geda-user@moria.seul.org [25]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:russ.d...@asu.edu 2. mailto:toldb...@gmail.com 3. mailto:pc...@cam.ac.uk 4. http://repo.or.cz/geda-pcb/pcjc2.git 5. mailto:geda-user@moria.seul.org 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 7. mailto:pc...@cam.ac.uk 8. http://repo.or.cz/geda-pcb/pcjc2.git 9. mailto:geda-user@moria.seul.org 10. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 11. mailto:geda-user@moria.seul.org 12. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 13. mailto:toldb...@gmail.com 14. mailto:pc...@cam.ac.uk 15. http://repo.or.cz/geda-pcb/pcjc2.git 16. mailto:geda-user@moria.seul.org 17. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 18. mailto:pc...@cam.ac.uk 19. http://repo.or.cz/geda-pcb/pcjc2.git 20. mailto:geda-user@moria.seul.org 21. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 22. mailto:geda-user@moria.seul.org 23. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 24. mailto:geda-user@moria.seul.org 25.
Re: gEDA-user: pcb+gl
It works. Thanks! :) On 11 May 2011 21:51, Thomas Oldbury [1]toldb...@gmail.com wrote: Ah, problem solved... needed to cd into the directory. On 11 May 2011 21:31, Russell Dill [2]russ.d...@asu.edu wrote: Did the clone succeed? Did you cd into the cloned repo? On Wed, May 11, 2011 at 12:53 PM, Thomas Oldbury [1][3]toldb...@gmail.com wrote:  I'm getting this problem when trying to run the last command:  thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental  origin/pcb+gl_experimental  fatal: Not a git repository (or any of the parent directories): .git  Any ideas?  On 11 May 2011 18:41, Peter Clifton [1][2][4]pc...@cam.ac.uk wrote:  On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote:  I've heard a lot about this pcb+gl and I like it... and it turns out  I    fetched my git a few days from the enabling of it, so I think I  missed    the bus for it...   In git HEAD, there is some GL support. What I've always called   pcb+gl is a feature branch I've been maintaining separately from   the   main PCB git repository.   The aim is to merge it all to upstream git HEAD eventually!.   To get the most speed and fancyness (including the more translucent   thin-draw polygons), check out PCB from here:   git clone git://[2][3][5]repo.or.cz/geda-pcb/pcjc2.git   git checkout -b pcb+gl_experimental origin/pcb+gl_experimental   (If your card can cope with it, the pcb+gl_experimental branch has   better rendering speed and a few extra bits and pieces).   Otherwise, the default checkout should be the pcb+gl branch.   As others have said, just run ./configure and GL should be enabled   as   the default. You might need to install your distro's libgtkglext-dev   package before it will build.   Best wishes,   --   Peter Clifton   Electrical Engineering Division,   Engineering Department,   University of Cambridge,   9, JJ Thomson Avenue,   Cambridge   CB3 0FA   Tel: +44 (0)7729 980173 - (No signal in the lab!)   Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)   ___   geda-user mailing list   [3][4][6]geda-user@moria.seul.org   [4][5][7]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References  1. mailto:[6][8]pc...@cam.ac.uk  2. [7][9]http://repo.or.cz/geda-pcb/pcjc2.git  3. mailto:[8][10]geda-user@moria.seul.org  4. [9][11]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [10][12]geda-user@moria.seul.org [11][13]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:[14]toldb...@gmail.com 2. mailto:[15]pc...@cam.ac.uk 3. [16]http://repo.or.cz/geda-pcb/pcjc2.git 4. mailto:[17]geda-user@moria.seul.org 5. [18]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 6. mailto:[19]pc...@cam.ac.uk 7. [20]http://repo.or.cz/geda-pcb/pcjc2.git 8. mailto:[21]geda-user@moria.seul.org 9. [22]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 10. mailto:[23]geda-user@moria.seul.org 11. [24]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [25]geda-user@moria.seul.org [26]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:toldb...@gmail.com 2. mailto:russ.d...@asu.edu 3. mailto:toldb...@gmail.com 4. mailto:pc...@cam.ac.uk 5. http://repo.or.cz/geda-pcb/pcjc2.git 6. mailto:geda-user@moria.seul.org 7. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 8. mailto:pc...@cam.ac.uk 9. http://repo.or.cz/geda-pcb/pcjc2.git 10. mailto:geda-user@moria.seul.org 11. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 12. mailto:geda-user@moria.seul.org 13. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 14. mailto:toldb...@gmail.com 15. mailto:pc...@cam.ac.uk 16. http://repo.or.cz/geda-pcb/pcjc2.git 17. mailto:geda-user@moria.seul.org 18. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 19. mailto:pc...@cam.ac.uk 20. http://repo.or.cz/geda-pcb/pcjc2.git 21. mailto:geda-user@moria.seul.org 22. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 23. mailto:geda-user@moria.seul.org 24. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 25. mailto:geda-user@moria.seul.org 26. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___
gEDA-user: pcb+gl minor polygons glitch
On my ThinkPad X201, I am encountering a minor issue with PCB+GL... Not a show stopper, but a bit annoying. I notice that when I move the cursor, occasionally a random triangle extending from the middle of the board to the outer edge will be highlighted. I'm using Ubuntu 10.10 and the GPU is an Intel of some sort, not sure exactly which one. There seems to be no definite pattern... is this a confirmed bug with PCB+GL or just a glitch with my laptop/software combination? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gschem
Okay, the problem is definitely with Guile rather than gschem. Please make sure that you have its paths set up correctly so that it can find its Scheme library. I have the following environment variables set in Windows Vista, GEDABIN=D:\Program Files\gEDA\bin GEDADATA=D:\Program Files\gEDA\share\gEDA GUILE_LOAD_PATH=D:\Program Files\gEDA\share\guile\1.8 I also have D:\Program Files\gEDA\bin in the PATH variable. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hiding individual layers of a layer-group
I was already running pcb+gl - so that was a very fast fix. I didn't know about thin-draw :P I still think it would be handy to be able to turn of individual layers regardless of whether they are grouped though... On Thu, May 12, 2011 at 3:45 AM, Peter Clifton [1]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 07:16 -0700, Colin D Bennett wrote: On Wed, 11 May 2011 13:12:55 +0100 Peter Clifton [2]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote: Hi folks, I've just started using separate layers so for my polygons so that I can hide them when necessary. This works fine until I group them with the appropriate layer. Ie - top and ground in a layer grouping - with ground being the layer I am putting polygons on. When I go to hide the ground layer - the top layer is also hidden. If I put them in separate groups this doesn't happen - however it seems that if I put them in separate groups the DRC breaks... is there any way around this?? To achieve the visual clarity I guess you're looking for, switch to the pcb+gl branch and turn on thin draw polygons. Alternatively, thin draw polygons in git HEAD might still help you. The keyboard short-cut is Ctrl + Shift + P I do find that Thin Draw Polygons is helpful sometimes. However I also find many times that I would like to be able to show only specific layers (not whole layer groups). For instance, if I want to rip up all my ground plane polygons, I would like to be able to show only the ground plane layer (which is in the top layer's group) so that I can select all to select only the ground plane copper. How about some middle ground compromise - let it switch the layers off for the purposes of selection / rendering etc.., but still draw a faded (or de-saturated) version of their contents to aid not drawing geometry which would clash with other (hidden) sub-layers in the group. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: [3]+44 (0)7729 980173 - (No signal in the lab!) Tel: [4]+44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list [5]geda-user@moria.seul.org [6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:pc...@cam.ac.uk 2. mailto:pc...@cam.ac.uk 3. tel:%2B44%20%280%297729%20980173 4. tel:%2B44%20%280%291223%20748328 5. mailto:geda-user@moria.seul.org 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl minor polygons glitch
Thomas Oldbury wrote: is this a confirmed bug with PCB+GL or just a glitch with my laptop/software combination? I haven't seen this on my desktops, yet. They have ATI cards plugged in, driven by radeon and fglrx. From a hardware point of view they are pretty far from your set-up. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
Colin D Bennett wrote: (It would be fantastic if pcb could adjust traces dynamically as components are moved.) One of my favorite daydreams during manual routing: A plugin that handles all all tracks like tensioned rubber band. Then let go of the components and TWANG! -- The board area shrinks to minimum dimensions. :-) ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
Stephan Boettcher wrote: My schematics usually look almost like the layout. The pins of the symbols are placed like on the package. When in doubt, my design works the other way. The schematic should be as readable as possible. Preferred signal direction is left to right, top to bottom. If no other constraints are imposed, my layout look roughly like the schematic. This is convenient when debugging. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: crosscompile for windows with minipack
On 05/10/2011 11:05 PM, Kai-Martin Knaak wrote: As mentioned in the thread Where is pcb-20100929 for Win32 ? I tried to go the minipack way to crosscompile geda and PCB for windows. There were warnings at compile time -- about 2200 lines. I get a ton of those as well. I should probably redirect warnings and errors to the build log, with instructions to look in it in case of a build failure. Cesar ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl minor polygons glitch
On Wed, 2011-05-11 at 22:39 +0100, Thomas Oldbury wrote: On my ThinkPad X201, I am encountering a minor issue with PCB+GL... Not a show stopper, but a bit annoying. I notice that when I move the cursor, occasionally a random triangle extending from the middle of the board to the outer edge will be highlighted. I'm using Ubuntu 10.10 and the GPU is an Intel of some sort, not sure exactly which one. There seems to be no definite pattern... is this a confirmed bug with PCB+GL or just a glitch with my laptop/software combination? It might be a driver issue. I use Intel GM45 hardware myself, have confirmed excellent performance on a couple of GeForce cards, but have also heard reports of visual artaefacts on some Intel machines - possibly due to driver problems. If you have a digital camera which can record video, can you send a short clip of the problem occuring to me? (I presume it may be difficult to screen-shot, but give that a try too). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gerbview
On 05/11/2011 01:21 PM, Kai-Martin Knaak wrote: When run with wine, gerbview.exe shows a GUI where all text fails to render. The gerber view itself is fine as long as one of the lower render options are selected. No antialias, no transparency. There is some spew on the command line (see below). I attached a screenshot of the GUI with garbled text. gerbv seems to work fine under wine for me, with correct text, antialias and transparency. You could try using a newer version of wine (mine is 1.2.2). Cesar ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gerbview
On Wed, 2011-05-11 at 20:57 -0300, Cesar Strauss wrote: On 05/11/2011 01:21 PM, Kai-Martin Knaak wrote: When run with wine, gerbview.exe shows a GUI where all text fails to render. The gerber view itself is fine as long as one of the lower render options are selected. No antialias, no transparency. There is some spew on the command line (see below). I attached a screenshot of the GUI with garbled text. gerbv seems to work fine under wine for me, with correct text, antialias and transparency. You could try using a newer version of wine (mine is 1.2.2). Old versions of wine were pretty buggy in regards glyphs rendered through pango / cairo. Something these toolkits do is just different than most Windows apps. Running GTK / pango / cairo apps under Windows has always worked correctly to my knowledge. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: autocrop.c vs. pcb (git head)
I'm trying to load autocrop.so to my recently compiled (from git HEAD) pcb. What I get is this: dl_error: /home/leva/.pcb/plugins/autocrop.so: undefined symbol: ClearAndRedrawOutput Is there any way to tweak pcb and/or autocrop.c to work together? Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autocrop.c vs. pcb (git head)
Replace it with this: gui-invalidate_all (); ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autocrop.c vs. pcb (git head)
On Thu, 2011-05-12 at 03:03 +0200, Levente Kovacs wrote: I'm trying to load autocrop.so to my recently compiled (from git HEAD) pcb. What I get is this: dl_error: /home/leva/.pcb/plugins/autocrop.so: undefined symbol: ClearAndRedrawOutput Is there any way to tweak pcb and/or autocrop.c to work together? Edit autocrop.c and change ClearAndRedrawOutput (); to Redraw (); In general, you need to rebuild every plugin when you build a new version of PCB from git. plugins poke internal APIs and data-structures, which do change from time to time. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autocrop.c vs. pcb (git head)
On Wed, 2011-05-11 at 21:29 -0400, DJ Delorie wrote: Replace it with this: gui-invalidate_all (); More commonly, you would call Redraw (), and draw.c knows this means to poke gui-invalidate_all(), keeping the drawing model details more localised to draw.c and the GUIs. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autocrop.c vs. pcb (git head)
On Thu, May 12, 2011 at 03:03:20AM +0200, Levente Kovacs wrote: What I get is this: dl_error: /home/leva/.pcb/plugins/autocrop.so: undefined symbol: ClearAndRedrawOutput Is there any way to tweak pcb and/or autocrop.c to work together? If someone who has been hacking on the GUI can tell me what the functional replacement is (or if it's simply unnecessary now) I can fix the plugin. Levente: You could simply delete that line from the source and recompile. The worst that might happen is that you have to force the screen to redraw somehow after autocropping. -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minipack-result -- gerbview
Cesar Strauss wrote: gerbv seems to work fine under wine for me, with correct text, antialias and transparency. You could try using a newer version of wine (mine is 1.2.2). I will, when the update hits debian/wheezy. Currently debian is at v1.0.1 for oldstable, stable, testing and unstable, too. ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
