Re: gEDA-user: homebrew UV photoplotter for direct exposing of photo-etch-resist on laminate

2010-06-23 Thread Christoph Lechner
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DJ Delorie wrote:
   The last time I tried it, several years ago, it was 0.8mm pitch
 and an Apple LaserWriter 16/600PS (canon EX engine) and got crap
 results.  Now I have HP 8100DN and 8550DN printers; do you think
 either of those would be worth a try?
 
 Print these and inspect them under a microscope: 
 http://www.delorie.com/pcb/spirals/
 
 The etched board will almost always be worse than whatever toner is on
 the paper.
 
 I'm willing to obtain (to dedicate to this task) any printer that'll
 provide good results for this.
 
 Go UV!  There's a bit more investment, but the results are far more
 reliable.
 
 Either way, I suspect you'll be much happier with your results with a
 hacked laminator: http://www.delorie.com/electronics/laminator/
 Stock laminators are too cool for toner transfer and too hot for UV
 lamination.
My laminator does 195°C after a modification... I feed the PCB into the
laminator 4 times.

The CLJ4600 black toner starts to melt at about 175°C -- the paper
sticks to the PCB then after passing one time through the laminator.

- - cl
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Re: gEDA-user: homebrew UV photoplotter for direct exposing of photo-etch-resist on laminate

2010-06-21 Thread Christoph Lechner
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Armin Faltl wrote:
 Thanks for the link, very interesting
Well, those people don't care about Laser safety, I guess ...

My method of choice is toner transfer.

- - cl
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Re: gEDA-user: homebrew UV photoplotter for direct exposing of photo-etch-resist on laminate

2010-06-21 Thread Christoph Lechner
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Dave McGuire wrote:
 On 6/21/10 4:55 PM, Christoph Lechner wrote:
 Armin Faltl wrote:
 Thanks for the link, very interesting
 Well, those people don't care about Laser safety, I guess ...
 
   Why do you say that?  Surely they were wearing goggles.  Anyone smart
 enough to build such a system is surely smart enough to wear goggles
 while operating it.
I'm sure that most folks showing of laser stuff on the Internet don't
care too much about laser safety. One point could be that laser googles
are costly. Or maybe they don't know.

 
 My method of choice is toner transfer.
 
   I'm seriously considering putting together a laser plotter
 specifically because I've never gotten good results with toner transfer. :-(
So, when do you consider a result as good? With toner transfer I do the
TQFP44 w/ 0.8mm pin spacing footprints of ATMega16 regularly. It just works.

But there's a big difference when you compare different printers, even
when made by the same vendor. For example Laserjet 4000 prints don't
work for me, so I do my toner transfer stuff with my Color Laserjet
4600. Both printers using original HP supplies.


- - cl
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Re: gEDA-user: Strange polygon behavior (pcb 20091103)

2010-05-23 Thread Christoph Lechner
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Tamas Szabo wrote:
 Christoph Lechner wrote:
 When I enable thin draw poly mode, the outline of the polygon shown is
 just as I want it to be. If pcb would fill only the region within the
 contour, there would be no problem.
 
 Ok, this it not he solution, but for me, if I remove R1 and X1 the
 problem disappear. Did you realized it?
Yes, I can confirm that. But I didn't realize it before. But what is
wrong about these two components?

My workaround was to overlap multiple non-concave polygons resulting in
the polygon I need.

 
 Anyway, earlier I had a similar problem with one of my board. I deleted
 some wires (overlapped, etc), moved some components, and it became fine.
 
 Of course I think it is not the right way things should work (maybe a
 bug:-)
 
 Further, try to generate a gerber as well and check that too. Is it
 appear on the gerber output?

The wrong polygon does appear on the Gerber output as well. So it's not
the GUI, but some of the internal workings of PCB.

It's the last edge of the polygon contour causing the trouble. When
drawing new tracks, they remove the polygon copper only within the
contour I defined, not in the unwanted part of the polygon.

- - cl
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gEDA-user: Strange polygon behavior (pcb 20091103)

2010-05-22 Thread Christoph Lechner
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Hi,

adding some final polygons to my layout, pcb (version 20091103) exhibits
some strange behavior regarding polygons. The polygon produces a short
circuit between the two pins. What's surprising, the filled area is
outside the contour I entered at one corner.

See the attached screenshot. The polygon causing the pain is blueish.

The PCB file to reproduce is attached as well.

When I enable thin draw poly mode, the outline of the polygon shown is
just as I want it to be. If pcb would fill only the region within the
contour, there would be no problem.

How can I work around that problem? I've been trying, but found no
working solution.

- - cl
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inline: screenshot.png

broken-poly.pcb.gz
Description: GNU Zip compressed data


screenshot.png.sig
Description: Binary data


broken-poly.pcb.gz.sig
Description: Binary data


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Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-10 Thread Christoph Lechner
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Christoph Lechner wrote:
 Hi,
 
 just doing the PCB for my new power supply and I'm wondering how to add
 another layer to the component group of layers _without_ breaking all
 preexisiting tracks.
 After adding the new layer in the Preferences window and pressing 'O' to
 optimize the rat lines, pcb counts all nets as unconnected. The board
 has about 95% SMD components and it happens that their pads are
 considered as unconnected after inserting the new layer.
 
 Is there some trick I'm missing?
The problem doesn't show up when I use gsch2pcb from geda 1.6.0.
But the board I'm doing was created using gschem from geda 1.4.0, so I'm
still experiencing the problem.

I don't understand too much about the internals of the pcb file format,
so I wasn't able to figure out that makes the difference in the PCB
files. If I knew the problem, I probably could fix up my pcb file ...

- - cl

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gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-08 Thread Christoph Lechner
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Hi,

just doing the PCB for my new power supply and I'm wondering how to add
another layer to the component group of layers _without_ breaking all
preexisiting tracks.
After adding the new layer in the Preferences window and pressing 'O' to
optimize the rat lines, pcb counts all nets as unconnected. The board
has about 95% SMD components and it happens that their pads are
considered as unconnected after inserting the new layer.

Is there some trick I'm missing?

- - cl
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Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-08 Thread Christoph Lechner
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kai-martin knaak wrote:
 Christoph Lechner wrote:
 
 After adding the new layer in the Preferences window and pressing 'O' to
 optimize the rat lines, pcb counts all nets as unconnected. 
 
 Hmm. I just added a new layer below top layer to the attached little board. 
 This did not break connections to SMD pads. 
 
 Can you try to reproduce with this little test board? If you get broken 
 connections, please send the offending layout to the list, so we can analyze 
 what's going on here. 
 
Can't reproduce the problem with your small board. I can insert a couple
of new layers at random positions in the layer list without breaking it.
The reason for that could be that your test board has through hole parts
only. It's the SMDs that break.

I created my PCB file using gsch2pcb at the very beginning. I'll play
around a little bit to find out why my PCB breaks while yours won't break.

- - cl
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Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-08 Thread Christoph Lechner
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Christoph Lechner wrote:
 I created my PCB file using gsch2pcb at the very beginning. I'll play
 around a little bit to find out why my PCB breaks while yours won't break.
Created a simple test case that reproduces the problem for me. Looks
like gsch2pcb does something that pcb dislikes.

For me it breaks when I open the file (created by gsch2pcb), add some
new layers and press 'o' to optimize rats. Please the the tar file tc.tgz.

When I start up pcb with a new file, doing some stuff, and then adding
some new layers it won't break. I just added two 1206 to a new PCB
(created by pcb) and a net (by drawing on the rats layer). Then I routed
the net by hand. Here adding some layers won't break it. File
'wontbreak.pcb'.

I'm still running the old geda 1.4.0.
PCB version 20091103 (but pcb-20081128 has the same behavior).

- - cl
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tc.tgz
Description: application/compressed-tar
# release: pcb 20091103
# date:Sat May  8 16:25:34 2010
# user:cl (,,,)
# host:localhost.localdomain

# To read pcb files, the pcb version (or the cvs source date) must be = the 
file version
FileVersion[20070407]

PCB[ 5 5]

Grid[1000.00 0 0 0]
Cursor[0 0 0.00]
PolyArea[2.00]
Thermal[0.50]
DRC[699 400 800 800 1500 1000]
Flags(nameonpcb,uniquename,clearnew,snappin)
Groups(1,c:2,s:3:4:5:6:7:8)
Styles[Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600]

Symbol(' ' 18)
(
)
Symbol('!' 12)
(
SymbolLine(0 45 0 50 8)
SymbolLine(0 10 0 35 8)
)
Symbol('' 12)
(
SymbolLine(0 10 0 20 8)
SymbolLine(10 10 10 20 8)
)
Symbol('#' 12)
(
SymbolLine(0 35 20 35 8)
SymbolLine(0 25 20 25 8)
SymbolLine(15 20 15 40 8)
SymbolLine(5 20 5 40 8)
)
Symbol('$' 12)
(
SymbolLine(15 15 20 20 8)
SymbolLine(5 15 15 15 8)
SymbolLine(0 20 5 15 8)
SymbolLine(0 20 0 25 8)
SymbolLine(0 25 5 30 8)
SymbolLine(5 30 15 30 8)
SymbolLine(15 30 20 35 8)
SymbolLine(20 35 20 40 8)
SymbolLine(15 45 20 40 8)
SymbolLine(5 45 15 45 8)
SymbolLine(0 40 5 45 8)
SymbolLine(10 10 10 50 8)
)
Symbol('%' 12)
(
SymbolLine(0 15 0 20 8)
SymbolLine(0 15 5 10 8)
SymbolLine(5 10 10 10 8)
SymbolLine(10 10 15 15 8)
SymbolLine(15 15 15 20 8)
SymbolLine(10 25 15 20 8)
SymbolLine(5 25 10 25 8)
SymbolLine(0 20 5 25 8)
SymbolLine(0 50 40 10 8)
SymbolLine(35 50 40 45 8)
SymbolLine(40 40 40 45 8)
SymbolLine(35 35 40 40 8)
SymbolLine(30 35 35 35 8)
SymbolLine(25 40 30 35 8)
SymbolLine(25 40 25 45 8)
SymbolLine(25 45 30 50 8)
SymbolLine(30 50 35 50 8)
)
Symbol('' 12)
(
SymbolLine(0 45 5 50 8)
SymbolLine(0 15 0 25 8)
SymbolLine(0 15 5 10 8)
SymbolLine(0 35 15 20 8)
SymbolLine(5 50 10 50 8)
SymbolLine(10 50 20 40 8)
SymbolLine(0 25 25 50 8)
SymbolLine(5 10 10 10 8)
SymbolLine(10 10 15 15 8)
SymbolLine(15 15 15 20 8)
SymbolLine(0 35 0 45 8)
)
Symbol(''' 12)
(
SymbolLine(0 20 10 10 8)
)
Symbol('(' 12)
(
SymbolLine(0 45 5 50 8)
SymbolLine(0 15 5 10 8)
SymbolLine(0 15 0 45 8)
)
Symbol(')' 12)
(
SymbolLine(0 10 5 15 8)
SymbolLine(5 15 5 45 8)
SymbolLine(0 50 5 45 8)
)
Symbol('*' 12)
(
SymbolLine(0 20 20 40 8)
SymbolLine(0 40 20 20 8)
SymbolLine(0 30 20 30 8)
SymbolLine(10 20 10 40 8)
)
Symbol('+' 12)
(
SymbolLine(0 30 20 30 8)
SymbolLine(10 20 10 40 8)
)
Symbol(',' 12)
(
SymbolLine(0 60 10 50 8)
)
Symbol('-' 12)
(
SymbolLine(0 30 20 30 8)
)
Symbol('.' 12)
(
SymbolLine(0 50 5 50 8)
)
Symbol('/' 12)
(
SymbolLine(0 45 30 15 8)
)
Symbol('0' 12)
(
SymbolLine(0 45 5 50 8)
SymbolLine(0 15 0 45 8)
SymbolLine(0 15 5 10 8)
SymbolLine(5 10 15 10 8)
SymbolLine(15 10 20 15 8)
SymbolLine(20 15 20 45 8)
SymbolLine(15 50 20 45 8)
SymbolLine(5 50 15 50 8)
SymbolLine(0 40 20 20 8)
)
Symbol('1' 12)
(
SymbolLine(5 50 15 50 8)
SymbolLine(10 10 10 50 8)
SymbolLine(0 20 10 10 8)
)
Symbol('2' 12)
(
SymbolLine(0 15 5 10 8)
SymbolLine(5 10 20 10 8)
SymbolLine(20 10 25 15 8)
SymbolLine(25 15 25 25 8)
SymbolLine(0 50 25 25 8)
SymbolLine(0 50 25 50 8)
)
Symbol('3' 12)
(
SymbolLine(0 15 5 10 8)
SymbolLine(5 10 15 10 8)
SymbolLine(15 10 20 15 8)
SymbolLine(20 15 20 45 8

Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-08 Thread Christoph Lechner
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DJ Delorie wrote:
 Did you check the layer groups after adding, to make sure they still
 made sense?

The new layer has been added to group 2 (group 2 contains three
pre-defined layers: 'component', 'GND-comp', 'Vcc-comp'). Nothing else
was changed in the layer grouping.

I just press the add button in the Preferences dialog.

IMHO quite interesting, only the files I create using gsch2pcb (from
geda 1.4.0) break. The ones I create from scratch using pcb only and the
file sent by kai-martin don't cause any trouble when I add additional
layers.

On Monday I'll create a PCB file with gsch2pcb from the current gEDA
release.

- - cl
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Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-08 Thread Christoph Lechner
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kai-martin knaak wrote:
 Christoph Lechner wrote:
 
 The reason for that could be that your test board has through hole parts
 only. It's the SMDs that break.

 The resistors R1 - R4 are SMD footprint 0805
Your right. I missed that.

But your design 'survives' the insertion of additional layers nevertheless.

- - cl
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Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?

2010-05-08 Thread Christoph Lechner
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kai-martin knaak wrote:
 Christoph Lechner wrote:
 
 IMHO quite interesting, only the files I create using gsch2pcb (from
 geda 1.4.0) break. The ones I create from scratch using pcb only and the
 file sent by kai-martin don't cause any trouble when I add additional
 layers.
 
 Maybe, this is another instance of the infamous hyphenation bug.
 Do any of your footprints have a hyphen - in their file name? Unless the 
 hyphen separates a revision number at the end of the file, it is a source of 
 grief. gnetlist interprets it as part of a m4 definition and goes ahead. 
 This can result in very strange behavior in pcb.
Indeed, some of my pcb footprints have a '-' in their filenames.

But why does the strange behavior even occur when there are only two
1206 around?

- - cl
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Re: gEDA-user: gedasymbols.org down

2010-02-28 Thread Christoph Lechner
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Greg Cunningham wrote:
 On Sat, 2010-02-27 at 09:36 -0600, John Griessen wrote:
 Greg Cunningham wrote:
 Winter in Pennsylvania, summer here in Tasmania.  need rsync  round-robin
 dns.
 Rsync is being used for mirroring, but I'm not sure what the DNS setup is.
 Ping says it is alternating.  The mirror server was quick for a while
 after I added an A record at my hosting service's DNS server, but
 is back to slow unresponsive, and does eventually serve pages after multiple 
 attempts.

 How do you do round robin DNS?  I think DJs DNS server may still be on and 
 overruling
 mine.

 John

 
 Sorry for the delay, but I have had a major electrical re-fit at work.
 Long day...
 
 The other guys have answered adequately.
 
 I spoke without enough thought.  RR dns facilitates load sharing rather
 than redundancy.  Someone else with more experience in fail-over may
 offer a better suggestion.
I don't know what infrastructure is required for the gedasymbols web
site to work.

But I'll assume you run a MySQL database and you need some data volume
mounted as well.

Remote replication/high availability is quite hard to setup, because
it's so easy to get a what HA guys call a split brain situation: The
data on both nodes begins do diverge. Just think of one of the internet
connections going down. I can tell you from experience that split brain
is a real mess.

I've got some experience with high availability using Linux HA (now
called Pacemaker), DRBD (for the block device replication) and MySQL
replication. But in the setups I'm managing, the servers are mounted in
the same rack, with replication connection over gigabit loopback cable.

To change the A record when failover happens one could do an update of
the DNS entry at runtime. But I'm not sure if this can be done for the
gedasymbols.org entry. Of course your provider has to offer this service
to you, maybe quite expensive?

What about not running the server at home, but collocated at a data
center? THat would be somewhat easier to do.

- - cl
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Re: gEDA-user: gedasymbols.org down

2010-02-27 Thread Christoph Lechner
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Dave McGuire wrote:
 On Feb 27, 2010, at 10:36 AM, John Griessen wrote:
 Winter in Pennsylvania, summer here in Tasmania.  need rsync 
 round-robin
 dns.

 Rsync is being used for mirroring, but I'm not sure what the DNS setup
 is.
 Ping says it is alternating.  The mirror server was quick for a while
 after I added an A record at my hosting service's DNS server, but
 is back to slow unresponsive, and does eventually serve pages after
 multiple attempts.

 How do you do round robin DNS?  I think DJs DNS server may still be on
 and overruling
 mine.
 
   BIND round-robins returned records automatically.  For example, you
 can set up multiple A records for the same name, and successive queries
 return all of them rotated by one.
ok. but then you have a 50% chance to hit the dead node.

I can't resolve gedasymbols.org at the moment. Timeout.

BTW I've seen professional data centers go down with a blackout.
Shouldn't happen, but the 20kV - 400V power transformer of the whole
data center exploded due to a short circuit somewhere. Peaces of wire
all around the transformer, because the secondary was un-winded.
The power generators didn't start up properly, so when the UPS'
batteries were empty, the lights went out.

- - cl
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Re: gEDA-user: new ethernet chip...

2009-11-25 Thread Christoph Lechner
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DJ Delorie wrote:
 Digikey has the new KSZ8851 series... multiple bus options
 (spi/8/16/32), built-in PHY, only 85 milliamps, under $10:
 
 http://www.micrel.com/page.do?page=product-info/embedded_control.jsp
 
 Anyone know anything about these chips?  They look like I should be
 switching to them :-)
 
Although it's OT: When I want something with network connection, I don't
build a circuit on my own. Instead I use hacked up WLAN routers,
upgraded using OpenWRT. That's an open source firmware replacement that
you can run on many EUR 30 WLAN routers.
Given the amount of time you need for the from-scratch stuff, it's
really cheaper. And it's Linux, so code development is no problem at all.

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Re: gEDA-user: new ethernet chip...

2009-11-25 Thread Christoph Lechner
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DJ Delorie wrote:
 I have an openwrt box, but I often want something other than a router,
 usually something where the network part is SIGNIFICANTLY smaller than
 the special-purpose part of the project.  My last big project I used
 32-QFN ethernet chips to reduce space!
ACK, when it comes to space requirements, custom circuits are better.
Plus power consumption might be an issue.

But nevertheless, for example I'm planning to build a HV laboratory
supply so I can play around with tubes.
And I want to hook I up to my computer. The network connection will be
done using a OpenWRT modified WLAN router via WLAN.

So if my HV supply breaks, I'm not screwing up my whole Ethernet network :)

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Re: gEDA-user: new ethernet chip...

2009-11-25 Thread Christoph Lechner
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Dave McGuire wrote:
 On Nov 25, 2009, at 5:49 PM, Christoph Lechner wrote:
 Digikey has the new KSZ8851 series... multiple bus options
 (spi/8/16/32), built-in PHY, only 85 milliamps, under $10:

 http://www.micrel.com/page.do?page=product-info/embedded_control.jsp

 Anyone know anything about these chips?  They look like I should be
 switching to them :-)

 Although it's OT: When I want something with network connection, I  
 don't
 build a circuit on my own. Instead I use hacked up WLAN routers,
 upgraded using OpenWRT. That's an open source firmware replacement  
 that
 you can run on many EUR 30 WLAN routers.
 Given the amount of time you need for the from-scratch stuff, it's
 really cheaper. And it's Linux, so code development is no problem  
 at all.
 
Eh.  One can't easily start selling a bunch of them, or releasing  
 the design as open hardware, if they're made from hacked-up consumer  
 gear.  And purpose-built hardware certainly doesn't preclude the use  
 of Linux.
true, but I'm a hobbyist. So I dislike the bare-metal approach.
Instead I want it simple, no multi-layer PCBs etc.

I'm not going to sell these, so maybe a series of 5+ for personal use
but not more.

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Re: gEDA-user: xgsch2pcb config dialog

2009-11-15 Thread Christoph Lechner
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Peter Clifton wrote:
 Hi everyone,
 
 Just to let you know, that Andrey Smirnov has added support for writing
 config settings into your gsch2pcb project file from within xgsch2pcb.
 
 This means you can adjust footprint search paths, M4 vs. non-M4 file
 search order preferences, and many more advanced options present in the
 gsch2pcb project file.
 
 I've taken the liberty of attaching a small screen-shot here. This was a
 major missing feature in xgsch2pcb until now.
No problem :)

I think 50k attachments are OK, but _some_ (see the mail from T.R. :)
attach files sized 1M which I think is somewhat too much, because most
people on the list won't take a look at the PCB file (in that particular
case).

 
 Please fetch, test, enjoy.. and I'm sure you'll join me in thanking
 Andrey for his efforts.
Yes, great stuff. Another step to make the GEDA suite more user-friendly.


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Re: gEDA-user: gEDA and pcb status and minigration from Eagle

2009-11-12 Thread Christoph Lechner
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Bill Gatliff wrote:
 Kai-Martin Knaak wrote:
 Just don't want to ride a dead horse and notice later that the projects
 freeze
 
 No way. There way too many independent core developers. Even if they all 
 were to quit coding, I am sure some power users would carry on the flag. 
 Some users already did forks for their own purpose...
   
 
 Indeed.
 
 Given the proprietary nature of Eagle, you'd be far more screwed if they
 decided to kill the software than gEDA.
ack.

But what I really hate about proprietary software is the fact that you
have to pay for the most recent release.

Others mentioned it already, but the ASCII file format is a big plus of
gEDA and PCB. Keeping the files in revision control systems is no
problem, as the diffs are so small compared to a binary file where the
whole file is stuffed in the RCS.

Or for example I coded my own script to keep my symbols in sync with the
Xilinx fitter report. Given the pin count of todays CPLDs or FPGAs this
saves me a lot of hassle.

You can create net lists for AFAIK 20+ PCB programs

So, don't hesitate to check it out
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Re: gEDA-user: Working on xgsch2pcb-0.1.3 for Gentoo

2009-10-27 Thread Christoph Lechner
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Peter Clifton wrote:
 On Wed, 2009-10-28 at 00:25 +0100, Stefan Salewski wrote:
 
 unknown action `PF0)'
 unknown action `PF1)'
 unknown action `PF2)'
 unknown action `PF3)'
 unknown action `PF4)'
 [...]
 
 PCB is being asked to run the .cmd file produced by gnetlist. For some
 reason, this is failing. Perhaps you could send me the .cmd file to look
 at.
We had this on the list a long time ago. I guess there is some Atmel uC
around there.

Is it like in my posting from January?
http://archives.seul.org/geda/user/Jan-2009/msg00114.html

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Re: gEDA-user: )(

2009-10-05 Thread Christoph Lechner
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Kai-Martin Knaak wrote:
 On Sat, 03 Oct 2009 14:03:55 +0100, andrew whyte wrote:
 
 but rather than going down the route of
 needing schematics symbols, footprints and 3d models for each component
 in a design, could we add a height attribute to the schematics (this
 wouldn't be a big job for the designer using gattrib).  Then if someone
 could script something that takes the board outline, and adds block
 shapes based on the PCB footprint (outline) and the height for each
 component, the results would be a viable 3D skyline that would be
 workable from a CAD perspective, low maintenance, and would also give
 you an idea of the 3D system.
 
 This is good for most components. But some need more information to take 
 full advantage from 3D. The models for connectors and switches should 
 give the height and coordinates of the necessary holes. Components with a 
 heatsink should hint, where they need to be screwed. 
 
 Why not allow three levels of detail: 
 
 1) No 3D info given -- Guess some decent height from the silk of the 
 footprint.
I won't recommend that. Guessing is a bad idea because if it's wrong,
bad things can happen: The PCB doesn't fit into the case.

 
 2) Height info given -- Draw a rectangular solid based on outline and 
 height
Why not extrude the silk screen outline? That would work for many
complicated parts like most heatsinks, capacitors, IC sockets.

 
 3) Full 3D model present -- Add the model to the 3D representation of 
 the board.
That's the best way -- but of course it's a lot of work to come into a
position where you have all the 'standard' parts you work with all day
in a perfect 3d model.

Do you know Eagle3D? They produce some PovRAY files from the Eagle PCB
files and render them.

http://www.matwei.de/doku.php?id=en:eagle3d:eagle3d

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Re: gEDA-user: )(

2009-10-02 Thread Christoph Lechner
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Bill Gatliff wrote:
 Kai-Martin Knaak wrote:
 On Thu, 01 Oct 2009 23:58:52 +0100, Peter Clifton wrote:

   
 As an older (code no longer in existence) example, perspective like this
 is not hard to achieve:

 http://www2.eng.cam.ac.uk/~pcjc2/geda/gerbv_GL.png

 (That IIRC, is cairo-rendered onto a texture, then stretched onto a
 quad).
 
 IMHO, this is cheating. 3D objects would at least need ray tracing to 
 look half way real. If there is an urge to push 3D output of pcb layouts, 
 it would be wise not to reinvent the wheels. I'd suggest an export in a 
 3D format and delegate rendering to a third party application like the 
 excellent blender.
   
 
 Cheating or not, all the examples he posted look _awesome_!  :)
I agree.

When will that code hit the stable release of PCB?

I'm really looking forward.

 
 Let's say the objective of the 3D effects/output in PCB were to test
 against a 3D model of the whole system--- not just to visualize the
 (populated) PCB.  Would Blender be the right output format then?
Do you know Eagle3d? They generate a Povray input from Eagle.

http://www.matwei.de/doku.php?id=en:eagle3d:eagle3d

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Re: gEDA-user: Mr. Filter 0.1 released

2009-08-20 Thread Christoph Lechner
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asom...@gmail.com wrote:
 I've just posted the first public release of my new project, Mr.
 Filter.  It's an analog active filter design assistant.  Currently
 only low-pass and high-pass SallenKey filters are supported, but I'm
 working on extending it.  Gschem is used in the build process to
 generate all the schematics.  The project is hosted at
 https://sourceforge.net/projects/mrfilter/ .
Hi!

Just tried to visit the project's web site http://mrfilter.sourceforge.net/.
But all I got was a window prompting for username and password ...

But the screenshots are quite nice. Maybe I'll give it a spin.

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gEDA-user: PCB: how to merge polygon and component pads?

2009-08-16 Thread Christoph Lechner
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Hi,

I'm just doing the artwork for a SMPS power supply and I'm wondering if
it is possible to make a polygon and the pads of some component merge
completely. So not the usual way with a ring around every pad where you
see the tracks hidden under the poly :)

BTW: How do I set the clearline flag for existing tracks ?
SetFlag(Selected, clearline) does not work.

CU
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Re: gEDA-user: PCB: how to merge polygon and component pads?

2009-08-16 Thread Christoph Lechner
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Kai-Martin Knaak wrote:
 On Sun, 16 Aug 2009 17:38:17 +0200, Christoph Lechner wrote:
 
 I'm just doing the artwork for a SMPS power supply and I'm wondering if
 it is possible to make a polygon and the pads of some component merge
 completely. So not the usual way with a ring around every pad where you
 see the tracks hidden under the poly
 
 total connection is one of the thermal styles. You can cycle through 
 the styles of a via with shift-click.
 
 http://geda.seul.org/wiki/geda:pcb_tips#what_is_the_easiest_way_to_create_a_thermal_via
 
 
 BTW: How do I set the clearline flag for existing tracks ?
 SetFlag(Selected, clearline) does not work.
 
 Perhaps, you mean the join flag.
 
 http://geda.seul.org/wiki/geda:pcb_tips#the_polygons_are_shorting_my_tracks_what_can_i_do_about_it
OK, so I asked two FAQs at the same time.

The join flag actually was what I was looking for.
But when I select the polygon and press 'S' it floods over tracks from
different nets even if they have the clearline flag set.

But I like DJ's solution, because it's selective: The 'S' changes all
pads in the contour while I only want some (caps, inductors, MOSFET)
connected in that way.

Another question just comes to mind: How do I make sure that the
different polygons (each one connected to a different net) don't short?
The DRC doesn't find them.

CU
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Re: gEDA-user: B9A pin base

2009-08-04 Thread Christoph Lechner
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DJ Delorie wrote:
 How to put tube on a PCB (software, not the real board), anyway?
 
 Tubes aren't special - you create a footprint using vias such that you
 have plated holes wherever the tube's socket needs them (you normally
 wouldn't solder the tube itself in).  In the case of spade-type pins,
 you'd use the width of the spade pin as the diameter of the drill
 (plus a few thou for clearance).
 
 (see http://cgi.ebay.com.my/ws/eBayISAPI.dll?ViewItemitem=350093246441)
 
 I think the only tricky part is figuring out *where* the nine holes
 go, without a PDF spec for the socket.  It looks like there's ten
 evenly spaced slots, so every 36 degrees?  Might want to write a perl
 script to generate the footprint, using math to figure the
 coordinates.
Coded a Perl script some time ago, doing the task. I also made a PCB
footprint, which never made it to a physical PCB, so handle with care :)
BTW: I'd suggest using ceramic sockets like these:
http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItemitem=110409712742
But PCB through-hole tube sockets tend to stress the tube so the vacuum
might degrade -- at least some claim that.

CU
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Re: gEDA-user: MOSFET high-side driver schematic symbol suggestion?

2009-07-06 Thread Christoph Lechner
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Bill Gatliff wrote:
 Guys:
 
 
 Anyone care to suggest a schematic symbol for a MOSFET high-side 
 driver?  I'm having artist's block.  :)
What about a box, with some pins? ;)
This is the way IRF does it.
http://www.irf.com/product-info/datasheets/data/ir2184.pdf

Or see the app notes of some IC makers.

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Re: gEDA-user: MOSFET high-side driver schematic symbol suggestion?

2009-07-06 Thread Christoph Lechner
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Bill Gatliff wrote:
 Christoph Lechner wrote:
 -BEGIN PGP SIGNED MESSAGE-
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 Bill Gatliff wrote:
   
 Guys:


 Anyone care to suggest a schematic symbol for a MOSFET high-side 
 driver?  I'm having artist's block.  :)
 
 What about a box, with some pins? ;)
 This is the way IRF does it.
 http://www.irf.com/product-info/datasheets/data/ir2184.pdf
   
 
 That's what my current symbol looks like.  :)
 
 I'm considering dividing it up into two sub-symbols, however.  One for 
 the driver itself, and the other showing the power leads (for 
 decoupling caps, etc.).
I won't do that as it adds some extra confusion when you have to look
which parts belong together. Usually a half bridge driver has 14 pins
max. so no need to split it in bank like a FPGA.

 
 I might make the driver symbol look like a typical sideways triangle 
 a'la an op-amp, but there are three pins: the input, the output, and the 
 source voltage feedback.  So re-using that metaphor seems like a bad 
 idea--- but I might do it anyway. :)  Otherwise, it'll be just a boring 
 old box with three pins.
Or two driver symbols in a big box like Joerg suggested ...

The problem with a half-bridge driver is that you don't have two
identical drivers in a package. For the high-side driver a possible
symbol would look like
 |\/--- boost cap
 | \
in --|  *-- out
 | /
 |/
(I hate ASCII schematics) but the low side driver is different, of course.

That's a big pro for the box plus pins solution.

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Re: gEDA-user: hierarchy and refdes_renum

2009-06-25 Thread Christoph Lechner
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John Doty wrote:
 On Jun 24, 2009, at 3:22 PM, Christoph Lechner wrote:
 
 I'm planning a stepper motor card for 4 motors, so I wanted to put the
 motor drivers and all the stuff around in one subcircuit.
 The problem is that for example the out-1.sym instrace called HOME  
 (=the
 HOME pin of the symbol) is renamed into HOME1 by gnetlist. I run
 gnetlist only on the subcircuit. Don't know if it's OK to do so ...
Oh, I made a mistake. Of course, the components are renamed by
refdes_renum and not by gnetlist! Didn't use gnetlist on that design
because my progress has stalled since then.

 In that approach, you run gnetlist on the top level schematic to  
 produce a flat netlist, as required by may (most?) printed circuit  
 layout programs. Running gnetlist on the subcircuit will treat the IO  
 connectors as physical components.
Never made it to running gnetlist because the refdes problem is a
show-stopper. But when looking at the gTAG example I found out that
gnetlist has many options to make the netlist for your needs out of a
hierarchical design.

Do I really have to run refdes_renum on the subcircuit only?
Is there a tutorial about subcircuits on the net explaining all the
steps in detail?

CU
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Re: gEDA-user: hierarchy and refdes_renum

2009-06-25 Thread Christoph Lechner
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Anthony Shanks wrote:
 Just curious, did you try spnet yet?
Not yet.

But I successfully compiled and installed the source package a few
minutes ago.
My box is running the old Debian 3.1 release, btw.

But my problem isn't a netlisting problem but a refdes renumbering
problem, so I have to fix the refdes renumbering first.

CU
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gEDA-user: Some thoughts about PCB track attrs in your schematic [was: Re: autorouter fixes and enhancements]

2009-06-25 Thread Christoph Lechner
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Dave McGuire wrote:
 On Jun 22, 2009, at 1:33 PM, Stefan Salewski wrote:
 A bunch of fixes and enhancements to the original pcb autorouter
should now be available in the git repository.
 I wonder if the PCB autorouter should be more closely bound to the
 gschem schematics. For example, in the schematics we may specify
 priority of nets (fast signals, power, ...), trace width or clearance
 for net segments. Maybe by attributes? I have no idea how  
 commercial EDA
 software handles this.
 
I don't know how commercial EDA software handles this either, but  
 regardless of what they do, this functionality sounds extremely  
 powerful.
5 years or so ago, I had to work with Protel98. The solution there was
to add a special symbol (a red crosshair, if I'm right) to the net in
question and then specify PCB properties like track width in the schematic.

But I believe that would be possible to realize even with the current
versions of the tools (gschem, gnetlist, gsch2pcb, pcb).
In gschem one would add a new component to the library with one pin that
has to be attached to the net we want to have special properties. In the
value attribute one would say width=50mil.
IMHO the best way is to add another script to the toolchain.

So:

   gnetlist(*)
gschem --   *or*   -- the new tool -- import into pcb
   gsch2pcb  |  ^
 +--+
  (import attributes of nets
   via ExecuteFile)

The new tool would then create a script of actions to run using
ExecuteFile in PCB. OTOH the special component has to be filtered out
from the stuff fed into PCB, so it appears if there were no instances of
that component. Then after importing the filtered gnetlist output into
PCB (the (*) arrow), one executes the script generated by the filter
program and so the track width attributes of the nets are set to the
proper value.
Because the component was attached in the schematic fed into gnetlist we
know which net to set the track width.


CU
- - cl
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Re: gEDA-user: hierarchy and refdes_renum

2009-06-24 Thread Christoph Lechner
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Anthony Shanks wrote:
 What is your end goal here? Just to have hierarchical schematics or do
 be able to produce a hierarchical netlist? IMHO hierarchical
 schematics in gschem work perfectly fine, it's netlisting them that as
 of right now is very hackery/broken which is why I started a new
 netlister spNet. You can download the latest version here
 http://spnet.code-fusion.net but be warned the documentation is very
 shotty/inaccurate since I haven't officially released it yet. Refer to
 my last post on this list for more details.
I'm planning a stepper motor card for 4 motors, so I wanted to put the
motor drivers and all the stuff around in one subcircuit.
The problem is that for example the out-1.sym instrace called HOME (=the
HOME pin of the symbol) is renamed into HOME1 by gnetlist. I run
gnetlist only on the subcircuit. Don't know if it's OK to do so ...


But I will check out spnet tomorrow!

CU
- - cl
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gEDA-user: hierarchy and refdes_renum

2009-06-20 Thread Christoph Lechner
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Hi all,

I'm just trying around with hierarchy. This is my first hierarchy
design, and some questions remained open. I used the gTAG example as a
starting point.

What symbols do you use to 'declare' the pins in the subcircuit? I used
the in-1.sym and out-1.sym, but using the refdes for the pin identifier
looks like a hack to me. Is the used of these two symbols still state of
the art or are there better ways to follow?
So when renumbering the parts in the file, refdes_renum attaches a 1
suffix to all the refdes attributes of the in-1 and out-1 symbols on the
sheet, which is just a mess. Some Perl warnings pop up on the command
line, BTW.

What can I do to fix it?

I run the outdated gEDA suite 1.4.0, but I md5-verified that in-1.sym,
out-1.sym and refdes_renum are the same in the newest 1.4.3 release.

CU
- - Christoph
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gEDA-user: What is the logic in gnetlist/spice-sdb when to add a 'X' prefix to an identifier?

2009-02-08 Thread Christoph Lechner
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Hi all,

I'm just doing SPICE simulation of a SMPS.

The schematics are drawn using gschem, the SPICE netlist is generated
using the gnetlist and the spice-sdb backend (I'm still running gEDA 1.4.0).

Some of the diodes in the circuit are modelled by a SUBCKT, so I have to
manually add a X prefix to these diode identifiers in the SPICE netlist
(for example D101 = XD101) for the SPICE simulation to work. Because I
hate this somewhat:
How do I get spice-sdb to add the 'X' prefix automatically like it does
for example for ICs? I'm using the file and model-name attributes to say
what model to use.

- - cl
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Re: gEDA-user: What is the logic in gnetlist/spice-sdb when to add a 'X' prefix to an identifier?

2009-02-08 Thread Christoph Lechner
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al davis wrote:
 On Sunday 08 February 2009, Christoph Lechner wrote:
 Some of the diodes in the circuit are modelled by a SUBCKT,
 so I have to manually add a X prefix to these diode
 identifiers in the SPICE netlist (for example D101 = XD101)
 for the SPICE simulation to work. Because I hate this
 somewhat:
 How do I get spice-sdb to add the 'X' prefix automatically
 like it does for example for ICs? I'm using the file and
 model-name attributes to say what model to use.
 
 How can it know?
Well, I thought: maybe there's some attribute dedicated to this case ...
 
 I recommend that you add the X on the schematic.  Doesn't the 
 netlister just pass the label through?
Not really. If I call the diode XD108, the netlister calls it DXD108.

Wouldn't it be a work-around to call the diode U108? I'll try that.

- - cl

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Re: gEDA-user: What is the logic in gnetlist/spice-sdb when to add a 'X' prefix to an identifier?

2009-02-08 Thread Christoph Lechner
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Stuart Brorson wrote:
 I recommend that you add the X on the schematic.  Doesn't the
 netlister just pass the label through?
 Not really. If I call the diode XD108, the netlister calls it DXD108.

 Wouldn't it be a work-around to call the diode U108?
 
 I doubt that will work.
You're right. It didn't work :(

 2. Change the DEVICE attribute of your diode to something other than
 DIODE.  I forget what the desired attribute value should be, but it
 probably doesn't matter if you just give the symbol an X refdes.
That's what I did now. I set the DEVICE attribute to BZX84C18, the name
of the part. The refdes was changed to UD108, so the spice-sdb netlister
now calls the part XUD108.
That's OK for me, although this designator is a little bit ugly.

- - cl

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Re: gEDA-user: german article in the linux magazin online now

2009-01-27 Thread Christoph Lechner
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John Luciani wrote:
 On Mon, Jan 26, 2009 at 5:58 PM, Christoph Lechner cl0...@l-mx.de wrote:
 
 Almost everybody is using Eagle or the evil Target 3001 because it's
 so easy.

 
 People often confuse ease of doing a single task with a productive workflow
 for a project.
Some people consider a microcontroller + LCD display + some stuff a
project. That kind of a project can be done with any CAD tool, I guess.

 What is Target 3001 ?
Target 3001 is a EDA package that is quite popular in Germany (in the
German edition of Wikipedia they say that a poll done by Elektor 05/2004
amongst the readers had the result that Target 3001 was number 2 in
the popularity ranking. I don't have that particular issue at hand, but
I bet that the 'winner' is Eagle!

Some linkz:
* http://en.wikipedia.org/wiki/TARGET_3001!
* http://www.ibfriedrich.com/ (the company behind Target)
* http://en.wikipedia.org/wiki/Elektor

- - cl
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Re: gEDA-user: german article in the linux magazin online now

2009-01-26 Thread Christoph Lechner
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Stefan Salewski wrote:
 The last discussion about gEDA in a german forum which I can remember is
 this:
 
 http://www.mikrocontroller.net/topic/120373#new
 
 It may be better to ignore it, because it contains some really stupid
 statements.
There are some crazy guys hanging out there on mikrocontroller.net :)

And don't miss this one (in German as well):
http://www.roboternetz.de/phpBB2/zeigebeitrag.php?t=22180highlight=geda

 
 I think you reported about a german magazin article about (free) EDA
 tools which not even mention gEDA some time ago?
That was the Elektor EDA market survey, see my posting from 08/28/2008.
But applies to some other magazines, too.

People wanting one-click installation all the time should better head
for the clinic 8-)

Almost everybody is using Eagle or the evil Target 3001 because it's
so easy.


- - cl
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Re: gEDA-user: some pcb-20081128 nuisances/bugs

2009-01-07 Thread Christoph Lechner
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Christoph Lechner wrote:
 * (this one is maybe a result of my scarce pcb skills) after working for
 a while (and highlighting some nets during that time), pressing the
 'Select' button doesn't high light the net permanently; the net is only
 flashing.
OK found a way to reproduce this one:
1) Highlight one net in the PCB Netlist window by pressing the
'Select' button
2) With the net this highlighed run the DRC
3) now the nets flash for a short time instead of being highlighted.

HTH
- - cl


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gEDA-user: some pcb-20081128 nuisances/bugs

2009-01-06 Thread Christoph Lechner
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hi all,

after running PCB rev. 20081128 for some time, I think it's time to
report some troubles I ran into. Maybe the bugs are already reported or
(even better) fixed.

* My design contains an ATmega16 microcontroller and there are pins
named PD5 (OC1A) in gschem. When I run the .cmd file generated by
gsch2pcb in PCB this becomes PD5 (OC1A in the info window popping up
then hitting ctrl-r. On the shell msgs like unknown action `PC6)'
appear. Appears to be a parser problem ...
* Sometimes the meaning of the layer visibilty buttons is inverted. To
reproduce this, one start with a new layout, draws a single line on the
silk screen. Then hide the silk screen by pressing the 'silk' button.
Select 'Start New Layout' from the menu. Now lines drawn on the silk
screen are invisible, although the 'silk' button is active. Now the
meaning of the button is inverted!
* (this one is maybe a result of my scarce pcb skills) after working for
a while (and highlighting some nets during that time), pressing the
'Select' button doesn't high light the net permanently; the net is only
flashing.
* lines drawn on the silk screen of the layout have the 'found' flag set
(making them greenish), arcs for example don't have the 'found' flag
set. Doesn't apply to elements on other layers.


Another question (no bug!):
I need another layer for ensuring the creepage distance. What's the
correct procedure to insert a new layer without breaking up all the
routed tracks?

- - cl
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Re: gEDA-user: some pcb-20081128 nuisances/bugs

2009-01-06 Thread Christoph Lechner
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Dan McMahill wrote:
 Christoph Lechner wrote:
 
 * My design contains an ATmega16 microcontroller and there are pins
 named PD5 (OC1A) in gschem. When I run the .cmd file generated by
 gsch2pcb in PCB this becomes PD5 (OC1A in the info window popping up
 then hitting ctrl-r. On the shell msgs like unknown action `PC6)'
 appear. Appears to be a parser problem ...
 
 
 could you post the line from the .cmd file that contains PD5 in it?  It 
 is surely a quoting/escaping issue but I'm not sure where the fix is 
 needed.  It may be that the gschem backend needs improving.  My guess is 
 that I did not have spaces in pin names in mind when I did that bit.
The line is
ChangePinName(U302, 14, PD5 (OC1A))

I'm not running the most recent version of the gEDA suite, my gsch2pcb
version is 1.6.

- - cl
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Re: gEDA-user: geda/PCB missing in 'Elektor' CAD software comparison

2008-08-29 Thread Christoph Lechner
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Bert Timmerman wrote:
 Hi all,
Hi,

 
 Having a subscription to Elektor since 1978 or so, I have rarely seen any
 article based on *nix kind of OS applications.
OK, I was born in 1984, so I don't have that much Elektor experience :)

 Elektor seems to live in it's own M$ based universe.
Might be true. But OTOH, in their review of the Eagle suite of tools
they mention that Eagle is available for Windoze as well as Linux and
Mac OS.

 
 Most applications (including most firmware), which can be downloaded from
 the Elektor website, can only be installed/run from a M$ based platform.
 
 At best one is given a hex file or source (Visual Basic ?) to play with.
 
 IMHO, not a Open Source / Open Hardware mindset at all.
I blame the authors of the articles too, because they decide if their
source code or whatever is available or not.

So why did I start using the geda suite, although there was a Protel
installation ready to use?
The reason was that I realized that every design I do with any
commercial software just makes it harder to switch the software. It's
like some sort of cage around _your_ design. Because you want to reuse
your schematics, you want to use your symbols etc. pp. So first, I
started to do schematic capture with gschem, doing only the layout with
commercial software. So at least schematics are under my control.

That's just another point I'd add to a letter.

Feel free to add other points to add. This is why I kicked off that thread!


 Anyway, it's not all bad, they seem to have good HW designs from time to
 time, so I keep the subscription, ... and it keeps me busy in maintaining at
 least one M$ platform, so I do not estrange from my collegues at work and
 keep in touch with the evil empire :-)
 
 Kind regards,
 
 Bert Timmerman.
 
 PS: Maybe a proper win-gEDA installer will get the attention of Elektor.
They're possibly missing a simple, one-click installation. For some
systems, RPMs (or whatever package manager they use) exist, keeping the
level of frustration low.
But building programs on your own is part of the Linux experience :) Not
kidding; I believe that advanced Linux users sometimes have to compile
something on their own. If you have all the dev packages of the
libraries on your box, it's almost like a one-click installation. (OK
you have to enter 'make' ...)

regards
Christoph
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gEDA-user: geda/PCB missing in 'Elektor' CAD software comparison

2008-08-28 Thread Christoph Lechner
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Hi all,

in the recent 'Elektor' Sep. 08 issue (Elektor is a hobbyist level
magazine about electronics sold in Germany and some other countries)
they have a article mentioning about 30 CAD software packages (some sort
of market survey). But the geda suite is missing there. PCB is missing
as well! But: IMHO I think that the geda+PCB suite can out-perform most
of the packages there.

I know that some geda hackers from Germany are hanging out here. So why
don't we send a letter to the editor, pointing out that there is free
software out there? They (the folks at Elektor) even encourage to do so,
if readers think something's missing!

The range of software packages featured is from some feature limited, so
called free (not open source!) programs, up to the EUR 3000 range. The
only open source software is KiCad.
They wrote some paragraphs about every package about what's good and
what's not. They looked for schematic capture, PCB layout, auto routing
and simulation.

regards,
- cl
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gEDA-user: gschem 1.4.0 crashing while editing symbol attributes

2008-08-23 Thread Christoph Lechner
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Hi all,

I can crash gschem version 1.4.0 reproducibly by doing the following:

1) fire up gschem from the shell (empty sheet!)
2) add a spice-directive-1 symbol
3) highlight the new symbol and type ee to open the Edit Attributes window
4) right click the 'file' attribute and select delete from the menu
popping up
5) click on the value of the 'value' attribute and remote the question
mark by hitting the backspace key
6) then right click on the now empty value of the 'value' attribute
(doesn't work for me if the value field isn't empty)

*crash*

This is what is written to the terminal
[EMAIL PROTECTED]:/tmp$ gschem
gEDA/gschem version 1.4.0.20080127
gEDA/gschem comes with ABSOLUTELY NO WARRANTY; see COPYING for more details.
This is free software, and you are welcome to redistribute it under certain
conditions; please see the COPYING file for more details.


(gschem:10226): Gtk-WARNING **: GtkTextView - did not receive
focus-out-event. If you
connect a handler to this signal, it must return
FALSE so the entry gets the event as well

Gtk-ERROR **: file gtktextview.c: line 4482 (blink_cb): assertion
failed: (GTK_WIDGET_HAS_FOCUS (text_view))
aborting...
Aborted
[EMAIL PROTECTED]:/tmp$

My intend was to paste some text from the clipboard into the value field
of the directive. I wasn't able to crash gschem by using for example the
resistor-1 symbol, so maybe only symbols having many default attributes
are affected.

Maybe this is an old issue, but I'm reporting nevertheless.

BTW: Still running Debian 3.1, so maybe that's the reason for the
behavior. But the build process worked without any complaints and the
prerequesites (gtk2, libguile, ...) are met by my system. Besides that
issue, gschem works for me like a charm and I can do my almost-every-day
work with it.

regards
Christoph
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Re: gEDA-user: gschem 1.4.0 crashing while editing symbol attributes

2008-08-23 Thread Christoph Lechner
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Peter Clifton wrote:
 On Sat, 2008-08-23 at 10:56 +0200, Christoph Lechner wrote:
 -BEGIN PGP SIGNED MESSAGE-
 Hash: SHA1

 Hi all,

 I can crash gschem version 1.4.0 reproducibly by doing the following:

 1) fire up gschem from the shell (empty sheet!)
 2) add a spice-directive-1 symbol
 3) highlight the new symbol and type ee to open the Edit Attributes window
 4) right click the 'file' attribute and select delete from the menu
 popping up
 5) click on the value of the 'value' attribute and remote the question
 mark by hitting the backspace key
 6) then right click on the now empty value of the 'value' attribute
 (doesn't work for me if the value field isn't empty)

 *crash*
 
 Thanks for the report.
No problem. :)

Just found out that it's even easier to crash it.

Just place a resistor, delete the contents of the value field in the
Edit Attributes window (just as above). Then with the text field still
having the focus click some other window on the screen (for exampe a
shell window)

Then I get the same stuff on the shell.

regards
Christoph
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Re: gEDA-user: ngspice subckt problems

2008-08-15 Thread Christoph Lechner
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al davis wrote:
 [Spice differences and troubles ...]
 
 If you want to use Gnucap, I will help you make it work.  It 
 will help me, by having a set of real files that somebody is 
 using.
Thank you for that offer.

Today I picked some old machine of the doorstopper class (P3 800 MHz),
installed Debian 4.0 on it and compiled gnucap successfully. So I'm
ready by now :)
I guess reading the gnucap documentation is a good starting point for me.


 The background of why I now want to use ngspice is that I
 want to play with the parameters a little bit to get out the
 maximum possible output voltage swing. (This circuit is
 intended for scope tube deflection.) = Lots of simulation
 runs.
 So one needs some sort of scriptable spice environment, for
 example a UNIX command line program :)
 
 That's another place where they are all different.
 
 NGspice doesn't offer much in this regard.  Gnucap offers much 
 more in being scriptable and ability to play with parameters.
 
 Gnucap lets you make arbitrary changes to the circuit 
 interactively, so doing a bunch of what-if's is actually very 
 easy.  It also will give you a lot more info about your 
 circuit, but only if you ask.
Changing the circuit interactively is really cool, so one doesn't have
to launch the program over again and again ...

Christoph


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gEDA-user: ngspice subckt problems

2008-08-14 Thread Christoph Lechner
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Hi all,

(this is actually a ngspice posting, so maybe it's off-topic?)

I'm just trying to use my spice model in ngspice.
LTspice/SwitcherCad from Linear Technology runs it like a charm.

The .cir file was created from my gschem schematics file by running
gnetlist -g spice-sdb -o triode2.cir triode2.sch. getnetlist -g drc2
runs without any error message in the DRC file. It only prints some
warnings:
NOTE: Found pins without the 'pintype' attribute: X102:1 X102:2 X101:1
X102:3 X101:3 X101:2
But I don't believe that these have something to do with my problem.

If I run ngspice I get some error messages:
Too few parameters for subcircuit type 12at7 (instance: x102)
Too few parameters for subcircuit type 12at7 (instance: x101)

The 12at7 subcircuit model is a triode model by Norman Koren:
http://www.normankoren.com/Audio/Tubemodspice_article.html

It appears to me that the offending line in the spice file is
X102 vplate2 vg2 vcat 12AT7
The subcircuit in the model file begin with
.SUBCKT 12AT7 1 2 3  ; P G C

So I really don't know where's the problem :(

For the curious:

PDF of the schematic
http://www.cl-projects.de/projects/sc/triode2.pdf
.cir file working fine in LTSpice
http://www.cl-projects.de/projects/sc/triode2.cir

The background of why I now want to use ngspice is that I want to play
with the parameters a little bit to get out the maximum possible output
voltage swing. (This circuit is intended for scope tube deflection.)
= Lots of simulation runs.
So one needs some sort of scriptable spice environment, for example a
UNIX command line program :)

What's wrong?

regards,
Christoph
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Re: gEDA-user: ngspice subckt problems

2008-08-14 Thread Christoph Lechner
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Stuart Brorson wrote:
 If I run ngspice I get some error messages:
 Too few parameters for subcircuit type 12at7 (instance: x102)
 Too few parameters for subcircuit type 12at7 (instance: x101)

 The 12at7 subcircuit model is a triode model by Norman Koren:
 http://www.normankoren.com/Audio/Tubemodspice_article.html

 It appears to me that the offending line in the spice file is
 X102 vplate2 vg2 vcat 12AT7
 The subcircuit in the model file begin with
 .SUBCKT 12AT7 1 2 3  ; P G C
 
 I believe that the ; to start a comment is a syntax from PSpice
 which is undefined in ngspice.  Please remove the ; P G C stuff and
 try again.
This didn't help. Removed all the comments beginning with ; and also
removed all unused tube models.

Uploaded this file as well
http://www.cl-projects.de/projects/sc/triode2-stripped-down.cir

regards
Christoph
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Re: gEDA-user: ngspice subckt problems

2008-08-14 Thread Christoph Lechner
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Werner Hoch wrote:
 Hi Christroph,
Hi Werner,

 On Donnerstag, 14. August 2008, Christoph Lechner wrote:
 Uploaded this file as well
 http://www.cl-projects.de/projects/sc/triode2-stripped-down.cir
 
 You're .SUBCKT line is longer:
 .SUBCKT 12AT7 1 2 3
 + PARAMS: MU=60 EX=1.35 KG1=460 KP=300 KVB=300 RGI=2000
 + CCG=2.3P  CGP=2.2P CCP=1.0P
 
 The lines beginning with '+' are part of the subcircuit definition.
OK, I'm not that familiar with the Spice subcircuit syntax. Actually I
considered Spice as some sort of black-box.

 These are parameters of the subcircuit. ngspice can not simulate such 
 subcircuits by default. 
 
 You have to build ngspice with the configuration 
 option --enable-numparam.
Have tried this, but it didn't help me either.

I ran
./configure --prefix=/opt/ngspice --enable-numparam --enable-xgraph
to configure the new Spice installation. Then I did the usual 'make' and
'make install' stuff.

The tarball I downloaded is ng-spice-rework-17.tar.gz, dated 2005-08-30.


I'm also sure that I run the right ngspice binary in /opt/ngspice,
because I can only run 'ngspice' on my command line when I add
/opt/ngspice/bin to my path.

Or do I need some developer version, as the one I used is about 3 years old?

regards
Christoph
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Re: gEDA-user: ngspice subckt problems

2008-08-14 Thread Christoph Lechner
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Stuart Brorson wrote:
 Alternately, why don't you grab the latest Gnucap?  Al (the main
 developer) updates the release tarball quite regularly.
Hmm, looks like the g++ compiler of Debian 3.1 (still running that
fairly 'mature' distro :) can't handle the source code of gnucap. Looks
like the code of gnucap triggers some bug in the really old g++ version
that shipped with Debian 3.1.

g++ dies with
make[2]: Entering directory `/loc_files/ngspice-build/gnucap-2008-05-27/src'
g++ -DHAVE_CONFIG_H -I. -I..   -DNDEBUG  -g -O2 -MT d_mos8.o -MD -MP -MF
.deps/d_mos8.Tpo -c -o d_mos8.o d_mos8.cc

cc1plus: out of memory allocating 2653014200 bytes after a total of
24993792 bytes


So I'll have to wait until Monday ...

regards
Christoph
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Re: gEDA-user: LaTeX in schematics

2007-11-24 Thread Christoph Lechner
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Dan McMahill wrote:
 Peter TB Brett wrote:
 Hi there,

 I want to print some mathematics on a gEDA schematic, and was wondering if 
 anyone has ever successfully used e.g. TeX markup in the EPS output to do 
 so...

 Thanks,

 [..]
 
 I'd love to see something similar implemented in gschem.  That ability 
 is why I still use tgif for presentation quality schematics or block 
 diagrams.
I agree. Having something TeX-/LaTeX-like in gschem would be a wonderful
feature. But I don't have any clue how to do this. Actually one is best
off if the TeX output would be something in vector representation, but
TeX output in any bitmap format will do as well. (Although I don't have
no _real_ idea about how to implement a feature like that. Don't know
enough about the internals of both TeX and geschem)

OTOH the only thing I use TeX syntax in gschem is when I document why I
use this value for that resistor and things like that. It's so plain and
simple usually that one can really figure out how it would look like
without tex :)


- - cl
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Re: gEDA-user: database driven component chooser - part II

2007-10-04 Thread Christoph Lechner
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Rui Tavares wrote:
 What are the credentials (user  passwd) for this:
 http://levente.obudanet.hu/phpmyadmin/
User name 'guest' and NO password :)
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Re: gEDA-user: database driven component chooser - part II

2007-10-02 Thread Christoph Lechner
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Levente wrote:
 Christoph Lechner [EMAIL PROTECTED] wrote:
 OK. I took a look at the database. So a question came to mind when I saw
 the layout of the 'device' table:
 Why do you store the relationship between entries in the 'device' table
 and entries in the 'supplier' table in fields named supplier*,
 ordering_code*, price* in the 'device' table? What if there are more
 than 3 suppliers for any given part?

 As the relation between 'device' and 'supplier' is a many-many
 relationship, you'd be better off creating just another table, holding
 the device's ID, the ID of the supplier and fields for the ordering_code
 and the price. Then you only need to LEFT JOIN the tables
 rel-device-supplier and supplier and you get all suppliers for a given
 part. This would give you a somewhat tidier DB layout ...
 
 Ok,
 
 I have modified the structure of my database. Thank's for the hint.
Ok, seen that. Looks really nice now.

But make sure to add an ID field with autoincrement turned on to the new
relation table 'source' to avoid collisions. These can really screw it up :(

Why not add an index over 'dev_ID' and 'sup_ID'? Would tweak the
performance quite alot.

Just another 2 cents :)

CU
- - cl
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Re: gEDA-user: database driven component chooser - part II

2007-10-01 Thread Christoph Lechner
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Jonatan Åkerlind wrote:
 On sön, 2007-09-30 at 13:33 +, Levente wrote:
 But in a nutshell, it looks up a component from a mySQL database, and
 parse the result. The database is online, and so you can see what is
 inside.
 
 How hardcoded is it towards mySQL? After all postgresql is a good
 alternative often forgotten about.
Usually porting between MySQL and postgresql isn't that hard, given the
MySQL SQL queries follow the SQL standard. The problem is that MySQL
accepts some SQL queries that other DB packages like postgresql don't
accept! A quite popular mistake is not to list all fields you don't use
an aggregate function on in your GROUP BY clause. MySQL accepts this ...
while others don't.

CU
- - cl
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Re: gEDA-user: database driven component chooser - part II

2007-10-01 Thread Christoph Lechner
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Levente wrote:
 Duncan Drennan [EMAIL PROTECTED] wrote:
 I'm back from Stuttgart where I could hack a bit on my database stuff.
 Now, I have a command line SQL client, which can be used as a chooser. It
 takes command line arguments as search parameters, and makes an SQL query, 
 and
 prints the result.
 Levente, where could I find out more about what exactly your programme does?
 
 I am about to write a README for it, and check it into my CVS repository, but
 my washingmachine died, so I have to go to my parents to do the whashing.
 
 But in a nutshell, it looks up a component from a mySQL database, and
 parse the result. The database is online, and so you can see what is
 inside.
OK. I took a look at the database. So a question came to mind when I saw
the layout of the 'device' table:
Why do you store the relationship between entries in the 'device' table
and entries in the 'supplier' table in fields named supplier*,
ordering_code*, price* in the 'device' table? What if there are more
than 3 suppliers for any given part?

As the relation between 'device' and 'supplier' is a many-many
relationship, you'd be better off creating just another table, holding
the device's ID, the ID of the supplier and fields for the ordering_code
and the price. Then you only need to LEFT JOIN the tables
rel-device-supplier and supplier and you get all suppliers for a given
part. This would give you a somewhat tidier DB layout ...

just my 2 cents
- - cl
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Re: gEDA-user: PCM making methods - was - Re: alarm clock update

2007-09-12 Thread Christoph Lechner
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Daniel Sandström wrote:
 Do you have any links about CuCl?

 
 This looks very interesting, so I did a bit of googling and these links
 seems to deal with most aspects:
 
 http://www.xertech.net/Tech/CuCl_ech.html
 http://members.optusnet.com.au/~eseychell/PCB/etching_CuCl/index.html
The first one only contains BW pictures, so the second one is much
better, as color matters :)

Thanks
- - C. Lechner
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Re: gEDA-user: PCM making methods - was - Re: alarm clock update

2007-09-12 Thread Christoph Lechner
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John Griessen wrote:
 Hmm  recommend optimum specific gravity to be between 1.240 to 1.330
 
 I wonder if the wine gravity gauge I have has that range
AFAIK the density of ethanol is below 1g/cm^3 :)

I'd prefer a hydrometer as used when measuring the density of the acid
in car batteries. IMHO the ideal density value of the sulfuric
acid/water mixture in the car battery is in the range of 1.3g/cm^3:
A fully charged car battery has an electrolyte density of 1.28g/cm^3,
while a completely discharged car battery has one of about 1.1g/cm^3.

- - C. Lechner


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Re: gEDA-user: Clearing vias (Was: Last code sprint's IRC log and pictures)

2007-08-21 Thread Christoph Lechner
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Bob Paddock wrote:
 On Monday 20 August 2007 09:32, Christoph Lechner wrote:
 Exactly. If you draw a track in Protel, its ends are rounded; it adds
 a filled circle with diameter=track width to the end points
 
 Which has the really annoying effect of giving you a rounded end
 poking out of a pad when you enter the pad from the other side.
 Sometimes resulting in DRC errors. 
 Protel/DXP snaps to the center point of the pad, and the rounded end doesn't
 always end where the pad does and gets close to the next
 pad of a device.
Never seen that. Of course my artwork should be a snap for PCB tools.
The most 'extreme' artwork style I use is 2 layer PCB with 10/10mil
rules. Not that hard. But, before I let some PCB fab commit my stuff on
FR4, I want to do a prototype board on my own.

 
 You can move things around as you like. Then once you need the polygon
 rebuild, you double click the polygon plane and a dialogue pops up,
 showing the parameters used when you first created that fill. Then you
 click OK and it recomputes the plane. The baseline is that it isn't done
 automagically at all, you have to do it as you want/need.
 
 Because it is slow and crash prone in my experience with it.
Thats right. Whenever I work with Protel, I begin a new file about every
two hours as file corruption happens sometimes. But it's M$ Windoze
software :) Somewhat OT, BTW.

- - C. Lechner
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Re: gEDA-user: Last code sprint's IRC log and pictures

2007-08-20 Thread Christoph Lechner
Ales Hvezda wrote:
 I finally got around to posting the irc log from the last code sprint
 held on 2007/08/05:  
 
 http://geda.seul.org/sprints/irclog_sprint_20070805.txt
 
 Also, it wasn't a particularly productive code sprint for me, mainly
 because I was chasing a subtle hidden bug, but on the plus side I did
 take lots of pictures of DJ making some PCBs.  You can find the set here:
 
 http://geda.seul.org/projects/djs_pcbs/
Cool stuff, but some questions anyway:

How wide are those tracks on the picture
http://geda.seul.org/projects/djs_pcbs/IMG_2205s-1-0.html ?
What's the purpose for that green stuff seen on some of these pictures?
I've never seen this before, although I'm doing PCB artwork using a
modified laminator for toner transfer on a regular base. (The target
temperature of the laminator was set to about 185°C, the old one was
110°C. So it's sorta stress for the device)

There are some pictures of my current project on the net:
http://www.cl-projects.de/projects/glcd_controller/

Actually there are some small holes in the copper areas. That's because
the PCB went through the laminator only once. Normally I'd send it
through the laminator for about 6 times in different directions.
So the temperature had to be higher than normal, and I ended up with a
molten laminator :( But at least the PCB is OK.

- C. Lechner



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Re: gEDA-user: Clearing vias (Was: Last code sprint's IRC log and pictures)

2007-08-20 Thread Christoph Lechner
Peter Clifton wrote:
 There are some pictures of my current project on the net:
 http://www.cl-projects.de/projects/glcd_controller/
 
 Inspired by the detailing around pins on that PCB, I wounder how easy it
 would be to make PCB output like the attached glcd-clearances.png? (This
 is a re-coloured zoom in on a couple of the pins from the above
 project).
I've added a screenshot of the area around the RS232 DB9 connector. This
is how it looks in the PCB tool I use (Protel 98).
BTW, go get the dimensions the big round pads in the images you attached
are 200mil, the tracks are 15mil.

 PCB's output, pcb_clearances.png shows sharp copper edges where clipping
 against a polygon occurs. This can often leave thin slivers of track
 which may / may not connect in production.
Those very thin copper areas at the intersect of the circle around the
pad and this straight, vertical line deliver random results, depending
on how far your etchant can go.

 If its possible to detect these thin slivers and cut them out (if below
 some minimum width), possible rounding their ends as shown?
Don't know, maybe the pcb coders will join this discussion :)

But I'd guess it's the result of different implementations. Protel draws
all those lines and circles that define the outline of the copper area
using tracks with an user-definable width. pcb appears to use tracks
that are infinitely thin. So you get problems.
As you see in the attachment I've made (this is the PCB artwork in
Protel 98) the circles around big pads look clumsy. Actually these
aren't circles at all. When Protel fills an area with a polygon plane
(this is how they call it) they compute and draw the outline of the
plane first (and draw this outline using tracks with an given width) and
then fill the plane with tracks. You can define
1) the track width
2) the grid size, i.e. the space between the tracks
So here I set grid size  track width to obtain a closed fill.

CU
- C. Lechner


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Re: gEDA-user: Clearing vias (Was: Last code sprint's IRC log and pictures)

2007-08-20 Thread Christoph Lechner
Forgot to send the attachment ...

- C. Lechner
inline: rs232-conn.png

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Re: gEDA-user: Clearing vias (Was: Last code sprint's IRC log and pictures)

2007-08-20 Thread Christoph Lechner
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

Peter Clifton wrote:
 On Mon, 2007-08-20 at 13:57 +0200, Christoph Lechner wrote:
 Peter Clifton wrote:
 
 But I'd guess it's the result of different implementations. Protel draws
 all those lines and circles that define the outline of the copper area
 using tracks with an user-definable width. pcb appears to use tracks
 that are infinitely thin. So you get problems.
 As you see in the attachment I've made (this is the PCB artwork in
 Protel 98) the circles around big pads look clumsy. Actually these
 aren't circles at all. When Protel fills an area with a polygon plane
 (this is how they call it) they compute and draw the outline of the
 plane first (and draw this outline using tracks with an given width) and
 then fill the plane with tracks. You can define
 1) the track width
 2) the grid size, i.e. the space between the tracks
 So here I set grid size  track width to obtain a closed fill.
 
 I knew some packages used this technique of rasterizing with tracks to
 form polygons, but I wasn't aware they made it this obvious to the user.
 I guess setting the track width defines the end radius and size of
 feature it will add though.
Exactly. If you draw a track in Protel, its ends are rounded; it adds
a filled circle with diameter=track width to the end points


 Once you've filled an area with polygon, can you still move things about
 (and have the polygon re-flow), or do you have to rip it up and start
 again?
You can move things around as you like. Then once you need the polygon
rebuild, you double click the polygon plane and a dialogue pops up,
showing the parameters used when you first created that fill. Then you
click OK and it recomputes the plane. The baseline is that it isn't done
automagically at all, you have to do it as you want/need.
But my work flow as that I route all tracks on the PCB and when I'm done
I apply the polygon plane. This way, it's easy to see when you have to
swap two pins on a CPLD/FPGA etc.

 I always find myself playing tricks with PCB (using separate polygons,
 adjusting clearance on unrelated elements etc..) in an attempt to make
 boards look nicer and have less of those infinitesimal tracks, and
 other oddly shaped clearance leftovers. Perhaps I shouldn't worry so
 much about visual appearance though!
When doing some prototype boards, I never care about the appearance :)
Of course, final work should look professional, whatever it is...

 I don't know enough about how PCB's internal geometric data-structures
 or the new polygon code work to even postulate whether this kind of
 behaviour is possible. Whether it could be done fast is yet another
 question.
Protel pours the whole copper plane in about 15 seconds on a Pentium III
800 MHz machine. Using 15mil wide tracks and 13mil grid size. So it
should be feasible to do it fast enough.

Actually you can watch Protel doing it. First of all it follows all the
tracks and pads on the entire PCB with the correct spacing to form the
outline. Then it fills the area using 15mil tracks. The outline process
needs about 10 seconds, so the fill takes another 5 seconds to perform.

CU
- - C. Lechner
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gEDA-user: What's your way of syncing CPLD design and gschem symbols???

2007-03-08 Thread Christoph LECHNER

Hi!

How do you keep your Xilinx CPLD design in sync w/
your gschem symbol files?

I mean, after you have drawn all your schematics and
build up the essentials of your CPLD design (esp. the
pins must exist :)), when doing the PCB artwork shuffling
the CPLD pins can give a really improved PCB layout ...

But the problem for me was to keep the symbol in sync
w/ the Xilinx Fitter report, so to do the work auto-
matically I hacked a Perl script (~6kB) last year,
but before adding some required upgrades  improvements
to the script I just wanted to ask how you do the sync
job!

For those not familiar with the Xilinx report files
I added a example Xilinx pin-out report for a small
Xilinx device (sorry for the attachment!)
Files with this structure are converted to symbols.

BTW: How do split up large ICs in multiple (different)
symbols? For example: One symbol for power, clk and JTAG
and one symbol for the rest of the design.

- cl



Pin List


Pin Num
Pin Type
Assigned Signal


1
I/O
clko1


2
I/O
rst


3
I/O
rotenc_b


4
I/O
hid_irq


5
I/O/GCK1
clki1


6
I/O/GCK2
clki2


7
I/O/GCK3
pclk


8
I/O
PGND


9
I/O
PGND


10
GND
GND


11
I/O
q_in0


12
I/O
q_in1


13
I/O
PGND


14
I/O
tp5


15
TDI
TDI


16
TMS
TMS


17
TCK
TCK


18
I/O
tp4


19
I/O
tp3


20
I/O
tp2


21
VCCINT
VCC


22
I/O
tp6


23
GND
GND


24
I/O
rotenc_pb


25
I/O
rotenc_a


26
I/O
lcd_cp


27
I/O
tp7


28
I/O
pb_b


29
I/O
tp1


30
TDO
TDO


31
GND
GND


32
VCCIO
VCC


33
I/O
q_in2


34
I/O
tp0


35
I/O
clko2


36
I/O
pb_c


37
I/O
lcd_sd


38
I/O
l_q_in


39
I/O/GSR
sclk


40
I/O/GTS2
pb_a


41
VCCINT
VCC


42
I/O/GTS1
pb_d


43
I/O
queue_irq


44
I/O
q_in3











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gEDA-user: What's your way of syncing CPLD design and gschem symbols???

2007-03-08 Thread Christoph LECHNER

Hi!

How do you keep your Xilinx CPLD design in sync w/
your gschem symbol files?

I mean, after you have drawn all your schematics and
build up the essentials of your CPLD design (esp. the
pins must exist :)), when doing the PCB artwork shuffling
the CPLD pins can give a really improved PCB layout ...

But the problem for me was to keep the symbol in sync
w/ the Xilinx Fitter report, so to do the work auto-
matically I hacked a Perl script (~6kB) last year,
but before adding some required upgrades  improvements
to the script I just wanted to ask how you do the sync
job!

For those not familiar with the Xilinx report files
I added a example Xilinx pin-out report for a small
Xilinx device (sorry for the attachment!)
Files with this structure are converted to symbols.

BTW: How do split up large ICs in multiple (different)
symbols? For example: One symbol for power, clk and JTAG
and one symbol for the rest of the design. I would create
the symbols and give them the same refdes ... don't know
if this is the correct way to make it work!

- cl




Pin List


Pin Num
Pin Type
Assigned Signal


1
I/O
clko1


2
I/O
rst


3
I/O
rotenc_b


4
I/O
hid_irq


5
I/O/GCK1
clki1


6
I/O/GCK2
clki2


7
I/O/GCK3
pclk


8
I/O
PGND


9
I/O
PGND


10
GND
GND


11
I/O
q_in0


12
I/O
q_in1


13
I/O
PGND


14
I/O
tp5


15
TDI
TDI


16
TMS
TMS


17
TCK
TCK


18
I/O
tp4


19
I/O
tp3


20
I/O
tp2


21
VCCINT
VCC


22
I/O
tp6


23
GND
GND


24
I/O
rotenc_pb


25
I/O
rotenc_a


26
I/O
lcd_cp


27
I/O
tp7


28
I/O
pb_b


29
I/O
tp1


30
TDO
TDO


31
GND
GND


32
VCCIO
VCC


33
I/O
q_in2


34
I/O
tp0


35
I/O
clko2


36
I/O
pb_c


37
I/O
lcd_sd


38
I/O
l_q_in


39
I/O/GSR
sclk


40
I/O/GTS2
pb_a


41
VCCINT
VCC


42
I/O/GTS1
pb_d


43
I/O
queue_irq


44
I/O
q_in3











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Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

2007-03-08 Thread Christoph Lechner

Hi!

Sorry for posting the same message two times!
Please, ignore this one and answer only to the
second message.

- cl


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Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

2007-03-08 Thread Christoph Lechner

Andy Peters schrieb:


It might be easier to work backwards, from the schematic, and have it 
back-annotate into the .ucf (user constraint file), which is the file 
used by the Xilinx tools for pinouts (and timing specs, etc etc).  It 
gets even more complicated when schematic net names don't match the CPLD 
design pin names, or when you connect the same schematic net to two FPGA 
pins (like when doing external clock feedback).


This isn't really a problem for small CPLDs but it's a right royal PITA 
with large FPGAs.

Fortunately I only use XC9572XL CPLDs for most of
my designs :)

And as you already wrote there's no problem with the
net names, as they map 1:1 between the VHDL source
and the schematic symbol.

- cl


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Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

2007-03-08 Thread Christoph Lechner

Andy Peters schrieb:
It might be easier to work backwards, from the schematic, and have it 
back-annotate into the .ucf (user constraint file), which is the file 
used by the Xilinx tools for pinouts (and timing specs, etc etc). 

It's true that ripping off everything exept the pairing
Pin Names - Pin Numbers
from the gschem symbol is a snap compared to building/
updating a symbol from the Fitter report. But how would
you make sure that the user of gschem doesn't put an input
pin at an reserved location, i.e. a JTAG or PWR pin.
The timing issues following from forcing the Xilinx tool
to use a user-defined pin-out are non-trivial IMHO, at
least for CPLDs. So I guess it would be better regarding
timing issues to run Xilinx ISE (or another vendor's tool)
first and then go to gschem and create/update the symbol.

But nevertheless, I'm looking forward to the new FPGA
flow ...

The (at the moment) missing link between logic design
tools and gschem is a big show-stopper for the gEDA
suite, I guess.

- cl


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