Re: gEDA-user: why some skip KiCAD and gEDA
On Thu, Sep 08, 2011 at 10:27:52PM +0100, Peter Clifton wrote: On Thu, 2011-09-08 at 13:43 -0600, Mark Rages wrote: On Thu, Sep 8, 2011 at 12:38 PM, Colin D Bennett co...@gibibit.com wrote: On Thu, 08 Sep 2011 17:50:33 +0200 Stefan Salewski m...@ssalewski.de wrote: For me, I never loved the many tool changes, and I was never able to remember all the key combinations. er is edit rotate, ve is view extend. For the later I am not really sure -- have not used gschem for a year. Don't forget, while “ve” is View Extents, “ev” alters all invisible text and attributes making them visible! It is not like “en” which just toggles the display mode to show invisible text, but “ev” actually changes the entities. For my money, we could kill ev and its menu item completely. I don't think it serves any useful purpose, and has caused me many a headache. Full agreement here. One feature I would like to see in gschem is to have two grids: - the default grid when moving objects or anything - a finer grid automatically used when moving a single attribute I find myself very often switching to a finer grid when editing attributes to put them in the right place, especially in denser parts of the schematics where proximity hints at which component the attribute refers. And then I switch back to the default grid when I'm done with the attributes (otherwise I inevatibly end up with off-grid pins). It's the constant switching back and forth that annoys me. OrCad had this 20 years ago: it automatically used a 1/10 pin spacing grid when moving attributes. For the GUI I don't know whether you would have to put two grid settings (with limits) or keep a single grid and use a selectable fraction of the main grid (1/2, 1/5, 1/10). I really don't mind changing grids for the other case where I have to, which is when drawing symbols. You've really no choice in this case: user settable grid is better than no snap mode (which gschem allows to use as a fallback in any case). Personally, I have no problems with the two key shortcuts in gschem, now that cut/copy/paste/undo/redo use standard accelerators: there are far too many commands to map them to single keystrokes. Besides that if you use use special characters, they may be impossible to type with a single hand on some keyboard layouts, like | for thin lines in PCB, which is AltGr (ISO_Level3_Shift in X keysyms) 1 (the digit), the single AltGr key being at the right of the space bar (I have fairly large hands, and yet I can't type it with a single hand, so I have to move my right hand off the mouse). Staying with 2 Latin alphabetical characters (which are present on basically all keyboard layouts and do not require finger acrobacies) avoids these problems, and may even be better for some kinds of disabilities. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: why some skip KiCAD and gEDA
On Thu, Sep 08, 2011 at 10:32:26PM +0100, Peter Clifton wrote: On Thu, 2011-09-08 at 13:10 -0500, John Griessen wrote: gschem is not as key binding configurable as PCB as far as I can tell. Adding that would be a fine goal. It is actually - its just not immediately obvious. Look in your $PREFIX/share/gEDA/system-gschemrc file and find: (define file-keymap '((w . file-new-window) (n . file-new) (o . file-open) (s . file-save) (e . page-close) ; yes this is okay; reusing page-close (a . file-save-as) (l . file-save-all) (p . file-print) (r . page-revert) ; yes this is okay; resuing page-revert Whom are you suing again ? ;-) (i . file-image) (t . file-script) (c . file-close-window) (q . file-quit))) (Those go with the second letter to 'f', which activates the file menu). Finally, the global keymap: ; All keys in the global-keymap *must* be unique (define global-keymap '((Escape . cancel) (a . add-keymap) (b . add-box-hotkey) (c . edit-copy-hotkey) (d . edit-delete) (e . edit-keymap) (f . file-keymap) (h . help-keymap) (i . add-component) (l . add-line-hotkey) (m . edit-move-hotkey) (n . add-net-hotkey) (o . options-keymap) (bracketright . options-scale-up-snap-size) (bracketleft . options-scale-down-snap-size) (p . page-keymap) (r . view-redraw) (s . edit-select) (t . attributes-keymap) (u . edit-undo) (v . view-keymap) (w . view-zoom-box-hotkey) (x . view-pan-hotkey) (Left . view-pan-left) (Right . view-pan-right) (Up . view-pan-up) (Down . view-pan-down) (y . buffer-keymap) (z . view-zoom-in-hotkey) (period . repeat-last-command) (Shift colon . edit-invoke-macro) (comma . misc-misc) (equal . misc-misc2) (Shift plus . misc-misc3) (Delete . edit-delete) (Shift greater . page-next) ; Deprecated; preserved for backward compat (Page_Down . page-next) (Shift less . page-prev) ; Deprecated; preserved for backward compat Fortunately these were deperacted, they were useless on a Spanish keyboard: since less and greater are on the same key, less being the unshifted state and greater the shifted one. Bottom line: do not rely on non-Latin characters in the default accelerators, you'll always find at least one keyboard layout where they fail or are extremely awkward to use. Even numbers are hard to use (they need Shift on french keyboards, the non shifted top row being mostly special and accented characters). Believe me, I'm French, and I can't stand the French keyboard layout. (Page_Up . page-prev) (Alt q . file-quit) (Shift B . add-bus-hotkey) (Shift H . hierarchy-keymap) (Shift U . edit-undo) (Shift R . edit-redo) (Shift Z . view-zoom-out-hotkey) (Control x . clipboard-cut) (Control c . clipboard-copy) (Control v . clipboard-paste-hotkey) (Control z . edit-undo) (Control y . edit-redo) (Control a . edit-select-all) (Control Shift A . edit-deselect))) ; finally set the keymap point to the newly created datastructure (define current-keymap global-keymap) Notice there are plenty of single-key bindings there already, for example, the group at the bottom. Hope that helps, -- Peter Clifton pc...@cam.ac.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: accel keys (was: why some skip KiCAD and gEDA)
On Fri, Sep 09, 2011 at 01:58:14AM +0200, Kai-Martin Knaak wrote: DJ Delorie wrote: But gschem and pcb have completely different toolsets and common tasks. It would be difficult to make them the same outside of the usual common key mappings (cut, paste, undo). There are a few more that could potentially be matched: gschempcb * start drawing a net [n] start drawing a track [F2] * edit some text [ex] edit some text [n] * rotate by 90° [er]rotate by 90° [F9] + mouse click * find specific text [t shift-f]select by name (no accel, yet) * cut selected objects [del]cut selected objects [backspace] * draw a rectangle [b] draw a rectangle [F5] + mouse click * draw a circle [ai]draw a circle (no GUI tool) * edit attributes [ee] edit attributes (no accel, yet) * toggle rubberband [or]toggle rubberband (no accel, yet) * increase grid spacing []] increase grid spacing [ctrl-g] * decrease grid spacing [[] decrease grid spacing [ctrl-shift-g] Thanks for these two. I had not found them, probably because [ and ] are not really intuitive (at least to me) and are on the third level on my Spanish keyboards (the plain keys are dead_grave and +). Gabriel increasingly unhappy with moderation of geda-user Seconded. Can't the moderators at least whitelist usual contributors... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Sat, Aug 27, 2011 at 08:37:59PM -0600, John Doty wrote: On Aug 27, 2011, at 8:12 PM, Dan McMahill wrote: This problem goes beyond diodes and transistors. For example, the old 10H series of ECL parts came both in DIP packages as well as PLCC packages. Some of the parts though, would be in a 16 pin DIP or a 20 pin PLCC and so the pin numbers didn't agree between the two packages. Yep. I recently got bit by this with the LT1078 opamp (different pinouts in DIP8 and SO8). I've used the LT1013 (since 1993 or so) which has the same feature. Linear Technology originally (early 90s) claimed that this was because they had to rotate the die when fitting it into the SO8 package. I distincly remember having to create a special symbol under OrCAD to have the right pinout for this device. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [PATCH] Fix distance display in lesstif HID.
Hi,
in src/did/lesstif/main.c, the Distance function is called
with the parameters in the wrong order.
This small patches fixes the problem. I still think that
the format is wrong, or at least the rounding to integer
mm/mil taking only the grid into account, but I've not yet
decided on how to fix it. The worse is that often the display
is wrong because the decimal part is truncated (displaying
say -24 between two grid points on a 5mil grid).
Gabriel
diff --git a/src/hid/lesstif/main.c b/src/hid/lesstif/main.c
index 811ac26..be9a330 100644
--- a/src/hid/lesstif/main.c
+++ b/src/hid/lesstif/main.c
@@ -2321,7 +2321,7 @@ mark_delta_to_widget (BDimension dx, BDimension dy,
Widget w)
else
{
int angle = atan2 (dy, -dx) * 180 / M_PI;
- BDimension dist = Distance (0, dx, 0, dy);
+ BDimension dist = Distance (0, 0, dx, dy);
buf = pcb_g_strdup_printf (%m+%+.*mS, %+.*mS (%.*mS, %d\260), UUNIT,
prec, dx, prec, dy, prec, dist, angle);
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Re: gEDA-user: [PATCH] Fix distance display in lesstif HID.
On Mon, Aug 01, 2011 at 04:31:01PM -0700, Andrew Poelstra wrote: On Mon, Aug 01, 2011 at 04:51:51PM +0200, Gabriel Paubert wrote: Hi, in src/did/lesstif/main.c, the Distance function is called with the parameters in the wrong order. This small patches fixes the problem. I still think that the format is wrong, or at least the rounding to integer mm/mil taking only the grid into account, but I've not yet decided on how to fix it. The worse is that often the display is wrong because the decimal part is truncated (displaying say -24 between two grid points on a 5mil grid). Thanks, Gabriel. I have pushed your fix. In future, when I convert the lesstif HID to allow arbitrary user units, I will use the default precision for pcb-printf. This will be 0 for cmils, 2 for mils, 4 for mm, etc. Fine, than I'll stop worrying about it. Right now I sometimes have to set the grid to something like 2.5mil when I only needed 5 mil for the sole purpose of displaying the fractional part in the relative coordinates window. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power relay question
On Thu, Jul 28, 2011 at 07:26:25PM -0600, John Doty wrote: On Jul 28, 2011, at 7:03 PM, DJ Delorie wrote: Or 4000-series CMOS logic. Nice thing about 4000 series in this application is that it can operate on unregulated 12V. I thought of that, but a linear regulator just for the pic would be cheap, and you get debounce, multi-input state machines, and a watchdog for no extra cost... Simple state machines and debounce are easy with MSI, too, and you don't need a software development setup. Arguably easier to debug a simple MSI circuit than a program. Another way to implement it might be with a Silego GreenPak prgrammable mixed signal array: http://www.silego.com/index.php?page=greenpak It's cheap, and the programmin hardware + 50 chips is only $20 (+S/H) or so until the end of the month (so hurry up). For Europe, the S/H charge is a bit steep ($50), but even then it's less than €100 for a programmer, 150 chips and shipping plus handling. The development software is only available for Windows and MacOS, sadly no Linux version :-( I'm afraid that a 10F200 is a bit short on I/O (4 pins for 2 sensors and 2 motors is really at the limit). Personnally I started with 12F508 (IIRC) and then switched to 12F609 because of the capability of brown-out reset: otherwise switching power off and on sometimes failed to perform a full reinitialization of another chip (a synthesizer from the Analog's ADF4xxx series), when the power supply dropped below the minimal voltage to preserve internal configuration latches. You may not have this problem, but this kind of very intermittent failure is incredibly hard to diagnose: it only happened if the power was switched off for the right amount of time, and not on all boards... Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Anybody ever had a board assembled (pick and place)?
On Wed, Jul 27, 2011 at 08:13:42PM -0400, Ethan Swint wrote: On 07/27/2011 05:57 PM, Stephen Ecob wrote: On Thu, Jul 28, 2011 at 5:35 AM, yamazakir2yamazak...@gmail.com wrote: I sometimes get boards done at 4pcb, I didn't know they do assembly. How much to they charge? And how big of a reel do you have to send them? And you just cut tape the amount of parts you need to assemble the amount of boards you want to manufacture? A length of tape with no reel can be put onto a spare reel quite easily, there's usually no charge. The tape does need a leader of around 300mm (varies) that has no components. If your tape has no leader then one option is to junk the components on the leader length - not very expensive if you're talking about 60 millicent resistors but a problem for expensive components. One house I've worked with is Advanced Assembly, which is just down the street from Advanced Circuits. (They'll pick your boards up from 4PCB's will-call.) IIRC, it was ~$100 for the first moderate board (150 or so SMT components), add ~$30 if you do SMT on both sides, and $0.50 per thru-hole device. Additional boards run cheaper, as usual, and they will do a quick-turn on the first two or three boards and send them to you to verify before populating the rest of the order. The quick-turn boards are billed at the same rate as the rest of the order, so you don't pay a premium on them. A Assembly will purchase components on your behalf, but of course you pay a bit extra for that. Actually, for the last board I sent to manufacturing here in Spain, the assembly house bought most components and what they charge me is close to the cheapest price I could get, and I don't have the hassle of ordering and shipping them the components. The only ones they did not procure are the microwave capacitors (Dielectric Labs C06BLxxx), the Piconics conical chokes and the germanium tunnel diode chips from M-Pulse microwave. Actually I have to install myself the last two since the assembly house does not do bonding. For the microwave capacitor, they accept to install it despite the fact that I only got them in bulk and not on tape. The components include a low noise op-amp (LT1028A) and a temperature sensor (AD590JF), which make the bulk of the cost. In addition there are fairly common components like BAT54S Schottky diode, a trimmer (Vishay T63YB), a transistor (BCX52), a choke (EPCOS SIMID B82422H) and a few capacitors (4 603 and 2 1206) and eight resistors (all 0603). The board is small (1x3/4), on 20mil thick RO4003C substate with Ni/Au finish, and costs €30.70 assembled (plus the cost of the 3 components mentioned above and the work to install the last 2). There is a weird mixture of through hole, SMD (both sides), and bonded components. The steep part are the NRE charges (€775), but I shall hopefully amortize them over more and larger series in the future (the first batch is for 50 boards). This said, the custom made milled aluminum mechanical enclosure in which these board ar installed costs way more than the board itself, once finished. This assembly house is close to Sevilla, Spain. That's almost 300km away from my work place, but I've not found anything closer. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Warp pointer nonesense
On Mon, Jul 25, 2011 at 12:49:00PM -0400, DJ Delorie wrote: Speaking of pointer warping: why is the pointer not warped when swapping sides (with TAB for example) ? At least it's not done with the lesstif HID. That's intentional. I strongly disagree with that choice. I'm aware that max XWarpPointer claims that There is seldom any reason for calling this function., but this is the exception that confirms the rule IMHO. No, changing the way you look at the board is not a valid reason to rip control of the mouse away from the user. Then there is an inconsistency: the mouse pointer does not move on the screen but the crosshair does move to stay at the point where it was before pressing the TAB key. Then the crosshair jumps back to the pointer position as soon as you move the mouse. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Warp pointer nonesense
On Mon, Jul 25, 2011 at 01:15:17AM +0200, Kai-Martin Knaak wrote: Peter Clifton wrote on the other list where mere users are not allowed to post: If no-one has any objection, I will remove the code which warps the mouse pointer when selecting nets in the netlist window. Speaking of pointer warping: why is the pointer not warped when swapping sides (with TAB for example) ? At least it's not done with the lesstif HID. I don'y use the GTK one enough to bother, but it does not seem to warp the pointer either from a quick glance at the code. I'm aware that max XWarpPointer claims that There is seldom any reason for calling this function., but this is the exception that confirms the rule IMHO. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb grid improvements... status of patch?
On Wed, Jul 13, 2011 at 08:30:43PM -0700, Andrew Poelstra wrote: These too will be changed as we move away from a strict mm/mil configuration. I'm not sure what to do about them. Right now I have a giant table of default/max/min for all these units, which totals 12 values per unit. Times ten currently-supported units, this is 120 values! Storing defaults for all of them would require 40 lines... including things like cm, km, cmil, that most users would never use. Then what happens when we add support for new units? For user-defined units? Great. As an astronomer, I really need to be able to define my PCB in astronomical units and parsecs :-) Regards and thanks for the work you're doing, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb grid improvements... status of patch?
On Wed, Jul 13, 2011 at 01:56:23PM -0400, DJ Delorie wrote: Great. As an astronomer, I really need to be able to define my PCB in astronomical units and parsecs :-) A while back, I had jokingly suggested supporting attoparsecs... And why we are at it, get rid of the 1/2 oz and similar copper weights, specify it in solar masses per square parsec instead :-) Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [Off-Topic] pcb grid improvements... status of patch?
On Wed, Jul 13, 2011 at 11:27:48AM -0700, Colin D Bennett wrote: On Wed, 13 Jul 2011 11:05:56 -0700 Colin D Bennett co...@gibibit.com wrote: On Wed, 13 Jul 2011 19:55:02 +0200 Gabriel Paubert paub...@iram.es wrote: Great. As an astronomer, I really need to be able to define my PCB in astronomical units and parsecs :-) You'll have to wait for 64-bit internal unit storage... (when metric internals [nm units] is implemented) Correcting myself: 2**64 nm ≈ 0.123 AU 2**128 nm ≈ (2.3×10**18) AU I guess 64-bit numbers won't do it for you! The dynamic range of values you need for some modelling code in astronomy is, well, astronomical. 25 years ago, I had to move some scientific code from an IBM 370 mainframe to a VAX. The dynamic range of single and double precision on the nefarious IBM hexadecimal floating point was roughly 10^+/-76 (16^+/-64). The VAX could only reach 10^+/-38 (2^+/-128) in both single and double precision at the time (later they added the so called G-float format with an 11 bit exponent like IEEE). It turned out that I had to be very careful and scale several variables because otherwise I triggered overflows and underflows on the VAX. I must admit that I've never run into problems with IEEE double precision (10^+/-308). Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Manufacturers of PCB on ceramic substrates?
Hi Bob, according to the archives, you were looking in August 2006 for manufacturers of PCB on ceramic substate. Did you find anything? I'm looking for something similar now, for a circuit containing a few Hittite HMC975 switches (it's not cryogenic, however). Another problem I have is that, on an alumina substrate, with a dielectric constant close to 10 and 5mil thick, I get a line width of about 0.13mm (5mil), which is reasonably well matched to the dimensions of the bonding pads of the chip, but I am unable to find capacitors narrower than about 0.25mm (10mil) with low losses in the 4-20GHz range. Anybody knows of a capacitor manufacturer that could provide this kind of device? Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Manufacturers of PCB on ceramic substrates?
On Tue, Jun 21, 2011 at 05:10:48PM +, Mark Stanley wrote: From: Gabriel Paubert [...] I am unable to find capacitors narrower than about 0.25mm (10mil) with low losses in the 4-20GHz range. Anybody knows of a capacitor manufacturer that could provide this kind of device? We use Dialectric Labs (http://www.dilabs.com) single layer caps. Their min buy is $500 but they have designer kits, engineering kits, and samples on their website. Thanks, I've been using Dielectric Labs RF capacitors for over 15 years, but the smallest standard size I've found in their catalog is 10mil, which is about twice the width of 50 Ohms transmission line on the substrate I want to use. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug in PCB's Gerber generation?
On Thu, Jun 16, 2011 at 08:44:13PM +0200, Gabriel Paubert wrote: Hi Andrew, I just pulled PCB from git head and I have trouble with arcs in Gerber output. I strongly suspect the latest commit: layers which do not have arcs appear fine in gerbv, but automatic zooming layers which contain arcs zoom out and give coordinates in the range of several meters (with the screen staying lack). Also my outline has a single arc in one corner and this is precisely this segment which is missing. I can not prepare a test case right now but will tomorrow (it's almost 9 pm here), if you've not beat me to fix it before. For some reason Andrew replied priavtely, but I want to thank him for having fixed the bug in git head, and having added a testcase for arcs. Now it is the drill file (I did not come around to checking it yesterday, sorry) which is incorrect: too targe blobs and in the wrong place :-( Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug in PCB's Gerber generation?
On Fri, Jun 17, 2011 at 10:49:34AM +0200, Gabriel Paubert wrote: On Thu, Jun 16, 2011 at 08:44:13PM +0200, Gabriel Paubert wrote: Hi Andrew, I just pulled PCB from git head and I have trouble with arcs in Gerber output. I strongly suspect the latest commit: layers which do not have arcs appear fine in gerbv, but automatic zooming layers which contain arcs zoom out and give coordinates in the range of several meters (with the screen staying lack). Also my outline has a single arc in one corner and this is precisely this segment which is missing. I can not prepare a test case right now but will tomorrow (it's almost 9 pm here), if you've not beat me to fix it before. For some reason Andrew replied priavtely, but I want to thank him for having fixed the bug in git head, and having added a testcase for arcs. Now it is the drill file (I did not come around to checking it yesterday, sorry) which is incorrect: too targe blobs and in the wrong place :-( Correction: only the coordinates are wrong, the sizes look correct. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug in PCB's Gerber generation?
On Fri, Jun 17, 2011 at 11:41:22AM +0200, Gabriel Paubert wrote: On Fri, Jun 17, 2011 at 10:49:34AM +0200, Gabriel Paubert wrote: On Thu, Jun 16, 2011 at 08:44:13PM +0200, Gabriel Paubert wrote: Hi Andrew, I just pulled PCB from git head and I have trouble with arcs in Gerber output. I strongly suspect the latest commit: layers which do not have arcs appear fine in gerbv, but automatic zooming layers which contain arcs zoom out and give coordinates in the range of several meters (with the screen staying lack). Also my outline has a single arc in one corner and this is precisely this segment which is missing. I can not prepare a test case right now but will tomorrow (it's almost 9 pm here), if you've not beat me to fix it before. For some reason Andrew replied priavtely, but I want to thank him for having fixed the bug in git head, and having added a testcase for arcs. Now it is the drill file (I did not come around to checking it yesterday, sorry) which is incorrect: too targe blobs and in the wrong place :-( Correction: only the coordinates are wrong, the sizes look correct. And it turned out to be relatively easy once you understand the %m conversion: mixing imperial and metric can easily veer you off course, you don't need to be close to Mars. diff --git a/src/hid/gerber/gerber.c b/src/hid/gerber/gerber.c index 5e0b7b6..f949d42 100644 --- a/src/hid/gerber/gerber.c +++ b/src/hid/gerber/gerber.c @@ -646,7 +646,7 @@ gerber_set_layer (const char *name, int group, int empty) Aperture *ap = findAperture (curr_aptr_list, pending_drills[i].diam, ROUND); fprintf (f, T%02d\r\n, ap-dCode); } - pcb_fprintf (f, X%06.0mmY%06.0mm\r\n, + pcb_fprintf (f, X%06.0mlY%06.0ml\r\n, gerberDrX (PCB, pending_drills[i].x), gerberDrY (PCB, pending_drills[i].y)); } Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bug in PCB's Gerber generation?
On Fri, Jun 17, 2011 at 01:35:11PM +0200, Kovacs Levente wrote: On Fri, 17 Jun 2011 12:42:09 +0200 Gabriel Paubert paub...@iram.es wrote: - pcb_fprintf (f, X%06.0mmY%06.0mm\r\n, + pcb_fprintf (f, X%06.0mlY%06.0ml\r\n, Is this commited? No, I don't have write privileges, nor do I want them since I don't have time to work on significant improvements. I hope that Andrew will pick this up and commit it when he checks his mail. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Bug in PCB's Gerber generation?
Hi Andrew, I just pulled PCB from git head and I have trouble with arcs in Gerber output. I strongly suspect the latest commit: layers which do not have arcs appear fine in gerbv, but automatic zooming layers which contain arcs zoom out and give coordinates in the range of several meters (with the screen staying lack). Also my outline has a single arc in one corner and this is precisely this segment which is missing. I can not prepare a test case right now but will tomorrow (it's almost 9 pm here), if you've not beat me to fix it before. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
On Tue, May 31, 2011 at 05:09:25AM +0200, Kai-Martin Knaak wrote: Richard Rasker wrote: OK, I'll start by reading up on the light vs. heavy symbol discussions. Do I understand correctly that heavy symbols basically have certain nets with predefined names (e.g. VCC, GND) implicitly included, whereas light symbols offer the pins to connect those nets oneself? Not quite. There seems to be a consensus, that hidden nets are bad style. Here I respectfully disagree, unless or until you can make a single schematic pin correspond to a (potentially long) list of physical pin. To my knowledge this is not the case right now. Of course the pin numbers should not be shown on the schematics: they would use up too much schematics real estate and are not interesting anyway (even relatively simple and cheap FPGA devices like XC3S700A has 88 power pins in the 256 pins BGA package, that's ~35% of the pins): you can't check anything in a BGA package and even on package that can be probed, it is extremely hard to find, say, a bad solder joint since all pins of the same power rail are internally connected together. At least, I haven't seen anyone advocate net attributes in the default lib. That's very different. More often than not I have to override the net=VCC attribute in the existing library for simple logic devices, so the fact that there is a default can lead to errors (it would be better to have an attribute hidden_pins=list_of_pins that produces an error at netlist generation time if some of these pins have no net=attribute). We no more leave in the world where the logic power supply is +5v, period . In some cases it is even the net=GND:whatever that I have to override (microwave GaAs switches often work with a negative power supply, and GND is the positive power rail). Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcjc2 tessellation
On Sun, May 29, 2011 at 02:30:08PM +0100, Peter Clifton wrote: On Sun, 2011-05-29 at 11:37 +1000, Russell Shaw wrote: Hi, In _borast_bentley_ottmann_tessellate_bo_edges() which is from _cairo_bentley_ottmann_tessellate_bo_edges(), i see you deleted case CAIRO_BO_EVENT_TYPE_INTERSECTION: What effect does this have on the types of polygons that can be rasterized? Think i know now. Polygons can't have edges that cross other edges. You got it.. PCB doesn't allow self intersecting polygons, so I removed support for rendering them in an attempt to manage the complexity (and hopefully improve speed of) the tessellator. So, what happens if one directly tinkers with the PCB file with an editor or script and creates a self interscting polygon by mistake? It's not so far fetched, I sometimes edit coordinates in the file to match mechanical design. I can make a mistake or, if it is a script (which also happens), it can have a bug. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: IPC standard SMT footprints (0603, 0402 vs. RESC0603N etc.)
On Wed, May 25, 2011 at 07:11:49AM -0700, Colin D Bennett wrote: On Wed, 25 May 2011 06:41:26 -0700 Colin D Bennett co...@gibibit.com wrote: (1) Why is RESC0603L/N/M much smaller than '0603'? (2) Why is there no similarly named set of RESC0805L/N/M for 0805 size? (3) Why does RESC1608M nearly match the '0603' footprint? Is there an imperial/metric naming confusion happening? I thought 0603 was a standard name for this size. I think I've answered some of this for myself... from Wikipedia's “Surface-mount technology” article: 01005 (0402 metric) : 0.016 × 0.008 (0.4 mm × 0.2 mm) 0201 (0603 metric) : 0.024 × 0.012 (0.6 mm × 0.3 mm) 0402 (1005 metric) : 0.04 × 0.02 (1.0 mm × 0.5 mm) 0603 (1608 metric) : 0.063 × 0.031 (1.6 mm × 0.8 mm) 0805 (2013 metric) : 0.08 × 0.05 (2.0 mm × 1.25 mm) 1206 (3216 metric) : 0.126 × 0.063 (3.2 mm × 1.6 mm) So the source of the confusion over footprints is that '0603' is a valid name for both a metric and an imperial size.. both different? Whoever decided to name the packages that was must have been on crack. Indeed. I found a set of recommended footprints that distinguishes resistors from capacitors: http://www.ibselectronics.com/pdf/pa/walsin/smt_notes.pdf I have used it quite successfully, including for long edge capacitors (0612 or 1632 metric) and 4 resistors in a single package (4x0603 or 4x1608 metric). I also took into account the recommendations on page 10 when ordering the stencil, shrinking a bit the solder paste apertures generated by PCB. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: IPC standard SMT footprints (0603, 0402 vs. RESC0603N etc.)
On Wed, May 25, 2011 at 11:10:13AM -0700, Colin D Bennett wrote: On Wed, 25 May 2011 16:56:46 +0200 Gabriel Paubert paub...@iram.es wrote: On Wed, May 25, 2011 at 07:11:49AM -0700, Colin D Bennett wrote: On Wed, 25 May 2011 06:41:26 -0700 Colin D Bennett co...@gibibit.com wrote: (1) Why is RESC0603L/N/M much smaller than '0603'? (2) Why is there no similarly named set of RESC0805L/N/M for 0805 size? (3) Why does RESC1608M nearly match the '0603' footprint? Is there an imperial/metric naming confusion happening? I thought 0603 was a standard name for this size. I think I've answered some of this for myself... from Wikipedia's “Surface-mount technology” article: 01005 (0402 metric) : 0.016 × 0.008 (0.4 mm × 0.2 mm) 0201 (0603 metric) : 0.024 × 0.012 (0.6 mm × 0.3 mm) 0402 (1005 metric) : 0.04 × 0.02 (1.0 mm × 0.5 mm) 0603 (1608 metric) : 0.063 × 0.031 (1.6 mm × 0.8 mm) 0805 (2013 metric) : 0.08 × 0.05 (2.0 mm × 1.25 mm) 1206 (3216 metric) : 0.126 × 0.063 (3.2 mm × 1.6 mm) So the source of the confusion over footprints is that '0603' is a valid name for both a metric and an imperial size.. both different? Whoever decided to name the packages that was must have been on crack. Indeed. I found a set of recommended footprints that distinguishes resistors from capacitors: http://www.ibselectronics.com/pdf/pa/walsin/smt_notes.pdf I have used it quite successfully, including for long edge capacitors (0612 or 1632 metric) and 4 resistors in a single package (4x0603 or 4x1608 metric). I also took into account the recommendations on page 10 when ordering the stencil, shrinking a bit the solder paste apertures generated by PCB. Thanks for the note. It is a curious coincidence that I was actually reading this very PDF at the moment I read your message! I had just found it on Google. Have you found the Walsin-recommended footprints for SMD chip resistors and capacitors to be useful, and an improvement over other footprints such as the pcb default 0603, RESC1608N, etc.? Useful, yes. Actually I found this document a long time ago and have been using exclusively these footprints for my designs so I cannot compare with the others. They work very well for my circuits. I had to interpolate them in a project in which I used high frequency chokes from the Murata LQW04A series in a weird 03015 (metric 0804) package. The other interesting part of the document was, as I mentioned, the specification for the stencil apertures. My fairly uniformed understanding is that the IPC standard specifies the one set of footprints for use both resistors and capacitors. (e.g., 0603-least, 0603-nominal, 0603-most.) But is differentiation between device types useful? At least the package height differs (MLCC is square along the X axis, while chip resistors are flatter, having a height H much less than the Y dimension), but I don't know how this would affect placement and soldering. Resistors have metallization basically on the underside, while capacitors terminals wrap around the device. They really need the extra length for properly wetting the large and high end contact. My guess is that you would not see a measurable difference when installing a resistor on a capacitor footprint, but the other way around would be extremely sensitive to small placement error before reflow (with risk of tombstoning). This guess is based on a limited experience. This said, most capacitors look to have a square profile, but resonance frequencies observed on microstrip line change between mounting the layers parallel or perpendicular to the ground plane. The problem is that, for most capacitors, it is very hard to determine the orientation of the layers. By the way, for chokes like Murata LQW18 series, I use the resistor footprint. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: IPC standard SMT footprints (0603, 0402 vs. RESC0603N etc.)
On Wed, May 25, 2011 at 02:40:58PM -0700, Colin D Bennett wrote: On Wed, 25 May 2011 23:03:06 +0200 Gabriel Paubert paub...@iram.es wrote: This said, most capacitors look to have a square profile, but resonance frequencies observed on microstrip line change between mounting the layers parallel or perpendicular to the ground plane. The problem is that, for most capacitors, it is very hard to determine the orientation of the layers. That's interesting. Are you saying that for high-frequency, critical signals, the orientation of the chip capacitor affects its performance in the circuit? Is the SMD tape/reel packed in such a way that the capacitors are optimally oriented, ready for pick-and-place onto a PCB? Yes, at least for some high frequency capacitors; look at the following, the last 2 graphs are really amazing: http://dilabs.com/pdfs/Pg%2010-11%20MLC%20Application%20Notes.pdf I have never seen such a large difference myself, but I have seen a measureable difference in some cases. I don't know about capacitors from other manufacturers. When I use capacitors from Dielectric Labs, that's in small quantity, so I get them in bulk in plastic bags and I have to orient them myself. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB crash on rotating polygons in buffer
On Thu, May 19, 2011 at 06:19:05PM +0100, Peter Clifton wrote: On Thu, 2011-05-19 at 14:26 +0200, Gabriel Paubert wrote: In the meantime, I have a 100% reproducible bug with the following backtrace: Program received signal SIGSEGV, Segmentation fault. r_delete_entry (rtree=0x0, box=0x7d8c60) at rtree.c:1101 1101r = __r_delete (rtree-root, box); Now fixed with this commit: commit c12cc6f769b5ccc603a75361fae3adc930934506 Author: Peter Clifton pc...@cam.ac.uk Date: Thu May 19 18:13:43 2011 +0100 buffer.c: Update polygon r-tree when adding a polygon to the buffer. This resulted in a crash when rotating a buffer containing a polygon, as the polygon r-tree associated with the buffer was NULL despite the polygon count being non-zero. Thanks a lot. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB crash on rotating polygons in buffer
On Tue, May 17, 2011 at 11:48:47AM +0100, Peter Clifton wrote:
On Tue, 2011-05-17 at 10:11 +0200, Gabriel Paubert wrote:
I'm sure other languages use even more modifiers, but could
someone apply the following patch:
Committed, thanks! I made the equivalent change to the GTK HID whilst I
was at it, and wrote a commit message for you.
Thank you for committing. Maybe my memory is failing, but I don't
remember seeing the message when using the gtk gui (which I sometimes
do). Anyway it can't hurt gtk users, and it was really annoying to
see the message log window pop up when I typed the AltGr key for the
first time after starting PCB.
I look forward to reviewing any more patches you have for gEDA and PCB.
I might prepare a less trivial patch over the week-end since
the weather forecast is not good here for working on a swimming pool.
But it first needs careful testing.
In the meantime, I have a 100% reproducible bug with the following
backtrace:
Program received signal SIGSEGV, Segmentation fault.
r_delete_entry (rtree=0x0, box=0x7d8c60) at rtree.c:1101
1101 r = __r_delete (rtree-root, box);
(gdb) info stack
#0 r_delete_entry (rtree=0x0, box=0x7d8c60) at rtree.c:1101
#1 0x00433040 in RotateBuffer (Buffer=0x752960, Number=value
optimized out) at buffer.c:1216
#2 0x0041fd1a in ActionPasteBuffer (argc=2, argv=0xa5e970, x=value
optimized out, y=value optimized out) at action.c:6076
#3 0x0049158f in hid_actionv (name=value optimized out, argc=2,
argv=0xa5e970) at hid/common/actions.c:246
#4 0x00491978 in hid_parse_actionstring (rstr=value optimized out,
require_parens=value optimized out) at hid/common/actions.c:330
#5 0x004b67cb in lesstif_key_event (e=0x7fffdff0) at
hid/lesstif/menu.c:1211
#6 0x004af635 in work_area_input (w=0xa0dee0, v=value optimized out,
e=0x7fffdff0, ctd=value optimized out) at hid/lesstif/main.c:1345
#7 0x773e7d9a in XtDispatchEventToWidget () from /usr/lib/libXt.so.6
#8 0x773e8577 in ?? () from /usr/lib/libXt.so.6
#9 0x773e7561 in XtDispatchEvent () from /usr/lib/libXt.so.6
#10 0x773e76f3 in XtAppMainLoop () from /usr/lib/libXt.so.6
#11 0x004b085a in lesstif_do_export (options=value optimized out) at
hid/lesstif/main.c:1931
#12 0x0045c9ff in main (argc=2, argv=0x7fffe398) at main.c:1097
which happens when rotating a buffer which contains a single polygon (or a
combination
of tracks and polygons).
Simply take the attached PCB file, select the polygon, cut it (Ctrl-X)
and rotate the buffer (Shift-F7). Instant-crash (TM) :-)
Gabriel
# release: pcb 1.99z
# To read pcb files, the pcb version (or the git source date) must be = the
file version
FileVersion[20070407]
PCB[tdmtnr 12 12]
Grid[2500.00 0 0 1]
Cursor[62500 37500 -2.899683]
PolyArea[2.00]
Thermal[0.50]
DRC[699 400 800 800 1500 800]
Flags(nameonpcb,swapstartdir,clearnew,snappin)
Groups(1,c:2,s:3:4:5:6:7:8)
Styles[Signal,2000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600]
Symbol(' ' 18)
(
)
Symbol('!' 12)
(
SymbolLine(0 45 0 50 8)
SymbolLine(0 10 0 35 8)
)
Symbol('' 12)
(
SymbolLine(0 10 0 20 8)
SymbolLine(10 10 10 20 8)
)
Symbol('#' 12)
(
SymbolLine(0 35 20 35 8)
SymbolLine(0 25 20 25 8)
SymbolLine(15 20 15 40 8)
SymbolLine(5 20 5 40 8)
)
Symbol('$' 12)
(
SymbolLine(15 15 20 20 8)
SymbolLine(5 15 15 15 8)
SymbolLine(0 20 5 15 8)
SymbolLine(0 20 0 25 8)
SymbolLine(0 25 5 30 8)
SymbolLine(5 30 15 30 8)
SymbolLine(15 30 20 35 8)
SymbolLine(20 35 20 40 8)
SymbolLine(15 45 20 40 8)
SymbolLine(5 45 15 45 8)
SymbolLine(0 40 5 45 8)
SymbolLine(10 10 10 50 8)
)
Symbol('%' 12)
(
SymbolLine(0 15 0 20 8)
SymbolLine(0 15 5 10 8)
SymbolLine(5 10 10 10 8)
SymbolLine(10 10 15 15 8)
SymbolLine(15 15 15 20 8)
SymbolLine(10 25 15 20 8)
SymbolLine(5 25 10 25 8)
SymbolLine(0 20 5 25 8)
SymbolLine(0 50 40 10 8)
SymbolLine(35 50 40 45 8)
SymbolLine(40 40 40 45 8)
SymbolLine(35 35 40 40 8)
SymbolLine(30 35 35 35 8)
SymbolLine(25 40 30 35 8)
SymbolLine(25 40 25 45 8)
SymbolLine(25 45 30 50 8)
SymbolLine(30 50 35 50 8)
)
Symbol('' 12)
(
SymbolLine(0 45 5 50 8)
SymbolLine(0 15 0 25 8)
SymbolLine(0 15 5 10 8)
SymbolLine(0 35 15 20 8)
SymbolLine(5 50 10 50 8)
SymbolLine(10 50 20 40 8)
SymbolLine(0 25 25 50 8)
SymbolLine(5 10 10 10 8)
SymbolLine(10 10 15 15 8)
SymbolLine(15 15 15 20 8)
SymbolLine(0 35 0 45 8)
)
Symbol(''' 12)
(
SymbolLine(0 20 10 10 8)
)
Symbol('(' 12)
(
SymbolLine(0 45 5 50 8)
SymbolLine(0 15 5 10 8
Re: gEDA-user: PCB crash on rotating polygons in buffer
On Thu, May 19, 2011 at 02:23:10PM +0200, Gabriel Paubert wrote: On Tue, May 17, 2011 at 11:48:47AM +0100, Peter Clifton wrote: On Tue, 2011-05-17 at 10:11 +0200, Gabriel Paubert wrote: I'm sure other languages use even more modifiers, but could someone apply the following patch: Committed, thanks! I made the equivalent change to the GTK HID whilst I was at it, and wrote a commit message for you. Thank you for committing. Maybe my memory is failing, but I don't remember seeing the message when using the gtk gui (which I sometimes do). Anyway it can't hurt gtk users, and it was really annoying to see the message log window pop up when I typed the AltGr key for the first time after starting PCB. I look forward to reviewing any more patches you have for gEDA and PCB. I might prepare a less trivial patch over the week-end since the weather forecast is not good here for working on a swimming pool. But it first needs careful testing. In the meantime, I have a 100% reproducible bug with the following backtrace: Program received signal SIGSEGV, Segmentation fault. r_delete_entry (rtree=0x0, box=0x7d8c60) at rtree.c:1101 1101r = __r_delete (rtree-root, box); (gdb) info stack #0 r_delete_entry (rtree=0x0, box=0x7d8c60) at rtree.c:1101 #1 0x00433040 in RotateBuffer (Buffer=0x752960, Number=value optimized out) at buffer.c:1216 #2 0x0041fd1a in ActionPasteBuffer (argc=2, argv=0xa5e970, x=value optimized out, y=value optimized out) at action.c:6076 #3 0x0049158f in hid_actionv (name=value optimized out, argc=2, argv=0xa5e970) at hid/common/actions.c:246 #4 0x00491978 in hid_parse_actionstring (rstr=value optimized out, require_parens=value optimized out) at hid/common/actions.c:330 #5 0x004b67cb in lesstif_key_event (e=0x7fffdff0) at hid/lesstif/menu.c:1211 #6 0x004af635 in work_area_input (w=0xa0dee0, v=value optimized out, e=0x7fffdff0, ctd=value optimized out) at hid/lesstif/main.c:1345 #7 0x773e7d9a in XtDispatchEventToWidget () from /usr/lib/libXt.so.6 #8 0x773e8577 in ?? () from /usr/lib/libXt.so.6 #9 0x773e7561 in XtDispatchEvent () from /usr/lib/libXt.so.6 #10 0x773e76f3 in XtAppMainLoop () from /usr/lib/libXt.so.6 #11 0x004b085a in lesstif_do_export (options=value optimized out) at hid/lesstif/main.c:1931 #12 0x0045c9ff in main (argc=2, argv=0x7fffe398) at main.c:1097 which happens when rotating a buffer which contains a single polygon (or a combination of tracks and polygons). Simply take the attached PCB file, select the polygon, cut it (Ctrl-X) and rotate the buffer (Shift-F7). Instant-crash (TM) :-) I forgot to mention that this is a regression, it does not happen on another machine on which I have a binary compiled on April 26th. Oh, and I see that I have left the netlist in the PCB file. But I suspect that thos os irrelevant. Bonus point to the person who guesses what this circuit is supposed to do ;-) Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pressing = key causes PCB to freeze for a few minutes
On Tue, May 17, 2011 at 03:04:18PM -0400, Vanessa Ezekowitz wrote:
On Mon, 16 May 2011 23:29:46 +0200
Kai-Martin Knaak k...@lilalaser.de wrote:
Peter Clifton wrote:
the two '=' or remove the whole part 'a={= Key=}', what will
remove this key-binding for this menu-item.
Yes, I can recommend removing this key binding.
I do in my local builds for the same reason, plus the fact that
sometimes the optimiser makes mistakes and causes shorts on my boards!
For me, the Auto-Optimize step (in particular the Unjaggy and De-bumpify
optimizations) actually removes some hand-placed vias - particularly those
which I've placed up against an SMT pad as part of hand-routing the majority
of the board. I only noticed this today, but I can't be sure when that
behavior started.
As for keys, I would like to see a default hotkey added to turn Orthogonal
Moves on/off (I toggle this setting quite frequently while cleaning up after
the autorouter).
Ditto. What about + which is a little cross after all?
I'm aware it's Shift-= on american keyboards, which is currently
defined as auto-optimize. But I am of the strong opinion that
operations which may perform a large number of changes to the
board should not have keyboard accelerators, so that you can
not trigger them my mistake.
I'm aware that they can be undone, but even then...
Regards,
Gabriel
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Re: gEDA-user: Pressing = key causes PCB to freeze for a few minutes
On Wed, May 18, 2011 at 03:09:10PM -0400, Vanessa Ezekowitz wrote:
On Wed, 18 May 2011 13:54:15 +0200
Gabriel Paubert paub...@iram.es wrote:
On Tue, May 17, 2011 at 03:04:18PM -0400, Vanessa Ezekowitz wrote:
On Mon, 16 May 2011 23:29:46 +0200
Kai-Martin Knaak k...@lilalaser.de wrote:
Peter Clifton wrote:
the two '=' or remove the whole part 'a={= Key=}', what will
remove this key-binding for this menu-item.
Yes, I can recommend removing this key binding.
I do in my local builds for the same reason, plus the fact that
sometimes the optimiser makes mistakes and causes shorts on my boards!
For me, the Auto-Optimize step (in particular the Unjaggy and De-bumpify
optimizations) actually removes some hand-placed vias - particularly
those which I've placed up against an SMT pad as part of hand-routing the
majority of the board. I only noticed this today, but I can't be sure
when that behavior started.
As for keys, I would like to see a default hotkey added to turn
Orthogonal Moves on/off (I toggle this setting quite frequently while
cleaning up after the autorouter).
Ditto. What about + which is a little cross after all?
I'm aware it's Shift-= on american keyboards, which is currently
defined as auto-optimize.
Fittingly unshifted = would also work, since the two lines could imply
parallel, as in move the object parallel to the path the mouse takes.
I don't really care. Well, on a Spanish keyboard, + does not need
any modifier but = is actually Shift-0.
As I've already said, the only things that worries me is potentially
pervasive and time-consuming operations triggered by single keystrokes.
Especially since I'm sometimes forced to use different keyboards,
American of French (and occasionally other ones, but it's unlikely
that I use PCB on these machines) so I may easily hit the wrong key.
Regards,
Gabriel
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Re: gEDA-user: Pressing = key causes PCB to freeze for a few minutes
On Mon, May 16, 2011 at 11:29:46PM +0200, Kai-Martin Knaak wrote:
Peter Clifton wrote:
the two '=' or remove the whole part 'a={= Key=}', what will
remove this key-binding for this menu-item.
Yes, I can recommend removing this key binding.
I do in my local builds for the same reason, plus the fact that
sometimes the optimiser makes mistakes and causes shorts on my boards!
Another candidate is the short cut to Auto-Optimize. This is supposed
to be Shift+=. However, on German keyboards you have to type [shift-0]
to get the = character. What would I type to get Shift+= ?
Same on Spanish keyboards.
By the way, my pcb log window is always littered with lots
of 'Key not tied to an action message because the | key
(short cut for thin draw) is a third level key on Spanish keyboards.
I'm sure other languages use even more modifiers, but could
someone apply the following patch:
diff --git a/src/hid/lesstif/menu.c b/src/hid/lesstif/menu.c
index 297768b..8de2952 100644
--- a/src/hid/lesstif/menu.c
+++ b/src/hid/lesstif/menu.c
@@ -1140,6 +1140,7 @@ lesstif_key_event (XKeyEvent * e)
case XK_Super_R:
case XK_Hyper_L:
case XK_Hyper_R:
+case XK_ISO_Level3_Shift:
return 1;
}
Gabriel
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Re: gEDA-user: pcb: Track routing strategies and tips
On Wed, May 11, 2011 at 02:26:43AM +0200, Kai-Martin Knaak wrote: Colin D Bennett wrote: Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. Put extra care into component placement. IMHO, placement is more critical to the design than routing. Indeed. I've been told y a professional (her job is to lay out PCB with expensive commercial tools) that she has never seen a good or even acceptable automatic placer. However she claims that automatic routers are now reasonably good, far from perfect, but the help. I have very similar problems in FPGAs: I often can only reach the performance I want when helping by fixing the location of the large blocks (mostly RAM and DSP). One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. Yep. This is a good default. It avoids road blocks by tracks on both sides. It's called Manhattan routing. It's a good starting point, but you should at least perform some via reduction run at some later stage. Do you ever use the pcb autorouter Rarely. Basically only for fun... or do you always route by hand? Mostly. Always in practice, but that's because my circuits are simple but almost invariably involve microstrip and/or coplanar line for the most important signals (and mechanical design of the enclosure is as critical as the PCB layout). I'm in the process of designing a much more complex board with FPGA, DDS and no real high frequency signal (highest frequency being the 400MHz DDS clock). But the layout is going to be done by the person mentioned above (using CadStar at the moment). BTW, there is no gschem-CadStar netlister, or did I miss it? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL - now with background image rendering support!
On Tue, May 03, 2011 at 10:37:01PM +0100, Peter Clifton wrote: On Tue, 2011-05-03 at 19:46 +0200, Kai-Martin Knaak wrote: Peter Clifton wrote: I'm very close to being able to push the basic 2D portions of PCB+GL into git HEAD. I feel like a supporter at the course of a marathon race: Go, Peter. Go! Ok, spurred on by that encouragement, I've tidied up and pushed the first couple of PCB+GL patches to git HEAD. git HEAD PCB will now render using OpenGL by default with a GTK HID build. If that doesn't work for you, build with ./configure --disable-gl Great. Anyway the current gtk drawing code would have failed with gtk3, but it seems that even the GL code will run into trouble: - GdkDrawable and GdkPixmap have been eliminated, you have to use Cairo whether you like it or not - expose-event has disappeared, it is now called draw, and it has differen parameters - I hope that gtkglext will still work, but what do I know? Ok, I'm an archaic lesstif user. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL - now with background image rendering support!
On Wed, May 04, 2011 at 12:14:16PM +0100, Peter Clifton wrote: On Wed, 2011-05-04 at 09:21 +0200, Gabriel Paubert wrote: Great. Anyway the current gtk drawing code would have failed with gtk3, but it seems that even the GL code will run into trouble: - GdkDrawable and GdkPixmap have been eliminated, you have to use Cairo whether you like it or not - expose-event has disappeared, it is now called draw, and it has differen parameters - I hope that gtkglext will still work, but what do I know? Unknown.. but I expect it will be ported eventually. GTK 3.0 will be a problem for both the gEDA and PCB code bases, but given our adoption rate of new versions of things.. I don't expect it will be a pressing concern for some years yet. We'll have to have caught up by the time distros stop shipping support for GTK2.0 though. I have no doubt that distros will ship gtk2.0 for a long time, at least Debian only dropped gtk1.2 with Lenny, a few months ago. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Thu, Apr 14, 2011 at 10:14:13PM +0200, Krzysztof Kościuszkiewicz wrote:
On Wed, Apr 13, 2011 at 10:41:23PM +0100, Peter Clifton wrote:
pin[pinnumber=1] {pinnumber=2;}
pin[pinnumber=2] {pinnumber=1;}
I've long seen this to be the most sane way of managing back-annotation
into a hierarchy. I would go as far to say refdes should be
back-annotated as such:
#X1 #X1 #R1 {refdes = R99;}
#X1 #X2 #R1 {refdes = R123;}
#X1 #X3 #R1 {refdes = R3;}
That looks neat powerful - and starting to closely resemble XPath/XSLT/CSS
transformations.
But I think we're actually getting farther from something that:
* is backwards compatible with the name=value attribute definition/syntx
* can be simply used to add hierarchy/depth to attribute assignments
It would be best to keep these two things aligned - syntax used for
general transformations should be a natural extension of the one used
for attribute definitions.
And a small comment regarding hierarchy separators - I would personally
choose anything that does not require shift-keystroke to type the most
commonly used separator - so '/' and '.' seem to be the two natural
candidates.
That's not a very compelling criterion; on my spanish keyboard:
- the following characters need shift:
!·$%/()=?¿*_:;
(the slash is actually shift+7, which is messy to type when
with the left hand when you have the right hand on the mouse)
- the following ones need the AltGr key (called ISO_LEVEL3 in X):
\|@#~¬{[]}œ€¶ŧ←↓→øþæßðđŋħĸ«»¢“”µ
(and ł, but I don't think that you want to use this Polish
specific character as a separator)
Side note, I have an old (2001) black Apple keyboard, which has
two AltGr keys. Most Spanish keyboards only have one, on the
right side; it is _impossible_ to type with one hand some
combinations using AltGr with these, most notably \|@#, which
are on the number row starting from the extreme left above
the Tab key until digit 3 (well I can type the #, but I have
relatively large hands).
- and finally the following ones need both shift and AltGr:
£™±°Ω®Ŧ¥↑§©‘’×÷
A french or german keyboard will be different (I'm french,
but I can't stand the layout of french keyboards).
Regards,
Gabriel
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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Fri, Apr 15, 2011 at 02:16:23PM +0200, Stephan Boettcher wrote:
Gabriel Paubert paub...@iram.es writes:
A french or german keyboard will be different (I'm french,
but I can't stand the layout of french keyboards).
I'm using us keyboards exclusively, in Germany. I type a lot more
[]{}\| than äöüß.
I believed that the ß has been suppressed in a recent reform of the
german language. But to be fair also, the umlauts are much
less frequent in german than accents, diaeresis and special characters
in spanish and french (ñçœ), æ is elso used in french but extremely rare.
I really have to type every day in three languages (french, english,
and spanish) and it's really painful on an US keyboard.
Besides that, it seems to be admitted in german to replace
ä, ö, and ü by the letter followed by e.
There is no such mechanism in spanish, and suppressing the tilde
on top of the n in the classical Prospero Año Nuevo (Happy New
Year) message could be embarrassing ;-)
Gabriel
P.S.: I remember perfectly that when the first IBM PC arrived in
France in the early 80s, there were no \ on the keyboard. You had
to type a contrived combination (Ctrl+Alt+I can't remember what)
of keys to type the path separator, and it was at the command line
under DOS, without tab completion or any kind of help. Also using
TeX on a mainframe, the \{} characters were actually çéè, I won't
comment on the legibility of said TeX source...
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Re: gEDA-user: OFF: capacitors for RF power amplifier
On Wed, Apr 13, 2011 at 09:31:24AM +0100, Andy Fierman wrote: If you are going to model the PA - particularly to look at resonance effects - then you should include reasonably accurate models for the inductors and capacitors which include their major parasitic components. The Murata Chip S-Parameter Impedance Library is a handy tool for looking at their ceramic capacitor and inductor behaviour. http://www.murata.com/products/design_support/mcsil/index.html or there's an online version: http://ds.murata.com/software/simsurfing/en-us/index.html Andy. signality.co.uk On 12 April 2011 23:57, Wojciech Kazubski w...@o2.pl wrote: I'm currently designing a power amplifier for the HF (3-30MHz) radio band. I am selecting capacitors for the low pass harmonic filter bank at the output. My question is what kind of capacitors should I use? I apply not more then 100V of say 30MHz maximum. My best bet is to use X7R capacitors with as much DC voltage rating as I can get. I don't know if there's any connection between the DC and AC losses. Thanks, Levente The biggest problem can be the current handling capacity. Very few capacitor makers specify this. Usually if a capacitor is rated for 100V this means 100V DC wthout any current. Only special purpose capacitors for RF power applications have HF current ratings, see Anerican Technical Ceramics for example: http://www.atceramics.com Another manufacturer is Dielectric Labs: http://www.dilabs.com but they are not cheap, especially the porcelain ones. However, they have very good temperature characteristics and high to very high voltage ratings. Dilabs basically only manufactures capacitors for high frequency applications. For RF do not use X5R/X7R (good only for supply bypassing), use NP0/C0G or similar low loss ones. Agreed, well X5R/X7R can be used for loop filters in PLL and servo applications, when the bandwidth is not too critical, as long as you meet the stability criteria (but I use 25 or even 50V rated capacitors when the voltage on the capacitor never exceeds 3.3V). The problem is that you can't use anything else when you have size constraints and need capacitors in the 0.1 to 10 microfarad range: very low loop bandwidths for either crystal (VCXO) oscillators and even much lower for thermal stabilization loops. On the other hand, class Y and Z dielectrics should not even be allowed; a look at temperature and voltage dependence graphs should suffice to convince any circuit designer. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Panelisation and outline layers
On Wed, Apr 13, 2011 at 10:38:05AM -0400, DJ Delorie wrote: Another option is to look at gerbv and see if it has merging capabilities. I know PCB is careful to use a consistent set of apertures across gerbers; Yes, and thank you very much for that feature... I've used it to merge layers (mostly manually, it's not even difficult), obvisouly checking the result with gerbv before sending to the fab. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: default pcb stackup change?
On Mon, Apr 11, 2011 at 03:20:11AM -0400, DJ Delorie wrote: I basically agree, but why stop here and not add a Z coordinate to each layer? You deleted the answer to that: Note that this would be an interim change until we get around to either a new-board-wizard or new-means-load-template. Well, I did not really understand that paragraph. Anyeay, fine with me, although I don't really see the interest of an interim step. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: transition of pcb internal units to metric (SI, mm)
On Mon, Feb 07, 2011 at 01:11:09PM -0800, Colin D Bennett wrote: On Mon, 7 Feb 2011 15:09:08 -0500 DJ Delorie d...@delorie.com wrote: this is NOT what the current software does True. there are NO plans to change any of it. False. I will add only this: anyone with questions about the metric units/nanometer/64-bit change should read every single post in the following thread before proceeding so everyone does not have to repeat themselves: First message subject: Re: pcb crooked traces, Date: 2010-10-07 23:00:50 GMT. http://thread.gmane.org/gmane.comp.cad.geda.user/32808 The topic of metric units internally has come up on the list at least three or four times now in various forms, so I think we should have a brief FAQ item for this that summarizes (1) the specific issues it addresses (45-degree line stubs; precision of metric footprints and layouts), (2) the options proposed along with reason for accepting or rejecting each option (e.g., why integers are preferred to floating point, why the file format does not need to incompatibly change), and Spaeking of this, with floating point values, it is also extremely easy to lose precision on formatted file I/O. For double, you need something like 17 digits and the procedure conversion to/from ASCII is also much slower than for integers (not a problem with modern machiness since PCB files are relatively small, but it is very visible when you read text files with 10 of millions of floating point values). Of course the other possibility is to use the hexadecimal floating point format (%a on output), but in this case you lose the advantage of human readability (and at this point why use a text format?). Speaking of the coordinates and dimensions, I would not be opposed in writing them to files as mm.fraction with up to 6 digits in the fraction (suppressing trailing zeroes). I think it would make the file more readable for humans, not really harder to process with scripts (I sometimes use awk on my pcb files). Files might even be a bit shorter, but that's not the motivation. This said, I see that pcb uses bison or flex or some of these parser generators which I've never been able to understand, and I don't know at all what complications it may add to the grammar. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Fri, Oct 08, 2010 at 05:07:45PM -0400, DJ Delorie wrote: So... if pcb were to be limited to a 2 meter by 2 meter board, would it actually be a painful limitation to anyone? MAXINT nm is 84.5 inches (just over 7 feet). Anyone who needs more than 84x84 inch boards can re-compile PCB with 64-bit units. I seem to remember that I saw a rigid PCB manufacturer which alowed up to 2 meters or a bit more, but I can't find it any more. Another data point is that Rogers will ship some aminates from their antenna series with sizes up to 50x110 or almost 1.3mx2.8m. This is only on special order, so some (limited) demand must exist. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Fri, Oct 08, 2010 at 11:14:04PM +0100, Peter Clifton wrote: On Fri, 2010-10-08 at 15:42 -0400, DJ Delorie wrote: Any idea of the loss of performance given that virtually all PCs these days are actually 64 bit machines? My dual-core 3.2GHz machine supports 64-bit, but I installed a 32-bit OS for compatibility. So, 64-bit math is a performance hit for me. I'm not certain that is true.. or are you compiling with CFLAGS for a non 64-bit CPU? I thought the 32/64 bit OS issue was mostly to do with address pointers, rather than aritmetic. I was fairly sure one could execute 64bit native CPU arithmetic instructions under a 32-bit OS, just that the executable would not be portable to machines which didn't support those instructions. Not on the 64 bit version of x86 for integer computations. The most significant half of the 64 bit integer registers are not accessible at all in 32 bit mode. On other architectures, I think it works (for PPC I'm sure, Sparc and MIPS I believe so), but we are in an x86 monoculture these days. ARM does not (yet) have a 64 bit version AFAIK. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Sat, Oct 09, 2010 at 10:15:15AM +0200, Armin Faltl wrote: DJ Delorie wrote: Please forgive my ignorance, but can't one just define a 64bit integer on a 32bit system? Yes, but there's a loss of performance if you do that. if one really is anal about it, use 'long long int' which is an 80-bit integer on Intel That's so wrong that I don't know where to start. long double is 80 bit floating point and going away (it was introduced with the aberration known as the stack-based x87 floating point unit)- machines and they are handled by the floatingpoint unit, despite they are real integers (and, xor, shift, rot, mod, ...) No. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Thu, Oct 07, 2010 at 04:23:34PM -0700, Andrew Poelstra wrote: On Fri, Oct 08, 2010 at 01:00:50AM +0200, kai-martin knaak wrote: I prefer 1 mm, sometimes 0.5 mm :-) (Are there any plans to make inside pcb metric?) I would vote for this. +1 Really, the inch is by definition 2540µm, not the other way around since over 50 years ago. Besides that, the vast majority of the packages I use are defined in metric dimensions (1mm BGA, 0.65mm TSSOP, 0.5mm QFN). There are some still defined in inch but they have too few pins (=8) to matter. (But no, not that I've heard.) Neither. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Thu, Oct 07, 2010 at 04:48:37PM -0700, Andrew Poelstra wrote: On Thu, Oct 07, 2010 at 05:37:48PM -0600, John Doty wrote: On Oct 7, 2010, at 5:00 PM, kai-martin knaak wrote: (Are there any plans to make inside pcb metric?) A couple of years ago I suggested making the fundamental units nanometers, since that would make decimal fractions of inches exactly representable as integers down to 0.01 mil. 0.01 mil = 254 nm by definition. Even on a 32-bit system, this would allow 4-meter boards, unless I'm going crazy. So if anyone has the tenacity to actually switch the units, this seems like a better idea than millimeters. Besides that 64 bit have become commonplace now. You really need signed integers in some places, and there boards which are larger than 2 meters (for some antennas AFAIK). I think that it should have done when switching from mil to finer units. 0.01 mil is 254nm, and using 2nm (exactly 127 times finer) as an unit does not sound right. On the other hand, 1mil was 25.4µm so 100nm would have worked. Unless you wanted to design chips with PCB (you don't want, use the right tool for the job). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
On Mon, Oct 04, 2010 at 12:09:22AM +0200, Armin Faltl wrote: Rick Collins wrote: At 08:24 AM 10/3/2010, you wrote: Rick Collins wrote: I really have no idea how things work in the gEDA/PCB world. With FreePCB the library has a default orientation for parts and there is a centroid vector to allow the pin 1 orientation to be set compatibly with the Gerber files. If you use someone else's design you need to verify that their library parts were done correctly or you need to use the same footprints which are a part of the layout and so are available. There is no reason to screw up something as simple as this. How the Gerber file looks depends on the footprint definition. Once one knows *exactly* a) how the transformations work b) that all libraries/generators(/custom made footprints) conform to a sensible standard checking is as superfluous as with screw diameters and pitches and before that point I don't believe it's simple enough. I really don't know what you are talking about. The footprint will show up on your layout in some orientation. That is the orientation it will have on the board in the Gerber files. How will the transformations affect that? What you see is what you get. Yes, what I see is what I get. And to see it, I have to read the source code of the CAD system, unless it's stated somewhere more accessible - like in a standard ;-) E.g., where is the centroid of a 3-leged part? Is it: a) the center of the bounding box of the pads b) the center of the bounding box of the pad centers c) the center of gravity of the pad centers (each weight 1) d) the center of gravity of the pad areas e) (0, 0) in the footprint definition file (or a designated vector inthere) Take as an example a SOT89 transistor like NXP's BCX52-16 (I've just used one in a recent design) and look at the recommended footprints: Package page: http://www.nxp.com/#/page/content=[f=/packages/SOT89.xml] Package drawing: http://www.nxp.com/documents/outline_drawing/sot089_po.pdf Reflow footprint: http://www.nxp.com/documents/reflow_soldering/sot089_fr.pdf I'm not sure what point a pick and place machine would like to use as centroid, probably the crossing of the two axes in the last drawing. This apparently rules out options b, c, and d, but seems to work with option a. I'm guessing here, but pick and place machine have to orientate the part very fast, so it is important that they pick the component from a principal axis of inertia. It is not always easy to determine where the axis lies when the component is asymmetric, which is frequent with power components. For another example, look a DPAK or D2PAK components (SOT404, SOT428, etc). I'm not even sure that they option a) would work, but it might be a good default, provided you can override it. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Diode pin numbers reversed?
On Sun, Jun 13, 2010 at 10:57:50PM -0700, Matthew Lai wrote: Am I having a brain fart or does the stock diode-1 symbol have opposite pin numbers as the ALF300 footprint? EDA vendors never get it right, so how could gEDA? Really I edit my footprints and diode symbols to use A and K, netlisters complain, of course, at least for single diodes, since it wants the pin number to end with a digit (why?, it is also painful for transistors). However since now I use more often dual (or more) packages, I don't have this problem: the netlister is happy with A1, K1, A2 and K2 (as if it were a BGA!) Now the right solution to avoid having a proliferation of symnbols might be to have a way to specify attributes that map from pin name to pin numbers on every instance. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Looking for DSP
On Wed, Mar 24, 2010 at 10:30:00AM -0400, Ethan Swint wrote: OT, but we're running out of leads at my company to locate ~25 TI DSPs - TMS320F280x (substitute 1,2,6,8,9 for X). Anybody here have a couple that they're willing to sell, or know of some other parties who may? For x=1, Newark has right now 53 in stock: http://www.newark.com/texas-instruments/tms320f2801pza-60/digital-signal-controller-dsc-ic/dp/03M1089 Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Tue, Mar 09, 2010 at 11:33:11PM +, Peter Clifton wrote: On Tue, 2010-03-09 at 18:27 -0500, Dan McMahill wrote: pstoedit converts postscript to various formats. So I suppose you could try pcb export to postscript and then pstoedit to produce dxf. That said, there are always issues with file conversions and I suspect you're much better off letting pcb directly produce dxf. But it may just work. NB: The code being talked about is DXF - PCB outline... not PCB-DXF. It seems that we now have _three_ people who have independently written such a tool. I guess this suggests people are wishing to design boards which fit in a given mechanical envelope, as exported from a mech.-cad package. In my case, it is just the opposite, I build the enclosure around the constraints of the circuit (high frequency). I wanted to attach a photo, but it's 1.7MB, which is a bit heavy for the mailing list, I believe. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Tue, Mar 09, 2010 at 07:56:42PM -0500, DJ Delorie wrote: One of my long-term projects is to add layer types to layers, and allow for sub-circuits (i.e. elements). Then we'd have a true paste layer, and you could define elements as complexly as you need. But it's been on the list for a long time, and hasn't happened yet :-( Indeed, however how hard would it be to add a nopaste flag to a pad to indicate that you don't want paste for this specific pad? An example would be for very large pads, where you would want to define a partially filled pad (a grid) later on the paste layer. And while we are at it adding a paste shrink parameter for middle sized pads, where you typically want a paste area somewhat smaller than the pad itself. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Wed, Mar 10, 2010 at 10:13:16AM -0500, DJ Delorie wrote: Indeed, however how hard would it be to add a nopaste flag to a pad to indicate that you don't want paste for this specific pad? Only as hard as running the ChangePaste() action. I wasn't aware of its existence. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
On Mon, Mar 08, 2010 at 09:18:56AM -0800, Anthony Shanks wrote: Is there a way to make a square polygon with round edges in pcb? Not to my knowledge, I have done it by cutting the corners at 45 degrees and adding a non polycon-clearing zero length track at the corner (in one case I also used an track drawn with the arc tool, but I don't remember why, perhaps because there was a component pad/pin in the area). One more unrelated question. Is there a way to place vias with a default soldermask clearance less than 0? Yes, I almost exclusively use tented vias. Enable the soldermask layer and press Shift-K repeatedly until the via is fully covered. Or edit the pcb source file, manually or with a script. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
On Mon, Mar 08, 2010 at 09:47:55AM -0800, Anthony Shanks wrote: Sorry that was a mis-statement. Is there anyway to place vias that have a soldermask clearance MORE than 0? What I typically do is to se all parameters of a via to be what I want, and then type a on top of the via to perform copies. This way I have very few types of vias. However, I have never used the autorouter (not of much use for microwave signals). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
On Tue, Mar 02, 2010 at 09:21:25PM -0800, Donald Tillman wrote: On Mar 2, 2010, at 2:35 AM, Peter TB Brett wrote: The usual approach is to buy SMT packages containing 2 or 4 transistors on a single piece of silicon (i.e. literally back-to-back on the wafer). They're invariably well-matched enough for all but the most ultra- precise applications, in my experience. Which dual/quad transistors are these? Who makes them? For example Diodes/Zetex, navigate a bit the site and you'll find at: http://www.diodes.com/products/catalog/list.php?parent-id=28 that they are: Built with adjacent die from a single wafer: DC Current Gain, hFE, VCE(sat), VBE(sat) are matched to a 2% maximum tolerance. Besides being at the same temperature. Unfortunately Analog's SSM2210 is obsolete. But even random dual transistor pairs (I've used BC857BS dual PNP) have very good matching on average. It's not guaranteed and some may stand out as being much worse than average, but often temperature tracking (I'm repeating myself) dominates the variations between individual transistors in actual circuits. (And back-to-back? Are you sure? That doesn't sound right. That would have to involve separate processes for each side, and so the transistors wouldn't be matched.) No, they are side by side. Most dual transistors I've seen have the transistors on separate dies. Huh? We must live on different planets. The ones I've seen are diffused as neighbours on the same wafer. And so there's no matching and no offset spec; it's just like picking up 2 or 4 individual transistors. Some have specs, some have not. But they are diffused together in close vicinity, and that's the important point that guarantees similarity and temperature tracking. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
On Tue, Mar 02, 2010 at 02:01:51AM -0500, DJ Delorie wrote: Do they even make SOT-23 sockets? For matching, can you just press them onto a pcb carrier? Something that plugs into a breadboard, and gives you three big copper pads to contact? Assuming holding them down with your finger or even just letting gravity do the work, it might be sufficient. From my experience, gravity is insufficient. The contact quality is too poor if you don't have anything to press the device against the pads. I was testing at ~1GHz, but it should not affect that much, except that you need some plastic stick insted of a finger (too much disturbance, probably stray capacitance). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
On Tue, Mar 02, 2010 at 10:35:22AM +, Peter TB Brett wrote: On Mon, 1 Mar 2010 22:50:29 -0800, Donald Tillman d...@till.com wrote: This particular project uses some analog IC design styles implemented with hand-matched discrete transistors; diff amps, current mirrors and so forth. So I'd need an efficient way to hand-match surface mount transistors. With TO-92's I can just slap them into a rig and collect them into batches. Surface mount? I dunno. Do they even make SOT-23 sockets? The usual approach is to buy SMT packages containing 2 or 4 transistors on a single piece of silicon (i.e. literally back-to-back on the wafer). They're invariably well-matched enough for all but the most ultra-precise applications, in my experience. Indded. Another important point is that you won't end up with devices operating at different temperatures which is crucial for differential circuits (Vbe of a bipolar transistor drops at about 1.5 to 2mV per degree, even cheap op-amps have offset drifts in the few µV/° range, thanks to the input transistors being close on the same substrate). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I get the router to go where I want it to?
On Tue, Feb 16, 2010 at 10:50:11PM +0100, Maciej Pijanka wrote: On Tue, 16 Feb 2010, Jim Lynch wrote: I have a board I'm developing (maybe) that is a backplane. It has 9 edge connectors mounted on it and when I went to autoroute it Oh Lord! I've never seen such a mess! Traces all over, a million or so vias, etc. You'd think it would be a simple set of parallel lines, but no. So I ripped it up and started autorouting them one at a time. The first one went well, then the second row didn't. I'm guessing that I'm trying to violate some sort of clearance rule but I don't know which one or how to fix it. I may even have the pins too large. Take a look at the image Looks like pin to track clearance causes some of your problems, you may enable auto enforce drc and try to route track manually between pins and see if it fit at all, if not then change clearance lets say to 8mil, and try again. Usually its doable to place one track between two adjacent 0.1 spaced pins, i was told that one put two tracks between them, but i haven't seen that myself. I was told that one PCB manufacturer (in Denmark at the time, it was 1985 or 1986) was able to put up to seven tracks between DIL pads at 0.1 spacing. But I never saw it myself. A bit later (1988?), when multilayer was still a very expensive proposition and frequencies were not what they were today, I got a board with a 680x0 processor (can't remember whether 12 or 16MHz) and something like 1MB of UV EPROM and 2MB of SRAM on which I saw up to four, very narrow, tracks between two pins at the standard 0.1 spacing. Of course these were with relatively smooth transition of 74LS TTL and a few PAL, 70-80 ns memory cycles and on a single Eurocard (100x160mm), so lines were never very long compared to the rise and fall time. Crosstalk, what is crosstalk? However, to come back to your problem, it really depends on the pad and hole size that you need for your connector. Many connectors really need a much larger hole than a standard DIL package. Best regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Latex
On Fri, Feb 12, 2010 at 09:09:52PM +0100, Stefan Salewski wrote:
On Mon, 2010-02-08 at 11:12 +0100, Gabriel Paubert wrote:
The main use of this macro is to be able to control the pagestyle of a
figure
which occupies a whole page. By placing:
\floatcontrol{\thispagestyle{empty}}
between the \begin{figure} and \end{figure}, header/footer/page number is
eliminated from the page on which the figure (schematics in this case)
appears.
I think
/thispagestyle{empty}
should do the same.
No, \thispagestyle{empty} does not work as expected inside floats.
I had to encapsulate it in a token list associated with the (full
page) figure to issue the commands for the page on which the figure
would be placed.
Try it if you don't believe me. But a look at the definition of
\thispagestyle shows that it uses \global and \gdef, which means
that it will be associated with the next page to be produced by
the output routine, while whole page floats, or page containing
only floats will always come after.
Gabriel
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Re: gEDA-user: OT: Latex
On Sat, Feb 06, 2010 at 02:15:48PM -0500, Dave McGuire wrote:
On Feb 6, 2010, at 2:10 PM, gene glick wrote:
I use OpenOffice for quick dirty stuff, but LaTeX (with PDF
output) for anything that has to look good. Lyx is pretty nice but
those types of front-ends usually just get in the way.
First off, thanks for the input from all.
So you write in a text editor, add in your own codes? OK.
I typically use emacs, yes. Admittedly I don't write very long
documents...anything I write that's more than 20-30 pages is usually
postprocessed with a C compiler, not TeX. ;)
Ditto.
This is new to me since I've used MS Word for ever, and Open Office
to a lesser extent in the past 2 years. I dread using Open Office for
reports :( It's a huge struggle every time to get stuff to look nice.
All the rhetoric about TeX sounds good. So now I will see. Lyx seems
ok to me so far. The option to edit directly is always there - I
think.
Anyway, time to fire up the Chevelle SS396, pop the clutch, burn some
rubber, and haul butt up the learning curve :)
There you go. :) TeX is extremely powerful, but there's a big
learning curve involved. It sacrifices time and ease of use for
absolute control and unbelievably beautiful typesetter-quality output.
And stability over releases. I have documents that I wrote in TeX 25
years ago and the layout does not change (well Latex has evolved a bit
from \documentstyle to \documentclass and so on), but on average
the backwards compatibility is outstanding.
There is one thing for which I don't use Latex, these are tables, for
some reason I always found using TeX's raw mechanism (\halign) much
more straightforward.
By the way, for my needs of including schematics in a report, I wrote
a macro something like 20 years ago that provides one feature I sorely
needed. I called it floatcontrol.sty and have attached it.
The main use of this macro is to be able to control the pagestyle of a figure
which occupies a whole page. By placing:
\floatcontrol{\thispagestyle{empty}}
between the \begin{figure} and \end{figure}, header/footer/page number is
eliminated from the page on which the figure (schematics in this case)
appears. I've not tested if with recent Latex, but it works perfectly with
Latex 2.09. The original part of this macro is that it uses TeX's token
list registers, which I have not seen used very often, if ever.
Gabriel
% Hacking to modify the external pagestyle inside figure or table environment
% Note that the definitions of the \newtoks...@x, must be at least as large
% as the list of potential float boxes \...@x, as there is a one to one
% relationship. (\...@a is associated to \...@a, and so on)
% This list MUST correspond to the list of the latex float boxes,
% This set of macro assumes that the name of the boxes is of the form
% \bx@'c' where c is one character of category 11. These macro also fail
% if escapechar is not `\, but it is very likely to be true of LaTeX, too.
\newtoks...@void
\...@void={}
\newtoks...@a
\newtoks...@b
\newtoks...@c
\newtoks...@d
\newtoks...@e
\newtoks...@f
\newtoks...@g
\newtoks...@h
\newtoks...@i
\newtoks...@j
\newtoks...@k
\newtoks...@l
\newtoks...@m
\newtoks...@n
\newtoks...@o
\newtoks...@p
\newtoks...@q
\newtoks...@r
\def\...@tcontrol#1{\global\@currtoks{#1}}
\let\floatcontr...@gobble
\d...@xfloat#1[#2]{\ifhmode \...@bsphack\@floatpenalty -...@mii\else
\...@floatpenalty-\@miii\fi\d...@captype{#1}\ifinner
\...@parmoderr\@floatpenalty\z@
\el...@next\@currb...@freelist{\@tempcnta\csname ft...@#1\endcsname
\multip...@tempcnta\@xxxii\advan...@tempcnta\sixt@@n
\...@tfor \...@tempa :=#2\do
{\...@tempa h\advan...@tempcnta \...@ne\fi
\...@tempa t\advan...@tempcnta \...@\fi
\...@tempa b\advan...@tempcnta 4\relax\fi
\...@tempa p\advan...@tempcnta 8\relax\fi
}\global\cou...@currbox\@tempcnta
\expandafte...@metoks\@currbox
\glob...@currtoks\tk@void\let\floatcontrol\...@tcontrol
}...@fltovf\fi
\global\setb...@currbox\vbox\bgroup
%\boxmaxdepth\z@ % commented out 15 Dec 87
\hsize\columnwidth \...@parboxrestore}
\de...@metoks#1{\expandafter\@n...@metoks\string#1}
\expandafter\def\expandaft...@n@metoks\string...@#1{
\ed...@currtoks{\csname t...@#1\endcsname}}
\d...@comflelt#1{\setbox\@tempboxa
\vbox{\unvb...@tempboxa\box #1\vskip\floatsep}
\...@metoks#1\the\@currtoks}
\d...@comdblflelt#1{\setbox\@tempboxa
\vbox{\unvb...@tempboxa\box #1\vskip\dblfloatsep}
\...@metoks#1\the\@currtoks}
\d...@wtryfc #1{\global\setb...@outputbox\vbox{\unvbox\@outputbox
\vsk...@fpsep\box #1...@metoks#1\the\@currtoks}
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Re: gEDA-user: OT: Search for good SMD and IC prober
On Fri, Feb 05, 2010 at 09:06:34PM +0900, Torsten Wagner wrote: Dear geda users, I know it is off topic but I guess it is somehow related to PCB and many of you face the same problem or found already a solution. I am looking for a good set of micro probes to address single pins of ICs or other SMD components on a PCB. I saw some kit which looks very promising but a bit pricey [1] however, Down to 0.2mm (8mil pitch)? That's half the smallest pitch I've seen. Can such a pitch be soldered, even with paste printing and reflow? I'm still unsure about which kind of systems exist and what might be considered as good and what is actually not worse the money. Actually, I am looking for something to contact single legs of SMD-packed ICs for debugging and testing purpose. I tried a very cheap clamps [2], however, they are not really good for my purpose and the clamps are weak and inaccurate. Most probably o.k. for the price but I am looking for something more reliable and precise. It also depends on what you want to measure, only a voltage or do you want to look at the signal with a scope, up to which frequency? If it's for debugging, you probably want the connection to be reliable, and in this case nothing beats soldering a wire (the clips of my LeCroy scope work down to 0.5mm pitch, but they are fragile and they easilsy snap off when moving something around). However, at high frequencies, even a fairly short wire can cause significant distortion. For testing/verification after production, when you only need the contact for a short time, you can find very thin tungsten probes that give good contact (either for multimeters or for scopes). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Silver Epoxy: was Parts Manager Working Document
On Wed, Jan 20, 2010 at 05:42:26PM -0500, Mark Stanley wrote: On Monday 18 January 2010 22:16:00 Gabriel Paubert wrote: On Mon, Jan 18, 2010 at 09:00:35PM -0500, Mark Stanley wrote: I'll get you the information tomorrow when I get back to work. For long term storage we keep it packed with dry ice (CO2) in the freezer and store the in- service tube in the refrigerator. We've had in-service tubes last up to six months. That's a single component, right? They typically need -20 or -40°C for conservation from what I've seen. Yes. I'm using H20E in a single syringe. It's packed in a small cooler and surrounded with dry ice then covered over with balled-up newspaper and then the lid is taped shut. It has already lasted several years in the freezer. Ok, so it's H20E (as I said it looks like the industry's workhorse). Just had an offer from another distributer in Spain, and it's €380 for an ounce (non premixed). In theory, non premixed should last longer, although room temperature conservation is recommended. I can't understand why it would not conserve better at a lower temperature: there is a potential crystallisation problem but it can be solved by heating the individual components to 50°C for a few hours before mixing. The problem is that room temperature can be very high in summer in the south of Spain and the air conditioning may be cut-off, especially during the week-end. Apparently, the worst scenario is repeated temperature cycles, and I'd rather avoid it. Well, I think I'm going to buy some H20E and see how it works out. It can't be worse than CW2400... You mentioned only having a small fridge but you should be able to set the controls so that it will actually freeze. The solder paste and other products I have in the fridge needs 0-5°C for best conservation. The lab is already really full and I don't want to mix chemicals and food in the same freezer. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Parts Manager Working Document
On Mon, Jan 18, 2010 at 11:05:02AM +0100, Florian Teply wrote: Florian Teply use...@teply.info wrote: On Saturday 16 January 2010 06:03:18 Edward Hennessy wrote: On Jan 12, 2010, at 4:18 AM, Florian Teply wrote: I'm gonna try and make up a list of properties of components starting with passive devices. I'll go from very generic properties to more exotic ones in a way i guess will be okay with most users and put that list up for discussion. Excellent. Thanks. No prob, was about do do that anyways as i wanted to have such database for my own use. Left it at work though, hopefully i'll have it in a state for discussion by monday afternoon. Hmm, looks like i have finished said document, at least i can't think of anything to add. Surely, it's not finished yet and does only cover resistors, capacitors and inductors so far as i can't make up my mind whether diodes should go with semiconductors or with passives... Anyways, it is to be found at: http://www.teply.info/gEDA/passive_properties.txt Anny and all comments welcome, i'll add them to the document. Consider that some inductances that I use are not symmetric. While I don't know of any asymmetric resistors (but maybe they exist), some microwave broadband inductors are asymmetric (you can't swap pins 1 and 2, as for polarized capacitors): http://www.piconics.com/Conicals.html Coilcraft has similar products. In other ways, for two terminal components, some are symmetric dipoles, others are asymmetric. Diodes might fall in the second category, but diacs might fall in the first. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Parts Manager Working Document
On Mon, Jan 18, 2010 at 02:23:16PM +, Peter Clifton wrote: On Mon, 2010-01-18 at 14:45 +0100, Gabriel Paubert wrote: Consider that some inductances that I use are not symmetric. While I don't know of any asymmetric resistors (but maybe they exist), some microwave broadband inductors are asymmetric (you can't swap pins 1 and 2, as for polarized capacitors): http://www.piconics.com/Conicals.html I've never seen that kind of thing before (although I don't work in RF). That's always the case in electronics given the variety of components that are available. For switching power supplies etc.. the physical positioning of coils can (sometimes) matter. Assume that given a applied current, the inductor produces a magnetic field pattern which isn't symmetric about the axis you can swap the component around. This could affect interference in the circuitry if you swapped the component around. For all other inductors I've seen, it's only a matter of turning around the inductor when assembling the board. More complex inductive components like transformers are another matter of course, but I restricted myself to two terminal devices. In practice most inductors have an axis of symmetry and a radiation pattern so symmetric that the orientation does not matter; conical inductors are really different in this respect. On the other hand what I have seen with axial inductors is putting them at right angle to minimize coupling, and spacing them apart as much as possible. Which terminal of the coil is wound innermost could affect EMC / electrostatic coupling. (Probably a more important effect than the previous one?) Probably, but once again, it's a matter of turning the inductor around at assembly time. Best regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Parts Manager Working Document
On Mon, Jan 18, 2010 at 09:22:56AM -0500, David C. Kerber wrote: No, I meant passives, because it's not active. I don't consider semiconductor to be the opposite of passive. To me, a diode fits in the groups discrete (vice integrated), passive (vice active), and semiconductor (vice ???) as well, IMO. Of course, it doesn't really matter much, as long as the decision make some sense, which either one does. Actually, to be nitpicking, some diodes have a negative resistance region and can be used as active devices: tunnel diode oscillators (or amplifiers but they are messy with two terminal devices) anyone? And yes, I do use tunnel diodes, in bare dies actually. I bonded a couple of them last Friday, but am still fighting problems with the attachment of the backside, which is the cathode for that particular model, on the substrate with conductive (silver) epoxy. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Silver Epoxy: was Parts Manager Working Document
On Mon, Jan 18, 2010 at 06:26:41PM -0500, Mark Stanley wrote: On Monday 18 January 2010 16:46:59 Gabriel Paubert wrote: And yes, I do use tunnel diodes, in bare dies actually. I bonded a couple of them last Friday, but am still fighting problems with the attachment of the backside, which is the cathode for that particular model, on the substrate with conductive (silver) epoxy. What kind of problems are you having? a) That I am a beginner with this technique. b) That I don't (yet) have the right tools to handle the dies, that are small (square 15mil/side). They are ordered and should be here early next month. I end up with either not enough epoxy or too much with the die drowned in epoxy. c) That I still have to order the proper epoxy (the one I bought from Farnell has a pot life of 10 minutes, which is annoyingly short). d) That the components are germanium based, therefore very sensitive to temperature and I cannot use epoxies with cure temperatures above 125°C. e) That the distributors in Spain take outrageous margins ($200 becomes €400), so I'm trying to find a cheap way to get the epoxy. I've used silver epoxy to build hundreds of modules with bare dies and the only problem I have is replacing the dies. There is only one bare die in the circuit, and I've not had any problem removing one previously glued (enough room around the die, we're speaking of a single 50 ohms coplanar line reaching the diode, backside to ground plane). This may indicate that the gluing was not perfect (to put it mildly). The die is small so the force to remove it is rather small too. Besides that heating above Tg of the epoxy helps: http://epotek.com/SSCDocs/techtips/Tech%20Tip%208%20-%20Reworking%20Cured%20Epoxy.pdf It's point 4 in the above document, the other solutions are not selective enough and may cause collateral damage. With only 1 die I wouldn't care, but I don't like exotic chemicals or sulfuric acid on my PCBs. What epoxy did you use (manufacturer and reference)? I've spent quite some time trying to find the best epoxy for my application over the last two weeks but am still undecided. Actually I was considering either Epotek H20E which seems to be an industry workhorse, or Alfaadhesives' E10-110 because of the convenience of the pouches (combined with high Tg and low cure temperature although the cure schedule is strange). It's a real pain to get off the substrate without damaging other parts. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: CR2032 with supercap, was Re: [SOT] suggestion for a SMT switch
On Sun, Jan 03, 2010 at 09:14:49PM -0500, Jason wrote: Have I mentioned I feel like a bull in a china shop as I plow through datasheets, learning as I go? ;-) Details are below, but the big question is, can I use a 200 mF supercap (EDLC) to dump 100 mA into the motor for short periods ( ~ 1 second)? The reason I ask is because the Panasonic datasheet, found at [4], lists a Maximum Operating Current of 10 uA... That doesn't make sense to me. Nothing I've researched today on supercaps says I can't do it. Bob Paddock wrote: DJ Delorie wrote: Otherwise, look for the smallest MOSFET that will handle your current, as smaller size usually means smaller leakage current. For example, the Fairchild 2N7002K (SOT-23) leaks 1 uA when off (Vgs == 0) but the 2N7002T (SOT-523) leaks only 1 nA when off. Better check the Gate/Source (Vgs) turn on voltage of the 7002, it is not the best at 3V (It is 2.5V Max). It would be better to use something like the FDV305N that will turn on at 1.5V. good call. The output high voltage of an I/O pin on the pic is Vdd - 0.7V, or 2.3V with a fresh battery. It really depends on the load, the 0.7V drop being for a given load current. The gate of a MOSFET has such a high impedance that it will end ramping up close to 3V eventually (but it really depends on the PIC output structure: is pull up transistor N or P channel?). You also have other possibilities: - using a P channel mosfet, changing the polarity of the output (low for motor on and putting eventually a pull-up resistor in parallel with the gate to drive VGS closer to zero). - buffering the output through a 1G04 gate (but beware of ICC, although it is typically much lower that the guaranteed ICC which increases dramatically at high temperatures). Also your impedance between the motor and the coil cell are not well matched, unless you can put a big low leakage, low ESR cap across the voltage point going to your motor/switch combo. What will happen is you will turn on the motor, the voltage will sag from the coil cell to the point that your micro resets, that then turns off the motor, the low ESR cap will minimize this from happening. I already have a cap in place, I'll double check the value to account for the new load. Thankfully, the motor will only run for a second or so when the device state changes (haptic notification). That cap is there for in-circuit programming. I found this [1] discussion on providing higher current from a CR2032 while avoiding brownout. This comment [2], on the same page, goes through some math for calculating cap values. Assuming I need to draw 100mA for 1 sec, that's 0.100 Coulombs. The pic has a minimum operating voltage of 2V. Worst case, the battery is down to 2.7V, so I want no more than 0.5V drop when the motor runs. From [2], my capacitor should be 200mF. Yikes. Some chaotic googling found this [3], which introduced me to the idea of supercapacitors. Digikey has one [4] that seems to fit the bill. It's datasheet claims a low ESR of 200 ohms. That seems much higher than the 1 or 2 ohms I've seen in other places. Well, there is a supercap in the device that controls the heating of my house. The device is powered by 2xAAA (or AA, can't remember, changed tham last 3 years ago) with option of using a lithium cell (can't remember which model either). The supercap is used to provide power while toggling the relay that actually switches the mains and actually enable another set of relays, a bit gross, but works well and was already installed when I bought the house. I know it quite well, since my nephew has the same device which started to act up and was fixed by replacing the supercap (0.047F, so hard to read that I ordered .47F first, too big to fit). However, you want to have power for longer than this device. The PowerStor series from Cooper Bussmann might fit your bill (1kHz ESR down to 0.2 Ohms), but they are neither cheap nor very small (especially the lowest ESR PA series): http://www.farnell.com/datasheets/87303.pdf You can buy them from Newark, which has quite a lot in stock (Farnell charges me extra to ship them to Europe, but at least I can get them). Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: More strange ideas: Start PCB layout from symbols view
On Sun, Dec 06, 2009 at 06:12:41PM -0500, DJ Delorie wrote: instead of C-crap-crap so it can run under Ancient UNIX. I've been writing in C++ on Unix for, oh, twenty years now. How ancient is your Unix? Actually, I've been looking at the code, and I wonder why it's not plain C. If there is anything C++ specific, I missed it. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reducing the amount of jumpers
On Sat, Nov 28, 2009 at 08:44:12PM -0500, DJ Delorie wrote: I never plate my vias. I use 13.5 mil holes and 25 mil diameter copper, very tiny. Wow! You are able to pass a wire larger than the hole? :-) Now realistically, thin wire is often sufficient, unless you have very large currents. I've already soldered chokes made of AWG47 wire (~35µm). And a few days ago, I finally made my first thermocompresion bondings, threading 0.7mil (18µm) gold wire through the wedge hole. It turns out to be easier than I thought :-) Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb [PATCH] Added ActionSetViasTented to allow for setting the solder mask of vias to be fully tented.
On Sun, Nov 29, 2009 at 06:16:40PM +0100, Bert Timmerman wrote: Hi all, And another patch. This one is created from a fresh branch so it should be able to apply without the former patch. Before people believe that tented vias are isolated, they are not, or at least not always. I've been badly surprised by that (contact with a metallic heatsink that happend to touch a tented via. I had to machine a (very small) cavity in the heatsink to avoid the problem. Now what's the difference between that command and a more generic SetViaMask with zero for the mask size; not SetViaMaskGap, simply a command set sets an absolute mask size for all|selected|whatever vias. BTW, I tend to tent all my vias (trivial through an awk script). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Dsub15 HD
On Fri, Nov 27, 2009 at 07:40:54AM +0100, Bert Timmerman wrote: Hi Anthony, Anthony Shanks wrote: Finally getting the hang of the footprint file format, here is a footprint of a dsub 15 high density connector (Analog VGA) if anyone needs it. More footprints to come. Congrats :) Just a couple of notes for you to keep an eye on : - ordering of pin numbers looks weird to me, this might bite with (your) gschem symbols. Indeed. - I do not have a drill size 46.85 mils , or is this metric 1.189 mm ? Metric. A fab will probably use 1.2 final (drilled larger and plated down to roughly 1.2). - pad diameter is 70 mils. - annulus = 11.57 mils, is that large enough for hand soldering ? Yes (it is the radius, not the diameter). Actually I've neer had problems even when using the minimal diameter given by the fab. But my solder contains lead, and wets really well, not the crap RoHS thing (which does even deserves the name of solder). - solder mask hole is 65.06 mils, giving a -2.47 mils overlap with the pad. Strange. I typically give 3 mils of margin to the solder mask (would give 76mil here). There are exceptions for BGA (soldermask defined landing pad), but that's not the case here. I'd add that the origin choice is strange: not at pin 1, not in the center. For my footprints, I always try to put the origin at the geometric center (in this case this would be in the middle of the second row of pins). I can see arguments to put it at pin 1, but not where it is right now. ctrlr, and you get a popup dialog with values. I for one always check pin dimensions in a text editor (with calculator nearby as I live in the metric universe). Me too, but my version of PCB reports dimensions in mm when the grid is set to metric. The only remaining problems is roundoff in some cases. note to devs IMHO, it's is a major pitah that pcb doesn't allow for interactive entering/changing these values in the popup dialog (that is present values in entry boxes instead of text labels). Seconded! Maybe I should scratch that itch myself. I encourage you. /note to devs Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Number of Layers
On Fri, Nov 27, 2009 at 12:41:45PM -0500, Tony Radice wrote: The idea of a 56 layer board makes my eyes water. I Have worked on a 36, and that was (believe me) BAD ENOUGH!! I've never seen more than 24 myself, and designed with more than 6, but I suspect that your 36 layer PCB had blind and buried vias. As long as you don't have blind and buried vias in PCB, I'm not sure that such a large number of layers is really useful in practice: vias that occupy all layers really complicate things like BGA exit patterns (on the inner rings). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Number of Layers
On Fri, Nov 27, 2009 at 01:05:29PM -0500, DJ Delorie wrote: 64 bit machine? Ready for the 128 bit machines yet? ;-) No, that was 32-bit. Hey TeX uses 32 bit coordinates which an unit which is way smaller than PCB and the maximum paper size is around 10 meter IIRC (with a ~5nm resolution). 32 bit (actually 31, there is a sign) gives a large range for linear dimensions: 2^31 times the lattice spacing of silicon is a bit above 1 meter. So 32 bit is sufficient for the largest chips. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint requests for pcb
On Mon, Nov 23, 2009 at 10:42:24PM -0500, DJ Delorie wrote: Note: the SOT416 and SC70-5 might match some of the other footprints, like SOT-23-5 or SOT-323-t. Check the dimensions. I may be mistaken, but SC70-5 is much smaller than SOT323 (0.65mm pin spacing instead of 0.95mm). Here is the SC70-5 footprint I use for an amplifier (LPV511). If memory serves, I took it from Philip's (ne NXP) website and it is the wave solder version (easier to hand solder with the large corner pads). There is a different (reflow probably) footprint in the LPV511 datasheet on National's website. Element[ U4 81500 49000 -1953 4658 0 80 ] ( Pad[3543 2953 3543 2953 2362 2400 2962 1 square,edge2] Pad[3543 -2953 3543 -2953 2362 2400 2962 3 square,edge2] Pad[-3543 -2953 -3543 -2953 2362 2400 2962 4 square] Pad[-3543 2953 -3543 2953 2362 2400 2962 5 square] Pad[3149 0 3936 0 1574 2400 2174 2 square,edge2] ElementLine [-5118 -4528 5118 -4528 600] ElementLine [5118 -4528 5118 4528 600] ElementLine [-5118 4528 5118 4528 600] ElementLine [-5118 -4528 -5118 4528 600] ElementArc [-196 4529 1182 1182 270 90 600] ElementArc [-197 4528 1181 1181 180 90 600] ) Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to deal with single/dual parts?
On Sun, Nov 22, 2009 at 10:22:41PM +, Kai-Martin Knaak wrote: On Sun, 22 Nov 2009 18:32:08 +0100, Stefan Salewski wrote: Scheme is one of the simplest programming languages there is. It's simplicity is much like the game of go -- Just four short rules need to be obeyed. Yet, the actual game is so complex that computers have yet to consistently beat top rank human players. Scheme is a programmable programming language. As such, it can and must be expanded on the fly to achieve the same features hard coded into most other computer languages. Yes, this is flexibility taken to the extreme. This kind of power and beauty obviously appeals to grad students of computer science. However, extreme flexibility comes at a price. The price is non-intuitive syntax and a lack of predefined algorithmic structures like loops. In addition, there are vastly different scheme code styles. A scripting interface to an application does not need generalized programmability. But it should be as intuitive as possible. So a general user can easily whip up the script needed for his/her particular purpose. It is no coincidence that popular scripting languages like perl, tcl or php do not feature such general flexibility. Ouch, tcl and perl (I don't know php) are two of the languages I can't stand. The tk part of tcl/tk is quite god (from what I've used through tkinter in Python) but tcl? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Switch gschem to another scripting language?
On Sun, Nov 22, 2009 at 06:24:18PM -0500, Stuart Brorson wrote: Why have we so much scheme in gEDA? IMO, if there is a problem with scripting in gEDA, the problem is that the guile developers (and not the Scheme language) have created problems for us repeatedly. Specifically, they have moved the API many times, breaking gEDA every time they spin a new guile release. Also, they have embedded all kinds of libraries into their implementation which become required dependencies, leading to dependency hell for folks who want to build gEDA from source. Dependency growth and seem to be an unavoidable fact of life with all scripting language and a consequence of immoderate featuritis. Look at the number of libraries that are loaded when starting a Python interpreter (and how it has exploded from a really old version like 1.5). In this respect, Scheme seems tremendously lightweight (for the time being). IMO, the solution to the guile problem is to simply take control and use our own interpreter, maybe including the TinyScheme source into libgeda, or something like that. However, I understand that others don't want the discussion to go in that direction, so I'll leave my point at that. So why don't people like Scheme? Here's my opinion: 1. There are lots of folks who whine about learning another language. I already know TCL, so why should I learn Scheme? As John Doty says, this attitude stinks. It implies that the person with this attitude doesn't want to learn, which is a terrible attitude for a practicing engineer. I ignore those people since they whine about gEDA, but don't actually contribute code. From my experience, I have soemetimes had to modify a few lines of Scheme (nothing serious) and I found it way easier than modifying any other scripting language that I did not know... (Ok, I did some list 25 years ago, but it's long forgotten). 3. Some people are confused by Scheme's many parentheses. It is true that poorly indented Scheme code can be hard to read, but the same is true of obfuscated Perl, or any poorly structured program. And FWIW, the netlists implemented by Scheme back-ends in gnetlist are generally well written and easy to understand. Is there really a difference between obfuscated Perl and line noise? :-) Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA-dev: Arc intersection connectivity bug
On Fri, Nov 13, 2009 at 01:42:33AM +, Peter Clifton wrote: On Thu, 2009-11-12 at 17:03 -0500, DJ Delorie wrote: The file format and internal data formats support it, but there's no way other than editing the file to set width and height to different values. The OpenGL hid won't render that properly, but that is my bug ;). I just assumed rx == ry == radius, and clearly that might not be the case if people start editing their files manually ;) Anyway, right now you won't be able to produce the corresponding photoplotter files. While as far as I know Gerber only allows circular interpolation: http://www.artwork.com/gerber/274x/rs274xrevd_e.pdf it may be possible to produce elliptical arcs by using the SF command (scaling factor). Neither the PCB nor the Gerber file format allow to describe ellipses with arbitrary orientation. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA-dev: Arc intersection connectivity bug
On Fri, Nov 13, 2009 at 08:28:33AM +, Ineiev wrote: On Thu, 2009-11-12 at 20:06 +, Ineiev wrote: Probably the function should be rewritten almost completely. I'll try tomorrow. And this is what comes in the attachment. First, I suggest computations against the centerlines of arcs; this simplifies the geometry and does not impose limitations because we have no square-ended arcs. The general method is to use IsPointOnArc to test several candidates and return false if all tests results are negative. Thus, the suggested sequence is: (1) check the ends of each arc against the other arc. this is done unconditionally, as it would be needed in all groups of cases (2)..(4) under certain conditions. generally, the nearest distance from one arc to another is achieved either on an end of the first or the second arc, or on the line connecting the centers of the arcs. (2) check concentric arcs. it is treated now almost correctly; but the bounding boxes are irrelevant; also, I'd s/l == 0\.0/l 0\.5/ because I believe that the compiler should have freedom to optimise the former to false. No, there are very few things that you can optimize in floating point computations. Not even adding 0.0, multiplying by 1.0 or comparing a number with itself. That is unless you use some weird options like -ffast-math. Gabriel. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA-dev: Arc intersection connectivity bug
On Fri, Nov 13, 2009 at 09:13:08AM +, Ineiev wrote: On 11/13/09, Gabriel Paubert paub...@iram.es wrote: On Fri, Nov 13, 2009 at 01:42:33AM +, Peter Clifton wrote: Anyway, right now you won't be able to produce the corresponding photoplotter files. While as far as I know Gerber only allows circular interpolation: http://www.artwork.com/gerber/274x/rs274xrevd_e.pdf it may be possible to produce elliptical arcs by using the SF command (scaling factor). Neither the PCB nor the Gerber file format allow to describe ellipses with arbitrary orientation. IMO if PCB would fully support such complicated curves, it would better support something general like beziers; it would not be much harder, but more useful. Well, expect the size of the Gerber files to explode and OpenGL performance to drop... I'm not really sure that I need even elliptical arcs for a start. OTOH, I'd like to be able to have arc segments as boundary for polygons, since it would simplify some common microwave structures. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Kudos
On Tue, Nov 03, 2009 at 01:02:33PM -0700, Eric Brombaugh wrote: On 11/03/2009 12:35 PM, Duncan Drennan wrote: * gschem magnetic nets - always seem to snap to the wrong thing for me so I end up turning them off always. Need to tweak my config file. You can temporarily disable this feature by holding in the CTRL key. I guess that should be added to the wiki somewhere By golly, it works. Thanks for the tip! I would for one prefer to have the capability of inverting the way the Ctrl key works. It is possible? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB grid question
On Wed, Oct 21, 2009 at 10:46:47PM +0200, Stefan Salewski wrote: On Wed, 2009-10-21 at 22:12 +0200, michalwd1979 wrote: Hello, During design of my first more complicated board I run into problems with grids - element's pins often do not fall onto grid point. Sure -- if I have an element with 0.65 mm pitch and one with 0.5 mm pitch it will not fit nice. And if you have even two wit the same grid and different orientations (pin 1 on top or bottom) or with a different number of pins, they will not even be always aligned from PCB point of view due to the rounding to 0.01mil. This leaves small dots when you delete a track and move/remove a component. (It would be less of a problem if internal PCB units were metric, almost all the component I use now are metric and the imperial ones are on a grid of 5µ I believe). I assume you know that Settings/Crosshair snaps to Pins/Pads can help to ensure that traces go to the center of pads. And that you know that you can grab elements at center or at individual pads for positioning. (For version 20081128 pads have two snapping points -- not always what I want...) Indeed, I do not understand the reason for this change, having one snap point at the center of the pad was much nicer for me in practice. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB grid question
On Thu, Oct 22, 2009 at 05:47:40AM +0100, Peter Clifton wrote: On Thu, 2009-10-22 at 06:44 +0200, michalwd1979 wrote: Thank You all for replies! Yes I know about snap to pins option. I'm using opengl version compiled from git, and I did not noticed 2 snapping points for pads. Nope ;) That is one of the various little changes which needs to be sorted out from that branch, distilled - and if people want it, pushed to git HEAD. Please, or at least give us a choice. When you have a rectangular pad and want a track that exits along the larger side, the fact that it does not snap to the center is annoying. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Information on PCB
On Wed, Oct 21, 2009 at 05:37:21PM -0400, DJ Delorie wrote: You don't need to be physically present to party^H^H^H^H^Hcode with us :-) No but it always falls at odd times for me (Spain), and I've never used IRC or something similar. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
On Mon, Oct 19, 2009 at 03:18:25PM +0100, Andy Fierman wrote: So your consultant thinks it's a bad idea to have a Vcc plane because it takes up space that you could use for additional ground planes and that you might need to run traces ... ... and then urges you to run power traces where? In the - now empty - Vcc plane layer? Or in the same layer as your already (according to your consultant) full signal layers, leaving you a whole layer to put a shiny new ground plane into? Hmmm. Suppose you have a 6 layer PCB with one continuous ground pane and one continuous Vcc plane (dream on ...). It's not ideal but not everyone wants to pay the extra for 8 layers. layer 1 = signal (set up for 50R trace impedance w.r.t. ground plane) : small spacing : layer 2 = ground plane : small spacing : layer 3 = signal (set up for 50R trace impedance w.r.t. ground plane) : big spacing! (to minimise Xtalk between layers 3 to 4) : layer 4 = signal (set up for 50R trace impedance w.r.t. Vcc plane) : small spacing : layer 5 = power plane : small spacing (set up for 50R trace impedance w.r.t. Vcc plane) : layer 6 = signal The problem is that you often have no choice with regard to layer spacing. For 6 layers, low cost prototype quantity, my fab does indeed have a large spacing in the middle, a small one between layers 2 and 3 (and 4 and 5), and an intermediate one between the outer layer and the next one. That's really messy for impedance control... All the return currents for signals on layers 4 6 run over the power plane until they get decoupled to layer 2 ground plane. Not ideal but if the Vcc plane is properly decoupled to the ground plane with good ceramic decouplers adjacent to all signal sources and destinations (some of which may be dedicated and some shared Vcc decouplers anyway) then that is OK. Indeed. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
On Mon, Oct 19, 2009 at 10:07:00AM -0500, John Griessen wrote: Andy Fierman wrote: So your consultant thinks it's a bad idea to have a Vcc plane because it takes up space . . . Hopefully you can gently persuade your boss that this is not quite what the very expensive consultant meant to say. So, are there no conditions where leaving out a VCC plane makes sense? He might not have meant to compare to 3GHz motherboards. If he meant to deal with RF transceivers as special case zones, and the rest of the circuits operate below some clock speed like 600MHz, I can imagine a stack up like: for a four layer board... signal + VCC = GND1 = signal2 = GND2 = signal3 + VCC2 Congratulations, you've fitted 3 signal planes and 2 ground planes on a 4 layer board! I must admit that making an additional plane come out of nowhere would sometimes simplify my boards... or for a six layer board signal1 = signal2 = GND1 = signal3 = GND2 = signal4 = signal5 Again, 5 signal planes plus 2 ground planes out of 6. Lack of caffeine? Now if we could just specify blind vias easily with pcb... Holy grail. But first thing (even for 3 D viewing) would be to be able to specify a Z coordinate for each layer, layers with the same Z corrdinate being merged. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
On Mon, Oct 19, 2009 at 10:50:49AM -0400, Gene Heskett wrote: On Monday 19 October 2009, Bob Paddock wrote: Boss just sent around something he got from a consultant on doing proper EMI design (which I've been doing for years already, I thought until consultant came up with this): Eliminate separate Vcc planes. What's he/she smoking, it must be great stuff and I want a sample. Keep some for me also. Thanks. This ancient practice is long overdue for an overhaul. Years ago, the leaded capacitors were not able to provide a good enough short at VHF and above, so the reasoning was that the parallel plates of Vcc and ground made a good UHF capacitor. The problem with this is twofold: it takes away one or more ground planes, and more importantly doesn’t allow the designer to control where the noise current goes. Noise follows the path of least impedance, which may be anywhere on the PCB after you punch holes in the Vcc plane for vias and to route traces that have no other room to go. The best way to control noise is to use a separate trace for Vcc, and apply series and shunt elements to control the noise currents. There is no attribution as to were that advice comes from. And as a C.E.T. with 60 years of electronics experience, troubleshooting to the part level, I sure as heck would not want my name attached to such advice. Well, the assumption is that there are traces that have no other romm to go than the VCC plane. This is something that I would never do (either you have a plane only interrupted by the unvaoidable vias or you don't have a plane). I sometimes do an exception for double layer boards, but of course never in an area of high frequency signals... Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
On Mon, Oct 19, 2009 at 06:43:42PM -0500, Darrell Harmon wrote: On Mon, Oct 19, 2009 at 5:27 PM, Dan McMahill d...@mcmahill.net wrote: my recent experiences are more in line with Larry's. Most C for a given package and voltage seems to be the best meaning that above resonance it is no worse than smaller capacitance value devices and below resonance it is better. And yes, this seems to fly in the face of what has been recommended in the past. I've not done any careful measurements of older technology bypass caps but I wonder if this is one of those rules which became obsolete 15-20 years ago and no one noticed... -Dan I have done some testing of various passives (mostly 0402) and came to the conclusion. I tested both shunt and series capacitors on a 50 ohm transmission line with a VNA. What was most interesting to me was that the large value capacitors performed better as series coupling caps than the small ones. The single layer caps in the 1 to 100 pF range frequently had parallel resonances in the 10 to 30 GHz range. Most of the multilayer caps (10 nF to 1 uF) performed well to at least 30 GHz. And for the shunt case? Some manufacturers (ATC, Dielectric Labs) also offer specific broadband coupling capacitors, did you try them? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: chassis ground - symbol errors, I wonder?
On Sat, Oct 03, 2009 at 01:28:53AM +0200, Stefan Salewski wrote: On Sat, 2009-10-03 at 01:10 +0200, Stefan Salewski wrote: On Fri, 2009-10-02 at 14:43 -0700, S. Aguinaga wrote: Hello Fellows, I've added a chassis ground and used the symbol: chassis.sym The symbol seems to be corrupt for gEDA 1.4.3: ste...@amd64-x2 ~/gEDA/DAD $ cat /usr/share/gEDA/sym/IEC417/chassis.sym v 20031231 1 P 200 300 200 100 1 0 0 L 50 100 350 100 3 0 0 0 -1 -1 L 350 100 300 0 3 0 0 0 -1 -1 L 200 100 150 0 3 0 0 0 -1 -1 L 50 100 0 0 3 0 0 0 -1 -1 Try one of the other ground symbols shipped with geda or from www.gedasymbols.org. gnd-3.sym from my page there looks similar. After closer inspection: I think the IEC417 symbols are for schematics or block diagrams only, not for generating net lists. Correct. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sym files sorting
On Fri, Oct 02, 2009 at 09:34:12PM -0700, Steven Michalske wrote: On Sep 22, 2009, at 7:34 AM, Kai-Martin Knaak wrote: The gschem gui seems to append new items to the bottom of the file. As a consequence, symbols done with the GUI are a pain to edit in a text editor. Pins mix with comments and attributes in no particular order. It would be nice, if the internals were sorted by type, by value, and/ or by position. Did anyone write a script to sort the internals of a sym file? Keep in mind what happens to the files in a revision control system, sorting might not be the best option. Or would it help the revision control systems, after an initial sort nightmare ;-P I think so. If we do sort them, I'd vote for alphabetical on keyname. It has to be more sophisticated than this to minimize (heuristically of course) sizes of diffs between versions. Sort by element type first (rectangles, lines, text, pins...) and then by some part of the content: text for text elements, certainly not location, this will automatically sort attributes by name, but not by the value, however you may want to classify text between attributes and random text. Sort the pins by pinnumber (or pinseq, since pinnumber may change between packages for the same chip) attribute. For other elements I have no idea. However, typically a symbol only has one box, (or very few) the the sorting on the B tag should be sufficient, and these are heuristics after all. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
On Tue, Sep 29, 2009 at 05:21:16PM +, Kai-Martin Knaak wrote: On Tue, 29 Sep 2009 17:01:23 +, Michael Sokolov wrote: I'm told that the OMAP3430's Package-on-Package configuration requires at least six layers to get all the signals out. Ugh. OK, that explains the need for a lot of layers. But how does the need for blind/buried vias arise? The balls of the BGA occupy most of the real estate available on top layer. If all vias penetrate the hole stack, this occupation maps to all other layers too. Actually most often the top layer looks like a two interlaced grids: - one grid of pads to solder the balls, - one grid of vias that go allow to route the signals to other layers That's as long as you don't use exotic techniques like via-in-pad. Basically the two outermost rings of the BGA can be routed on the top layer (there is room for one trace between pads). The next two rings can be routed to the second copper layer with simple vias. But then every additional ring needs one layer if you don't have blind vias (buried vias are not necessary for BGA exit patterns), since there is only room for one trace between vias. With blind vias it is possible to route 2 rings per layer, and this adds up quite fast for large BGA. Of course there are also sometimes stupid packaging decisions by manufacturers, one example is the Spartan3A in BGA256 package where they decided to put some power connections on the second ring. The worst case: on the first ring it is easy to put a via just outside without blocking the exit for the second ring, from the third ring on you need a via anyway. Spartan2/2E in the same package did not have this stupid pinout. Therefore realistically blind vias for BGA exit patterns are only necessary for 20x20 matrices and larger (the center is often taken by power supplies which are easier to route). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind and buried vias?
On Mon, Sep 28, 2009 at 08:28:19PM +, Michael Sokolov wrote: How about we move this thread back to its original topic of blind and buried vias, not arguments regarding whether or not PCB is part of gEDA. I have some questions out of plain curiosity: completely aside from the question of how they ought to be handled by GNU PCB or any other PCB design tool, I wonder how these blind/buried vias work at a more basic level: 1. How are blind/buried vias made physically? I thought they glued the layers together first, then drilled the holes. By drilling layers before gluing them, although for the external layer, there are other processes like laser etched microvias. 2. How are they represented in the Gerber+drill file set that passes from the PCB design tool to the fab? By several sets of drill files. I was even bitten by what can be considered as a bug in OrCad 15 years ago: I had moved a through hole component to the other side of the board and I had two drill files for the two layer board (the first one was something like drl0-15.ncd and the other one drl15-0.ncd). I sent only one to manufacturing and the holed for the component on the back side was not drilled, I don't know why OrCad thought that a hole going from top to bottom was so different from one going from bottom to top to put them into two different files, but that is what happened. By the way, it was only a double-sided board (on some expensive high frequency laminate from Rogers, signals were up to ~5GHz). Anyway, I managed to screw-up the first batch. I'm asking out of plain curiosity - I hope that I never have to make a board with such vias as I've heard that they add a bit of sadomasochistic flavor to board bringup/debug efforts - but then I guess some boards are so cramped for space that you can't avoid them... Indeed. Although I have never needed them. Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB 20081128: Autoscrolling moves in wrong direction for solderside
On Sat, Sep 12, 2009 at 04:09:48PM -0400, gene glick wrote: Stefan Salewski wrote: Maybe one more unknown minor bug: If we select an element and move it to the window borders, then the display scrolls. If we flip the board with TAB key, select an element and moves it to the lower border, the display scrolls in wrong direction. For PCB 20081128 GTK. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user I find the autoscroll works sometimes, and sometimes not. I haven't spent any time to figure out why? I'm glad to learn that there is an autoscroll. If there is one feature of pcb that has never worked for me, it is that one (well maybe there are more). I only used versions of PCB that I compile myself, from the git repository and more often with the lesstif than with the gtk interface. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: merge multi symbol components
On Wed, Jul 22, 2009 at 10:55:33AM +, Kai-Martin Knaak wrote: On Tue, 21 Jul 2009 22:28:37 -0400, DJ Delorie wrote: Note that I have at least one schematic where the merging of the symbols would have duplicated pins; this is intentional and they're supposed to be connected together. Just to be sure: The duplicated pins refer to the same physical pin, do they? If this is true, a merge of pin lists would be correct. The main case I'd like to catch is unintentionally duplicated symbols. If both, refdes and all pins are identical, it is safe to assume an error. Well, could we use the pintype attribute as a hint? Passive and power typically might be duplicated. I doubt you will have frequent duplicate inputs and/or outputs. (In a typical FPGA design, I might duplicate the Vref pins for some I/O standards because several symbols share the same I/O bank, however the inputs and outputs will use different pins). I might be very wrong on this, however. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: merge multi symbol components
On Wed, Jul 22, 2009 at 06:07:54AM -0500, Bill Gatliff wrote: Kai-Martin Knaak wrote: The main case I'd like to catch is unintentionally duplicated symbols. If both, refdes and all pins are identical, it is safe to assume an error. Nak. In my case, I use one symbol to refer to all 8/16/32 bits of a GPIO port on a microcontroller. I'll use a few bits from that port on one page, and a few on another. Connect it to an NC symbol to explicitly show that you don't use that pin in that instance of the symbol. But the rules start to become inscrutable. If I'm dealing with a wired-OR input, then the same pin might get used on several different sheets. And if that's the only pin on a port that gets used, then your logic would trip it as an unintentionally duplicated symbol. Ok, that one is really harder. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Broken mail clients
On Wed, Jul 22, 2009 at 12:19:37PM +0100, Peter TB Brett wrote: Hi everybody, Recently there has been an increasing number of people who customarily post to the list with geda-u...@seul.org in both To: and Cc: fields. This results in my getting two copies of every e-mail you send, and is starting to get irritating. Could you please ensure that your mail client is configured so as to avoid this? I suspect a list configuration problem. My mailer eliminates duplicates, but it is not clever enough to guess that geda-u...@seul.org and geda-u...@moria.seul.org are equivalent. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB patches
On Mon, Jun 08, 2009 at 04:30:15PM -0400, DJ Delorie wrote:
Thanks, are the alt keys correct in linux?
Yup.
I think so. But on my spanish keyboard, I get an annoying
“Key not tied to an action” message in the log window
every time I type the AltGr key (which is needed for |, the
shortcut for thindraw, among other characters like \...@#~{[]}µ).
According to xev, this key is:
KeyPress event, serial 34, synthetic NO, window 0x2a1,
root 0x46, subw 0x0, time 2941158078, (170,-13), root:(174,14),
state 0x0, keycode 113 (keysym 0xfe03, ISO_Level3_Shift), same_screen YES,
XKeysymToKeycode returns keycode: 64
XLookupString gives 0 bytes:
XmbLookupString gives 0 bytes:
XFilterEvent returns: False
KeyRelease event, serial 34, synthetic NO, window 0x2a1,
root 0x46, subw 0x0, time 2941158182, (170,-13), root:(174,14),
state 0x80, keycode 113 (keysym 0xfe03, ISO_Level3_Shift), same_screen YES,
XKeysymToKeycode returns keycode: 64
XLookupString gives 0 bytes:
XFilterEvent returns: False
Gabriel
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Re: gEDA-user: Can we fix the HTML stripping on this list?
On Tue, Jun 09, 2009 at 06:23:35AM +, Michael Sokolov wrote: Dave McGuire mcgu...@neurotica.com wrote: I vote for automatic and immediate unsubscription of people who post messages in HTML. I second that! Thirded, apologizing for the neologism. What does HTML stand for anyway (and all these makeup languages) ? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
On Fri, May 22, 2009 at 05:02:25PM +, Michael Sokolov wrote: John Griessen j...@ecosensory.com wrote: but then, the international reach of the internet along with closed borders and regulated trade may put me out, way out :-) You mean Ineiev's offer being 15-40 times cheaper than what you and everyone else has offered? Yeah, that pretty much guarantees that I'll go with him. :-) Yes, I know the saying that you get what you pay for. But this is a *hobby* project on which I don't expect to make any money ever. I have mentioned the possibility of one ISP wanting me to make 100 of those units, but after I had made that post I have rechecked the availability of all the parts on my BOM and confirmed what I had feared: the RS8973 SDSL transceiver chip, the one that the whole design revolves around, is no longer available by any means other than buying other old SDSL routers on eBay and desoldering that chip. I have 10 such sacrificial routers in my stash which have been acquired for that specific purpose. There is one other chip in my design which I would like to keep in there for sentimental reasons (TI SN75LBC784 EIA-423 transceiver), and it has also apparently become unobtainium. I have 25 of those on hand. Indeed, while some distributors apparently still have a non-negligible stock of Conexant's RS8973 (www.americaii.com claims 1943), the transceiver is obsolete. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Outsourcing PCB layout
On Mon, May 25, 2009 at 03:35:07PM +, Michael Sokolov wrote: Gabriel Paubert paub...@iram.es wrote: Indeed, while some distributors apparently still have a non-negligible stock of Conexant's RS8973 (www.americaii.com claims 1943), Thanks for the pointer, I'll check it out! I'm not affiliated in any way to AmericaII but I was looking a few weeks ago for the high speed grade (-5) of a Xilinx Spartan3A (some part of the design has to run at 400MHz, only 20 flip-flops or so, but that's a case where the speed grade makes a difference); I ended up buying the parts from them since other distributors only carried -4 or gave me 12-13 weeks of delay. the transceiver is obsolete. Sorry, I did not express myself well, I meant the TI part (SN75LBC784), that one does not appear in stock in any of my providers. Yes, Mindspeed doesn't want to make, sell or support it any more because they have M289xx as the new replacement. Care to know why they obsoleted RS8973 in favor of M289xx? RS8973 was open source-friendly, whereas M289xx is completely closed. See this page for the full gory details: http://ifctfvax.Harhan.ORG/OpenSDSL/chips/mindspeed.html Interesting... Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Simple LM741 Op-Amp Example
On Sun, May 17, 2009 at 12:29:52AM -0400, Michael B Allen wrote: Hi, I'm just paying around but I'm trying to do a simple LM741 Op-Amp simulation. Here is my schematic: http://207.192.69.113/~miallen/lm741.pdf It can't work, but I have difficulty guessing what you want to do. If you want an inverting amplifier, you have to put a resistor in series with V2 (between V2 and the inverting inputof the opamp), and probably change the DC voltage of V2 to 1/2 V1. IOW, the inverting input is used for the feedback, but if you connect it to a voltage source with zero impedance, it can't do its work. If I blindly mess with resistor values I can get the simulation to actually complete but the input node isn't giving me a good SIN. Is my voltage divider wrong? How do I get -4.5 and +4.5 to Vss and Vcc respectively? By using 2 voltage sources of 4.5V in series and using the common point as a reference? But it's not the root of the problem. Voltages are only differences or potential between nodes. The node you use as a reference is arbitrary (not in practice, but in a simulation). Regards, Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: soldering QFN packages with exposed bottom pad?
On Tue, Apr 28, 2009 at 02:56:07PM -0500, John Griessen wrote: DJ Delorie wrote: I would think that mounting the chip upside down . . . I suppose you could hand-solder some copper foil or desolder braid to the pad, as long as you're careful to not short the pins. Then it would look like a dead, gutted bug. I'm going to look into methods of dealing with BGAs in prototypes since Bill's tech says they're less trouble after a learning curve. I've heard and can imagine the way they pull themselves to alignment by surface tension between the grid of chip balls and the grid of lands on the pcb. Yes, but it works much better with leaded solder. I've got a small reflow oven at work and I've seen 0603 capacitors and resitors center themselves. With a BGA, it will be hundreds of points pulling themselves into alignment. But I don't see how you are going to put the solder paste without a stencil. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
