gEDA-user: BatchPCB
Hello, I wanted to drop a quick question to see if anyone here has had any trouble with their gerbers being interpreted correctly by batchpcb drc tool. My design looks just fine in viewmate and the protoexpress auto DRC passed the design. It seems the only room for error is in the batchpcb project submission page where it inquires about the software tool used for the design. I think this is for the drill file number format. I'm not really sure what I needed to put there so I tried a few different options. I opened the drill file and it looked like the format was 1.3 normal. My design didn't have a back silk screen layer so I created a simple one by hand but that didn't get around the issue either. This is what the log file generates from batchpcb's drc checker for both the top and bottom layers: Beginning GCODE run Invalid DCODE 0 GCode execution failed! Here is the thread on the support forum for batchpcb: http://forum.sparkfun.com/viewtopic.php?p=44189#44189 Thanks, Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Ubuntu Vmware Player Image
I finished creating a Ubuntu Vmware player image that has geda, pcb, geda-utils, subversion and a few others installed. I posted it on my web page under the downloads-Tools section at www.jendylabs.com http://www.jendylabs.com/files/Ubuntu-7.10-desktop-i386.zip Later, Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: VMPlayer Image
Sorry for the delay. It looks like someone recently posted a Ubuntu image, which is great. Anyway here is a link to the page which has the fedora core 5 based Vmware images that I use. The image has 20060822 build of pcb installed. There's plenty of bandwidth available yet and the download speed saturated the downlink on my cable modem at 600KB/s. http://www.jendylabs.com/index.php?section=9 Cheers, Jeff On 3/9/07, Sztrikó János [EMAIL PROTECTED] wrote: I'm interested in it. Have you found a host, is it available now? Thanks, Janos Jeff VR wrote: Well, based on the discussion I think there is definitely some interest and it's worth providing. I haven't made huge strides to make the image smaller but compressed it's around 830MB. I've got a couple hosting options I'm looking into with sufficient bandwidth. It should be available in a couple of days. Jeff VR ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: ERP Systems
I'm very interested to see how your evaluation turns out. I watched some of the demos of TinyERP and it looks like it will meet my needs. I'm not sure I need as much material management as your looking for. I'm mainly looking for something to track my limited inventory of parts so I can run shortage lists, bill of materials, part number management (dist. P/N, mfg P/n, desc, etc) before building boards. Just blue skying here but it would be pretty sweet to synchronize part numbers, desc, etc with the gEDA library and BOM output with an ERP format. Even importing and exporting BOM's and parts would be slick. Jeff VR On 3/5/07, Seb James [EMAIL PROTECTED] wrote: On Sat, 2007-03-03 at 20:56 -0500, Bob Paddock wrote: A couple of people had asked what Open Source ERP Systems where around. http://freshmeat.net list 48 of them. SourceForge has many others. I had played the most with http://www.compiere.org/ but found it to be week in the area that I was most interested in, material management. Linux support for Compiere came from the Fyracle project, http://en.wikipedia.org/wiki/Fyracle , based on the FireBird database, however, from the Fyracle news server: As most of you probably noticed, Compiere Inc. became ever more reluctant to accept input from its community. A number of active Compiere users have started Adempiere, with the intent to create a true community around the code base. http://www.adempiere.com/ Source Developers that contribute improvements of Compiere, CRM, Shopfloor, POS, Helpdesk, Financials Accounting, Supply Chain, Knowledge and Business apps in an open and unabated fashion. Most of the ERP systems do the easy stuff like Accounting, or the visible stuff line Web front ends, like that is a big deal these days. What I'm look for is The supply chain approach models stochastic events influencing a manufacturing organization's shipment and inventory performance in the same way that a mechanical engineer models tolerance buildup in a new product design. The objectives are to minimize on-hand inventory and optimize supplier response times. With the gory math to support that here: http://www.unusualresearch.com/supplychain/supplychain.htm In a simplified form something that has some clue of shop floor scheduling, and inventory management. Right now I'm looking at http://tinyerp.org/but still have several more to look at. If I every decide on one, I'll let the list know. If you know of any that don't show up on Freshmeat or SourceForge let me know, please. In the end maybe I'll just write my own in MUMPS I wrote a framework for Business Process Software, called phpOrganisation. One of the things I do with this is accounting for my own business, but it has potential as a base to build this sort of system. It currently looks like an accounting system, but it's really a web application with a good contacts database system which can be a springboard for any business process application. Just thought you might be interested in having a look at the project. It has been quiet for the last year - it would be great to re-vitalise it. Seb James -- http://www.phporg.netphpOrganisation http://www.esfnet.co.uk Embedded Software Foundry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: VMPlayer Image
Well, based on the discussion I think there is definitely some interest and it's worth providing. I haven't made huge strides to make the image smaller but compressed it's around 830MB. I've got a couple hosting options I'm looking into with sufficient bandwidth. It should be available in a couple of days. Jeff VR On 2/17/07, devrin talen [EMAIL PROTECTED] wrote: I would definitely be interested in it. - Devrin Talen On 2/16/07, Jeff VR [EMAIL PROTECTED] wrote: Is there any interest out there in a VMPlayer Image? I created as well as use one based off of Fedora Core 5. I made it available at the local IEEE meeting last night and 10 copies made there way out the door. Jeff VR ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA meeting in Sioux Falls SD
Sorry. I'll log in next time when I'm presenting in April to some Senior design students at a local university. Jeff On 2/16/07, Peter TB Brett [EMAIL PROTECTED] wrote: On Thursday 15 February 2007 21:09:41 Jeff VR wrote: Just in case there's someone interested in participating online. Warning: This requires a FLASH plug in for your browser. --- To join the online meeting --- 1. Go to https://freetrial.webex.com/freetrial/j.php?ED=94549382UID=0 2. Enter your name and email address. 3. Enter the meeting password: geda 4. Click Join. --- To join the teleconference only --- Call-in toll number (US/Canada): 650-429-3300 What, no IRC channel? Why not use #geda? Peter -- Fisher Society committeehttp://tinyurl.com/o39w2 CUSBC novices, match and league secretary http://tinyurl.com/mwrc9 CU Spaceflight http://tinyurl.com/ognu2 v3sw6YChw7$ln3pr6$ck3ma8u7+Lw3+2m0l7Ci6e4+8t4Gb8en6g6Pa2Xs5Mr4p4 hackerkey.com peter-b.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: VMPlayer Image
Is there any interest out there in a VMPlayer Image? I created as well as use one based off of Fedora Core 5. I made it available at the local IEEE meeting last night and 10 copies made there way out the door. Jeff VR ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA meeting in Sioux Falls SD
Where in the world is Sioux Falls? And did the subject specify the state of South Dakota??? Yep there's a few geeks in the Midwest, not just the east and west coast. :) Just in case there is anyone on on the mailing list that is in the Sioux Falls SD area. I would like to extend an invitation to this meeting who is entertaining the idea of doing a PCB design with gEDA. We are meeting at Colorado Technical University on Feb. 15. By the way there's pizza and soda involved. A couple of months ago I chose gEDA as the tool suite for laying out my first PCB. With a little help from people on this message board and a couple months of free time I was successful! I don't claim to be an expert at PCB design or even gEDA. But I do understand the basic design flow and can assist someone who needs a little assistance getting started. For many people the installation and use of Linux is just a little more than you care to bight off at one time, so I plan to provide a VMPlayer image at the meeting. Again I'm no electrical engineer since my background is Software Engineering so don't drive 2hrs to get that burning question about transistor saturation answered. There may be someone at the meeting that can answer it but it won't be me. If your interested and live nearby I would love to meet someone else who has worked with these tools. Get the details at: http://www.siouxland.org/ I apologize if this is a misuse of this message board. Thanks for your support, Jeff Van Roekel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-263 footprint
I'm excited to say the status is now: works great. On 11/16/06, John Luciani [EMAIL PROTECTED] wrote: On 11/16/06, Jeff VR [EMAIL PROTECTED] wrote: I just received my boards which are using this TO-263 footprint. They should be placing and assembling the board tomorrow but I just wanted to let you know that the footprint looks great. Glad to hear it. I look forward to the *works great* email ;-) (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-263 footprint
I just received my boards which are using this TO-263 footprint. They should be placing and assembling the board tomorrow but I just wanted to let you know that the footprint looks great. Thanks for the help, Jeff VR On 10/12/06, John Luciani [EMAIL PROTECTED] wrote: On 10/12/06, Jeff VR [EMAIL PROTECTED] wrote: I've been looking around for someone who has posted their TO-263 footprint. Does anyone have one they would be willing to share? I'm just looking for a starting point but I need a 5 lead TO-263 that I'll be using for an LM2595. I figured this is be a pretty common footprint so someone has to have already completed the work would be willing to share it. Below is a footprint for the NSM TS5B Package. The tab is pad 6 NB: Carefully check this footprint against the NSM print. I have not used this symbol on a PCB yet. If you find any mistakes please send me an email. (* jcl *) Element[0x0 TO263_170P_788L1_5N__National_TS5B_Package 0 0 -21000 -22000 0 100 0x0] ( Pad[-13400 35650 -13400 39950 4200 2000 6200 1 0x0100] Pad[-6700 35650 -6700 39950 4200 2000 6200 2 0x0100] Pad[0 35650 0 39950 4200 2000 6200 3 0x0100] Pad[6700 35650 6700 39950 4200 2000 6200 4 0x0100] Pad[13400 35650 13400 39950 4200 2000 6200 5 0x0100] Pad[-2650 0 2650 0 27500 2000 29500 6 0x0100] Pad[-17500 -1 17500 -1 7500 2000 9500 6 0x0100] ElementLine[-22750 -15250 22750 -15250 1000] ElementLine[22750 -15250 22750 43550 1000] ElementLine[22750 43550 -22750 43550 1000] ElementLine[-22750 43550 -22750 -15250 1000] ElementArc[-13400 29800 1000 1000 0 360 2000] ) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Thermal overries mask of neighboring via's and holes
On 11/3/06, bumpelo [EMAIL PROTECTED] wrote: Jeff VR wrote: As I was putting the finishing touches on my board and connecting my mounting holes to the GND plane I noticed what seems to me to be an oddity. I had a neighboring via that was appropriately clearing the GND plane polygon and meeting the DRC clearances. When I added the thermal to the mounting hole one of the thermal fingers went into the mask of the via. I think I'm using the right terminology? This happened again with a pin of one of my connectors. I didn't get an warnings after key o about shorts between the Net and GND? Should I create an example schematic? I'm using version 20050609. I realize this is an older version but I'm in a hurry to get my board done before doing a clean install from the CVS trunk or latest release. This bug was fixed with the polygon clipping code added recently. Only the current CVS code has this bug fixed. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Ok, Thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Symbol with 20 pins for a module of 40 connections
Hello, I'm trying to create a gschem symbol for one of my modules. It's connecting primarily with a surface mount connector that receives the pins from the module. The pins from the module will touch the pcb before the module is fully down on the connector so I added holes to allow them to pass through. To make the board a little cheaper I made the holes pins int the footprint and I just as well connect the pin hole to the appropriate pad so someday I could decide to leave off the surface mount connector all together. My visible schematic pins get assigned to pads of the footprint. The trick is I want to add the invisible pins that get associated with the paired visible pin. I know how to implicitly tie a pin to a net but the netname(net?) for my explicit pins gets overridden when I run gchem2pcb thus breaking my connection between my pad and pin. This is hard to explain let me try a visual. I want to connect each of these pairs. My footprint has 20 pads and 20 pins with the following numbering. Again the primary objective is to connect each pair within the symbol that represents this module and only have 20 pins visible on the schematic. Pad Pin 121 222 323 424 525 626 727 ... ... 20 40 I tried assigning pin 1 the same netname as pin 21 but I think when I convert the schematic to pcb it overrides that attribute with the netname from the schematic thus breaking the connection in the symbol between pin 1 and 21. Of course I could just add the 20 extra explicit pins to my symbol and then draw the nets on the schematic that connect each pair but this seems like clutter that the tools will allow me to avoid if I just new how to do it. Jeff VR ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Symbol with 20 pins for a module of 40 connections
I am not quite sure of the question so I hope this helps. You can have pins and pads in a footprint with the same the pin number and they will connect. In the footprint below I overlay pads (on component and solder side) with pins. (* jcl *) Element[0x0 DIP-8-300 0 0 -21000 -26500 0 100 0x0] ( Pad[-16500 -15000 -13500 -15000 6000 2000 8000 1 0x0800] Pad[-16500 -15000 -13500 -15000 6000 2000 8000 1 0x0880] Pin[-15000 -15000 6000 2000 8000 3500 1 0x01] Pad[-16500 -5000 -13500 -5000 6000 2000 8000 2 0x0800] Pad[-16500 -5000 -13500 -5000 6000 2000 8000 2 0x0880] Pin[-15000 -5000 6000 2000 8000 3500 2 0x01] Pad[-16500 5000 -13500 5000 6000 2000 8000 3 0x0800] Pad[-16500 5000 -13500 5000 6000 2000 8000 3 0x0880] Pin[-15000 5000 6000 2000 8000 3500 3 0x01] Pad[-16500 15000 -13500 15000 6000 2000 8000 4 0x0800] Pad[-16500 15000 -13500 15000 6000 2000 8000 4 0x0880] Pin[-15000 15000 6000 2000 8000 3500 4 0x01] Pad[13500 15000 16500 15000 6000 2000 8000 5 0x0800] Pad[13500 15000 16500 15000 6000 2000 8000 5 0x0880] Pin[15000 15000 6000 2000 8000 3500 5 0x01] Pad[13500 5000 16500 5000 6000 2000 8000 6 0x0800] Pad[13500 5000 16500 5000 6000 2000 8000 6 0x0880] Pin[15000 5000 6000 2000 8000 3500 6 0x01] Pad[13500 -5000 16500 -5000 6000 2000 8000 7 0x0800] Pad[13500 -5000 16500 -5000 6000 2000 8000 7 0x0880] Pin[15000 -5000 6000 2000 8000 3500 7 0x01] Pad[13500 -15000 16500 -15000 6000 2000 8000 8 0x0800] Pad[13500 -15000 16500 -15000 6000 2000 8000 8 0x0880] Pin[15000 -15000 6000 2000 8000 3500 8 0x01] ElementLine[-21000 -19500 -21000 19500 1000] ElementLine[-21000 19500 21000 19500 1000] ElementLine[21000 19500 21000 -19500 1000] ElementLine[21000 -19500 5250 -19500 1000] ElementLine[5250 -19500 0 -14250 1000] ElementLine[0 -14250 -5250 -19500 1000] ElementLine[-5250 -19500 -21000 -19500 1000] ) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user That's a very interesting way to do it. One problem I think that would cause is when the board went through the oven to much of the solder (paste) would flow into the hole and the surface mount pads wouldn't make a good connection. I would like to keep solder mask around the hole to ensure that the solder paste stays on the pad and out of the hole. The pins will get soldered to the holes when it goes through the wave. Here is what I have so far. Please excuse the mark not being in the center. It was one of the first footprints I created. Element[308000 53000 -5000 -15000 0 100 ] ( Pad[-2269 -94 4621 -94 3936 2000 5936 1 1 ] Pad[14463 7780 21353 7780 3936 2000 5936 2 2 ] Pad[-2269 15654 4621 15654 3936 2000 5936 3 3 ] Pad[14463 23528 21353 23528 3936 2000 5936 4 4 ] Pad[-2269 31402 4621 31402 3936 2000 5936 5 5 ] Pad[14463 39275 21353 39275 3936 2000 5936 6 6 ] Pad[-2269 47149 4621 47149 3936 2000 5936 7 7 ] Pad[14463 55023 21353 55023 3936 2000 5936 8 8 ] Pad[-2269 62897 4621 62897 3936 2000 5936 9 9 ] Pad[14463 70772 21353 70772 3936 2000 5936 10 10 ] Pad[101063 70772 107953 70772 3936 2000 5936 11 11 ] Pad[84331 62897 91221 62897 3936 2000 5936 12 12 ] Pad[101063 55023 107953 55023 3936 2000 5936 13 13 ] Pad[84331 47149 91221 47149 3936 2000 5936 14 14 ] Pad[101063 39275 107953 39275 3936 2000 5936 15 15 ] Pad[84331 31402 91221 31402 3936 2000 5936 16 16 ] Pad[101063 23528 107953 23528 3936 2000 5936 17 17 ] Pad[84331 15654 91221 15654 3936 2000 5936 18 18 ] Pad[101063 7780 107953 7780 3936 2000 5936 19 19 ] Pad[84331 -94 91221 -94 3936 2000 5936 20 20 ] Pin[9542 -94 4300 1600 5900 2500 1 1 pin] Pin[9542 7780 4300 1600 5900 2500 2 2 pin] Pin[9542 15654 4300 1600 5900 2500 3 3 pin] Pin[9542 23528 4300 1600 5900 2500 4 4 pin] Pin[9542 31402 4300 1600 5900 2500 5 5 pin] Pin[9542 39275 4300 1600 5900 2500 6 6 pin] Pin[9542 47149 4300 1600 5900 2500 7 7 pin] Pin[9542 55023 4300 1600 5900 2500 8 8 pin] Pin[9542 62897 4300 1600 5900 2500 9 9 pin] Pin[9542 70772 4300 1600 5900 2500 10 10 pin] Pin[96142 -94 4300 1600 5900 2500 11 11 pin] Pin[96142 7780 4300 1600 5900 2500 12 12 pin] Pin[96142 15654 4300 1600 5900 2500 13 13 pin] Pin[96142 23528 4300 1600 5900 2500 14 14 pin] Pin[96142 31402 4300 1600 5900 2500 15 15 pin] Pin[96142 39275 4300 1600 5900 2500 16 16 pin] Pin[96142 47149 4300 1600 5900 2500 17 17 pin] Pin[96142 55023 4300 1600 5900 2500 18 18 pin] Pin[96142 62897 4300 1600 5900 2500 19 19 pin] Pin[96142 70772 4300 1600 5900 2500 20 20 pin] )
Re: gEDA-user: Symbol with 20 pins for a module of 40 connections
[jg] I made a suggestion of how to change it here. See if it's what you thought... solid connection that you don't have to layout each time... See pin/pad one and two. JG See pin/pad one and two. The solid connection would do the trick and connect the pad and hole but I see one problem with this. Pads are going to remove the solder mask and unlike a trace the melted paste (solder) will want to follow the trace (pad) into the hole. Maybe I should just add the holes as pins onto the schematic symbol so I can make the connection with traces or lines. I noticed on my footprint I'm going to have to modify my pad slightly further away from the pins in order to get an effective mask between the two. JVR ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
Is you soldermask clear enough? I'm not sure. I haven't ordered my boards yet. My assembler requires the fiducial to not have the soldermask so the vision equipment is sure to get an accurate reading. Does this need to be a feature? I'm not an expert in PCB layout tools but given the importance of a good fiducial it seems worthy of some development time. Thanks, Jeff John Griessen wrote: I just tried making a rectangle of solder mask -- that's out. Jeff VR wrote: is their a way to get PCB to not put paste on a pad so I can go back to having a fiducial on one side of the board? This is in the manual: Pad [rX1 rY1 rX2 rY2 Thickness Clearance Mask Name Number SFlags] Pad (rX1 rY1 rX2 rY2 Thickness Clearance Mask Name Number NFlags) Pad (aX1 aY1 aX2 aY2 Thickness Name Number NFlags) Pad (aX1 aY1 aX2 aY2 Thickness Name NFlags) © rX1 rY1 rX2 rY2 Coordinates of the endpoints of the pad, relative to the element’s mark. Note that the copper extends beyond these coordinates by half the thickness. To make a square or round pad, specify the same coordinate twice. aX1 aY1 aX2 aY2 Same, but absolute coordinates of the endpoints of the pad. Thickness width of the pad. Clearance add to thickness to get clearance width. Mask width of solder mask opening. Name name of pin Number number of pin SFlags symbolic or numerical flags NFlags numerical flags only Can you look at your element file for the fiducial and change the mask flag and see what happens? This would give solder mask no opening, so fiducial covered with and also fiducial no stencil opening, so not pasted on... Is you soldermask clear enough? Does this need to be a feature? John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gPCB Polygon Best Practices
I spent the past few month becoming familiar with PCB and after finishing my schematic in gschem I'm ready to start the layout. Hooray! I've got a fairly good handle on the basics but there are few areas that I need a little assistance/guidance. The first is getting polygons and lines to play nicely together. My plan is to try and get my design on a 2 layer board. I've spent a lot of time arranging components to make routing as painless as possible. If I can get away with 2 layers I want a GND plane on the bottom layer which will be split up by traces that just couldn't fit on the components side of the board. So I did some practicing and drew a line for on the solder side of the board. Afterwards I drew a large rectangle(polygon) on the solder side when I had GND_SLDR chosen . I then figured out that keyj enforced the clearances around the line and nicely removed the GND polygon from the trace. Problems/Questions: 1. Even after the polygon was cleared from the trace the rat's nest was claiming that the net associated with the trace on solder side was shorting with GND??? I remove the trace and the error goes away...if I leave the trace and remvoe the GND plane the error goes away. How do I figure out what is wrong when visually the GND polygon is clearing the net? 2. Should I draw the GND plane at the beginning or should it be the last step? 3. I have unplated holes on one of my symbols that is enforcing a clearance on the component side but not on the Solder side. After I drew polygon associated with GND_SLDER I get warnings about a polygon to close to the holes. Why is there not a clearance on the Solder side of the board enforced for nonplated holes? How do I get this clearance around the holes to work? 4. Layer assignments. I understand that PCB goes up to 8 layers. In the preferences there is up to 8 groups and 8 different buttons two of which are unassigned by default. If I changed my design to a 4 layer design with the following configuration: Bottom (Layer 4): Signal and components Middle (Layer 3): GND Middle (Layer 2): VCC: 3.3, 5, and 12 Top (Layer 1): Signal and components How would I configure the groups and Y axis buttons in PCB layer preferences to acheive the results above? I saw in the info tab an example but I don't think it's exactly what I'm after. Any assitance is greatly appreciated. Thanks Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
DJ Delorie wrote: Tips like this really help cut down the learning curve. The curve would be shorter if it just didn't do that, of course. Sure. As a newbie I didn't realize that a small grid spacing would make operations down the road more difficult. While exploring this problem I was also trying to find a different way to set the clear flag. For instance if I draw the polygon over a lot of traces at the end of the routing phase there's probably a handy way to activate the polygon clearance (correct terminology?) for all the traces in that group. I found a command in the manual called ChangeJoin( SelectedItems). When I performed a select all and issued the command nothing seemed to happen. Shouldn't this command perform the same function as key j? So if I'm understanding this correctly let me re-summarize, inserting a few more questions as we go. The actual number of manufactured layers is determined by the number of groups in use. Mostly. Actually, it's determined by how many of those groups you send to the FAB :-) For example, I might add a few groups (as individual layers) for other purposes, then just omit those files when I send them off. PCB produces one gerber (CAM) file per layer group. It's up to you to send the right ones to the fab. The buttons labeled layers in PCB is actually associated copper. Think drawing layers. A layer group is the closest analog to copper layer. Each group of copper [drawing layer] be assigned different colors to help visualize the purpose of each set. Yes. How do you communicate to the board house which group(manufactured layer) is the top or layer 1(top), 2,3, bottom? Perhaps it's not so much that there is a top an bottom as it is which copper is grouped with each other. In nearly all cases, you have to tell them which is which via a README or a web form. When you export gerbers, it names the component-side one and the solder-side ones appropriately, with the remaining copper layers being numbered. It's up to you to rename them, rearrange them, document them, whatever, to tell the fab shop which is whick. The exceptions are companies like PCB-Pool, which accept GC-Prevue format, which allows you to import the gerbers and arrange and tag them appropriately, then send the whole project to them as a single file. Note that PCB emits one gerber (or postscript print) for each layer *group*, not for each *layer*. Is their a way to assign a PCB layer or set of copper to a specific net? So for instance my GND plane or polygon would be assigned to the GND net. Draw the polygon and tie it into the net with a thermal. PCB should figure the rest out from that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Thanks, that clears things up. I really appreciate the patience as I get up to speed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Trouble with Newlib footprint treaded as M4
When I use the newlib type footprint, TSSOP-65P-640L1-20N, Luciani made to my 74HC245 schematic symbol I have problems generating a netlist and pcb. I've been working with this problem for a couple of days trying to find out why this element is being treated as an M4 footprint. Based on the error message this is what I believe is happening. When I run gsch2pcb it generates the following error: stdin:58: /usr/bin/m4: Bad expression in eval: /2. If I let it keep running it will eventually print to the console /bin/sh: line 1: 21526 Killed/usr/bin/m4 -d -I. -I/usr/share/pcb/m4 -I /etc/pcb -I$HOME/.pcb -I. /usr/share/pcb/m4/common.m4 - caspian.pcb before finishing the rest of the schematic. I'm looking for some help in debugging this problem. Is there an intermediate step I can run to try and figure out if the problem is with the footprint or my schematic? What triggers the m4 library to kick in? Command I'm executing: $gsch2pcb project --use-files Contents of project: elements-dir ~/projects/gaf/pcb-elements elements-dir ~/projects/gaf/pcb-elements/luciani schematics caspian_1.sch caspian_2.sch output-name caspian The package: http://www.luciani.org/geda/pcb/footprints/TSSOP-65P-640L1-20N Thanks, Jeff VR Element[0x0 TSSOP-65P-640L1-20N 0 0 -7267 -18795 0 100 0x0] ( Pad[-12185 -11515 -9467 -11515 1614 2000 3614 1 0x0100] Pad[-12185 -8956 -9467 -8956 1614 2000 3614 2 0x0100] Pad[-12185 -6397 -9467 -6397 1614 2000 3614 3 0x0100] Pad[-12185 -3838 -9467 -3838 1614 2000 3614 4 0x0100] Pad[-12185 -1279 -9467 -1279 1614 2000 3614 5 0x0100] Pad[-12185 1279 -9467 1279 1614 2000 3614 6 0x0100] Pad[-12185 3838 -9467 3838 1614 2000 3614 7 0x0100] Pad[-12185 6397 -9467 6397 1614 2000 3614 8 0x0100] Pad[-12185 8956 -9467 8956 1614 2000 3614 9 0x0100] Pad[-12185 11515 -9467 11515 1614 2000 3614 10 0x0100] Pad[9467 11515 12185 11515 1614 2000 3614 11 0x0100] Pad[9467 8956 12185 8956 1614 2000 3614 12 0x0100] Pad[9467 6397 12185 6397 1614 2000 3614 13 0x0100] Pad[9467 3838 12185 3838 1614 2000 3614 14 0x0100] Pad[9467 1279 12185 1279 1614 2000 3614 15 0x0100] Pad[9467 -1279 12185 -1279 1614 2000 3614 16 0x0100] Pad[9467 -3838 12185 -3838 1614 2000 3614 17 0x0100] Pad[9467 -6397 12185 -6397 1614 2000 3614 18 0x0100] Pad[9467 -8956 12185 -8956 1614 2000 3614 19 0x0100] Pad[9467 -11515 12185 -11515 1614 2000 3614 20 0x0100] ElementLine[-7267 12795 -7267 -12795 1000] ElementLine[-7267 -12795 7267 -12795 1000] ElementLine[7267 -12795 7267 12795 1000] ElementLine[7267 12795 -7267 12795 1000] ElementLine[-7267 -12295 -6767 -12795 1000] ElementLine[-7267 -11295 -5767 -12795 1000] ElementLine[-7267 -10295 -4767 -12795 1000] ) elements-dir ~/projects/gaf/pcb-elements elements-dir ~/projects/gaf/pcb-elements/luciani schematics caspian_1.sch caspian_2.sch output-name caspian ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: AT90S2313
Ramakrishnan Muthukrishnan wrote: Hi, I am a geda newbie. I am trying to design a circuit and draw the schematics using gschem. The circuit uses AT90S2313 micro for which the symbol is available under micro. But I cannot see the pin 10, Vdd and pin 20 Vcc on it. Is there any reason for not putting them in there or is there anything I need to do to unhide them? I am sorry for the stupid question. :-( I've been working on my first design as well and had a similar question when using the ATMEG64 micro. What I found with many of the IC's I use in the library is that they were created with these pins assigned by default to the Vcc and Vdd nets. Since these pins are assigned by default the author, in an effort to reduce clutter on the symbol, didn't draw these pins and made the net attributes invisible. If you select the symbol, right click and go down into the symbol you can view these attributes. Then press 'e n' (Show invisible) followed by 'v e' (View Extents) you should see that the symbol has net attributes which assign these pins to the power and ground nets. Be sure to go up out of the symbol without saving. Someone else may be able to suggest an easier way to view this information. In my case I wanted to add some decoupling caps to the supply's of these devices so I modified the symbol to include these pins and deleted the default net assignments. Hope this helps, Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fiducial
joeft wrote: Dan's suggestions are similar to what I've received from one of our suppliers: Use a .050 diameter copper circle with .100 solder mask opening in 4 places. Making the part as a pin may include a drilled hole (which you don't want). What I did was make a part with one surface mount pad of the proper size. Be sure to place it on both sides of the board - they'll need it to load parts on both sides. Joe Dan McMahill wrote: Jeff VR wrote: I'm working on laying out my first PCB board. I understand that the pick and place machine uses reference points on the board called fiducials when placing my components. I'm planning on having my board assembled by a MyData 12 machine. So how do I incorporate this symbol and element on my PCB. I found a similar question on this mailing list dated a couple of years ago but it had no response. I searched the schematic symbol library and footprint libraries and I couldn't find anything obviouse. A little guidance from a seasoned PCB deasigner would be greatly appreciated. Thanks, Jeff I suggest creating a schematic element and a footprint for a fiducial and instantiate it in your schematic. I can't comment on that particular machine. In general though, you should use a minimum of 2 global fiducials and preferably 3. With 2 you can correct for x,y offsets and rotational offsets. With 3 you can correct for some nonlinear distortions like scaling, stretch, and twist. This is paraphrasing part of the IPC-7351 document. By global, I mean they're not for some particular part on the board. You should place these at 3 of the 4 board corners. The document recomments that you locate 2 diagonally across the board and the 3rd one has one x cooridinate and 1 y coordinate in common with the others. For example (X1, Y1), (X2, Y2), (X1, Y2) You may or may not need local fiducials near some high pin count fine pitch parts. If you do, place 2 of them diagonally across from each other just outside the package corners. The prefered shape and size is a filled circle of copper with solder mask completely removed. The diameter should be 1.0 mm. The diameter area free of soldermask should be 2x the diameter of the fiducial. I'd probably make an element with 1 pin to put in schematic and layout. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Ok, well I haven't created any parts yet which has increased my productivity as a person new to both the tools and PCB design. I'll follow the published documentation which I recall had some discussion of fiducials. As a newbie I'm tempted to ask if creating a fiducial is so incredibly simple that it doesn't make sense to include it in the standard libraries? Has anyone posted fiducials that I could use as a starting reference? Thanks a lot for your assistance guys. Jeff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
