Re: gEDA-user: Perl
On 05/27/2011 11:54 AM, DJ Delorie wrote: This is more anecdotal than anything else... I'm a Perl fan myself. (shudder) Javascript! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: request for newbie help
i've tried to find what i want in the docs without luck. (i've read eric raymond's and rick moen's notes re asking questions.) my background: i've worked as an electronic bench tech and have held several different kinds of jobs in the computer industry (sys adm, programmer/analyst, documenter for developer products (APIs and such) and data centers, taught intros to C, perl, python, and other languages). product and platform i've got geda 1.6.1.2 on ubuntu linux 10.04 (laptop) and dragged three simple components with connections into a circuit (seems the wires are properly connected), a battery, a potentiometer, and a voltmeter: battery + to top of pot, bottom of pot to battery -, voltmeter between wiper and bottom of pot. problem as i see it what i want to do is to activate the circuit by setting the battery to some voltage value and the pot to some resistance value and read the voltage difference between the wiper and the bottom of the pot. here are points of detail: * it's possible the software does not allow such emulation. does it? * i cannot find a tutorial that presents something close enough that i can infer out of it. * i cannot make sense of some of the important terms in the docs that i've found (extants, attributes...). * the help menu shows choices for gEDA docs, but no local help files appear (i guessed that maybe the choice activated my browser, but no). * the geda web site ( http://geda.seul.org ) mentions ways to contribute but without apparent links that let me access contributors (i believe i can help with user docs and possibly be a reasonably useful tester). first-cut attempt to communicate after some effort i've found this (and other) mailing list. i'm trying this list first before disturbing the flow of the developer's list (which i'm willing to do, but after reality checking for community expectations and good manners). if anyone can help me with the above points i'll be grateful. thanks, jim ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: git HEAD PCB now supports user-defined holes in polygons
Kai-Martin Knaak wrote: On Tue, 08 Jun 2010 10:51:10 -0400, Jim wrote: Oh, please make that change configurable without recompiling! It is already configurable without recompiling. This is how: 1) locate the file gpcb-menu.res on your box. 2) copy the file to $HOME/.pcb 3) edit to your needs, save 4) on start-up, pcb will read this localised copy. This will overwrite whatever settings were made by the system gpcb-menu.res ---)kaimartin(--- Thanks, that'll help a lot if they do change default behavior. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: git HEAD PCB now supports user-defined holes in polygons
Kai-Martin Knaak wrote: On Mon, 07 Jun 2010 02:10:57 +0100, Peter Clifton wrote: This is a file format bump, but remains backward compatible with old layouts. I get multiple warnings unknown flag `polygonholemode' if I open a new file with the old pcb. I assume, these are benign. I've now rebased my usual branches on top of this (mainly required work for the pour object branches), I just refetched the before_pours branch. It compiled and installed just fine. First notes: * You moved zoom to [ctrl-wheel]. I know, that this is in line with the way other major gnome applications like inkscape handle zoom. However, gschem and gerbv zoom with no modifier by default. I'd strongly vote for a consistent behaviour across geda applications. Oh, please make that change configurable without recompiling! It's really irritating (to me) to have to use two hands to do things if it's not absolutely necessary. I'll live without some other feature just to have wheel zoom without a modifier. Thanks for your efforts to make geda a better tool set! I second that! ---)kaimartin(--- Jim ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
kai-martin knaak wrote: Stephan Boettcher wrote: 1) new user makes a board not knowing much about the tools involved 2) default via size is set smaller than default DRC check. But isn't that perfect? When you start a new board it is mandatory to first think about design rules and default via/routing size on your board. When you fail to to so, isn't it reasonable for the DRC to fail as well? Definitely not. Applications should not use this kind of blackmail to enforce whatever work-flow the developers think is good practice. In particular, it should not allow to move on and fail long time after the supposes sloppyness happened. The purpose of default settings is to provide a reasonable working environment without user interaction. Settings that predictably make DRC fail kind of defeat this purpose. ---)kaimartin(--- I agree, if you want to make it mandatory to first think about design rules and default, don't allow any actions until those things are set. Just because I didn't know about the right way doesn't mean I should be punished much later in the process. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
kai-martin knaak wrote: Jim wrote: While we're talking about vias, why is the default via size smaller than the DRC checks for? Everytime I generate a board and forget to reset the via size the vias fail the DRC check. How do you generate your boards in the first place? With gsch2pcb, or by starting pcb with no file? These two ways use different sets of defaults. Unfortunately, the defaults used by gsch2pcb are hard coded somewhere in the source. By contrast, pcb reads the defaults from its config files in ~/.pcb/settings, or ~/.pcb/preferences If you want to improve your work-flow and have pcb set-up to your needs, you may first prepare an empty layout with a call of pcb. Then use gsch2pcb to populate the empty layout with components via the update mechanism. ---)kaimartin(--- Since a beginner at this most likely is following the tutorial and the tutorial uses gsch2pcb, I'd like to think of that method as being the natural way. I understand you can use these tools in a bunch of different ways, but a beginner won't know (most likely) any way except what is taught in the tutorial. That beginner would also not understand that it's important to set the via size as Stefan says. Of course, I'm a beginner and have no idea why a default via size is a bad thing. After all there is a default board size and I'm fairly certain almost no one leaves this setting alone. Anyway, it didn't make a lot of sense to have a checker complain about a default setting. But then I fall into the beginner category. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
DJ Delorie wrote: While we're talking about vias, why is the default via size smaller than the DRC checks for? PCB's defaults: via drill: 28 via size: 60 (annulus: 16) DRC min drill: 15 DRC min annulus:10 If you're using something else to generate initial boards (like gsch2pcb), the initial values for everything come from that program, not pcb itself. I don't recommend using gsch2pcb to create an *initial* board (either use pcb to create a blank board before using gsch2pcb, or use pcb's file-import). OK thanks for that info. Maybe someone who knows what they are doing could mention that in the tutorial? Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
Stefan Salewski wrote: On Mon, 2010-05-10 at 08:45 -0400, Jim wrote: Since a beginner at this most likely is following the tutorial and the There are many tutorials, at least more than one. The most recent and fine for beginners is from DJ -- he recommends generating the initial board with PCB, not gsch2pcb. See http://www.delorie.com/pcb/docs/gs/gs.html http://geda.seul.org/wiki/geda:documentation OK I'll look those links over, but if I google for geda tutorial the first link that comes up is: http://www.geda.seul.org/wiki/geda:gsch2pcb_tutorial You have to get to page three to see DJ's tutorial. I'm not arguing with you, I'm just saying that a beginner is likely to do pretty much what I did, which was perform that search. The link takes you to a very reasonable place, right on the geda site. Until one becomes involved with this community one probably won't recognize DJ's valuable contributions. It may be a good idea to somewhere in the geda tutorial, provide links to the others, if it is felt they are superior, or even to show some diversity. My thanks to all on this list that contibute. I can't say I've ever had as much help with any application as I've gotten from this group. You're the best! Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
Stefan Salewski wrote: On Sun, 2010-05-09 at 16:50 +0200, kai-martin knaak wrote: DJ Delorie wrote: The keys change the size of new vias, not the size of existing vias. Jared already told me so ;-) Since I am not the only one who misinterpreted the menu help, how about a little more verbose descriptions: Size of via tool +5 mil Shift+V Size of via tool -5 mil Shift+Ctrl+V Drill of via tool +5 mil Alt+V Drill of via tool -5 mil Shift+Alt+V ---)kaimartin(--- Same misunderstanding for me with key T for text size. I would suggest: Size for new vias +5 mil Shift+V But I always use Route Style dialog in PCB for via size -- never needed size adjustment on the fly. While we're talking about vias, why is the default via size smaller than the DRC checks for? Everytime I generate a board and forget to reset the via size the vias fail the DRC check. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
Stefan Salewski wrote: On Thu, 2010-05-06 at 20:53 -0400, someone who called himself Jim wrote: I'm not sure I'm saying that right. What I've done is generate a set of pcb edge fingers using elongated pads, How did you make the fingers? Just a guess, you may try to exchange starting and ending points of the pads? Manually with an editor. I tried exchanging, no help. however when I run pcb, the ratsnest connects to the far end of the fingers, i. e. the part that goes into the socket. Why do you care? Ratsnet is only a visible help for you while doing the layout, it has no other meaning. It looked like the autorouter was attaching to the wrong end of the fingers! I started over and removed some redundant connections and it's looking better. That gives me no end of grief trying to route the board. I've attempted to attach an image showing the problem. Thanks, Jim. Of course this may be something which the developers may improve -- access to your footprint and pcb data may be helpful. I've moved on. It's not probably worth their time and effort. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
Stefan Salewski wrote: On Fri, 2010-05-07 at 13:53 -0400, Jim wrote: Stefan Salewski wrote: Manually with an editor. I tried exchanging, no help. Interesting, and surprising for me. It looked like the autorouter was attaching to the wrong end of the fingers! Please note, ratsnest is not autorouter! In your first post you refer to ratsnest only -- this are simple straight lines indicating which copper areas should be connected, manually or with autorouter. Ratsnest lines often show the shortest connection (if you press O key for optimize), but this may not work in all cases. My guess was that ratsnest may point only to one arbitrary endpoint of a pad, not to the endpoint which results in shortest ratsnest line. But this in only a visible problem. You can connect your traces manually where ever you want to the pad. And I am sure that the autorouters will not care about rastnets at all. Yes, but when there are multiple lines laying on top of one another, it's hard to figure out where they go without refering back to the schematic. :) Anyway it's now a moot point. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
my...@iae.nl wrote: If you hover above a pad and hit the F key (Find Connections) all connections that are attached to that pad will be marked. It helps me to find out which pad is connected to what without the use of the schematic. I hope I understand your problem correctly. Robert. Yes, that's helpful. I like the tools but it's tricks like this one that frustrate me. I need to print out a cheat sheet for all the keys. Some of which don't work as advertised. E. g. Alt-V and Shift-V are supposed to change via drill sizes and via sized according to info-key bindings, but they don't. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How do I mark the connection point on a pad?
I'm not sure I'm saying that right. What I've done is generate a set of pcb edge fingers using elongated pads, however when I run pcb, the ratsnest connects to the far end of the fingers, i. e. the part that goes into the socket. That gives me no end of grief trying to route the board. I've attempted to attach an image showing the problem. Thanks, Jim. inline: pcb3.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Database on symbols, footprints and other (was Re: gattrib)
Armin Faltl wrote: Hi all, esp. authors of gpart, an attempt to run autoconf in gparts gives me: autoconf configure.ac:2: error: possibly undefined macro: AM_INIT_AUTOMAKE If this token and others are legitimate, please use m4_pattern_allow. See the Autoconf documentation. configure.ac:9: error: possibly undefined macro: AM_PROG_LIBTOOL The documentation of autoconf is incredibly long - I found m4_pattern_allow() but still don't know what to do. Trying to run automake gives errors as well. If you could tell me the correct setup for autoconf/automake or provide a working configure I'll have a next try. Regards, Armin You have to install libtool. Search for libtool via your distro yum or apt-cache for RPM or DEB distros. I have no idea how to do it for Windows. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Database on symbols, footprints and other (was Re: gattrib)
Armin Faltl wrote: Another strange thing with gparts: in 'sql/mysql/create-basic.sql' one finds: cut ... CREATE TABLE Symbol ( SymbolIDINTEGER UNSIGNED NOT NULL AUTO_INCREMENT, SymbolPath VARCHAR(500) NOT NULL, DeviceIDINTEGER UNSIGNED NOT NULL, PRIMARY KEY ( SymbolID ), FOREIGN KEY ( DeviceID ) REFERENCES Device, UNIQUE ( SymbolPath ) ); -- Create a table for symbol details (comments). -- -- Each symbol may have many comments. -- CREATE TABLE SymbolDetail ( SymbolID INTEGER UNSIGNED NOT NULL AUTO_INCREMENT, DetailVARCHAR(500) NOT NULL, FOREIGN KEY ( SymbolID ) REFERENCES Symbol, UNIQUE ( SymbolID, Detail ) ); ... cut - what is the purpose of auto-increment on a foreign key? Auto-increment would probably be the default behavior, but as it will break the foreign key constraint this, same as not assigning anything will prevent creation of that row. Actually it is worse (at least with PostgreSQL): the autoincrement counter falls behind, if the default behavior is not used. It can be assumed, that the SymbolID's from Symbol will form a gapless sequence. If for some reason, the SymbolID gets missed during creation of a SymbolDetail, the AUTO_INCREMENT will produce an integer that is probably low, because this is a bug. And this will happily attach the detail to a random symbol, instead of raising an exception. Wrong? Armin It's not impossible that mysql would quietly ignore an autoincrement attribute for a foreign key. I agree it looks wrong. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A little puzzled about the purpose of gschem
John Doty wrote: On Apr 28, 2010, at 9:41 PM, Dave McGuire wrote: Very rare?! I see 741s everywhere. WTF? Different worlds. You make my point. Why is anybody using anything so crummy in the 21st century? Perhaps, like me they have a pile of them. I'm staring at about 25 of them right now. ;) Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Why did some of my pins in pcb turn orange?
The rule checker seems to think all is OK. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Why did some of my pins in pcb turn orange?
Duncan Drennan wrote: The rule checker seems to think all is OK. It usually indicates a short - pressing o and having a look at the log window should tell you what is going on. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Ah! Thanks, I accidently moved a part over another and didn't see it. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: xgsch2pcb acts different from gsch2pcb
If I take my project.rc file and copy it to project.gsch2pcb and change the output-name to something else so I don't clobber my ongoing development and run xgsch2pcb, pcb then gives me a bunch of errors like: Warning! Net +3.3V is shorted to net +5V Warning! net +3.3V is shorted to net Vcc Warning! net +3.3V is shorted to net +5V Warning! net +3.3V is shorted to net GND Warning! net +3.3V is shorted to net +12V Warning! net +3.3V is shorted to net unnamed_net8 Those are just a few. However if I use gsch2pcb and run pcb manually, I get no errors and all the rats seem to be connected OK. I gitted the latest copy and recompiled xgsch2pcb into /usr/local/bin and it demonstrated the same wierd behavior. Any ideas? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: xgsch2pcb acts different from gsch2pcb
Peter Clifton wrote: On Sat, 2010-04-24 at 06:04 -0400, Jim wrote: If I take my project.rc file and copy it to project.gsch2pcb and change the output-name to something else so I don't clobber my ongoing development and run xgsch2pcb, pcb then gives me a bunch of errors Did you copy your board as well, or are you starting from a blank one? Starting from a schematic only. I let it build the board, netlist, etc. Try hitting O after opening the board you run gsch2pcb manually on.. does it have any messages then? Log: Can't add rat lines because no netlist is loaded. Can't add rat lines because no netlist is loaded. Importing PCB netlist /home/jwl/gaf/ether/etherboard.net 65 rat lines remaining The first two lines were generated because I had not loaded the netlist yet. O apparently wants a netlist to build rats from :) Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA programming
Ouabache Designworks wrote: Oh bull. Lots of IDEs (and just plain text editors) do that just fine. There's *nothing* about software development of any kind that is unique to or first appeared in Microsoft Windows. -Dave - Other than Bob and Clippy is there anything of any kind that is unique to or first appeared in Microsoft Windows? John Eaton I have yet to see anyone demonstrate the blue screen of death on Linux. Black and white, yes but blue was unique. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB configuration skin
Dave McGuire wrote: On Apr 23, 2010, at 12:23 PM, Larry Doolittle wrote: Lots of people speak Esperanto. It's all relative. Compared to, say, Spanish? I'm one of them. Multaj homoj parolas Esperanton. Mi estas unu el ili. Very cool. Translation? Come on, Dave. Pattern match. Multaj - multiple(many) homoj - homo(man) (and at this point you figure a j suffix might mean plural) parolas - like French parlez (talk) Esparanton - not sure about the n suffix The n suffix means it's an objective noun (vs a subjective) You're right the j makes it plural. So a plural object would end with a jn. Really it would end with an ojn because all nouns ( I think) end in o. It's a very regular language. Mi - My, Me estas - like latin est, spanish es: to be unu - latin unu, game/spanish uno, one el - spanish ili - wouldn't have guessed in isolation, but clearly them - Larry [who has never spoken a word of Esperanto in his life] Yeah ok, I see it, I was being lazy. ;) It really is a simple language! -Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: im new, soy nuevo
Armin Faltl wrote: Still, thanks for all the answers. I hope I don't stamp myself as troll with this last post of mine on the subject. Btw, where can I learn Jive? Start here: http://www.youtube.com/watch?v=0bhTxvzrUFo Armin HTH Jim ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB template?
I am designing a couple of boards (if successful more than 2) that have the same form factor. That is they are the same physical size and both (all) have fingers to plug into a card slot on a mother board. So I don't have to worry about registration of the fingers each time I come up with a new board, is there a way I can define a PCB template that includes the fingers? That seems like it would be hard to do since the fingers are a connector on the schematic and wouldn't line up right without some tricks. The other option might be if there were a command line to PCB that I could execute to tell it put pin 1 of conn1 at X, Y. Or would it be best to have a template that has a target in silk to line the fingers up? I'm open to the simplest solution. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB template?
Jim wrote: I am designing a couple of boards (if successful more than 2) that have the same form factor. That is they are the same physical size and both (all) have fingers to plug into a card slot on a mother board. So I don't have to worry about registration of the fingers each time I come up with a new board, is there a way I can define a PCB template that includes the fingers? That seems like it would be hard to do since the fingers are a connector on the schematic and wouldn't line up right without some tricks. The other option might be if there were a command line to PCB that I could execute to tell it put pin 1 of conn1 at X, Y. Or would it be best to have a template that has a target in silk to line the fingers up? I'm open to the simplest solution. DJ Delorie wrote: Create the PCB with the connector element pre-placed, using the grid and crosshairs to move it to the right position. Save that file. For each board you do, copy that file to the new *.pcb name and start editing... Ethan Swint wrote: Make a board with only the connector loaded, at the desired position. When you would like to lay out a new board, copy rename the template file, renumber the connector, then run gschem2pcb. It will make an additional .pcb file that you can then load layout data from file. -Ethan _ Vanessa Ezekowitz wrote: Since this template is a plug-in card, it made me think of how hybrid integrated circuits are generally treated as single components in many situations. If your template is simple enough, maybe you could create a custom footprint out of it. PCB's buffer-assisted footprint creation method may be useful here, but depending on what all is in your template, it might be easier to just edit (a backup copy of) your layout file with a text editor, and manually turn it into a footprint file. Then you could just place a connector in your schematic file (Gschem I assume) and assign this new footprint to it. When you import it, the new board template would be brought into the empty layout along with the rest of your components, and you would treat it like one. This means you can't make major alterations to the form factor of the device, but you said you wanted to keep that fixed, so that's probably OK. Thank you Gentlemen and Lady!(See I didn't blow it this time) I'll give these suggestions a try and see what works best for me. This list has to have the best support people I've been associated with. A big thanks to you all. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: input/output ports gschem
Felipe De la Puente Christen wrote: Hi, I did a design using input, output, and io ports based on the input-2.sym available in the library. I thought that the net attribute would make the net between the component's pin and the port to be named the same as the port's net attribute, but I was wrong and it's still necessary to put a netname on the nets involved to make the logical connection at the other side(another port + net + component's set). So the question(suggested by DJ) is: How are these input/output graphical ports supposed to work? Are they merely graphic things, or does that net attribute have a special/useful function? Thank you very much in advance. Best Regards, Felipe. I think they are just connections. That is, they are just a way to connect nets or wire things together. The way I use them is to have an Output on one schematic with the net set to a unique value that is the same as the net on an Input on another schematic. When the netlist is generated the two components (Input and Output) are connected. The net parameter seems to be the most important element. I'm not sure what the netlist value does. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do you grab something reliably in pcb?
DJ Delorie wrote: Settings - Only Names Thank you! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How do you grab something reliably in pcb?
I have yet to figure out the secret to this step. When I'm working in an area that's pretty crowded and I want to move something like the label on a part, I can't seem to figure out where the sweet spot is. Much of the time I a) move the part, b) move a trace, c) start to draw a red box around something, or d) end up with a red x on a part and the only thing I can do is draw red boxes. So can someone give me a hint or two? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OT: I2C pullup resistor location
I'm building a backplane board that will have a processor board (master) and 8 slaves using I2C across the backplane. Is there any advantage to placing the pullup resistors on the end of the backplane farthest from the processor board? I recall installing active termination on the old S-100 bus backplanes to overcome problems with ringing, I think. It's been too long. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA code sprint this coming weekend (April 3rd)
Ales Hvezda wrote: Hi, It's been a while since we had one of these, but this Saturday (April 3rd) there is going to be a gEDA code sprint at my place and on the 'net. Time wise, I'm thinking the usual of 10am to 5pm EDT (or whenever for virtual attendees). For those of you that are located in the Boston area, you are more than welcome to attend in person at my home. Please e-mail me (ahvezdaATseul.org) so that I can get a head count and for the address/directions. For those of you that are not local to New England, you are more than welcome to hang out in irc (irc.seul.org, #geda) and you'll probably get more work done anyways. :-) Thanks, -Ales Can you briefly outline what the purpose of this exercise is for those of us who are somewhat new to gEDA? Or is it one of those things, If you have to ask, you probably aren't interested? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA code sprint this coming weekend (April 3rd)
DJ Delorie wrote: It's a useful mechanism for us erstwhile gEDA developers to set aside other projects and spend some quality time concentrating on hacking and improving one or another of the gEDA tools. We'll also spend time discussing recent events affecting the project itself. For example, my goal is to finalize the new schematic importer in PCB. Since I'll be sitting next to Stuart, and he's had some issues with it, we can focus on getting them fixed. I'll have #geda up with everyone else, but not my regular email (unless I go hunting for it - like geda-user messages :) so it's a faster pace than my usual development, with less distraction. BTW - if anyone has NOT tried the new importer, please try it before Saturday and provide feedback! This is your chance to get your fixes/features done :-) DJ _ Thank to you both. So it does appear my latter assumption was true, If you have to ask :) DJ I've not tried the new importer but if you'd provide a pointer to instructions, I'll be glad to give it a try on the 4 boards I have in development now. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Odd behavior with gschem
Peter Clifton wrote: On Fri, 2010-03-26 at 21:11 -0400, Jim wrote: I have no idea what might be interfering with the operation. It's probably important to note that this is an OpenVZ container. I'm going to chalk it up to something to do with that. Sorry for the wasted bandwidth. I'll live with it for now. I'd take bets then it is OpenVZ doing something clever with the selection, perhaps trying (in a futile attempt) to convert it to something Windows would know how to interpret. Perhaps you can try turning off clipboard sharing (or whatever they call it) between the OpenVZ container and the host OS. I'm not aware of such a thing happening. Openvz isn't a hypervisor and as such only allows Linux containers, so MS Windows isn't a consideration. I'm wondering if it's some sort of X deficiency since I'm running via ssh with X forwarding to display GUIs from a virtual system? Anyway, since the right click works, I'm happy. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Odd behavior with gschem
I'm running the default gschem 1.6.? that comes with Ubuntu 9.10. I went in to duplicate a symbol (highlight, copy, paste) and it worked a few times (3 or 4 or 5). Then it stopped working. I could highlight and copy, but the paste selection under edit was greyed out. Am I doing something wrong? Did I fill a buffer? I could save my work and exit and come back in and continue, but eventually the paste would become unavailable again. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Odd behavior with gschem
Peter Clifton wrote: On Fri, 2010-03-26 at 06:24 -0400, Jim wrote: I'm running the default gschem 1.6.? that comes with Ubuntu 9.10. I went in to duplicate a symbol (highlight, copy, paste) and it worked a few times (3 or 4 or 5). Then it stopped working. I could highlight and copy, but the paste selection under edit was greyed out. Am I doing something wrong? Did I fill a buffer? I could save my work and exit and come back in and continue, but eventually the paste would become unavailable again. That is very strange. Although with Ubuntu 9.10, I think your gschem version is likely to be 1.4.3 (checked on packages.ubuntu.com), and that isn't a supported version any more. This said, I'm still interested to know why the problem you've seen is occurring, as the 1.4.x buffer code is still used in the 1.6.x series. gschem 1.6.x now uses the clipboard for copy-paste - meaning you can now transfer schematic elements between gschem windows from different gschem processes. It also means that paste won't work once you've copied something different somewhere else, but I don't think this is what you're seeing. Can you detail some exact steps to reproduce the issue, or is it more random? OK, not random. About says 1.6.1.20100214. Put a symbol on a schematic. Click away from the symbol and then click to select. Go to the Edit/copy menu. Then click on Edit/paste. Left click somewhere. The part is duplicated. Now repeat. Select nothing then select on of the two parts on the page. Edit/copy. The Edit/paste is now greyed out on my system and I cannot find a way of getting it to come back. The right click Copy seems to work differently, there is no paste option, but I discovered that if you left click the symbol appears and can be dragged. It doesn't seem to have the limit the Edit menu has. I must say I've never used a GUI where the top menu and the right click menus work differently at least with respect to the copy/paste functions. Not to say this isn't a nice feature (right click) but I found it quite by accident. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Odd behavior with gschem
Peter Clifton wrote: On Fri, 2010-03-26 at 13:03 -0400, Jim wrote: And once the paste is greyed out, a cut selection cannot be recalled (pasted) as far as I can tell. I wonder if some other program on your system is messing with the selection. I've not been able to reproduce it on my box with Ubuntu Lucid. It is odd that you have gEDA 1.6.1 from an Ubuntu Karmic install. (It would be present in Lucid though). I would have wondered if you'd got it from my PPA, but I recall only 1.6.0 being available there. ii geda-gschem 1:1.6.1-1 GPL EDA -- Electronics design software (sche cat /etc/issue Ubuntu lucid (development branch) \n \l Sorry I am running lucid. I have no idea what might be interfering with the operation. It's probably important to note that this is an OpenVZ container. I'm going to chalk it up to something to do with that. Sorry for the wasted bandwidth. I'll live with it for now. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: ten pages of command line options
DJ Delorie wrote: Would anyone answer a series of noobie questions? I wrote it, so I get to answer the noobie questions :-) And if an alien space ship destroys his internet connection, I'll be glad to back him up. Note: It is trivial to write perl scripts that are indecipherable so if you don't understand something don't waste a lot of time trying to figure it out. Just ask. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter: Line constraints
Peter Clifton wrote: Headline summary: git clone git://git.gpleda.org/pcb.git Perhaps the repositories should be easier to find from under the Development page at gpleda.org. Thanks. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
John Griessen wrote: Anthony Blake wrote: On Thu, Mar 18, 2010 at 12:56 PM, Windell H. Oskay wind...@oskay.net wrote: Also, can anyone think of a new name for the toporouter? There is already a commercial tool called the 'toporouter', which I don't want us to be confused with. untangler runtangler ( route untangler) grouter (gnu router) grout grout grout... groroute(gnu re-ripping organic route tool) growroute (gnu re-arranging organic wire router) goroute (gnu organic route tool) routeknot ( route knot want not) greenlight sigroute vinerouter liquidroute streamroute flowroute lamroute (laminar algorithm mapping router) ziptrace curveroute wraproute John There's a man with a lot of time on his hands! Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: if you people want to do it then put up the *cash*
John Griessen wrote: Ales Hvezda wrote: problem with for-pay servers is users are motivated, they help pay for a few months, then no more so any decisions that affect $$ need to account for probably Ales paying for it out of pocket I have absolutely no issues with removing me as a single point of failure, however, if you people want to do it then put up the *cash*, time, and get some buy-in from all people doing the development work. When my friends on the metalartists.org list lost the previous server and I started a mailman server for them they donated money via paypal to get to paid up for a year and a half after just a week. It might not be hard, even with this bunch to get virtual server money. For OpenVZ on Quantact.com servers you'd need to budget $30/month for the level of RAM needed to run mailman. These prices might even drop some as things progress, since some web hosters, (Network Solns), with canned web-app packages (not root accounts), now run at $11/month. I'm good for $20 for server support -- I expect that to go for a years worth after asking the rest of the people that care to contribute. So now the question is Who else will pledge money?. John I have two servers at MSTransactions that seem to work pretty well. For about $100 per year you get a dedicated server. You have to maintain it yourself, no cpanel, but I installed Virtualmin on them and run multiple virtual http hosts. Intel P3 667Mhz 256 MB 20 GB 500 Gb 10 Mbps 1 IPFREE 7.99/mo. *Configure* https://www.hostmds.com/client/cart.php?a=addpid=206 The only catch is the 10 Mbps speed, which might not be enough. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Questions about filling/using large nets/fills.
DJ Delorie wrote: First, make sure auto-enforce DRC is *disabled* so it will let you connect to something outside your net. Second, draw a trace/line out to that rectangle/polygon. Third, use the j key to join the trace/line to the rectangle/polygon. If you happen to have through-pins in that area, the thermal tool is used to connect them together. Thanks, that's excellent information. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Looking for my first fab shop.
Are there any fab shops that would be gentle with a very new, very inexperienced PCB designer? OH and reasonable for a prototype. Last time I laid up a board I used a drafting table and mylar. I may need a bit of handholding as I go along. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Bugmail
Peter Clifton wrote: Please can someone set up a mailing list (or point me at the existing one if there is such a thing) which tracks bugmail from PCB's sourceforge tracker. I see the gEDA and gerbv bugs which appear in their respective bug mailing lists, and I find that is usually a first step towards me being aware about what bugs people are submitting. (Only new bugs create mail for gEDA, not further comments). Or - in my ideal word, can we just dump the crappy sourceforge bug trackers and switch to Launchpad??? (Pretty please). So you are saying you get a email when a bug is opened but not when a change is made? Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Questions about filling/using large nets/fills.
I was playing around with filling in the blank space with copper and thought it made sense to put part of it at ground potential, however I can't seem to run a connection to a rectangle from a ground pin. How's one go about that? The second question is pretty similar, I have to lay out an audio amp circuit and little tiny wires that work well in digital electronics are much less useful for audio. So I want to have some rather large swaths of copper connected to parts. I nice wide ground path makes life in the audio world much easier. I know you can adjust the width of lines for the route styles. Is that the way to do it? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Questions about filling/using large nets/fills.
Peter Clifton wrote: On Sun, 2010-03-07 at 14:06 +, Kai-Martin Knaak wrote: The second question is pretty similar, I have to lay out an audio amp circuit and little tiny wires that work well in digital electronics are much less useful for audio. So I want to have some rather large swaths of copper connected to parts. I nice wide ground path makes life in the audio world much easier. I know you can adjust the width of lines for the route styles. Is that the way to do it? Choose the route style you want to change and click on the header Route Style just below the tool buttons. A dialog pops up, that allows you to set the line width along with several other parameters of the route style. Alternatively, close pcb and edit the line route-styles in $HOME/.pcb/preferences In addition, you can adjust the size of existing tracks with the s and S keyboard short-cuts when hovering over an existing track. (This works with other elements too). When placing tracks, you can adjust the widths with the l and L keyboard short-cuts. You should see the new track sizes listed in the status bar. Ctrl+R over an object gives you a report which will include its current width. If you fancy changing size on a number of selected objects, select them and execute an action. : brings up the command window / entry on the status bar. ChangeSize(selectedlines, 25, mil) or ChangeSize(selectedlines, 2, mm) Whatever.. Thank you both. Do you use the line tool to manually route? What's that ins tool for? It does strange things. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Well the problem is with whatever generates the net list. unnamed_net5R1-1 C3-2 U2-J2_2 Vcc U3-3 C2-2 U1-40 unnamed_net4U2-J1_2 U1-36 unnamed_net3U2-J1_1 U1-35 unnamed_net2U2-J2_3 U1-34 unnamed_net1U2-J2_4 U1-33 +3.3V U3-1 C3-1 C2-1 C1-2 U2-J1_9 U2-J1_10 U2-J1_13 U2-J1_14 U2-J1_15 U2-J1_16 U2-J1_17 U2-J1_18 U2-J1_11 U2-J1_3 U2-J1_4 U2-J1_5 U2-J1_6 U2-J1_7 U2-J1_8 U2-J1_19 U2-J1_12 U2-J2_20 U2-J2_11 U2-J2_12 \ U2-J2_13 U2-J2_14 U2-J2_15 U2-J2_16 U2-J2_17 U2-J2_18 U3-2 R1-2 C1-1 U2-J2_5 U2-J2_7 U2-J2_6 U2-J2_1 U1-1 U1-30 +3.3V has been assigned all the +3 pins and the ground pins. Why? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
In case anyone is interested, here's the entire schematic: http://fayettedigital.com/images/sch2.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Stefan Salewski wrote: On Sat, 2010-03-06 at 08:50 -0500, Jim wrote: In case anyone is interested, here's the entire schematic: http://fayettedigital.com/images/sch2.jpg Sorry, can not really help you. (For the experts it may be easier if you make all data files available, not only pictures.) Thanks, I didn't want to overload the message to start. I figured someone with more knowledge than I would tell me what they wanted. What I do in such cases: Delete part of the schematics, start from scratch, exchange symbols, exchange self made components by similar devices shipped with geda... I did a lot of that. I started with everything except the part you designed for me as geda symbols and footprints. Thinking there was a problem with one of them, I started replacing them with my own. Didn't help. Keyword: Minimal example which shows the problem, available with all source file, so developers can test it. One reason for shorts: Some symbols have hidden power pins, i.e. some logic symbols, but I think that is not the problem in your case. That was it! I borrowed a 7805 symbol and did not notice the hidden power (GND) pin when I rearranged the pins to fit my device. I was vaguely aware of such things but didn't give it a thought. Some remarks: You have VCC as input of voltage regulator and at pin 40 of your chip. Is this intended? Yes, U1 is a 5 volt part and U4 is a 3.3 V part. I should have just left the 3.3 V bus off and wrapped the net around the top of U4. I'll probably do that. This is a work in progress still. ;) Not related to netlist: Most people use capital F for farad. 0.1uF at input terminal and 10uF at output is not too common, but it may be fine for your regulator type. You may check with datasheet. Just sloppy work on my part. I know better. I haven't seriously dabbled in hardware for a long time. The spec sheet confirms a 100 nF on the input and a 10 uF on the out. This is a low dropout voltage part and behaves somewhat differently from a common VR. Sorry, no real idea of your problem. Yes real idea! You fixed it! Best regards Stefan Salewski Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Jim wrote: When I do an optimize rats nest I don't see anything but I do get a bunch of errors in the log like this: Snip Thank you one and all. I took Stefan's generated footprint, massaged the pin numbers and got the following working footprint! Element[ WIZ812MJ mod. WIZ812MJ 0 0 -35000 -122461 0 100 ] ( Pin[-45000 -45000 5118 2000 6318 3937 MOSI J2_1 square] Pin[-45000 -35000 5118 2000 6318 3937 D1 J2_3 ] Pin[-45000 -25000 5118 2000 6318 3937 D3 J2_5 ] Pin[-45000 -15000 5118 2000 6318 3937 D5 J2_7 ] Pin[-45000 -5000 5118 2000 6318 3937 D7 J2_9 ] Pin[-45000 5000 5118 2000 6318 3937 GND J2_11 ] Pin[-45000 15000 5118 2000 6318 3937 A8 J2_13 ] Pin[-45000 25000 5118 2000 6318 3937 A10 J2_15 ] Pin[-45000 35000 5118 2000 6318 3937 A12 J2_17 ] Pin[-45000 45000 5118 2000 6318 3937 A14 J2_19 ] Pin[45000 45000 5118 2000 6318 3937 GND J2_20 ] Pin[45000 35000 5118 2000 6318 3937 A7 J2_18 ] Pin[45000 25000 5118 2000 6318 3937 A5 J2_16 ] Pin[45000 15000 5118 2000 6318 3937 A3 J2_14 ] Pin[45000 5000 5118 2000 6318 3937 A1 J2_12 ] Pin[45000 -5000 5118 2000 6318 3937 TX_LED J2_10 ] Pin[45000 -15000 5118 2000 6318 3937 _INT J2_8 ] Pin[45000 -25000 5118 2000 6318 3937 _rd J2_6 ] Pin[45000 -35000 5118 2000 6318 3937 _SCS J2_4 ] Pin[45000 -45000 5118 2000 6318 3937 _RESET J2_2 ] Pin[-35000 -45000 5118 2000 6318 3937 MISO J1_2 ] Pin[-35000 -35000 5118 2000 6318 3937 D0 J1_4 ] Pin[-35000 -25000 5118 2000 6318 3937 D2 J1_6 ] Pin[-35000 -15000 5118 2000 6318 3937 D4 J1_8 ] Pin[-35000 -5000 5118 2000 6318 3937 D6 J1_10 ] Pin[-35000 5000 5118 2000 6318 3937 3V3D J1_12 ] Pin[-35000 15000 5118 2000 6318 3937 A9 J1_14 ] Pin[-35000 25000 5118 2000 6318 3937 A11 J1_16 ] Pin[-35000 35000 5118 2000 6318 3937 A13 J1_18 ] Pin[-35000 45000 5118 2000 6318 3937 NC J1_20 ] Pin[35000 45000 5118 2000 6318 3937 _LINK J2_19 ] Pin[35000 35000 5118 2000 6318 3937 A6 J2_17 ] Pin[35000 25000 5118 2000 6318 3937 A4 J2_15 ] Pin[35000 15000 5118 2000 6318 3937 A2 J2_13 ] Pin[35000 5000 5118 2000 6318 3937 A0 J2_11 ] Pin[35000 -5000 5118 2000 6318 3937 RX_LED J2_9 ] Pin[35000 -15000 5118 2000 6318 3937 _CS J2_7 ] Pin[35000 -25000 5118 2000 6318 3937 _wr J2_5 ] Pin[35000 -35000 5118 2000 6318 3937 SCLK J2_3 ] Pin[35000 -45000 5118 2000 6318 3937 3V3D J2_1 ] # mounting holes Pin[-49213 -65000 15748 2000 16948 12205 41 41 ] Pin[49213 -65000 15748 2000 16948 12205 44 44 ] Pin[-33465 65000 15748 2000 16948 12205 42 42 ] Pin[33465 65000 15748 2000 16948 12205 43 43 ] # five silk outlines ElementLine[-49213 -102362 -49213 -74374 1000] ElementLine[-49213 -102362 49213 -102362 1000] ElementLine[49213 -102362 49213 -74374 1000] ElementLine[-31299 -114961 31299 -114961 1000] ElementLine[49213 80748 -49213 80748 1000] Attribute(name WIZ812MJ) Attribute(author Stefan Salewski) Attribute(email m...@ssalewski.de) Attribute(dist-license GPL) Attribute(use-license unlimited) Attribute(date 03-MAR-2010) Attribute(description WIZ812MJ network module) Attribute(desc WIZ812MJ mod.) Attribute(documentation http://www.vintagecomputercables.com/datasheet/WIZ812MJ%20Datasheet_V_1.1.pdf;) ) I don't know what caused it to start to work but I upgraded an existing openvz container to Ubuntu lucid to get 1.6.0. I also, as was suggested, used underscores instead of dashes. I'm now on my way to finishing the project. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Harry Eaton wrote: On Fri, 2010-03-05 at 00:28 +, Kai-Martin Knaak wrote: On Wed, 03 Mar 2010 20:40:54 +, Peter Clifton wrote: Perhaps the pin identifier U102-J1-1 is causing issues. So this may be another incarnation of the hyphen-nastiness? Would it be possible to fix this tendency to misinterpret hyphens in names once and for all? So is this supposed to be element U102-J1 's pin 1, or is the element U102 's pin J1-1. The point is that we chose to use - as a name/number separator. It is reasonable to choose a single reserved character for that purpose in a lightweight protocol like our netlist format. We could of course allow the escape that -- becomes a literal hyphen in the string (which I don't think we've done). That won't solve the instant problem until both the netlister and netlist reader are changed to add that facility. Frankly I don't see it as much of a problem to just treat it as a reserved character and leave the code alone. But there are always people that want to put / in their filenames and name their variable if in C code. Not that I understand all the implications here, but if I were coding something that might have multiple dashes and the last dash separated a name/number it would be trivial to treat all the dashes as part of the name except the last one. I understand that's not the way it appears to be written, but it's not a seriously difficult programming problem. Also understand I've been programming since 1965 and while my degree is EE, my experiences are overwhelmingly software design so I'm biases a little. :) Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Peter Clifton wrote: On Wed, 2010-03-03 at 16:42 -0500, Jim wrote: Perhaps the pin identifier U102-J1-1 is causing issues. Thanks everyone. I think I understand the issues. I'll just go with pin numbers 1-40 and drop the J1 and J2 mess. It won't match the part, but I can translate easy enough. There are only 6 connections, VCC, GND MOSI MISO SS and SCLK. Most of the rest of the pins either go to ground or VCC, That was just a guess.. you might try J1_1 as the pin number, for example, which will still closely match the part, but not (assuming this is the issue) confuse the net-list code. OK thanks, I'll try it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Peter Clifton wrote: On Wed, 2010-03-03 at 09:41 -0500, Jim wrote: dpkg -l | grep -i geda ii geda 1:1.4.0.1 GPL EDA -- So I presume Debian or Ubuntu? I expect if you grab gEDA 1.6.1 from either the Debian sid repositories, or Ubuntu Lucid, you will be very pleasantly surprised at the improved graphics and feel of the suite. http://packages.debian.org/source/sid/geda-gaf There are several binary packages, so you'd need to grab them and dpkg --install *geda*.deb NB: I'm not 100% sure where best to suggest you grab them from. Probably under: http://ftp.debian.com/debian/pool/main/g/geda/ And similar, such as: http://ftp.debian.com/debian/pool/main/g/geda-gschem/ I'm hesitant to suggest you fiddle with your apt.sources, but there are of course ways to apt-get install from a newer distro release. For Ubuntu Lucid packages (which might work in Karmic, say), look here: http://packages.ubuntu.com/source/lucid/geda-gaf https://launchpad.net/ubuntu/+source/geda-gaf/ If you expand the tab next to 1.6.1, you can see and download the individual .deb files. If you want, let me know what distro version you are on. If people are interested, I can back-port the 1.6.1 package to a few different versions in my PPA. I'm running 8.04 LTS on my main system. I got burnt when they dropped support on a non LTS system. I don't have time to upgrade every few months. I do run openvz and can probably install most any distro. I have jaunty running on a container to support an Arduino project. I can probably upgrade it to Karmic. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Peter Clifton wrote: On Wed, 2010-03-03 at 08:55 -0500, Jim wrote: Peter Clifton wrote: On Wed, 2010-03-03 at 07:27 -0500, Jim wrote: Peter Clifton wrote: This is the only part of the file (board.pcb) that mentions the footprint and/or the pins. Element(0x0 Wiz812mj.fp U102 unknown 10 10 3 100 0x0) ( Pin(310 -450 60 28 J1-1 0x101) Pin(310 350 60 28 J2-1 0x101) Pin(310 -350 60 28 J1-2 0x01) Pin(310 450 60 28 J2-2 0x01) Has this board been opened and saved by PCB, or is it as produced by gnetlist / gsch2pcb. I ask, since PCB doesn't write out the Element header this way, it uses [ brankets ], which denotes a different coordinate multiplier, 0.01mil resolution I think. PCB has not saved Element(...) since Jan 2004! Footprints can still use this syntax, and PCB will read it - but it will save with the newer syntax. I'm afraid I'm no closer to solving the mystery. Perhaps you could email me the complete example board in which the netlist can't find the required pins, and I'll take a poke at what is wrong. Send any .cmd and .net file along too, as they might have clues as to the issue. Best regards, Originally when I wasn't getting a netlist, pcb had opened it, but when I went back and made the changes so the footprint file conformed to the rules, I was getting syntax errors from pcb so I'm guessing pcb wasn't rewriting anything if it couldn't figure out what I had. I've learned quite a bit from these posts so let me cogitate and try some things. Thanks for the offer. I hope I won't need to take you up on it. Some combination of your info and Stephan's design may do the trick. Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb doesn't find my pins
When I do an optimize rats nest I don't see anything but I do get a
bunch of errors in the log like this:
Can't find U102 pin J1-13 called for in netlist.
Can't find U102 pin J1-8 called for in netlist.
Can't find U102 pin J1-9 called for in netlist.
Can't find U102 pin J1-10 called for in netlist.
Can't find U102 pin J2-3 called for in netlist.
Can't find U102 pin J1-18 called for in netlist.
Can't find U102 pin J1-11 called for in netlist.
Can't find U102 pin J2-1 called for in netlist.
Can't find U102 pin J1-12 called for in netlist.
Nothing more to add, but there are
either rat-lines in the layout, disabled nets
in the net-list, or missing components
Did the following do something nasty to me? Also found in the log
previous to the above errors.
board.cmd : line 46 : ChangePinName(U102, J1-1, MOSI)
board.cmd : line 47 : ChangePinName(U102, J1-2, MISO)
board.cmd : line 48 : ChangePinName(U102, J1-11, GND)
board.cmd : line 49 : ChangePinName(U102, J1-3, D7)
board.cmd : line 50 : ChangePinName(U102, J1-4, D6)
board.cmd : line 51 : ChangePinName(U102, J1-5, D5)
board.cmd : line 52 : ChangePinName(U102, J1-6, D4)
board.cmd : line 53 : ChangePinName(U102, J1-7, D3)
board.cmd : line 54 : ChangePinName(U102, J1-8, D2)
board.cmd : line 55 : ChangePinName(U102, J1-9, D1)
board.cmd : line 56 : ChangePinName(U102, J1-10, D0)
board.cmd : line 57 : ChangePinName(U102, J1-13, A14)
... there are 25 or so changing the names of all the pins in both U102
and U101.
Extract from the symbol for U102:
v 20100302 1 1
P 2100 8500 1900 8500 1 0 0
{
T 1900 8550 5 8 1 1 0 0 1
pinnumber=J2-1
T 1900 8450 5 8 0 1 0 2 1
pinseq=2
T 1750 8500 9 8 1 1 0 6 1
pinlabel=3V3D
T 1750 8500 5 8 0 1 0 8 1
pintype=in
}
V 1850 8500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 2100 8100 1900 8100 1 0 0
{
T 1900 8150 5 8 1 1 0 0 1
pinnumber=J2-18
T 1900 8050 5 8 0 1 0 2 1
pinseq=23
T 1750 8100 9 8 1 1 0 6 1
pinlabel=A0
T 1750 8100 5 8 0 1 0 8 1
pintype=in
}
and
Pin(310 -450 60 28 J1-1 0x101)
Pin(310 350 60 28 J2-1 0x101)
Pin(310 -350 60 28 J1-2 0x01)
Pin(310 450 60 28 J2-2 0x01)
Pin(210 -450 60 28 J1-3 0x01)
Pin(210 350 60 28 J2-3 0x01)
Pin(210 -350 60 28 J1-4 0x01)
Pin(210 450 60 28 J2-4 0x01)
Pin(110 -450 60 28 J1-5 0x01)
Pin(110 350 60 28 J2-5 0x01)
Pin(110 -350 60 28 J1-6 0x01)
Just to show that I think the pin names match between the footprint and
the symbol.
I'm very confused.
I have just two parts in this. I generated two symbols and one
footprint. I used a DIL 40 600 footprint for the one part. I ran
just a few nets to see if I had everything set up OK. Obviously not.
Thanks,
Jim.
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Re: gEDA-user: pcb doesn't find my pins
Peter Clifton wrote: On Wed, 2010-03-03 at 05:01 -0500, Jim wrote: When I do an optimize rats nest I don't see anything but I do get a bunch of errors in the log like this: Can't find U102 pin J1-13 called for in netlist. Can't find U102 pin J1-8 called for in netlist. Can't find U102 pin J1-9 called for in netlist. Can't find U102 pin J1-10 called for in netlist. Can't find U102 pin J2-3 called for in netlist. Can't find U102 pin J1-18 called for in netlist. Can't find U102 pin J1-11 called for in netlist. Can't find U102 pin J2-1 called for in netlist. Can't find U102 pin J1-12 called for in netlist. Nothing more to add, but there are either rat-lines in the layout, disabled nets in the net-list, or missing components Did the following do something nasty to me? Also found in the log previous to the above errors. and Pin(310 -450 60 28 J1-1 0x101) Pin(310 350 60 28 J2-1 0x101) Pin(310 -350 60 28 J1-2 0x01) Pin(310 450 60 28 J2-2 0x01) Pin(210 -450 60 28 J1-3 0x01) Pin(210 350 60 28 J2-3 0x01) Pin(210 -350 60 28 J1-4 0x01) Pin(210 450 60 28 J2-4 0x01) Pin(110 -450 60 28 J1-5 0x01) Pin(110 350 60 28 J2-5 0x01) Pin(110 -350 60 28 J1-6 0x01) Just to show that I think the pin names match between the footprint and the symbol. Presume your U102 is still present and intact on the board? Show us the relevant fragment from the .pcb file. The footprint gets embedded in that file, and that is where (if anywhere) the changes will be made. The .cmd script should only change the label of pins. It is a little confusing that the action is called ChangePinName. Perhaps someone fixed that action to do something different. Both part show up on the board. See http://fayettedigital.com/images/wiz.jpg I also show the results of the D key, whatever that does. This is the only part of the file (board.pcb) that mentions the footprint and/or the pins. Element(0x0 Wiz812mj.fp U102 unknown 10 10 3 100 0x0) ( Pin(310 -450 60 28 J1-1 0x101) Pin(310 350 60 28 J2-1 0x101) Pin(310 -350 60 28 J1-2 0x01) Pin(310 450 60 28 J2-2 0x01) Pin(210 -450 60 28 J1-3 0x01) Pin(210 350 60 28 J2-3 0x01) Pin(210 -350 60 28 J1-4 0x01) Pin(210 450 60 28 J2-4 0x01) Pin(110 -450 60 28 J1-5 0x01) Pin(110 350 60 28 J2-5 0x01) Pin(110 -350 60 28 J1-6 0x01) Pin(110 450 60 28 J2-6 0x01) Pin(10 -450 60 28 J1-7 0x01) Pin(10 350 60 28 J2-7 0x01) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Peter Clifton wrote: On Wed, 2010-03-03 at 07:27 -0500, Jim wrote: Peter Clifton wrote: This is the only part of the file (board.pcb) that mentions the footprint and/or the pins. Element(0x0 Wiz812mj.fp U102 unknown 10 10 3 100 0x0) ( Pin(310 -450 60 28 J1-1 0x101) Pin(310 350 60 28 J2-1 0x101) Pin(310 -350 60 28 J1-2 0x01) Pin(310 450 60 28 J2-2 0x01) Pin(210 -450 60 28 J1-3 0x01) Pin(210 350 60 28 J2-3 0x01) Pin(210 -350 60 28 J1-4 0x01) Pin(210 450 60 28 J2-4 0x01) Pin(110 -450 60 28 J1-5 0x01) Pin(110 350 60 28 J2-5 0x01) Pin(110 -350 60 28 J1-6 0x01) Pin(110 450 60 28 J2-6 0x01) Pin(10 -450 60 28 J1-7 0x01) Pin(10 350 60 28 J2-7 0x01) That looks wrong - and is in some ancient syntax too.. it might have come directly from the footprint, but I'd have expected PCB to save in the newer format when such changes were made. An example from one of my designs, which has pin labels and pin names different: Element[ DIP14 U38 74HCT14 84 52 -8000 -5000 3 100 ] ( Pin[0 0 6000 2002 6600 3000 A 1 square] Pin[0 1 6000 2002 6600 3000 Y 2 ] Pin[0 2 6000 2002 6600 3000 A 3 ] Pin[0 3 6000 2002 6600 3000 Y 4 ] Pin[0 4 6000 2002 6600 3000 A 5 ] Pin[0 5 6000 2002 6600 3000 Y 6 ] Pin[0 6 6000 2002 6600 3000 GND 7 thermal(0t,1X)] Pin[3 6 6000 2002 6600 3000 Y 8 ] Pin[3 5 6000 2002 6600 3000 A 9 ] Pin[3 4 6000 2002 6600 3000 Y 10 ] Pin[3 3 6000 2002 6600 3000 A 11 ] Pin[3 2 6000 2002 6600 3000 Y 12 ] Pin[3 1 6000 2002 6600 3000 A 13 ] Pin[3 0 6000 2002 6600 3000 Vcc 14 ] [SNIP] ) Does anyone know the history of this? One might rationally assume the action ChangePinName does indeed change the pin name, not its label. (Yet n on an object changes the label). I was reading the Land Patterns pdf which I thought was the design document. I was also looking at other footprints and must have confused the two. However the Land Patterns doc does say the last parameter is a hex value and that's not working. So I changed it to: Pin(310 -450 60 20 66 30 MOSI J1-1 square) And it's giving me a syntax error on line 76 which is that line. 70 ElementLine(400 0 700 0 10) 71 ElementArc(350 0 50 50 0 180 10) 72 Mark(50 50) 73 ) 74 Element(0x0 Wiz812mj.fp U102 unknown 10 10 3 100 0 100 0x0) 75 ( 76 Pin(310 -450 60 20 66 30 MOSI J1-1 square) 77 Pin(310 350 60 20 66 30 3V3D J2-1 square) 78 Pin(310 -350 60 20 66 30 MISO J1-2 ) 79 Pin(310 450 60 20 66 30 _RESET J2-2 ) 80 Pin(210 -450 60 20 66 30 D7 J1-3 ) 81 Pin(210 350 60 20 66 30 SCLK J2-3 ) So I thought maybe the Element line wasn't right since it looks different from yours, so I changed it to Element( Wiz812mj.fp U102 unknown 10 10 3 100 0 100 ) And now it fails on line 74. I'm getting more confused by the minute. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TO-92 Best Practices
timecop wrote: Why woudl someone use to92 in 2010. Maybe they are like me and don't have the eyesight, equipment or dexterity to solder anything smaller than TO92 parts? Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Stefan Salewski wrote: On Wed, 2010-03-03 at 09:41 -0500, Jim wrote: Do you know where the definitive description of the footprint file can be found? It's not land_patterns_20050129.pdf which is what googling wanted me to believe. Thanks, Jim. Land_pattern_xxx is right, see link at bottom of this page: http://www.ssalewski.de/SFG.html.en I think I followed that pattern but it didn't work. I see you have a generator can it do a 4 row DIP? Something with a foot print like: o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o ? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Stefan Salewski wrote: On Wed, 2010-03-03 at 11:06 -0500, Jim wrote: Land_pattern_xxx is right, see link at bottom of this page: http://www.ssalewski.de/SFG.html.en I think I followed that pattern but it didn't work. I see you have a generator can it do a 4 row DIP? Something with a foot print like: o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o ? No problem with minimal manual tuning. Make two DIP parts, inner and outer rows. Copy the pins from one element into the other and rename the pins (number, name), all with a text editor. Should be easy -- I may do it for you if you give me all necessary data. I have never seen such an layout. If you can post a link to a datasheet of such a device, and if it is not too exotic, then I will extend my generator script for that shape. Best regards Stefan It's probably one of a kind. Not worth the trouble I don't think. The datasheet is here http://www.vintagecomputercables.com/datasheet/WIZ812MJ%20Datasheet_V_1.1.pdf It's not something everyone would mount on a PCB. Thanks for the offer, I'll take a shot at creating the FP the way you suggested. I need to learn the tool anyway. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Peter Clifton wrote: On Wed, 2010-03-03 at 21:23 +0100, Stefan Salewski wrote: On Wed, 2010-03-03 at 12:17 -0800, Steven Michalske wrote: On Mar 3, 2010, at 12:10 PM, Stefan Salewski wrote: Pin[-45000 -45000 5118 2000 6318 3937 1 1 square] snip Pin[-35000 -45000 5118 2000 6318 3937 1 1 square] This part could not be netlisted. Chould the pins be named J1-1 through J1-20 and J2-1 through J2-20... that would make it at least netlistable. Steve Sure -- I did care only about shape, not pin numbers. On Wed, 2010-03-03 at 21:10 +0100, Stefan Salewski wrote: I have generated a draft, just for fun. You have to check all dimensions carefully and change pin names/numbers. I do not know if something like J1-1 works, and I do not know Jims gschem symbol. I wonder if that syntax is tricking PCB, since internally it sometimes refers to connections as element_name-pinnumber Perhaps the pin identifier U102-J1-1 is causing issues. Thanks everyone. I think I understand the issues. I'll just go with pin numbers 1-40 and drop the J1 and J2 mess. It won't match the part, but I can translate easy enough. There are only 6 connections, VCC, GND MOSI MISO SS and SCLK. Most of the rest of the pins either go to ground or VCC, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
Stefan Salewski wrote: On Wed, 2010-03-03 at 12:05 -0500, Jim wrote: It's probably one of a kind. Not worth the trouble I don't think. The datasheet is here http://www.vintagecomputercables.com/datasheet/WIZ812MJ%20Datasheet_V_1.1.pdf It's not something everyone would mount on a PCB. Thanks for the offer, I'll take a shot at creating the FP the way you suggested. I need to learn the tool anyway. I have generated a draft, just for fun. You have to check all dimensions carefully and change pin names/numbers. And you may add more silk lines manually. This is the sfg input file: ste...@amd64x2 /mnt/data/stefan/Bash $ cat sfg-dat.txt Device = Global author = Stefan Salewski email = m...@ssalewski.de dist-license = GPL use-license = unlimited date = 03-MAR-2010 elementdir = ./ silkwidth = 10 mil silkoffset = 10 mil textpos = upperleft textorientation = horizontal refdessize = 100 mask = 6 mil clearance = 10 mil # generate complicated WIZ812MJ -- we have to put it together in text editor # start with outer rows -- discard long silk lines and top silk line Device = DIP defaultunit = mm hole-scale = 100 hole-add-on = 0 name = WIZ812MJ description = WIZ812MJ network module desc = WIZ812MJ mod. documentation = http://www.vintagecomputercables.com/datasheet/WIZ812MJ%20Datasheet_V_1.1.pdf; pins = 20 width = 22.86 # B pitch = 2.54 # J pad-dia = 1.3 drill-dia = 1.0 # guess silkbox = custom silkboxwidth = 25 # A silkboxheight = 33.02+2*4 # H+2E ovalpads = no p1silkmark = no p1coppermark = square Generate WIZ812MJ-outer.fp # inner pin rows and topmost silk line width = 22.86-2*2.54 # B-2K silkboxheight = 52+2*3.2 # F+2G silkboxwidth = 15.9 # L Generate WIZ812MJ-inner.fp # and upper outer mounting holes pins = 4 width = 25 # A pitch = 33.02 # H pad-dia = 4 drill-dia = 3.1 silkboxheight = 52 # F silkboxwidth = 25 # A Generate WIZ812MJ-h1.fp # and finaly lower inner mounting holes pins = 4 width = 17 # C pitch = 33.02 # H pad-dia = 4 drill-dia = 3.1 silkbox = no Generate WIZ812MJ-h2.fp After putting it together in an editor results in this footprint: ste...@amd64x2 /mnt/data/stefan/Bash $ cat WIZ812MJ.fp Element[ WIZ812MJ mod. WIZ812MJ 0 0 -35000 -122461 0 100 ] ( Pin[-45000 -45000 5118 2000 6318 3937 1 1 square] Pin[-45000 -35000 5118 2000 6318 3937 2 2 ] Pin[-45000 -25000 5118 2000 6318 3937 3 3 ] Pin[-45000 -15000 5118 2000 6318 3937 4 4 ] Pin[-45000 -5000 5118 2000 6318 3937 5 5 ] Pin[-45000 5000 5118 2000 6318 3937 6 6 ] Pin[-45000 15000 5118 2000 6318 3937 7 7 ] Pin[-45000 25000 5118 2000 6318 3937 8 8 ] Pin[-45000 35000 5118 2000 6318 3937 9 9 ] Pin[-45000 45000 5118 2000 6318 3937 10 10 ] Pin[45000 45000 5118 2000 6318 3937 11 11 ] Pin[45000 35000 5118 2000 6318 3937 12 12 ] Pin[45000 25000 5118 2000 6318 3937 13 13 ] Pin[45000 15000 5118 2000 6318 3937 14 14 ] Pin[45000 5000 5118 2000 6318 3937 15 15 ] Pin[45000 -5000 5118 2000 6318 3937 16 16 ] Pin[45000 -15000 5118 2000 6318 3937 17 17 ] Pin[45000 -25000 5118 2000 6318 3937 18 18 ] Pin[45000 -35000 5118 2000 6318 3937 19 19 ] Pin[45000 -45000 5118 2000 6318 3937 20 20 ] Pin[-35000 -45000 5118 2000 6318 3937 1 1 square] Pin[-35000 -35000 5118 2000 6318 3937 2 2 ] Pin[-35000 -25000 5118 2000 6318 3937 3 3 ] Pin[-35000 -15000 5118 2000 6318 3937 4 4 ] Pin[-35000 -5000 5118 2000 6318 3937 5 5 ] Pin[-35000 5000 5118 2000 6318 3937 6 6 ] Pin[-35000 15000 5118 2000 6318 3937 7 7 ] Pin[-35000 25000 5118 2000 6318 3937 8 8 ] Pin[-35000 35000 5118 2000 6318 3937 9 9 ] Pin[-35000 45000 5118 2000 6318 3937 10 10 ] Pin[35000 45000 5118 2000 6318 3937 11 11 ] Pin[35000 35000 5118 2000 6318 3937 12 12 ] Pin[35000 25000 5118 2000 6318 3937 13 13 ] Pin[35000 15000 5118 2000 6318 3937 14 14 ] Pin[35000 5000 5118 2000 6318 3937 15 15 ] Pin[35000 -5000 5118 2000 6318 3937 16 16 ] Pin[35000 -15000 5118 2000 6318 3937 17 17 ] Pin[35000 -25000 5118 2000 6318 3937 18 18 ] Pin[35000 -35000 5118 2000 6318 3937 19 19 ] Pin[35000 -45000 5118 2000 6318 3937 20 20 ] # mounting holes Pin[-49213 -65000 15748 2000 16948 12205 41 41 ] Pin[49213 -65000 15748 2000 16948 12205 44 44 ] Pin[-33465 65000 15748 2000 16948 12205 42 42 ] Pin[33465 65000 15748 2000 16948 12205 43 43 ] # five silk outlines ElementLine[-49213 -102362 -49213 -74374 1000] ElementLine[-49213 -102362 49213 -102362 1000] ElementLine[49213 -102362 49213 -74374 1000] ElementLine[-31299 -114961 31299 -114961 1000] ElementLine[49213 80748 -49213 80748 1000] Attribute(name WIZ812MJ) Attribute(author Stefan Salewski) Attribute(email m...@ssalewski.de) Attribute(dist-license GPL) Attribute(use-license unlimited) Attribute(date 03-MAR-2010) Attribute(description WIZ812MJ network module) Attribute(desc WIZ812MJ mod.) Attribute(documentation http://www.vintagecomputercables.com/datasheet
Re: gEDA-user: I am such a troll for posting to slashdot
These would work for me: [1]http://www.luciani.org/not-quite-ready/not-quite-ready-index.html [2]http://www.luciani.org/not-quite-ready/doc/sampler.pdf In the sampler.pdf, what's that symbol that looks like a zener with a third wire ? Is that a three terminal regulator like the 7805? I've not encountered it before. Thanks, Jim. References 1. http://www.luciani.org/not-quite-ready/not-quite-ready-index.html 2. http://www.luciani.org/not-quite-ready/doc/sampler.pdf ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Is there a way to get a footprint to place copper on both sides?
I'm trying to build a double sided board with fingers to insert into a edge connector. I realize I can add copper at the pcb step, but wondered if I could in any way build a footprint to do it for both sides? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is there a way to get a footprint to place copper on both sides?
Kai-Martin Knaak wrote: add the flag onsolder to the pad you want to put on the other side. See page 24 of [1]http://www.brorson.com/gEDA/land_patterns_20070818.pdf If you prefer to do footprints in the GUI of pcb, lines that are in the solder side layer group, get the onsolder flag. ---(kaimartin)--- Vanessa Ezekowitz wrote: There are a couple of Commodore 64 edge connector footprints in my [2]gedasymbols.org repository that demonstrate this also, in case that is useful to you: [3]http://www.gedasymbols.org/user/vanessa_ezekowitz/ Thank you, gentlemen. As always, this is the most helpful group. Jim References 1. http://www.brorson.com/gEDA/land_patterns_20070818.pdf 2. http://gedasymbols.org/ 3. http://www.gedasymbols.org/user/vanessa_ezekowitz/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How do I get the router to go where I want it to?
I have a board I'm developing (maybe) that is a backplane. It has 9 edge connectors mounted on it and when I went to autoroute it Oh Lord! I've never seen such a mess! Traces all over, a million or so vias, etc. You'd think it would be a simple set of parallel lines, but no. So I ripped it up and started autorouting them one at a time. The first one went well, then the second row didn't. I'm guessing that I'm trying to violate some sort of clearance rule but I don't know which one or how to fix it. I may even have the pins too large. Take a look at the image [1]http://fayettedigital.com/images/board.jpg You can see the first pin in the second row shoots off towards the bottom of the board where it tries to go outside of the connector to connect to the second connector. It's a euroboard (32 pin). The pin definitions from the footprint (my design) are all like: Pin[-10850 35000 7500 2000 9500 5200 1 1 square] Pin[-20850 35000 7500 2000 9500 5200 2 2 ] Pin[-10850 45000 7500 2000 9500 5200 3 3 ] Pin[-20850 45000 7500 2000 9500 5200 4 4 ] I see boards all the time where traces run between the pins so I know it's done and I cannot believe someone has in each case done a manual layout. Thanks for any pointers. The last time I had to lay up a pcb I used a drafting table, tee square and pen and ink. I think that was quicker. ;) And if someone notices, yes I'm the same guy that was asking questions before but for some reason the mail list is not getting my postings any longer so I had to try from my gmail account. Jim. References 1. http://fayettedigital.com/images/board.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Where do I put footprints?
I know this seems like a trivial question but I've googled for hours trying to find 1. What goes into gafrc other than component-library? 2. Where do I put my locally generated footprints? I tried putting them in the component-library, the same file with the schematic et al. Out of desparation I attempted to add a footprint-library line to the gafrc but that was rejected. I'm all out of ideas. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where do I put footprints?
John Griessen wrote: DJ Delorie wrote: I use the new pcb-import code, so I have pcb's footprint path set up to include an absolute path for the global tree, and . I.e. ~/.pcb/settings has this line: lib-newlib = /envy/dj/geda/gedasymbols/www/user/dj_delorie/footprints:. So, that : is the syntax for adding directory . also? with . added, any subdirs will be searched for footprints? Thanks, John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Thank you, gentlemen. Jim ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How do I fill?
I've poked at some documentation, what tutorials I could find and Googled for geda fill and haven't yet found instructions on filling. Is it called something else in pcb lingo? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Missing message?
I sent a message to the list, but it hasn't appeared. I had an attached jpg file, but it was small. Would that have prevented it from being published? Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Wrong pin assignment in an edited symbol.
Sent this once but never saw it, so I'll try again. Don't know what happened to the first one. I was following the tutorial on [1]http://geda.seul.org/wiki/geda:gsch2pcb_tutorial#custom_gschem_symb ols and attempted to modify the dual op amp as directed in that tutorial. When I went to add the two op amps to the schematic I noticed that when I changed the second one to slot=2, that the output pin remained number 1, but the input pins changed as expected. I examined the opamp-sym.sym file that I had edited and found this: slot=1 T 200 1300 5 10 0 0 0 0 1 numslots=2 T 200 1500 5 10 0 0 0 0 1 slotdef=1:3,2,1 T 200 1700 5 10 0 0 0 0 1 slotdef=2:5,6,7 T 200 1900 5 10 0 0 0 0 1 footprint=SO8 T 200 2100 5 10 0 0 0 0 1 footprint2=DIP8 T 200 2500 5 10 0 0 0 0 1 symversion=0.2 T 200 2700 5 10 0 0 0 0 1 documentation=[2]http://www.onsemi.com/pub/Collateral/LM358-D.PDF T 200 2900 5 10 0 0 0 0 1 description=opamp T 1895 600 8 10 0 0 0 0 1 net=Vcc:8 T 1795 400 8 10 0 0 0 0 1 net=Vee:4 That's not the whole file, but just the last few lines. There are no other references to slot in the file. [cid:part1.06020809.04010901@fayettedigital.com] I'm very new at this, so I'm not really sure where to start looking for a solution. Thanks, Jim. References 1. http://geda.seul.org/wiki/geda:gsch2pcb_tutorial#custom_gschem_symbols 2. http://www.onsemi.com/pub/Collateral/LM358-D.PDF inline: slot2.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Wrong pin assignment in an edited symbol.
John Doty wrote: Check the pinseq= attribute on the output pin. Should be 3, I suppose, but maybe it isn't. On Dec 2, 2009, at 11:12 AM, Jim wrote: When I went to add the two op amps to the schematic I noticed that when I changed the second one to slot=2, that the output pin remained number 1, but the input pins changed as expected. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com That fixed the problem, but I don't know why. It was the same as the sym that I copied (pinseq=5) from and that sym worked. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Gschem symbol for parallax propeller chip
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hello, I've been using geda suite for some time now. I made a symbol file for the Parallax Propeller chip. Where do I need to submit it to be included in the main database? You can find the symbol @ http://www.symbolengine.com/files/sym/propeller.sym -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFI8HdJcyIZ0UyYSoIRAoVeAJ90dIh7YKBeWdHg/+XKkGsXZ/bZxgCguRR+ fxHUVip4xjTxraQBxNhjwwU= =F9C7 -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: a note from a novice user
just hit bug after bug after bug... I hope that the intention of this email is not lost. I don't intend it as a flame, I would really love to see open source EDA software, and it looks like there is a lot of promise in this software. I just thought that the developers might benefit from a detailed explanation of a path that a novice user might take, and why a novice user would probably just give up before getting this software going. Best of luck, Jim PS: Maybe you guys should put together a little conference. It seems like with all of the gEDA developers in one room, there could be some solid work on consolidating these programs into a more unified project. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
