Re: gEDA-user: CERN goes for KiCAD
On Wed, 07 Sep 2011 22:37:46 +0200 Kai-Martin Knaak k...@familieknaak.de wrote: CERN software engeneers don't fear complexity -- not under the hood, nor on the interface. They strive for elegance and excellent results instead. See the structure and the UI of paw, or root. Well... When I was at CERN back in 2005 I noticed for example that they were moving from Linux to windows. They changed the mail servers TO some winXX server. So I feel that even in CERN there is a move towards the click click click direction. I mean integrated solutions etc. I don't know what is going on there nowadays though. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: CERN goes for KiCAD
On Wed, 07 Sep 2011 00:20:53 +0200 Kai-Martin Knaak k...@familieknaak.de wrote: We had a meeting at CERN on Friday and decided we would start contributing to the Kicad project in view of taking it to a level of quality and features suitable for our PCB design activities. It was to be expected. -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: time for a pcb release cycle?
On Tue, 6 Sep 2011 21:04:03 -0400 DJ Delorie d...@delorie.com wrote: there are any bugs This is with GTK GUI and yesterday's HEAD. 1. Set the copper diameter of vias for the current style 2. Go into the via tool. 3. Try place a via. The drill diameter will be the copper diameter. The copper diameter is a bit increased. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: time for a pcb release cycle?
On Tue, 6 Sep 2011 21:04:03 -0400 DJ Delorie d...@delorie.com wrote: When you do save buffer elements to file and you point the chooser to an existing file, pcb exits with this message: ** Gtk:ERROR:/build/buildd/gtk+2.0-2.20.1/gtk/gtkfilechooserdefault.c:8125:get_display_name_from_file_list: assertion failed: (had_selection) Aborted and the footprint not saved. :-( Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: time for a pcb release cycle?
Each time I save my layout, a message appears: layout changed. Do you want to load it? or something like that. Brr well of couse it changed! I saved it! :-) Ok, I know it is a good feature... -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: time for a pcb release cycle?
On Tue, 6 Sep 2011 21:04:03 -0400 DJ Delorie d...@delorie.com wrote: At this time, I'd like to ask folks to try the git head PCB and see if there are any bugs that must be fixed for this release, and/or work on Orthogonal moves doesn't work and sometimes some menu items in the GTK hid doesn't work. It might be the same problem for all the report I did so far. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: test repo
On Mon, 5 Sep 2011 16:43:43 -0400 DJ Delorie d...@delorie.com wrote: And nine women can have a baby in a month :-) -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gpcb-menu.res
On Tue, 30 Aug 2011 12:01:00 -0700 Andrew Poelstra as...@sfu.ca wrote: Fixed in git head. Thanks! Maybe I can see why the automatic layer (group) change doesn't work. Can you give me any clue where it is located in the code? Thank you Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gpcb-menu.res
I noticed that recent PCB doesn't interpret my gpcb-menu.res file located in ~/.pcb. Instead it writes the following line to the standard output/error: @�: No such file or directory and the following line to the log window: Note: home directory is /home/leva Loading menus from Loading menus from Using default menus cheers, Levnte -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: timestamps in pcb.git
I've just downloaded a snapshoot from http://git.gpleda.org/?p=pcb.git;a=summary and it created files with timestpamps in the future. The make tool is now confused and ends up in an endless loop. make: Warning: File `Makefile.am' has modification time 2.2e+04 s in the future -rw-r--r-- 1 leva leva706 2011-08-29 14:43 Makefile.am I think I shell wailt till 14:43. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: timestamps in pcb.git
On Mon, 29 Aug 2011 07:09:21 -0700 Andrew Poelstra as...@sfu.ca wrote: My dev server clock seems to have found its way out of sync. This happens every so often, because of some oddity with Xen and timezones. Perhaps setting the root and virtual domains to UTC will fix it; I'll try this now. Waiting a few hours will fix the build failure. I'll be sure to keep an eye out for this when pushing commits in the future. OK. So which is the latest commit? 728f350268e134ca116a6f79577843db7b18e82c or acf8d00db4a90b555d768341a97453914b7b4aec ? git is confused as well. -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: timestamps in pcb.git
On Mon, 29 Aug 2011 00:09:27 -0700 Andrew Poelstra as...@sfu.ca wrote: If you run touch `find` This will reset the timestamps on everything to your current time. make will take a while to run, since it will then believe everything has changed, but it won't get stuck anywhere. Other than that, nothing will be broken or confused. Ok. Thanks. I found that layer selection and toggle doesn't work as it was. I have to click 3 times (or something) to have the layer switched on or off. First click often moves the highlighted area to another line. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Mon, 29 Aug 2011 10:28:11 -0700 Colin D Bennett co...@gibibit.com wrote: Nice! That sounds very slick. Have you shared your code for this pin-mapping tool? What I do is I share my git repositories... http://git.logonex.eu/?p=utils4geda.git;a=tree;f=scripts4geda;h=e2d27439fbed3df645cfc65248ef690dd32956f4;hb=HEAD The magic is done by light2heavy.pl and gen_heavy_sym.pl, but you need other scripts as well. You should look at dbsym_update.pl as well, which calls other scripts. You can examine my makefile system too. http://git.logonex.eu/?p=utils4geda.git;a=tree;f=pskel;h=4acca5f5b50d8943656cbd9a4faf46726a0e804f;hb=ce4516e8a351b54818abfaacb215d7864b6d1b43 Makefile.sch is the one for schematics. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Mon, 29 Aug 2011 22:28:22 +0200 Levente Kovacs leventel...@gmail.com wrote: On Mon, 29 Aug 2011 10:28:11 -0700 Colin D Bennett co...@gibibit.com wrote: Nice! That sounds very slick. Have you shared your code for this pin-mapping tool? What I do is I share my git repositories... http://git.logonex.eu/?p=utils4geda.git;a=tree;f=scripts4geda;h=e2d27439fbed3df645cfc65248ef690dd32956f4;hb=HEAD The magic is done by light2heavy.pl and gen_heavy_sym.pl, but you need other scripts as well. You should look at dbsym_update.pl as well, which calls other scripts. You can examine my makefile system too. http://git.logonex.eu/?p=utils4geda.git;a=tree;f=pskel;h=4acca5f5b50d8943656cbd9a4faf46726a0e804f;hb=ce4516e8a351b54818abfaacb215d7864b6d1b43 Makefile.sch is the one for schematics. Bfff... this was an old commit... this one is head. http://git.logonex.eu/?p=utils4geda.git;a=tree;f=pskel;h=e4a14b5b812f2b235f875a959ad3967cdb4bb471;hb=b8920019ddd79ce76d9644689fe847be9332bfa9 Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Thu, 25 Aug 2011 14:21:26 -0700 Colin D Bennett co...@gibibit.com wrote: Do you really want to delete and re-add each of your dozens of transistors in gschem when you change the transistor to one with a different pinout? If you use a logically-pinned symbol, you can easily change the pinout by just editing the footprint attributes (gattrib, gschem property editor, export/import to/from spreadsheet, etc.). I don't want it. Conversation regarding TO-92 transistor package pinouts: http://thread.gmane.org/gmane.comp.cad.geda.user/37190/focus=37197 Well, I always say I won't get into the logical/physical pinning debate, but I always do. :-) For me, using logical pins on the schematic symbols such as transistors and diodes (*especially* diodes in IC packages like SOT-23) is the only way that makes sense ... at least until proper pin mapping is implemented. Let me go into details. My work flow is as follows. There are two libraries. One with heavy, another with light symbols. If you use heavy symbols, there's nothing to say. Everything is static. When you use a light symbol, a script finds a pinmap, and constructs a heavy symbol. Say for example if you have a SOT23 diode with A1A2K pinout you'll get a symbol with name like 'diode-SOT23-A1A2K.sym' this symbol is then copied to the project's symbol directory, and the original symbol name in the schematic is replaced by the name of the newly created symbol. The script will add other information as well like footprint name, etc. With this, you don't have to mess with your symbols nor with your footprints, and everything works quite well for me. Of course, everything is makefile driven... etc. The pinmap and symbol names are coming from a database. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Wed, 24 Aug 2011 08:21:17 -0400 Ethan Swint eswint.r...@verizon.net wrote: I've defined my own symbols and footprints to use 'A' and 'K' instead of 1 and 2. I don't think it's a good idea. Instead, I use my own library, where pin numbers are consistent. In addition I have my perl scripts which can add pin numbers to symbols according to pinmap files. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Thu, 25 Aug 2011 14:03:35 +0200 Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: Why not? Pinnumbers are numbers in the first place. Former versions of netlisters/PCB got confused by non-digital pinnumbers. With this approach you have to have a SOT23 footprint with 1,2,3 pinout, A,K,NC pinout, A1,A2,K pinout, B,C,E pinout etc. Sooner or later, your library will contain duplicated data. What if you discover that you want to modify the shape of the SOT23.fp footprint? You have to modify all of them. Yuk. I think a footprint must have only *one* pinout, that is a standard pinout of the package. Have an intermediate layer (scripts, database, pinmaps, etc.) that do the heavy lifting for you. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
On Tue, 23 Aug 2011 09:55:21 -0700 Colin D Bennett co...@gibibit.com wrote: It would be great if the gtk GUI could provide some options to increase available screen space Once I started to work on a patch to have the look and feel of the lesstif GUI in the GTK GUI. However, I think we should implement everything with toolbar (if I'm not mistaken) That would play nice on a dual headed setup. There were fights against GTK people not to take tear-off menus from gtk3. But they did AFAIK. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
On Tue, 23 Aug 2011 14:29:50 -0400 DJ Delorie d...@delorie.com wrote: That would play nice on a dual headed setup. One of my dream projects is to do a GUI for pcb that uses two or more monitors, with one monitor heavy on the toolbars and showing an overview thumber window, and the other monitor being 100% layout. There were fights against GTK people not to take tear-off menus from gtk3. But they did AFAIK. The lesstif tear-off model isn't so hot either. I've been considering writing my own from scratch to work around some of the weirdisms. As you might noticed I don't have too much programming skills but I support this as well. It would be nice to have for both HIDs. BTW... is there any TODO list of the project? File format change, GUI change, etc... with priorities... or the developers just do what they want to? Don't get me wrong, I don't say anything against it... just curious. But maybe it would be nice to have one... someone might pick up some of the tasks, and do it. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
On Tue, 23 Aug 2011 16:31:49 -0400 DJ Delorie d...@delorie.com wrote: I think dockable toolbars is the way to go. +1. And the ability to store toolbar states in configuration file, or *.pcb file. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Foss-pcb Proposed plan from CERN
On Sun, 21 Aug 2011 20:36:30 -0500 John Griessen j...@ecosensory.com wrote: CERN might come up with tip money for developers. Anyone have the time to be in a committee? I am very interested in this project. I don't really know what would be the tastks in the committee. Please let me know about any details. I subscribed to the mailing list. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: slotting question
On Fri, 19 Aug 2011 23:55:49 -0400 Dave McGuire mcgu...@neurotica.com wrote: I open up a new schematic, place two instances of 7404-1, edit the attributes of the second one, promote the slot attribute, edit the newly-accessible one, change it to 2, save it, save the sheet, exit gschem, restart, and load the sheet. I am guessing that you edit the symbol too. You don't have to. You just have to save the sheet, not the symbol. You should promote the slot attribute for both instances. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: viewing side vs. layers
The automatic layer change capability is missing from the current HEAD ( 7b590a617db3ca3ed69965b544f1468f82c39dfe ). I.e. when you swap viewing side with TAB. It works only once, then stops working. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer selective DRC
On Fri, 5 Aug 2011 17:36:25 + (UTC) Sparky scop...@gmail.com wrote: For my outline layer I did the following to add the attribute: Edit-Edit attribute of-CurrentLayer Left box: PCB::skip-drc Right box: 1 I'm sorry for the late answer. I'm not sure if you need this for the layer called outline. For the others, thank you for taking time playing with it. I didn't experienced any trouble with the feature. However, I'm not a heavy DRC user. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tag-Connect TC2030-MCP(NL) footprint, expert review
On Fri, 12 Aug 2011 11:04:54 -0700 Colin D Bennett co...@gibibit.com wrote: I've created gEDA/pcb footprints for the Tag-Connect I've done that before. I thought I made it public. I sent the footprints to the company, I received a tag connector for free, but my footprints didn't made to their homepage. :-) http://git.logonex.eu/?p=library.git;a=tree;f=electronic/footprint;h=1850fa21028a1f1e69284f1f6b67849e41fe4763;hb=HEAD tag_connector_*.fp Cheers, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Linux Desktop für gEDA
On Thu, 4 Aug 2011 20:08:31 +0200 Markus g...@traidl.de wrote: Hello, currently I am running the actual Ubunut Version and the new Unity (Gnome 3.0) Desktop. But I am not very happy with the new desktop. I am thinking about changing to xcfe. What desktop are you using for gEDA? (are the any advantages or disadvantages for KDE, Gnome or XCFE in relation to gEDA?) I use openbox without any window decorations, black background. I use the keyboard a lot. The system is Debian 6.0. Two monitors. At work I use Ubuntu something (I don't really care), two monitors and dumped down XFCE. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer selective DRC
If you add the attribute PCB::skip-drc to a layer, that won't be checked against DRC, and commections. Levente On Wed, 3 Aug 2011 23:56:23 -0700 Colin D Bennett colin-lp2cyvw5bivbdgjk7y7...@public.gmane.org wrote: On Thu, 04 Aug 2011 01:48:09 +0200 Kai-Martin Knaak kmk-g3ria76uax2m+vuuqax...@public.gmane.org wrote: Colin D Bennett wrote: A feature I have heard previously requested is to be able to mark certain layers as “no-DRC”. For instance, to allow special trace elements such as antennas that the DRC thinks are incorrect shorts between two nets. These should be omited from update_rats, rather than be ignored on DRC. The DRC as it is currently implemented, does not check for correct connectivty. It does not detect a short. Oh, that's right. I forgot since I tend to consider the Optimize Rats action and its feedback as a first pass of DRC, and the actual DRC action as a more detailed pass... but it seems like it would be ideal for a short to be detected by DRC. I think, this functionality would be best implemented with a flag don-t-check-connectivity added to the object. Put these antennas in a separate layer and make DRC special for this layer would still feel like a crutch. My current workaround is to actually connect the antenna input directly to ground on the schematic, so that pcb does not complain that the PCB trace antenna is a short. (See attached figure from the schematic.) For this specific and simple purpose, this works well enough for the moment. Regards, Colin -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: skpi_drc patch
On Mon, 20 Jun 2011 00:21:24 -0400 DJ Delorie d...@delorie.com wrote: Can you work on some documentation for it too? Sure. I can edit the pcb.texi document, but I have no clue where to put the related information. Or... shall I create an other document? Say... a text file? What is our documentation policy? Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: skpi_drc patch
On Fri, 17 Jun 2011 17:30:22 -0400
DJ Delorie d...@delorie.com wrote:
You want the (already global) AttributeGet() function.
l-no_drc = AttributeGet (l, PCB::skip-drc) != NULL;
This does assume that the attribute has *some* value, even if the
value is the empty string.
Thanks for pointing this out.
Attached is the new patch.
Levente
--
Levente Kovacs
http://levente.logonex.eu
diff --git a/src/find.c b/src/find.c
index eb4cac2..c5159ba 100644
--- a/src/find.c
+++ b/src/find.c
@@ -822,6 +822,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1169,6 +1171,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2901,6 +2905,21 @@ ListsEmpty (bool AndRats)
return (empty);
}
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer max_copper_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l-no_drc = AttributeGet (l, PCB::skip-drc) != NULL;
+}
+}
+
+
+
+
/* ---
* loops till no more connections are found
*/
@@ -2908,6 +2927,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool newone = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3350,6 +3370,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, ptr1, ptr2, ptr3, X, Y, Range);
@@ -3366,8 +3387,8 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB-Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum = max_copper_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum = max_copper_layer || ((LayerTypePtr)ptr1)-no_drc)
return;
}
}
diff --git a/src/global.h b/src/global.h
index daa82a9..08abbb8 100644
--- a/src/global.h
+++ b/src/global.h
@@ -303,6 +303,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
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Re: gEDA-user: Bug in PCB's Gerber generation?
On Fri, 17 Jun 2011 12:42:09 +0200 Gabriel Paubert paub...@iram.es wrote: - pcb_fprintf (f, X%06.0mmY%06.0mm\r\n, + pcb_fprintf (f, X%06.0mlY%06.0ml\r\n, Is this commited? Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: skpi_drc patch
Attached you can find the skip_drc patch for the current head.
It would be nice if it was checked in to git HEAD.
Thanks,
Levente
--
Levente Kovacs
http://levente.logonex.eu
diff --git a/src/action.c b/src/action.c
index 4f2e401..af93c19 100644
--- a/src/action.c
+++ b/src/action.c
@@ -6947,7 +6947,7 @@ find_element_by_refdes (char *refdes)
return NULL;
}
-static AttributeType *
+AttributeType *
lookup_attr (AttributeListTypePtr list, const char *name)
{
int i;
diff --git a/src/action.h b/src/action.h
index ee116e8..6dbaf2d 100644
--- a/src/action.h
+++ b/src/action.h
@@ -46,4 +46,5 @@ void warpNoWhere (void);
/* In gui-misc.c */
bool ActionGetLocation (char *);
void ActionGetXY (char *);
+AttributeType * lookup_attr (AttributeListTypePtr list, const char *name);
#endif
diff --git a/src/find.c b/src/find.c
index eb4cac2..cdd1063 100644
--- a/src/find.c
+++ b/src/find.c
@@ -94,6 +94,7 @@
#include set.h
#include undo.h
#include rats.h
+#include action.h
#ifdef HAVE_LIBDMALLOC
#include dmalloc.h
@@ -822,6 +823,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1169,6 +1172,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2901,6 +2906,22 @@ ListsEmpty (bool AndRats)
return (empty);
}
+
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer max_copper_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l-no_drc = lookup_attr ((l-Attributes), PCB::skip-drc) != NULL;
+}
+}
+
+
+
+
/* ---
* loops till no more connections are found
*/
@@ -2908,6 +2929,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool newone = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3350,6 +3372,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, ptr1, ptr2, ptr3, X, Y, Range);
@@ -3366,8 +3389,8 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB-Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum = max_copper_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum = max_copper_layer || ((LayerTypePtr)ptr1)-no_drc)
return;
}
}
diff --git a/src/global.h b/src/global.h
index daa82a9..08abbb8 100644
--- a/src/global.h
+++ b/src/global.h
@@ -303,6 +303,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
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Re: gEDA-user: Bug in PCB's Gerber generation?
On Fri, 17 Jun 2011 10:40:50 -0700 Andrew Poelstra as...@sfu.ca wrote: Good catch. I missed this in my test case as well, since I ran ``gerbv *.gbr'', forgetting about the .cnc file. I have committed your fix, checked that the output (of ALL files) is correct now, and fixed the test. Thanks for reporting! Thanks for commiting! -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Tue, 31 May 2011 21:59:04 +0100 Thomas Oldbury toldb...@gmail.com wrote: Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like each jumper to have a refdes and BOM entry if possible.) What I'd do is define a copper layer. Draw your jumpers on the that layer. Don't send the layer data to the fab house. Make sure you have mask openings on vias. Solder jumpers in the vias. I recommend using double sided boards. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL on non-accelerated hardware?
On Mon, 16 May 2011 10:17:34 +0100 Peter Clifton pc...@cam.ac.uk wrote: Anyway, it would be worth testing to check I tested it on my notebook. It has an Atom CPU with an intel GPU. With the GL renderer it can do 7fps. With the original renderer it is 7.2. No significant change. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: GL on non-accelerated hardware?
Hi, Is there any drawbacks running the GL renderer on system without hardware openGL support? Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL on non-accelerated hardware?
On Mon, 16 May 2011 10:17:34 +0100 Peter Clifton pc...@cam.ac.uk wrote: It would be slower than the non-GL version, due to the software emulation of the graphics calls. Your X11 driver might have had 2D acceleration for the non-GL version's rendering calls, for example. Even if the non-GL calls were software drawn, the GL ones are still more complicated. Anyway, it would be worth testing to check. I give it a test on my netbook later this week. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB crash
0x0097cdb4 in g_signal_emit_valist () from /usr/lib/libgobject-2.0.so.0 #24 0x0097d256 in g_signal_emit () from /usr/lib/libgobject-2.0.so.0 #25 0x004f53e5 in gtk_widget_activate () from /usr/lib/libgtk-x11-2.0.so.0 #26 0x003d39a0 in gtk_menu_shell_activate_item () from /usr/lib/libgtk-x11-2.0.so.0 #27 0x003d531f in ?? () from /usr/lib/libgtk-x11-2.0.so.0 #28 0x003cac64 in ?? () from /usr/lib/libgtk-x11-2.0.so.0 #29 0x003c4424 in ?? () from /usr/lib/libgtk-x11-2.0.so.0 #30 0x009658b9 in ?? () from /usr/lib/libgobject-2.0.so.0 #31 0x00967252 in g_closure_invoke () from /usr/lib/libgobject-2.0.so.0 #32 0x0097b5e6 in ?? () from /usr/lib/libgobject-2.0.so.0 #33 0x0097cc33 in g_signal_emit_valist () from /usr/lib/libgobject-2.0.so.0 #34 0x0097d256 in g_signal_emit () from /usr/lib/libgobject-2.0.so.0 #35 0x004f1636 in ?? () from /usr/lib/libgtk-x11-2.0.so.0 #36 0x003bca5d in gtk_propagate_event () from /usr/lib/libgtk-x11-2.0.so.0 #37 0x003bde07 in gtk_main_do_event () from /usr/lib/libgtk-x11-2.0.so.0 #38 0x006b239a in ?? () from /usr/lib/libgdk-x11-2.0.so.0 #39 0x001f85e5 in g_main_context_dispatch () from /lib/libglib-2.0.so.0 #40 0x001fc2d8 in ?? () from /lib/libglib-2.0.so.0 #41 0x001fc817 in g_main_loop_run () from /lib/libglib-2.0.so.0 #42 0x003be3c9 in gtk_main () from /usr/lib/libgtk-x11-2.0.so.0 #43 0x08119d4d in ghid_do_export (options=0x0) at hid/gtk/gui-top-window.c:2733 #44 0x080ab3c0 in main (argc=1, argv=0xb394) at main.c:1097 (gdb) Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 RES400.fp Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB crash
On Tue, 17 May 2011 00:10:07 +0100 Peter Clifton pc...@cam.ac.uk wrote: I'll try and fix it shortly. Peter, Thank you. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB GL Memory leak
On Sat, 14 May 2011 10:59:57 +0100 Thomas Oldbury toldb...@gmail.com wrote: After using PCB+gl for more than an hour or so on a basic 4-layer board, it is using nearly 3.5 GB of memory, slowing the system to a crawl and forcing it to page a lot of data. Is anyone else experiencing this issue? Do you have this issue with PCB compiled with --disable-gl ? Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autocrop.c vs. pcb (git head)
On Thu, 12 May 2011 02:32:00 +0100 Peter Clifton pc...@cam.ac.uk wrote: Edit autocrop.c and change ClearAndRedrawOutput (); to Redraw (); Thanks. In general, you need to rebuild every plugin when you build a new version of PCB from git. plugins poke internal APIs and data-structures, which do change from time to time. That is good to know. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: autocrop.c vs. pcb (git head)
I'm trying to load autocrop.so to my recently compiled (from git HEAD) pcb. What I get is this: dl_error: /home/leva/.pcb/plugins/autocrop.so: undefined symbol: ClearAndRedrawOutput Is there any way to tweak pcb and/or autocrop.c to work together? Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [spice] capacitor current
I want to simulate my low pass filters. So far, I managed to have my theoretical results. Now I want to know the currents of the capacitors vs. the frequency. I remember that the best way is to put 0V voltage sources in series of the capacitors, but I don't know how to get the AC current of the source. Could you provide any hint on this? The schematic attached. Any help is appreciated. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu PA_lpf.sch Description: application/geda-schematic ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [spice] capacitor current
On Sat, 16 Apr 2011 13:10:50 -0400 al davis ad...@freeelectron.net wrote: With Gnucap, just ask for the capacitor current. print ac i(c*) (this prints all capacitor currents) I use ngspice... will it work with that? -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [spice] capacitor current
On Sat, 16 Apr 2011 15:13:33 -0600 John Doty j...@noqsi.com wrote: If the refdes is V1, the current is V1#branch. Thank you. That did the trick. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OFF: capacitors for RF power amplifier
I'm currently designing a power amplifier for the HF (3-30MHz) radio band. I am selecting capacitors for the low pass harmonic filter bank at the output. My question is what kind of capacitors should I use? I apply not more then 100V of say 30MHz maximum. My best bet is to use X7R capacitors with as much DC voltage rating as I can get. I don't know if there's any connection between the DC and AC losses. Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
On Mon, 11 Apr 2011 16:58:37 +0200 Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de wrote: What value do you need? Try NP0/COG type, even if substantial more 120pf ... 1.5nF expensive. I guess the X ceramic will introduce more harmonics than it will filter out... Thanx for the hint. -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Wed, 06 Apr 2011 22:37:05 -0500 John Griessen j...@ecosensory.com wrote: Yes, Levente's way of handling that after the fact is practical and what I like to do, since then you keep all your DRC's working against error, and have one more step to do after DRC complete. Perhaps that method could be scripted with a makefile? Can commands from a script make a layer invisible and not part of DRCs? If so, then the starpoint connecting copper could be on a special layer for that purpose alone, and merged in by using visibility or not. Yes. There is a patch which adds the ability to ignore DRC. http://archives.seul.org/geda/user/Mar-2011/msg00096.html Else merge it in with gerbv as RS274-X only. I don't like this idea. You have to have control over connections at least at PCB level. I'd have it in gschem level. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Thu, 07 Apr 2011 14:10:02 +0200 Kai-Martin Knaak kn...@iqo.uni-hannover.de wrote: This patch uses layer attributes to differentiate. IMHO, for the split ground use case an attribute of an object (track, or pad, or pin) would be more appropriate. Properties of objects can be attached to a footprint. So you can have a star point symbol in the schematic. This would be impossible with layer attributes. Ah ok. Sorry for the missunderstanding. I thought one should put the short on a layer, that is not checked against DRC. So you don't have the DRC error. This approach is the subconductive layer in CR5000. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Tue, 5 Apr 2011 22:30:33 +0200 Markus Traidl g...@traidl.de wrote: The library department at my company defined a special component for that purpose. We have a 2, 3 or 4 Star Symbol for that. To that symbol a special footprint will be attached where the pins are connected. The component is a smd device and I can place it in the layout at the top or bottom side. Yes. But the CAD software you use have the concept of starpoint. gEDA doesn't. I thought that we could make a footpirnt with pads on top of each other, but that would bring more problems in than actually it solves. So far, the best option is to place a real component, and short it with a line, or physically with a solder blob. I prefer a 0603 resistor. Later I can cut the wires, and solder a 0Ohm...etc. For mass production, one can just let out the resistor from the BOM. When I used the CR5000 at my former job, we had lot's of troubles with starpoints. I think the workaround in gEDA is still a good way to go. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Mon, 4 Apr 2011 23:30:21 -0700 Russell Dill ru...@asu.edu wrote: The common way to track common ground planes seems to be to place a jumper between the planes so that the netlist can be sane. This requires a component to be placed on one of the outer layers of the board, which is a bit of an annoyance. Is there any other way of doing this? Maybe some kind of hacked component on an inner layer? What I do is I place a 0Ohm resistor, and when the layout is ready, I short it with a line. This will give DRC error, but I ignore it. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Tue, 5 Apr 2011 13:11:25 -0700 Russell Dill ru...@asu.edu wrote: Perhaps I'll go with a solder blob jumper. A drawbridge component in PCB that is just a special type of trace would be really nice. Yeah. I miss the concept of the star point. -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [gschem] netname refactor?
hi, Is there any way in gschem (or gattrib) to refactor netnames in a given set of schematics? Thnaks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: skip drc
On Thu, 10 Mar 2011 17:47:58 + Ineiev ine...@gmail.com wrote: Thank you! it would be nice if someone added corresponding bits of documentation to the patch. Could you please upload it to the tracker? It might get more attention. I'd really see it checked into the HEAD. Every time I compile a new PCB, I have to patch. Browsing the source, I see that there is some movement to support non-copper layers. I don't know the state of that. Still I think it is a good feature. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: skip drc
Hi,
I have rewritten the skip_drc patch (originally written by Ineiev) to apply
to the current git HEAD.
The original patch can be found here:
http://www.seul.org/pipermail/geda-user/2010-September/048721.html
My patch is attached.
Levente
diff --git a/src/action.c b/src/action.c
index de2738e..2ad20b1 100644
--- a/src/action.c
+++ b/src/action.c
@@ -7001,7 +7001,7 @@ find_element_by_refdes (char *refdes)
return NULL;
}
-static AttributeType *
+AttributeType *
lookup_attr (AttributeListTypePtr list, const char *name)
{
int i;
diff --git a/src/action.h b/src/action.h
index ee116e8..ca1cbc3 100644
--- a/src/action.h
+++ b/src/action.h
@@ -46,4 +46,7 @@ void warpNoWhere (void);
/* In gui-misc.c */
bool ActionGetLocation (char *);
void ActionGetXY (char *);
+
+AttributeType * lookup_attr (AttributeListTypePtr list, const char *name);
+
#endif
diff --git a/src/find.c b/src/find.c
index 615659d..167f149 100644
--- a/src/find.c
+++ b/src/find.c
@@ -94,6 +94,7 @@
#include set.h
#include undo.h
#include rats.h
+#include action.h
#ifdef HAVE_LIBDMALLOC
#include dmalloc.h
@@ -822,6 +823,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1169,6 +1172,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)-no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2896,6 +2901,19 @@ ListsEmpty (bool AndRats)
return (empty);
}
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer max_copper_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l-no_drc = lookup_attr ((l-Attributes), PCB::skip-drc) != NULL;
+}
+}
+
+
/* ---
* loops till no more connections are found
*/
@@ -2903,6 +2921,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool newone = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3345,6 +3364,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, ptr1, ptr2, ptr3, X, Y, Range);
@@ -3361,9 +3381,10 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB-Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum = max_copper_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum = max_copper_layer || ((LayerTypePtr)ptr1)-no_drc)
return;
+
}
}
else
diff --git a/src/global.h b/src/global.h
index 0420a18..8460714 100644
--- a/src/global.h
+++ b/src/global.h
@@ -301,6 +301,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
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Re: gEDA-user: Skip DRC on outline layer
On Thu, 10 Mar 2011 13:34:17 + Thomas Oldbury toldb...@gmail.com wrote: I am using an outline layer in PCB. It complains of DRC violations when the outline is too close to vias. Is it possible to get it to skip DRC on these? I theory, yes. You should apply the patch found in my last message. See the instructions found in here. http://www.seul.org/pipermail/geda-user/2010-September/048721.html However, it is not a good idea to place vias close to the edge of the board. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: net attribute for power I/O, clean appearance? (no “:1”)
On Tue, 8 Mar 2011 17:37:32 -0800 yamazakir2 yamazak...@gmail.com wrote: I wrote a custom netlister over a year ago that suppose this and hierarchical netlisting. http://spnet.code-fusion.net/ Can your netlister output a netlist for gEDA-PCB? -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breaking up power planes
On Sat, 19 Feb 2011 12:37:53 -0500 DJ Delorie d...@delorie.com wrote: I use the polygon editor. With the new Holes tool, it's a lot easier. You mean moving the vertex of a polygon? And waht are you doing when it is hidden by a clearance? Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
Hi, That is very good, that you start working on the layer structure of PCB. I'd turn the mask layer as a negative layer by definition. I had hard time when I was designing my first 4 layer board, because there is no way to switch on an inner layer with the inner pads of components without displaying all the components on the outer layer. Yes, I'd implement paste layers and non-conductive mechanical layers. Yes, get rid of the current grouping mechanism. I am really supporting this movement. Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Status of gEDA - gschm, pcb?
On Thu, 10 Feb 2011 18:09:21 + (UTC) three_jeeps jjhu...@gmail.com wrote: Where can I find the most up to date symbol library for gschem? (Do ppl actively contribute to it? For example, are there libraries for Atmel and TI processors?) I'd say... a lots of places. I use the mentioned gedasymbols.org, and I have my own library as well. http://git.logonex.eu/?p=library.git;a=tree;f=electronic Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: adding information to gerber output, anyone?
On Wed, 09 Feb 2011 23:29:52 +0100 myken my...@iae.nl wrote: Hello all, I didn't see any reply on my question so I guess the very busy and overloaded knowledge base of this list didn't find the time to look at it, so please consider this a friendly reminder ;-) Or am I asking a very silly question? (didn't find a answer by google) The question was: I was wondering if it is possible to add more information to the fabrication layer output of the gerber export (*.fab). Added: I like to do this through PCB, is there a variable I need to set? Or a command executed? So that every time the gerber is generated by PCB this information is stored automatically in the gerber fabrication layer output file. I like to add the copper thickness for that specific pcb (preferably for ever layer individually (inner/outer layer)). So far I came up with adding this information to the outline layer (but that doesn't end up in t A text on copper layers? Outside the board area? -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating a polygon without a pruned center
On Wed, 02 Feb 2011 13:13:16 -0500 David Carr d...@dcarr.org wrote: Hi all, Forgive me if this has been asked before, but my searching didn't uncover a solution: Here's an image of a board with a component and solder side ground planes: http://oscar.dcarr.org/tmp/board.png I'd like for the top ground plane (tan) to not be pruned in the center so that I can connect the dangling pieces to the solder side ground plane. Is there any way to do this? I think you want to do this: select the polygon, issue the command Morphpoly(selected) you can do this by pressing the : key I guess. Thanks, David Carr ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB antenna pattern
I am designing a zigbee interface, and I am using an inverted F antenna out of PCB pattern. The problem is that the terminals of the antenna pattern are shorted (well not on 2.4GHz), so I don't have any clue what to put to the schematic. So far, I simply grounded the antenna pin of the transceiver, but it can lead to misunderstanding. The other option is to have a two-pin symbol, but the pattern will cause short circuit when running the DRC. Any suggestion? Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: 100 inches?
Hi list, I discovered that PCB (the GTK HID) doesn't let me define boards greater than 10 mils. Is it intentional? N.B. I can make the board larger by editing the bcb file manually. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to make a foot print
On Wed, 5 Jan 2011 10:00:24 -0800 Colin D Bennett co...@gibibit.com wrote: [...] Actually, I am impressed with the flexibility of your footgen.py script. It looks like you've created many different types of footprints using it. I think we miss-understood each other. Or let me say I wasn't clear enough. footgen.py was written by Darrell Harmon. I'm just a user, who provided patches. http://dlharmon.com/geda/footgen.html However, unfortunately for me at least, I cannot use it for the majority of my footprints. Most of my custom footprints require individualized design. For instance: - SMT LED footprints with special oversized pads as specified by manufacturer for thermal dissipation. A good point. Please share your footprints if you can! - FFC/FPC connector, proprietary 1.25 mm SMT header, etc. with special extra pads for mechanical support, and silk screen indication of reference pin (e.g., arrow for pin 1). - SMT aluminum electrolytic capacitors, two-pin polarized devices that should have special silk screen including a beveled corner and + symbol by one pad. Well.. I became too lazy to do that. I put a + mark by hand to the layout, when someone else solders the PCB. I, and the pick and place machine know the polarity. :-) - Illuminated push-button, 5 pin through hole with non-standard pin arrangement. My point is not to take away from the usefulness of your script, but to show that many footprints (I would even say most) require manual design for the best results. The tool, pcb, should make this easier and faster for users. Yes. For example, I did footprints for the Tag-connector. http://www.tag-connect.com/website_html/what_is_it.html It was made by hand. For me, the most difficult part of drawing a footprint in pcb is getting various dimensions from part specifications into the pcb drawing as I create a footprint. If pcb had a dimensioning tool that could place dimension measurements on the drawing as one is working on it, then that would make my job much faster. As it is, I always sketch the footprint by pencil on graph paper and figure out dimensions from there based on part specifications, then transfer these into pcb as I draw, making heavy use of the Ctrl-M measurement tool. Yes. I too miss some GUI features, like put this 2cm away, copy that 10x with 100mil spacing, etc. I will say that I am getting much more confident and much faster at creating footprints in pcb as I gain experience with it, and I'm no longer scared when I face a new part with an odd footprint. :-) Yes! YES! That is the way! I am happy to hear that! :-) -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Voltage symbols and Spice
On Mon, 03 Jan 2011 23:52:12 +0100 Johnny Rosenberg gurus.knugum-re5jqeeqqe8avxtiumw...@public.gmane.org wrote: Den 2011-01-03 23:37:23 skrev John Doty j...@noqsi.com: [...] A bit off topic, but is it recommended to call something ”5VA” in this case? Couldn't it be confused with the fact that VA means Volt-Amperes, which is what you measure apparent power in? I would not start a netname by a numeric character (I don't have any reason why). I call this kind of nets as AVCC and DVCC. When I have more than one supply net I call them AVCC1, AVCC2, etc. I know this is a bit uncommon, because you have to have a table somewhere (at least one in your mind) which links which supply is what. AVCC2=5V, AVCC1=12V etc. Same goes for ground connections. AGND and DGND. HTH, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: European symbols?
On Fri, 31 Dec 2010 13:05:41 +0100 Johnny Rosenberg gurus.knu...@gmail.com wrote: So I am the only one that use still them? And why did they use a small circle for the NOT function at the output if the plotters had difficulties plotting them? They seems to be used pretty much in my country anyway. I used them for eight years at a company a few years back. When I was working for The Big Red German Automotive Electronic supplier company back in 2008, they were using rectangular shapes for OPAs as well. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: New year
Happy new year all! Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Seeing pin numbers in PCB
On Wed, 29 Dec 2010 23:48:00 -0800 (PST) Oliver King-Smith oliver...@yahoo.com wrote: I can measure the size of stuff using gerbv (there may be a better way to do this in pcb) Use Ctrl+M to set an origin. You have relative coordinates printed next to the cursor position. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to make a foot print
On Wed, 22 Dec 2010 17:29:24 -0800 Colin D Bennett co...@gibibit.com wrote: You are not alone. Making footprints in pcb takes a lot of practice, for me a least. I have made many footprints in pcb over the past couple of years and still I have to refer to guidelines, if I haven't made a footprint for some time and have gotten rusty. I recommend using footprint generators for the majority of the footprits. I use the footgen.py python script. I have created most of my footprints with the script. The inputs for footgen can be found here: http://git.logonex.eu/?p=library.git;a=tree;f=electronic/autolib/footprints;hb=HEAD All of my footprints including the generated and the manually drawn ones is located here: http://git.logonex.eu/?p=library.git;a=tree;f=electronic/footprint;hb=HEAD Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bugs, warts and feature requests (3)
On Thu, 23 Dec 2010 12:43:45 +0100
kai-martin knaak kmk-g3ria76uax2m+vuuqax...@public.gmane.org wrote:
• pcb feature request: Please put all the gerbers in a dedicated
subdir of the working directory by default. The name of the subdir
should be configurable.
• pcb feature request: Optionally zip all gerbers and the cnc files
to yield a single file that can be sent to the fab. The name of the
zip file might contain the current date.
The two can be done by hand or scripts or Makefile, etc. Like I did (a
Makefile snipet):
gerber: ${PCBNAME}.pcb
${PCB} -x gerber --gerberfile ${PCBOUTDIR}/${FILEBASE} ${PCBNAME}.pcb
later in the Makefile:
output: clean_output gerber pdf
cp ${FILEBASE}.pdf ${PCBOUTDIR}
tar -jcvf ${FILEBASE}_${DATE_S}.tar.bz2 ${PCBOUTDIR}
rar a ${FILEBASE}_${DATE_S}.rar ${PCBOUTDIR}
Levente
--
Levente Kovacs
http://levente.logonex.eu
___
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Re: gEDA-user: Resistor values…
On Sat, 25 Dec 2010 00:50:07 -0600 Vanessa Ezekowitz vanessaezekow...@gmail.com wrote: * If the part in question can usually be described by a single value, for the purposes of the signal flow in the schematic that is, then give it a default of value=0. That is bad. You have to think twice that is it a 0 Ohm resistor, or do I missed to attach normal value of that device? * If it is a discrete part that is specified entirely by its part number rather than a measurement, like a diode or a transistor, then pick a reasonable default; value=1N914 or value=2N. Again. Is it the default or real? Nobody knows. * If the part is something like a logic IC, use the standard name of the part in the fastest commonly available series for that particular gate; value=74F74 or value=74HCT245. * If none of these fits, then leave the value= attribute off entirely, since the user would have no choice but to get creative anyway. That will make gnetlist to crash! :-) Believe me I tried! I spent nights manually seeking for this. Don't do it. What I do is I keep my symbols light. Sometimes it doesn't even have pin-numbers! After I made my design, I update all my symbols, and attributes with an updater script, which pulls everything from a MySQL database. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Resistor values…
On Wed, 29 Dec 2010 13:18:24 -0500 DJ Delorie d...@delorie.com wrote: I regret that I made that comment. I wish it weren't so common. Such wars are a pointless waste of time and serve only to drive valuable contributors away. Soon, the only people working on gEDA/PCB will be those who enjoy complaining, as there will be nobody left willing to wade through the bitter arguments and actually write code. I agree with you. But I think that it is a fact that there are lots of wars. We should really concentrate on work. So let me make this perfectly clear - if you're not willing to write code, your complaints about how others write code will fall on deaf ears. As far as I know, those of us who DO write code, do it for purely selfish reasons - we benefit from our own work. We've said this before, it should be no surprize to anyone. I think in an open source domain, users and code writers are pretty much the same. I consider myself a user, but there is code in PCB of mine. I've written a few scripts for gEDA/PCB as well. It is not much, I know. I am willing to write code, but I'm not good at code writing (Never tried it seriously though). OTOH if you have suggestions on how to make gEDA/PCB better - easier to use, more functional, etc - feel free to voice them. If you can back them up with a solid design and usability models, that's even better. Discussions about the details and caveats are to be expected! Yes! I meant war that I feel everyone dumps their experience, favourite tool, etc. without working the problem. But as soon as the discussion degrades into yet another bikeshedding, the instigators of said bikeshedding have lost all credibility with me. New users - ask your questions without regret. There are no bad questions. Harvest the answers that are useful and ignore the crap. Yes. The let us start a Vi vs. Emacs comment was a joke. -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Christmas wishlist
On Sat, 25 Dec 2010 10:10:16 +0100 Stephan Boettcher boettc...@physik.uni-kiel.de wrote: Merry Christmas! Same to you and to the community! == PCB wishlist == The recent (and some not so recent) discussions made me think about how development of PCB could proceed to solve some of the feature request, in a future-proof way. This is what came up in my mind. === Make all layers explicit === Everything shall be layers. Silk, paste, mask layers shall be exlicit. Via-layers typically only contain filled circles, the holes. A via-layer defines to which subset of other (copper) layers it connects to. A Via is a hole on a via layer plus copper circles on all copper layers. Vias-layers will probably not be implememted before macros (below) are available. Until then, they may be special case macros, like they are now. The old layergroup mechanism will be replaced by defining for a copper layer to which other layers it electrically connects, in the same way as a via-layer does. File format/connectivity does not require different layer types. There is no difference between via-, copper-, graphical layers. Layer types steer footprint import, routers, drc, ... Those can be arbitrary attributes, understood by the respective HID engines. Yes. That would be nice === Make elements small layouts === An element shall be defined as a small layout, same syntax, same semantics. A pin/pad shall be an attribute on any piece of copper (which may then be drawn dark gray by the HID). On footprint import, some layer mapping needs to happen, so that generic pads and pins appear on and connect to the right layers. I like this idea. Then, there would be only one file format. In the same way, we could import other PCBs to e.g. a panel pcb. Only grouping needs to be implemented. The same way, we could define padstacks as well. === Introduce the concept of classes/macros === A macro is a sub-layout that can be instantiated at a higher level, positioned and rotated. Footprints and via-stacks are defined as macros. A via is defined as a via-stack macro instance, an element initially typically contains a single footprint macro instance. The HIDs will implement Copy-On-Write by default, so we can still change individual vias, pads, ... Or descend into the hierarchy, and edit the macro. COW can either create a new macro (default for Vias?) or copy the macro contents into the Element. Yes! === Hierarchical layout === Elements may contain Elements. Either with hierarchical netlist, or with flattened refdes, like gnetlist generates. When the higher level elements are defined as macros, a fully hierarchical layout is possible. === Convert the internal units from decimil to nanometer === Start by defining a variable (=254e-9), and make all output HIDs use that to convert to PS-point or gerber units or whatever. Then introduce attributes of the layout file which sets the internal units and the default unit of the file. Use 64bits integers. === ASIC HID === When all that is implemented, an HID(-mode) optimized for chip design is only a small step. Well, I'd focus on PCB layout for the first time. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Christmas wishlist
On Sat, 25 Dec 2010 18:14:27 +0100 Stephan Boettcher boettc...@physik.uni-kiel.de wrote: line layer=top ends=round 132 150 132 250 /line I'd add a current netname to copper objects line layer=top ends=round netname=GND 132 150 132 250 /line Or something like this. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Christmas wishlist
On Sat, 25 Dec 2010 22:07:16 +0100 Stephan Boettcher boettc...@physik.uni-kiel.de wrote: This is fundamentally different from how PCB treats copper, connectivity and netlist now, and restricts the flexifility of the tool that results from how it works now. So, that would be a separate set of changes. The current netname only as documentation? The thing made post my previous message, is that it is very annoying when unconnected line stays on PCB, and there is no chance to connect anything to it. Even to the net it was formerly connected. Other solution to this would be to let anything to be connected to copper objects (Via, line) when it is not connected to anything. Anyway, a flexible format (like xml) can accomodate everything, syntactically. I was thinking mostly about semantics, now. Ok, I like your ideas. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
On Sun, 19 Dec 2010 22:12:30 -0500 DJ Delorie d...@delorie.com wrote: I changed the overlapping vias test in two ways... 1. Via copper is now allowed to overlap when vias are created. Via *drills* are not. 2. Vias which violate this rule in a *.pcb file are preserved at load time. Thus, PCB will make a modest attempt at preventing users from making vias that might be difficult to manufacture, but if the user finds a way around the restriction, PCB will let them get away with it. Simply moving an existing via is an adequate way around it. I think this should trigger a non-copper DRC error. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bugs, warts and feature requests (2)
On Tue, 21 Dec 2010 13:17:50 +0100 kai-martin knaak k...@familieknaak.de wrote: • pcb missing feature: A GUI way to do FreeRotateBuffer() This does not have to be driven by the mouse. In many cases keyboard input would be preferred. yay! And it wold be nice to have absolute and relative moves as well. Like a nice little dialog with the following move selected items absolute/relative x.y • gschem missing shortcut: [ctrl-a] -- select all This is an almost universal shortcut that should be implemented in gschem too. yay • gschem wart: The single attribute dialog is blocking ( modal). Please let it behave like the multi attribute editor. yay • gschem wart: The GUI prevents the creation of pins with zero length. However, these pins work like a charm when done in a text editor. nay • gschem usability improvement: show the file name of the symbol in the multi attribute editor -- preferably in the header I don't understand that. • pcb feature request: Make minimum track distance when off grid optional. yay -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, 9 Dec 2010 14:45:47 +1100 Stephen Ecob silicon.on.inspirat...@gmail.com wrote: Boiling it down greatly, Clif and Kaimartin are both asking for more attention from the maintainers. Has the gEDA community given thought to the possibility of paid maintainers ? I'm a relative newbie, please let me know if this has already been thrashed through. If it is worth discussing, I guess the big questions are: 1. Would any of the existing maintainers be able to devote more time to gEDA if they had financial support to do so ? 2. Could we raise enough money to make this viable ? Why don't we put banners to our webpage: We need developers! We need contributors! or something like that. There might be some out there, who would spend more time on the project. I've seen this on other FOSS pages. Just an idea. -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FUNDING
On Mon, 13 Dec 2010 09:02:15 + andrew whyte ajwh...@gmail.com wrote: Hi Everyone, I realise that I am joining a very established thread, but I'd like to put forward 2 cents worth. Please don't be offended if what I'm saying isn't the same as your opinion. I have used gEDA as the main (but not only) tool for EDA in my company for two and a half years, I don't fully understand it - but I can use it for everything that I need to do (principally draw schematics layout PCBs). I know companies that would like to use gEDA, but must support a back catalogue of designs that were created using other tools. That is to say that they have no choice but to pay for their EDA tools. These people do pay alot for thier tools, but they have no chioce! As a gEDA user, I am not tied to it, and can use whatever software suits me. In an open software model, the companies choose to use a given tool because it is the most cost effective in an open marketplace. Whilst anyone who uses the tool is grateful to those who have created it, they don't owe anything to the developers who have published their source. Guilt complexes won't work on any shrewd business person; and I doubt those tactics are what we want to be doing if we are to encourage the adoption of gEDA as a standard tool in the industry anyway. This sounds very negative, so I'll try to describe how I think funding might be found. Because of the GERBER standard, FOSS stands a chance of creating competitive tools for EDA, this is much more difficult in areas where open standards don't exist. I don't know if this has come up before in this thread, but my opinion is that we may be able to shake down the relevant industry groups government bodies. gEDA is special because it opens the marketplace to SMEs. It seems to me that empowering individuals and companies is the purpose of groups like the IEEE ( the IET in the UK). Maybe they could spare some money for the development of a tool that could bring a new standard to the development of electronic products? Right now there is a big push to help small business hit by the recession - perhaps governments might have the right buttons pushed too? FOSS is about community and openness and opportunities for all... right? Negotiating with IEEE is a good idea. I wouldn't ask for money (first time), but I'd ask them to put links to our website, or give them lectures about the project. I wouldn't go with a commercial company. We should stay open, and neutral. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, 9 Dec 2010 21:55:37 +1100 Stephen Ecob silicon.on.inspirat...@gmail.com wrote: Good, we've established that money could help to improve gEDA :) What I'm *very* unsure of is whether we could raise enough to make a difference. Does anyone have any idea of how many of us make commercial use of gEDA ? As a business user I face the fact that if I choose to use commercial EDA software such as Altium then I'll pay $4K every year for a program that will make me go prematurely bald as I pull my hair out in frustration at bugs that I have no power to fix. I've chosen to use free software instead. Yes, PCB has many shortcomings - but I'm free to fix them. My business is just starting up, so cashflow is tight. At this stage I'm more inclined to contribute to gEDA by coding myself than by paying others to do it for me - but in the future I may have less time and more money. At that stage paying others to improve gEDA would make good business sense. I could easily justify $4K per year, perhaps more - businesses who use Cadence or Zuken are probably paying $20K per year. One business contributing $4K per year is almost insignificant - but 10 could achieve something worthwhile, 50 could fund a full time developer. But it's nothing more than a pipe dream unless there are others out there who think the same. Does anyone else think the same ? I've decided that when I make money with gEDA, I'll give some percentage back to the developers. I even felt a bit strange (sorry my English ends here) when I first sold a hardware to my fellow guy for $30. How can you ask money for something created by free software? Then I said that I ask money for my work. Afterwards, I donated some to the Linux found (more than $30 :-). In the other hand, I think we should concentrate on the priorities first. I know it will hurt some, but We have 2 (or more) autorouter. I know that they are nice, and usable, and required but we have rounding errors in the code as well. Which is important? We have 3D view, but we don't have negative layers. I'm sorry, if I annoy anyone. I just want you to see my point. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: component names hide all
On Thu, 09 Dec 2010 09:46:56 +0100 uv u...@peterpapp.com wrote: Dears, Is there any simple way to hide all component numbers on the board? Settings-Hide names -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in fiducials blocking solder paste
Hi, Attached is a fiducial example. Enjoy! -- Levente Kovacs http://levente.logonex.eu fidu.fp Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Wed, 01 Dec 2010 19:38:32 -0500 Ethan Swint eswint.r...@verizon.net wrote: Sorry for my late reply - but have you tried the BOM export (File - Export Layout-BOM). One of the output files from that is an XYRS (X, Y, Rotation, Side) text file. http://archives.seul.org/geda/user/Feb-2009/msg00351.html Yes, but as I pointed out earlier, it doesn't do what I want. It averages the coordinates of the pins/pads, and it is not good when you working with asymmetric element such as SOT223. cheers, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB vs. cursor position
Hi, Is there any way to get PCB *NOT* to save cursor position? Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Thu, 02 Dec 2010 12:21:00 -0500 Rick Collins gnuarm.2...@arius.com wrote: If the XYRS file output does not output proper centroids, I see this as a major issue. If they are not outputting the correct value for asymmetric parts, how do you see the centroid being defined exactly? Most of my footprints are generated, and the zero point is the center of the package. I think they are OK for pick point. There are other footprints, which I made manually. In that case, I imagine the best pick point and I put the zero point there. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB vs. cursor position
On Thu, 2 Dec 2010 12:40:53 -0500 DJ Delorie d...@delorie.com wrote: Aside from editing the sources? No :-P Okay... :-) Cold you tell me any point where to look? Thanks... Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Thu, 2 Dec 2010 12:40:39 -0500 DJ Delorie d...@delorie.com wrote: So change it :-) I rather write scripts than modify the source... Please note that my script now calculates placement angles as well! :-) -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB vs. cursor position
On Thu, 2 Dec 2010 14:41:01 -0500 DJ Delorie d...@delorie.com wrote: src/file.c WritePCBDataHeader() Thanks -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Thu, 02 Dec 2010 15:44:34 -0500 Rick Collins gnuarm.2...@arius.com wrote: I'm not asking about the pick point. I'm asking about the centroid. They are completely different things. As I think I said, the centroid is to tell the assembly house where to put the part. The pick point is a point on the part where the machine will attach the nozzle and has nothing to do with the position where the part is to be placed. Further, regardless of how you set your files, the pick point is selected by the assembly house to optimize how they pick the part. You have no way of knowing where this will be. That is good news. The centroid needs to be a spot on the part that everyone knows without requiring it to be explained. Unfortunately for oddly shaped parts, it does not seem to be well understood how to select the centroid. One document I have from Screaming Circuits says it is the center of the part including the pins and the body. I have yet to be able to find this info in an IPC document. The IPC document seems to leave out some other important info about rotations. You would think they would figure out this is a problem and fix it... I can't say if your centroids will give you trouble, but from what you are telling me, you are not defining them correctly. From what I have read, I'm not sure PCB does it correctly either. I found some references on the web that says they use the geometric center of the pins not including the package. I don't think that is right. Screaming circuits is not the ultimate reference for defining how this is to be done, but they have a document that covers all the bases and is easy to understand. In fact, when I pointed out that they had a discrpancy with the IPC docs, they immediately fixed it and put the updated doc on their web site. www.screamingcircuits.com Okay. Thank you for pointing out all that. I think I'll be fine with the centroids. It states that the centroid must be the center of the entire footprint. It gave me some information about the rotating angle. I go and tweak my script. Thank you again, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Wed, 01 Dec 2010 01:58:06 +0100 kai-martin knaak k...@familieknaak.de wrote: Is the goal you achieve a common one? If so, can the script be included in the distribution of pcb in some way, please? It would spare other users the need to reinvent the wheel. This is a good question. Well, I made a few scripts in the past. They are here: http://git.logonex.eu/?p=utils4geda.git;a=tree If someone thinks that some of them are worth distributing along with gEDA/PCB, then it can be downloaded from here. However, I don't think they should go with PCB. Instead I'd create a PCB goodies package, which would be full of scripts, and user contributed stuff. Even, it would be enough to have a web page full of user contributed links. Just my EUR 0.02 Note that the script now outputs the placement side of a particular element as well. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: New autorouter high effort mode
On Sat, 27 Nov 2010 08:53:38 +1100 Stephen Ecob silicon.on.inspirat...@gmail.com wrote: For my HE autorouter hack I have in mind to fork() off extra processes so that all of my CPU cores can run separate autorouter instances. As HE has an unbounded run time I'm thinking that the main PCB process should simply hang on to the UI to serve occasional display update requests from the other processes, and to kill off the auto routing processes on user command. I think it is enough to make multiple threads. They can run on different CPU cores. But I'm not usre. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB: coordinates and angles of the components
I have to put one of my boards into mass production. The factory require a text file which includes the coordinates of the SMDs, and their angle. The zero point must be at the lower left corner. I know the XY output of PCB, but it messes up the components with asymmetric pin layout (for example a SOT223 package). My wish would be to have some script which calculates the angle as the XY exporter, and simply put the coordinates of the component to the output file. Has anyone made such script? It would be great help. BTW... wouldn't it be nice to put the rotation angle of the components as comments in the PCB file, so it could be used later? Then there'll be no need such magic at the XY exporter. Just an idea. Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Tue, 30 Nov 2010 12:22:43 +0100 Kovacs Levente leventel...@gmail.com wrote: I have to put one of my boards into mass production. The factory require a text file which includes the coordinates of the SMDs, and their angle. The zero point must be at the lower left corner. I know the XY output of PCB, but it messes up the components with asymmetric pin layout (for example a SOT223 package). My wish would be to have some script which calculates the angle as the XY exporter, and simply put the coordinates of the component to the output file. Has anyone made such script? It would be great help. Answering to my own email... Thanks to open formats, I did it in an hour. The script searches for a special footprint (attached), and takes its position as reference. -- Levente Kovacs http://levente.logonex.eu refpoint.fp Description: Binary data gen_element_coords.pl Description: Perl program ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: creating new symbols
On Mon, 29 Nov 2010 19:34:36 +0100 Michał Dwużnik michal.dwuznik-re5jqeeqqe8avxtiumw...@public.gmane.org wrote: there's no visible clue in case of such error - segfault does not seem very elegant... You should file a bug report on SF project page. gEDA should not crash. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC check workaround for outline layer
On Tue, 23 Nov 2010 15:56:39 + Peter Clifton pc...@cam.ac.uk wrote: This is probably not something we'd commit as is to PCB, as for some cases, DRC warnings on the outline layer could be useful, but Bdale was looking for something along these lines on IRC yesterday. I'd love to see that patch in HEAD. Or maybe that version, which looks for layer attributes. Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC check workaround for outline layer
On Wed, 24 Nov 2010 12:04:44 + Peter Clifton pc...@cam.ac.uk wrote: I recalled there was a patch someone write which looked for attributes, but when I trawled through the Sourceforge mire for that patch, I couldn't find it, so knocked the above one out. I think it was this one: http://archives.seul.org/geda/user/Sep-2010/msg00052.html Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: exporting single pcb layers
On Fri, 19 Nov 2010 23:56:50 +0900 timecop time...@gmail.com wrote: In my windows PCB CAD I think the OP wants information about gEDA's PCB editor and not your PCB CAD. Your comment is irrelevant. -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: solderpaste on pads for BGAs
Hi all, I'd like to ask if solder-paste is necessary for BGAs. The BGA already has some tin, so the solder-paste on the pad wold be a bad idea. Do I miss something? Thanks, Levente -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problems compiling PCB Release 20100929
On Wed, 10 Nov 2010 21:19:20 + Peter TB Brett pe...@peter-b.co.uk wrote: Ignore me, I'm an idiot. Y'all are talking about PCB, not gEDA. Sorry! AFAIK, there are similar lines in the README of PCB as well. -- Kovacs Levente leventel...@gmail.com Voice: +36705071002 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist crash
On Sat, 13 Nov 2010 13:07:23 + Peter TB Brett pe...@peter-b.co.uk wrote: Could you please post a bug to the bug tracker, so we don't forget about this? Sure... -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
