Re: gEDA-user: verilog - gschem

2011-07-08 Thread Ouabache Designworks
 Message: 1
 Date: Thu, 07 Jul 2011 15:31:44 -0700
 From: [1]fr...@frankthomson.net
 Subject: gEDA-user: verilog - gschem
 To: [2]geda-user@moria.seul.org
 Message-ID:

 [3]20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97.wbe@e
 mail04.secureserver.net
 Content-Type: text/plain; charset=utf-8
   I've looked at the mailing list archives and seen people ask but
   haven't seen if anyone has code to take a verilog netlist and
 create a
   gschem file from it. I don't care about what the schematic looks
 like,
   can be ugly. I just need to get it into gschem format to run
 through
   gnetlist to a different netlist format.
   Why? Well, I'm getting files from different tools (gschem along
 with
   tools from other sites) and the common format I can generate is
 verilog
   which works out well because I'm using icarus verilog for
 simulation.
   The next step in the process requires running the design through
   gnetlist but since gnetlist only reads gschem files as input I
 need to
   get the verilog files to gschem to feed gnetlist.
   -Frank
 --

   The only difference between that and and PCB layout program is that you
   don't care about trace width and you can cross lines  without
   connecting them.
   What you need is a symbol generator ( trivial script) , and autoplacer
   ( trivial
   unless you want your result to be understandable and easily routed) and
   a autorouter ( PHD project and maybe a career).
   You should be able to do a script that generates a graphical rats nest
   that
   had all the correct connections. That should work.
   John Eaton

References

   1. mailto:fr...@frankthomson.net
   2. mailto:geda-user@moria.seul.org
   3. 
mailto:20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97@email04.secureserver.net


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Re: gEDA-user: Solving the light/heavy symbol problem

2011-05-24 Thread Ouabache Designworks
   Lot of good discussion here. Keep it up.
   I work in the asic/fpga arena and I am building a tool flow  based on
   the ip-xact standard (IEEE-1685). It has a lot in it that solves many
   of the problems in this discussion and I would suggest that gEDA might
   want to borrow a few tips from that standard.
   1) It is targeted for exchanging data between tools.  All the files use
   xml so that parsers are available for all languages.
   2) All objects have a unique identifier. Ip-xact uses a VLNV  for
   Vendor,library,component and version.  There are no name collision
   issues as long as the rules are followed.
   3) Multiple views are supported. I can created a view with one
   deliverable for simulation and a different view and deliverable for
   synthesis. I can generate a light symbol view as well as a heavy one.
   4) No problems with data duplication. By using correct by
   construction techniques you never duplicate data. You keep the master
   source in an ip-xact file and generate everything from there.
   5) Overlays are supported. You never modify anything that you do not
   have engineering responsibility for. If you want to change a library
   part for a local design then you create a local part that uses the lib
   part and then all the changes are made in the local part. The master is
   never touched.
   6) ComponentGenerators are supported. You can embed generators inside
   of a component that control how it is processed by other tools.
 John Eaton


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Re: gEDA-user: An idea: rework design support

2011-05-13 Thread Ouabache Designworks
   Would it be useful. Yes
   Would it be easy  No.
   When you cut a trace you might split a node into two nodes. Or then
   again you might not if there is a loop on the PCB. You would need to
   extract connectivity from the layout to be sure. The cut on the PCB is
   unlikely to map to a nice easy spot on the schematic where you could
   make the equivalent cut.  You may wind up having to redraw the
   schematic.
   John Eaton


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Re: gEDA-user: gschem: directly connecting two nets?

2011-01-24 Thread Ouabache Designworks
   The special symbols is supposed to fuse netnames as issued on the
   netlist,
   not labels on the schematic.
   ---
   If you are also fusing the copper on the board then I would kind of
   like to see that when I am viewing the schematic.
   You want to give the user a choice. If I pull up a component view then
   I want to see the signal names from the original designer. If I am
   traversing a hierarchy and open an instance view then I want to see the
   signal names that match the names in the parent instance.
   John Eaton


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Re: gEDA-user: gschem: directly connecting two nets?

2011-01-23 Thread Ouabache Designworks
 We would also need a way to force the chosen name of the net to
 choose
 when merging nets.  e.g.  When you merge a net named power with a
 net
 named 3v3_power, who wins?
 Steve

   The worst thing that you can do is to simply pick one and  change all
   the others names
   to match. Imagine  accidently connecting net FOO to a power grid and
   having every
   one of the power labels turn to FOO.
   This is one case where not allowing it might be the safest choice.
   John Eaton


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Re: gEDA-user: icarus, fork, and recursive tasks

2010-11-06 Thread Ouabache Designworks
 Message: 7
 Date: Sat, 6 Nov 2010 19:37:20 -0400
 From: DJ Delorie [1...@delorie.com
 Subject: gEDA-user: icarus, fork, and recursive tasks
 To: [2]geda-u...@moria.seul.org
 Message-ID: [3]201011062337.oa6nbkeu014...@envy.delorie.com
 I'm trying to simulate an MCU's bus processor, which has a couple of
 timing parameters all keyed off the start of a transaction.
 Naively, I did this:
  fork
 mcu_cson (address);
 mcu_wron (address);
 mcu_wdon (address);
 mcu_cswwait (address);
  join
 Each mcu_* task would wait the right number of cycles, toggle its
 line, and return.  However, they all called one task (twait()) that
 did wait the right number of cycles.
 Not to usefully, they all shared the one task (or variable), and
 thus
 all exited at exactly the same time.
 How do I do a local instantiation of a task?
 I'm running iverilog-0.9.20091230
 --

   task automatic twait
   John Eaton

References

   1. mailto:d...@delorie.com
   2. mailto:geda-user@moria.seul.org
   3. mailto:201011062337.oa6nbkeu014...@envy.delorie.com


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Re: gEDA-user: Functional blocks and PCB format changes

2010-09-13 Thread Ouabache Designworks
 On Fri, Sep 03, 2010 at 09:08:25PM -0700, Andrew Poelstra wrote:
  XML is far too heavy, agreed, and it's signal-to-noise ratio is
 abysmal.

   True on both counts and you would never want to handcraft a xml
   document.
   But thats not how your supposed to use it.   You want to write a tool
   in perl?
   You grab a xml lib, parse it into a perl data array to do all your work
   and then
   spit it back out as xml when you are finished. You never touch the xml.
   IC design is heading toward using xml  as a means to automate design
   creation.
   If the IP-xact group ever gets their act together you can expect to see
   it extend
   into PCA data as well.
   John Eaton


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Re: gEDA-user: Functional blocks and PCB format changes

2010-09-13 Thread Ouabache Designworks
 pin:
  pinNumber: 2
  pinName: rst
  x1: 1234
  y1: 4321
  x2: 2345
  y2: 4321
  layer: component
 or
 pinpinNumber2/pinNumberpinNamerst\pinNamex11234\x1y
 14321\y1x22345\x2y25432\y2layercomponent\layer\pin
 I call the second large, bloat, and ugly.

   -
   Here you go:
   ===
#!/usr/bin/perl  -w
 use strict;
 use warnings;
 my $filename = shift @ARGV;
 use XML::LibXML;
 my $parser = XML::LibXML-new();
 my $doc= $parser-parse_file($filename);
 foreach
 my $pin ($doc-findnodes('/pin')) {
   my($pinNumber)  = $pin-findnodes('./pinNumber/text()')-to_literal
   ;
   my($pinName)= $pin-findnodes('./pinName/text()')-to_literal ;
   my($x1) = $pin-findnodes('./x1/text()')-to_literal ;
   my($y1) = $pin-findnodes('./y1/text()')-to_literal ;
   my($x2) = $pin-findnodes('./x2/text()')-to_literal ;
   my($y2) = $pin-findnodes('./y2/text()')-to_literal ;
   my($layer)  = $pin-findnodes('./layer/text()')-to_literal ;
   print pin\n;
   print   pinNumber: $pinNumber\n;
   print   pinName: $pinName\n;
   print   x1: $x1\n;
   print   y1: $y1\n;
   print   x2: $x2\n;
   print   y2: $y2\n;
   print   layer: $layer\n;
}
   =
   Simple perl script will make things pretty again. (after you fix the
   your backslashes). Only takes
   one extra module (libXML) that you can apt-get on ubuntu.  Going back
   the other way is just as easy once
   you write a parser for your format.
   If size is an issue you can always store everything compressed.  Then
   we can have another argument about
   whether we should create our own compression scheme or use an existing
   one.
   John Eaton


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gEDA-user: Honey, I shrunk the schematic

2010-08-22 Thread Ouabache Designworks
   The grid units are arbitrary. Use a bigger title frame, and when you
   print to A4, everything will shrink.
   -
   Thats the advantage of ISO over English sheet sizes. You can't do that
   with A,B,C,D and E sized sheets
   John Eaton


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Re: gEDA-user: subnets

2010-08-16 Thread Ouabache Designworks
 Using blocks in mechanical CAD has some issues with this. In
 principle
 there are 2 ways to use a block:
a) copy and paste
b) reference
 Naturally the edit one modify all can only work with referencing.
 Sometimes in a single construction this is not desired, so when
 duplicating
 one has the choice between reference and copy. With mechanical
 constructions
 this goes as far as changing the appearance of a referenced block,
 when
 when an external block is changed independently. This can be useful,
 if the
 interface of the block is well understood.


   Asic synthesis has a step called uniquification where you create a
   module and
   instantiate it multiple times.  Uniquify  will create  a new module for
   each instance
   that can be modified independently from the others.  You can also
   modify the master
   to change all the instances.
   It can get a little messy in that once you modify an instance then you
   can no longer
   touch the master or else all changes to the instance are lost.
   John Eaton


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Re: gEDA-user: spice libs ( a little puzzled)

2010-04-28 Thread Ouabache Designworks
 What you consider common circuit elements are undoubtedly
 different from
  what I commonly use. That's how it goes. You have to build your
 own library,
  just like I had to when I was using Pspice back in the '90s.
 
 
 Which is precisely the problem. This isn't the 90s. I grew up on BBC
 microcomputers. Do I feel nostalgic about the things I used to be
 able to do
 with those beauties ? Yes. Do I think that the associated workflow
 with them
 was superior to the workflow today (even with something as
 unreliable as
 Windows) ? Not a chance.

   My first spice deck was really a deck. Hammered out on an IBM 026
   keypunch
   machine.
   The whole point of Open Source is that everybody doesn't have to
   reinvent the
   wheel.  You  spend time building a really nice and usable library then
   you make
   it available for everybody to use.
   Somebody will add some new components and someone else will add some
   nice support scripts and everybody benefits
   John Eaton


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Re: gEDA-user: gEDA programming

2010-04-23 Thread Ouabache Designworks
   Oh bull.  Lots of IDEs (and just plain text editors) do that just
 fine.  There's *nothing* about software development of any kind that
 is unique to or first appeared in Microsoft Windows.
  -Dave

   -
   Other than Bob and Clippy is there anything  of any kind that
   is unique to or first appeared in Microsoft Windows?
   John Eaton


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Re: gEDA-user: purpose of gschem

2010-04-22 Thread Ouabache Designworks
   I am not new (though a tad rusty) to spice, or the usual design
   process. Years ago, I went through an analog circuit design,
 followed
   by a VLSI design class that involved the use of H-Spice, Mentor
   Graphics and Cadence software, basically Design Architect,
 (Modelsim
   for digital design), Accusim, IC Station, DRC, LVS workflow, with
 the
   (IIRC) AMI05 library.

   I guess I am asking - what purpose does gschem serve (other than
 to
   create pretty pictures, and being a humongous waste of time
 otherwise
   since its basically asking you to enter the entire spice script,
 albeit
   in disparate pretty boxes) ?
 --

   The purpose of gschem is to provide X% of the functionality of the
   above mentioned
   tools at Y% of their cost where:
X/Y  = Some really big Number
   It is labor of love performed by designers who are fed up paying big
   $$$ for buggy eda tools.
   Those who want to take a turn being a tool maker instead of a tool
   user. Those who don't want
   to be dependent on an employer's licenses for their professional
   livelihood. Those who have
   spent time solving problems and want to help others with the same
   issues.
   Gschem is better called GAF ( gschem and friends) which is a open
   sourced tool set of
   various eda tools.
   Gschem itself is in pretty good shape. It's comparable to programs that
   I used that cost $3000.
   PCB is in good shape. I haven't used it for any boards but there is a
   lot of activity on these forums
   and a lot of people are using a gschem-PCB flow
   Beyond that it's kind of spotty. The gschem - spice flow is not
   polished and is more of an aide that
   is better than doing it all in text files while also providing usable
   documents.
   It's waiting for someone willing to come up with a solution and share
   it. You would need to create a
   library with all the basic spice components and attributes. Create any
   support tools or scripts that
   can do the gunt work and make the design flow easy and robust and then
   give it away for free.
   Around here people don't say Why doesn't somebody.. they say Why
   can't I
   John Eaton


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gEDA-user: Ubuntu 10.4 Beta2

2010-04-19 Thread Ouabache Designworks
   I am testing out the new ubuntu 10.4 beta 2 in hopes that it can
   replace my current 9.04 install.
   ( I tried 9.10 but to much was broken). 10.4 will install geda
   20100214  so I am also comparing
   that with 20081213 from 9.04.
   Comments
   The gschemrc layering is improving.  If I copy system-gschemrc
   ~/.gEDA/gschemrc then 20081213
   doesn't even come up, 20100214 does but duplicates the menu items. Do
   we need a reset menus command?
   Adding the switch from light - background in the menu was a great
   idea.  Kudos to whoever did it.
   Rubberbanding doesn't work on nets. I used to be able to drop a net at
   45 deg by hitting ctrl but not in 20100214.
   Buses still work , it's only on nets. Was this changed?
   There is a reference to a bus-ripper component that I could not find in
   any of the symbol libs. Does this exist?
   The little magnetic bubble that bounces to the nearest connect point is
   really nice. Good job on that one.
   John Eaton


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Re: gEDA-user: I2C ringing

2010-04-02 Thread Ouabache Designworks
 Message: 3
 Date: Fri, 02 Apr 2010 13:46:19 -0400
 From: Jim [1]...@k4gvo.com
 Subject: gEDA-user: OT: I2C pullup resistor location
 To: gEDA user mailing list [2]geda-u...@moria.seul.org
 Message-ID: [3]4bb62d6b.7050...@k4gvo.com
 Content-Type: text/plain; charset=ISO-8859-1; format=flowed
 I'm building a backplane board that will have a processor board
 (master)
 and 8 slaves using I2C across the backplane.  Is there any advantage
 to
 placing the pullup resistors on the end of the backplane farthest
 from
 the processor board?  I recall installing active termination on the
 old
 S-100 bus backplanes to overcome problems with ringing, I think.
 It's
 been too long.
 Thanks,
 Jim.

   No advantage.
   S-100 (yes I also built them) had an active driver and fast enough
   edges so that
   the length was long enough to be a transmission line. I2C is open drain
   so that
   the active driver is the pullup resistor.
   You might put it at the end so that it makes an open trace easy to
   detect.
   John

References

   1. mailto:j...@k4gvo.com
   2. mailto:geda-user@moria.seul.org
   3. mailto:4bb62d6b.7050...@k4gvo.com


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Re: gEDA-user: picking a googlized name

2010-03-19 Thread Ouabache Designworks
 Message: 8
 Date: Sat, 20 Mar 2010 12:59:37 +1300
 From: Anthony Blake [1]tony...@gmail.com
 Subject: Re: gEDA-user: Toporouter update?
 To: gEDA user mailing list [2]geda-u...@moria.seul.org
 Message-ID: [3]4ba40fe9.1020...@googlemail.com
 Content-Type: text/plain; charset=ISO-8859-1; format=flowed
 John Griessen wrote:
  kai-martin knaak wrote:
  Anthony Blake wrote:
 
  greenlight   ---
 
  I'd strongly suggest to invent a new word rather than take an
 existing
  buzzword. The term greenlight currently yields 1.5 Mio google
 hits.
  A greenlight router would be almost as invisible to internet
 searches
  as pcb ;-)
 
  Oh, it wouldn't be that bad.  Pcb is the tool's category name as
 well as
  being a
  common term.  Searching for greenlight router would narrow down
 just
  fine.
 I would have liked to use the name 'greenstone', which has special
 meaning for NZ.. it is a type of jade only found here. Unfortunately
 my
 uni supervisor has already used that name for a project:
 [4]http://www.greenstone.org/
 Maybe we could call it the greenstone router?
 Cheers,
 Anthony
 

   If you want to be found by google then follow the lead of the TV show
   numb3rs.
   Type that in and the show pops right up. Maybe we could set up a test
   page with
   some candidate names in the keywords to see what happens with a search.
   In today's world you pick the names that the search engines like or
   nobody will
   ever find you
   John Eaton

References

   1. mailto:tony...@gmail.com
   2. mailto:geda-user@moria.seul.org
   3. mailto:4ba40fe9.1020...@googlemail.com
   4. http://www.greenstone.org/


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Re: gEDA-user: any last minute advice prior to sending out for PCB fab

2010-02-24 Thread Ouabache Designworks
 On Tue, Feb 23, 2010 at 10:01 PM, gene glick
 [1]carzr...@optonline.net wrote:
  After a very long time, I am just about ready to send out 3
 different boards
  for fab. ?I would appreciate any advice to improve my chances of
 success.

   Don't send all three at once. Send one and get it all the way through
   your process before sending the last two.
   John Eaton

References

   1. mailto:carzr...@optonline.net


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Re: gEDA-user: which linux distribution

2010-02-21 Thread Ouabache Designworks
   I recently tried updating from ubuntu 9.04 to 9.10 but it was step in
   the wrong direction. Had to
   back it out.  Ever try doing an install when the bottom edge is off the
   screen?
   John Eaton


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