Message: 1 Date: Thu, 07 Jul 2011 15:31:44 -0700 From: <[1]fr...@frankthomson.net> Subject: gEDA-user: verilog -> gschem To: [2]geda-user@moria.seul.org Message-ID:
<[3]20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97.wbe@e mail04.secureserver.net> Content-Type: text/plain; charset="utf-8" I've looked at the mailing list archives and seen people ask but haven't seen if anyone has code to take a verilog netlist and create a gschem file from it. I don't care about what the schematic looks like, can be ugly. I just need to get it into gschem format to run through gnetlist to a different netlist format. Why? Well, I'm getting files from different tools (gschem along with tools from other sites) and the common format I can generate is verilog which works out well because I'm using icarus verilog for simulation. The next step in the process requires running the design through gnetlist but since gnetlist only reads gschem files as input I need to get the verilog files to gschem to feed gnetlist. -Frank ------------------------------ The only difference between that and and PCB layout program is that you don't care about trace width and you can cross lines without connecting them. What you need is a symbol generator ( trivial script) , and autoplacer ( trivial unless you want your result to be understandable and easily routed) and a autorouter ( PHD project and maybe a career). You should be able to do a script that generates a graphical rats nest that had all the correct connections. That should work. John Eaton References 1. mailto:fr...@frankthomson.net 2. mailto:geda-user@moria.seul.org 3. mailto:20110707153144.97bc9b90117a8175dad249389209a753.5acdf95b97....@email04.secureserver.net
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