gEDA-user: DIY thermographic camera?
Thermographic (IR) imaging cameras, such as you might use for an energy audit on your home, are $5k+. Could one get reasonably useful results from a hacked camcorder or digital camera with appropriate filters? Absolute accuracy would not matter, but I'd want it to be able to resolve relative temperature differences pretty well over a range of, say, 0C - 50C. Any thoughts? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DIY thermographic camera?
On Wed, Nov 05, 2008 at 07:49:26PM -0500, Bob Paddock wrote: Would this get you what you need?: http://www.melexis.com/Sensor_ICs_Infrared_and_Optical/Infrared/MLX90614_615.aspx have a couple of samples of them laying here but have not done anything with them yet. Alas, I'm looking for something that provides a multi-pixel image. What you have is a single-element sensor. Maybe with scanning optics and a lot of patience... ;) Thanks anyway, -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Way OT: Architectural CAD programs
I know this really has nothing to do with gEDA, but I figure there's likely some overlap in knowledge. I'm looking for a program to create building plans with -- floor plans and elevations would be the key outputs. Preferrably this would be free, open-source, and run on Linux, and would already have standard floor plan symbols (doors, etc.) built in so I don't have to draw that stuff by hand. I would really prefer a CAD program rather than a vector drawing program if possible -- i.e., I create a model of the building, and it can spit out plans and elevations from that model. I don't need really fancy engineering features like load analysis, though. Anybody have any recommendations? TIA, Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Export to Orcad?
I'm pretty sure the answer is still, as it has always been, no, but just to check: Can I get gschem to export to Orcad format, or any other schematic format? I need to send my design to the professionals for further work, who of course are not gEDA-friendly. I think it's probably going to come down to me giving them postscript/pdf and them re-entering the design in their own preferred package, unless there's a converter I'm not aware of. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Using 60Hz mains frequency for timing?
Just a quick non-gEDA design question -- I have the choice between using the zero crossings of the 60Hz mains voltage or my MCU clock (generated from an 18.432MHz quartz crystal producing a 48MHz CPU clock via PLL built into the MCU) for low-resolution timing. The crystal is not designed as a watch crystal, so its tolerance is probably pretty poor, and furthermore this board will see wide temperature swings, which I think has an affect on the crystal frequency as well. I have no idea how precise the 60Hz line frequency from the power utility is, but it at least is probably not temperature-dependant. Either one is easy to use -- I just want to be as accurate as possible. Anybody have suggestions? TIA, -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Using 60Hz mains frequency for timing?
Thanks very much to all who responded... and so quickly. I should have included more information on the application -- This is for building a power meter (watts and watt-hr) for measuring power consumption of particular circuits as well as the whole house (but not for billing purposes -- just informational). To give you an idea of what I mean by low resolution, The timing will affect primarily the watts output, which is calculated as 15-second averages. It is also somewhat important that the watt-hr accumulation correlate with the *monthly* energy bill, which comes from the utility's meter on the outside of the house. I am sure that older electromechanical meters rely on the 60Hz signal for timing; I'm not sure what newer digital ones do. It sounds to me like my 15-second periods will perhaps be slightly more stable with the crystal, but the 60Hz should get close enough. For the monthly comparison with the utility power meter, it sounds like the long-term stability of the 60Hz is likely to be far better. I get either signal for free already (with good glitch filtering on the zero-crossing detect), so neither is more convenient. Given all that, I think I will go for the 60Hz signal. Or maybe if I have some spare time I'll test one against the other -- assume the 60Hz is stable on a daily basis and check the drift of the crystal against it. Thanks for all the info. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Thu, Mar 27, 2008 at 06:36:38PM -0400, DJ Delorie wrote: ATX motherboard (or any pc motherboard shape, really, like micro-atx or some laptop). PCI/PCIe slots, ISA slots, standard connectors, SDRAM - whatever. A huge FPGA in the middle. [...] My understanding is that with the GHz busses on modern mobos you need to pay serious attention to matching trace lengths and impedances exactly for the different lines of the bus. I thought it was basically impossible to get it right without assistance from the CAD tool. Am I wrong? Is this actually practically feasible with a dumb CAD tool like pcb? No offense, really -- I love pcb! But it's dumb in the sense that it doesn't really contribute to the layout, just does a pretty good job of letting you do the layout. I've never had much luck with the autorouter even for moderately complex stuff, nevermind creating balanced busses. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: anyone has had success with 0.2mm?
On Mon, Dec 03, 2007 at 10:07:23AM -0800, Lope De Vega wrote: I'm trying to build a circuit with a cp2102, which has 0.5 mm between pins' center (actually 0.2mm between pins). It is a qfn-28 package. I have never played with toner transfer schemes, but I have done boards with 0.5mm pitch packages and had them professionally printed, then I soldered the chips on by hand. I have done it both with a toaster oven reflow process and with a plain old soldering iron. Each method has advantages and disadvantages, but it is doable. Whether or not you can do a toner transfer board with that kind of precision is another matter, and I'm sure DJ can say something about that. Having boards fabbed can be pretty cheap, especially if they're just one or two layers, and especially if you don't want soldermask. It was cheap enough that I skipped right past trying to etch boards myself. These days I do 4-layer boards mostly, so home etching is just not an option anyway. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: four-layer builds (was: anyone has had success with 0.2mm?)
On Mon, Dec 03, 2007 at 11:30:05AM -0800, Ben Jackson wrote: On Mon, Dec 03, 2007 at 01:28:36PM -0500, Randall Nortman wrote: These days I do 4-layer boards mostly, so home etching is just not an option anyway. Who are you using for 4 layer? I just submitted the order that got me started (and then sidetracked several times!) on gEDA/PCB: 5x10 4 layer silk/mask on both sides, 3 for $201 (plus about $20 2-day shipping) for a 10-day turn at Sierra Proto Express. (was 60 sq in x3 for $150 when I started!) I have used a few places so far: pcbfabexpress.com: Very good prices for qty 5, but less than 5 is not an option and more than 5 doesn't get you any discount. Good quality, standard 5-day turn. $50 per order (not per board) extra charge for fine-pitch SMT (0.65mm I think). pcbexpress.com (owned by Sunstone): Good prices for medium quantities, like 20 boards. I was unimpressed with the quality when I ordered (nearly 2 years ago). There were two problems: first, they ignored the part of pcb's gerber output that removes silkscreen from pads, which caused a few soldering headaches. Secondly, the drill tolerances were not great, and the preset drill sizes didn't match my board anyway. So with them rounding down my hole size, plus sloppy tolerances on finished hole size, I had to hammer (literally) some of my 100-mil headers in. protoexpress.com (Sierra): My recent orders have all been from here. Excellent quality, expedite at reasonable cost, very reasonable prices for small quantities. Everyboard raves about 4pcb.com, but so far I've never ordered from them because they're usually pretty expensive, at least for the sort of quantities I do. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA for mass production?
On Mon, Dec 03, 2007 at 02:28:13PM -0600, John Griessen wrote: Stefan Salewski wrote: Hello, til now I only did hand soldering of prototypes. But I am curious, can gEDA (pcb) data be used for automatic placement and soldering of boards? (This may be a stupid question, but currently I do not know which data board manufactures use for placement of devices.) The footprint origin is available and can be gotten somehow -- I have not done it yet. You will need to make your footprints compatible with the process; probably all with origin at pads centroid, or if you know there is an optimum grab point on top of the package that is not at footprint centroid, make sure that package has its origin there. I have only gotten as far as getting quotes, and for that the gerbers, BOM, and xy file were adequate. I think that because of the lack of any standard for defining the centroid and rotation precisely, assemblers are used to using the provided information as a starting point with manual review. I envision a simple CAD tool that includes a database of package dimensions and takes gerbers, BOM, and an xy file as inputs. A little manual intervention lets the tool find the correct package for each part number in the BOM, and then uses the xy file to draw a shadow/outline of the package over the gerber. The operator adjusts position and rotation manually. If the tool is smart, it will rember the postion/rotation offsets for that particular footprint and use them as defaults for any other parts of the same footprint. I don't think this would take long, and the assembly quotes I got all included NRE (non-recurring engineering) charges which would more than pay for the half an hour of labor to do all that. (NREs also included stencils and frames that hold the boards in place through the process.) If the industry has its act together enough to make that fully automated, I'd be surprised and pleased. I think that small-quantity prototype assembly doesn't even bother with all that and uses manually-guided pick and place machines. Those would presumably zoom to the coordinates provided in the xy file but then the operator finishes the job with a joystick. I will know early next year what it takes to actually go beyond the quoting step. I should also note that many of the shops I got quotes for wanted to handle getting the boards fabbed as well. They outsource this -- usually to Advanced Circuits/4pcb.com for low volume -- but I think they like to get their hands on the gerbers to adjust things like soldermask aperatures to fit their own particular process -- including the properties of the solder paste they intend to use. They also have to manufacture stencils appropriate for their process -- I doubt they just use the paste layer unmodified, since the ideal aperature depends entirely on the type of paste, stencil thickness, etc. The shops specializing in low-volume prototype assembly (which I think is largely manual) were happy to allow me to provide the boards. They still made the stencils from the gerbers. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [pcb] global puller
On Sat, Nov 24, 2007 at 09:52:26PM -0500, DJ Delorie wrote: Ok, I added the global puller to pcb cvs. It works mostly but always save before using it. Sometimes it goes nuts and you have to Ctrl-C pcb, sometimes it just adds scribbles to parts of your board, so treat it with some skepticism. This is very exciting, but given the dangerous nature of the command, I think it might be a good idea to add a layer of protection around it to keep the newbies safe. Perhaps require something to be manually added to the config file in order to enable the command, or pop up a warning the first time it's used to ask for confirmation -- something like that. Not everybody will have read the mailing list discussions carefully enough to realize how dangerous it is. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: firmware and the GPL license
On Thu, Nov 15, 2007 at 11:10:11AM -0500, al davis wrote: [...] RMS has claimed that GPL is not appropriate for hardware. [...] I think he said this in reference to the actual hardware design, not so much the firmware that runs on it. But the statement is really just as true of the firmware. Imagine the firmware running on your microcontroller-based refrigerator, which has no accessible user interface, and no way to get data in or out of the hardware without physically hacking it. What does it mean to make the software available to the user in this case? Even in the case of BSD-type licenses that require credit to be given in the documentation accompanying the software, what documentation? Sure, you could stick it in the manual for the appliance, but that would be confusing to the average consumer. What if the embedded device is truly embedded in such a way that the consumer doesn't even realize there's a computing device present -- maybe it's embedded into the structure of their home in the form of, say, moisture sensors that detect water leaks. The homeowner probably won't even see a manual or any documentation for something like that. Maybe it's buried inside the intelligent LED light bulbs intended to replace incandescent bulbs. Even the LGPL (which is used by uClibc, for example) isn't really appropriate for this kind of thing, since you still need to make the source of the library itself available to the users. That's just an obnoxious requirement for the manufacturer of those light bulbs, for example. The users will never take them up on it. Instead of using uClibc, they will just write their own code from scratch or purchase proprietary libraries. Admittedly, the light bulb example is a bit contrived, but I think it illustrates the point -- software is going to be increasingly embedded *everywhere*, and just for the sake of economic efficiency, it would be nice if it were largely based on free/open-source software, but the current licenses are not friendly to this sort of thing. So instead everybody reinvents the wheel, and as a result more bugs creep into your refrigerator. (And the development tools for those proprietary libraries are, of course, Windows-only, which isn't good for open-source either.) I would like to see uClibc in particular released under a more embedded-friendly license. Sorry to rant here, as it's not really relevant to gEDA. I should be ranting on the uClibc mailing list, I guess. I'm sure I wouldn't be the first. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 13mm X 27mm board
On Sun, Nov 11, 2007 at 10:29:28AM -0800, Dave N6NZ wrote: I need to make a 13x27mm board. pcb won't let me set any board dimension smaller than 15.something. Aside from changing the source and recompiling, you could also let PCB think the board is bigger and draw your outline on an unused layer. Name it outline, and tell the fab house to use that layer for routing out the board. I seems to me that 13x27mm isn't really enough room to maneuver when placing components and such anyway, so you might find it useful to have some space outside the outline as a temporary holding area for components. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 13mm X 27mm board
On Sun, Nov 11, 2007 at 01:58:24PM -0500, DJ Delorie wrote: I seems to me that 13x27mm isn't really enough room to maneuver when placing components and such anyway, The smallest board I've hand-populated was 5mm x 12mm. You get used to it. Sorry, I wasn't being clear. I meant placing components virtually, in pcb, during layout. I wasn't talking about actual assembly and soldering. I often start boards in pcb about 50% larger than I actually want them to be initially, draw an outline, and use the space outside the outline for temporary staging of components. This reduces clutter in my working area, and gives me a place to paste in groups of new components. Once everything has found a home inside the outline, I reduce the board size setting in pcb to be the actual size. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hotplate DEsoldering
On Sat, Nov 10, 2007 at 04:10:43PM -0800, Dave N6NZ wrote: DJ Delorie wrote: I just had an occasion to remove a bunch of SMT parts from a proto board (so they can be moved to the production board). I used the hotplate, because many of them had solder under the part, not next to. What are you using for a hot plate? The SparkFun site talks about using a cheap US$20 hot plate from Target. They mention uneven heating. A friend who happens to be a Mech E with a specialty in heat transfer suggested using one of the liquid filled hot plates, which are more expensive, but have a hollow core filled with oil or something that distributes the heat more evenly by convection. I recently used a very cheap aluminum-core stainless steel skillet on my stovetop to do some soldering. (Cheap knock-off of the All-Clad style tri-ply cookware.) This was to handle a chip that had an exposed pad on the bottom, not accessible to a soldering iron. I only did that chip that way, not the whole board, so it wasn't really a great test of evenness of heating, but I suspect it wasn't too bad. Anyway, that was a 4-layer board with two inner planes, which should have augmented the aluminum core of the skillet somewhat in spreading heat. I am a little nervous about the SparkFun suggestion, since it involves a non-stick coating. Don't those start to break down at right around the same temperature that solder melts, leading to the release of toxic fumes? Anyway, if you have a skillet that you trust to distribute heat evenly for cooking, give it a try. Just be sure to avoid getting any lead solder on something you intend to cook with in the future. Double-sided boards that come from a real fab will have solder coating on any exposed copper on the bottom. I used some parchment paper between the board and the skillet. The paper got a bit blackened, but never actually smoked or caught fire. (The stuff is meant to go in the oven, after all.) I wonder if the paper improved or degraded the evenness of heating? -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf capabilities
On Wed, Nov 07, 2007 at 09:44:24AM -0500, [EMAIL PROTECTED] wrote: I am looking using gEDA/gaf for my own activities and ran across an archived newsgroup exchange providing a critique of gEDA/gaf and a call for user input on what's important to them. Is there a gEDA/gaf page with a checklist of capabilities, e.g. http://www.4pcb.com/index.php?load=contentpage_id=46 ? I think it would be easier to list the things gEDA/gaf *can't* to than the things it can. I have used it to make fairly complex multi-layout boards, and never come across something I really needed that it couldn't do. The common complaint with the gEDA tools is that the learning curve is very, very steep. There are a handful of tutorials out there, but even after you go through those you have a lot left to learn on your own (at least last time I checked, which was a couple of years ago). Also, the tools are being developed faster than the documentation can keep up in some cases. Also, gEDA/gaf is a true example of a TMTOWTDI (tim-tow-dee) design, which is an old Perl acronym meaning there's more than one way to do it. There are many ways to use gEDA/gaf, and there's never consensus on the right way. So, you're left to make your own decisions, and in general you end up doing a lot of work yourself to get your whole workflow figured out. But once you invest that effort, the results are definitely worth it. Another annoyance is the lack of good symbol/footprint libraries relative to commercial tools. I end up making a lot of footprints myself, but again I have assembled a set of tools that automate that to a large extent, so it is not really a big deal. (Manufacturers often make ready-made symbols and footprints available in the common proprietary formats -- I wonder if anybody has thought of making a converter so we could import these into gschem/pcb?) If you have some specific concerns about capabilities you need, ask and we'll tell you if it can be done with gEDA. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Schottky symbol polarity
This was mentioned by somebody else on the list last year, but the discussion turned to problems with simulating SMPS's on ngspice, and the original issue was never really addressed: http://archives.seul.org/geda/user/Oct-2006/msg00167.html The issue is that schottky-1.sym has the cathode on pin 1 while all the other diodes (that I've checked) have pin 2 as the cathode. Is this just an old mistake that can't be fixed now because we have to preserve backward-compatibility? Or is there some logic to this? Is there any way to add a visible warning to the symbol (as an attribute, presumably, or permanent text) without breaking backward compatibility, and then create schottky-2.sym with the correct polarity? I ask because I just ran into it (again) myself, and it was only a little voice inside my head saying Wait, wasn't there some problem with this symbol that you ran into last time? that kept me from doing it wrong again. Granted, it only makes the silkscreen wrong, so once you figure out you've made the mistake you can just mount the part the other way. But still, that's a mistake that could fry some components if you don't catch it in time. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Dropping a few volts
So I have a 42VDC supply that I want to feed into a linear regulator. But almost all linear regulators want 40V absolute maximum, and the ones that have higher maximums are not reliably stocked anywhere. So I need to drop that down by at least 5V or so. The good news is that I'm only pulling around 70mA on this, so whatever drops it doesn't have to dissipate much power. It occured to me to use a normal shunt zener, but that will end up dissipating extra power through the zener, which is just wasteful. It also occured to me to put a bunch of diodes in series and use their Vf drops, but that would require quite a few diodes. So why not use a 5V zener (reverse biased) in *series* with the load? It will never dissipate extra power, only what is required by the load. Except then it occured to me that zeners have some sort of minimum current to keep them stable, which seems to be around 0.25mA. What would happen if my load started drawing 1mA, or was just disconnected entirely (leaving only the quiescent current of the linear regulator)? I *think*, from looking at the V vs I charts, that the zener would start leaking current with very little voltage drop, thereby subjecting the linear regulator to higher than its rated voltage. Though this would be only at a very small current, so maybe it wouldn't hurt? I dunno, but I suspect that operating it in that range 24/7 for a while would do some damage no matter what. So the idea I had is to put a resistor in parallel with the load sized to draw the zener's minimum current in all cases. That gets me back to wasting current -- but only ~0.25mA, which is orders of magnitude less than I'd waste in a shunt arrangement. (That works out to ~9mW). In terms of total power dissipation, this would be roughly the same as a zener plus an emitter follower (zener carries minimum zener current, transistor carries load current), but without the extra parts. Any thoughts? Am I crazy? TIA, -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Dropping a few volts
On Fri, Oct 12, 2007 at 09:48:12AM -0600, John Doty wrote: On Oct 12, 2007, at 7:20 AM, Randall Nortman wrote: So I have a 42VDC supply that I want to feed into a linear regulator. But almost all linear regulators want 40V absolute maximum, and the ones that have higher maximums are not reliably stocked anywhere. What's wrong with an LM317HV? Nothing at all. Great minds think alike, even if some of them are a bit slow -- I received your response while composing my previous message, in which I came to exactly the same conclusion. (And it only took me all morning to get there! Oh wait, I went to bed thinking about this problem -- how pitiful is that?) I don't even think I need the HV version, since my Vin-Vout is quite a bit below 40V. Another trick is to notice that the three terminal adjustable types aren't grounded: what matters in input-output differential. So, limit that with something like a 33V zener between input and output (to handle power on), and all will be fine. Oh, now there's an important tip. I hadn't thought about the startup voltages. Can I get away with putting a low-value resistor in front of the input capacitor, which would limit inrush current and cause Vin to ramp up slowly when power is connected? That might be cheaper and smaller than the zener. Plus, even zeners have a non-zero response time -- might the regulator be damaged during those microseconds? (nanoseconds?) -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Outline patch for Sierra (protoexpress.com)
I'm trying DJ's patch to export gerbers that Sierra will like
(below). I take it from reading the code that I am required to create
a separate layer called outline which contains my board outline?
And then this will automatically end up on one or both soldermask
layers?
This seems to be a bit of a problem, as I have pcb set so that the
available board area *is* my outline, and therefore it won't let me
draw a line with its center at the very edge of the board. If I
increase the board size, I'm going to have to move everything that's
there now and be very careful about lining up the outline. Perhaps I
should just create the outline with ye olde text editor?
On Fri, Aug 31, 2007 at 02:35:19PM -0400, DJ Delorie wrote:
The first two chunks have to do with when pins are drawn; we don't
want them on outline layers for example. The last chunk is the one
that adds the outline to the mask. I'm not sure what to do with it,
as I don't think it should be the default.
Index: draw.c
===
RCS file: /cvsroot/pcb/pcb/src/draw.c,v
retrieving revision 1.79
diff -p -U3 -b -w -r1.79 draw.c
--- draw.c6 Aug 2007 02:18:30 - 1.79
+++ draw.c31 Aug 2007 18:34:07 -
@@ -458,7 +458,6 @@ DrawEverything (BoxTypePtr drawn_area)
pad_callback, NULL);
}
SWAP_IDENT = save_swap;
- }
if (!gui-gui)
{
@@ -471,6 +470,7 @@ DrawEverything (BoxTypePtr drawn_area)
}
}
}
+}
if (TEST_FLAG (CHECKPLANESFLAG, PCB) gui-gui)
return;
@@ -749,6 +749,7 @@ DrawMask (BoxType * screen)
{
struct pin_info info;
int thin = TEST_FLAG(THINDRAWFLAG, PCB) || TEST_FLAG(THINDRAWPOLYFLAG,
PCB);
+ int i;
OutputType *out = Output;
@@ -783,6 +784,16 @@ DrawMask (BoxType * screen)
}
gui-use_mask (HID_MASK_OFF);
}
+
+ if (!gui-gui)
+{
+ for (i=PCB-Data-LayerN; i=0; i--)
+ {
+ LayerTypePtr Layer = PCB-Data-Layer + i;
+ if (strcmp (Layer-Name, outline) ==0)
+ DrawLayer (Layer, screen);
+ }
+}
}
static int
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gEDA-user: Updating footprints in place
If I have made a change to a footprint, is there an easy way to update a layout that uses that footprint, the way gschem can update embedded symbols? That is, replace the element on the layout with the new footprint, using the same position and rotation. (Obviously, a DRC check would be highly advisable after doing something like this.) I recognize that I could do this manually, but that sounds like a lot of trouble. If anybody has already scripted this, that would be very helpful. It seems like it should be possible, since the original footprint name seems to be stored in the pcb file (at least when it was put there by gsch2pcb, which is how all of mine get there). In the worst case, I think some cut paste with a text editor on the pcb file is probably easier than trying to do it manually in the GUI and get everything lined up properly (at least for newlib footprints -- m4 is not friendly to cut paste). Am I right? Copy and paste the new footprint, copy in coordinates and rotation from old footprint, remove old footprint? And the coordinates within the element seem to be relative to the element's base coordinates and rotation, so nothing else to do, right? -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Updating footprints in place
On Sun, Oct 07, 2007 at 12:45:47PM -0400, John Luciani wrote: [...] You could definately do it with a script but unless you have a lot of footprints to update or have to update a number of layouts it may not be worth it. Well, if the script is generic (rather than hard-coding which footprints you're looking for), it only ever has to be written once, and then used for many different footprints/layouts. The hardest part is searching paths for the updated footprints -- that part could be ripped from gsch2pcb (except that's written in C and this is a natural job for a higher-level language). The cleanup after the script finishes may be more difficult than the cleanup prior to doing a manual replace. If footprint changes are minor -- clearances, mask, silkscreen, etc., then cleanup should not be too bad. If you change pad widths or lengths, you might have problems. If you change the internal coordinate reference, fuggedaboutit. If your components are on the grid manual replacement goes quickly. Well, that all depends on what the grid means. I usually end up with boards that have components on different grids, and I often set up a module/cluster of components on one grid, then select and move it as a single mass, possibly onto another grid, and so the components then end up on a fractional grid of some sort. This is particularly likely when I'm using a metric grid on one module and imperial on another. The part I'm looking at right now ended up with its center on (1410.50,409.10), for one or both of those reasons (I can't really recall). For now, I have fixed my immediate problem with the power of emacs. Maybe I'll write that generic script, someday. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFP fan-out tips
On Sat, Oct 06, 2007 at 07:21:22AM -0400, Bob Paddock wrote: I route power inwards under the chip, with vias to the power planes and the decoupling cap on the other side. Sometimes doing that adds enough inductance to cause problems, in high frequency boards. What does high frequency mean? I'm in the 50MHz range. Do bigger vias provide significantly less inductance than smaller ones? I have been trying to use big vias for my high-current connections, but maybe that's just a waste of board space? Speaking of vias -- Anybody have any experience putting them right under an SMD pad? I'm not thinking of doing that for the little 0.5mm pitch pads (not enough room), but rather doing under 0603 or 0805 capacitor pads, to provide the connection to the plane layer. That would certainly save me some board space. I also have a couple of parts with exposed thermal pads, and the datasheets recommend vias underneath the pad to conduct heat to the other layers. But won't this cause wicking of the solder to the underside of the board? Is there any way to get a little ring of soldermask around a via that's in the middle of a pad? DJ -- you mentioned using 0402 caps. How tweezer-friendly are those? I find I lose maybe 10% of 0603 parts as they fly out of the tweezers and across the room. Thanks to all for the good advice, as usual. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: QFP fan-out tips
I've got a tiny little 100-pin 0.5mm pitch TQFP chip that needs a whole lotta I/O connected to it. I'm doing a 4-layer board (internal VCC and GND planes), but I'm still getting all tied up in knots, with vias all over the place. The connections tend to go off in different directions -- these aren't pretty 16-channel busses. Anybody have any general tips for dealing with this? I have seen that some layout programs do automatic fan-out on chips like this. I could certainly do that manually, but I'm not sure it will really help a whole lot. I still have a lot of signals to connect, and plus several of these pins are power pins that require their own decoupling capacitor and specify that it needs to be as close to the pin as possible. I find I might have to redefine as close as possible as I try to cram more connections in there. (Needless to say, the autorouter shrieks and flees in terror at the sight of this ratsnest, so I am stuck doing it all manually.) One thing that would help would be if I could use the internal VCC/GND planes for routing the odd trace or two, but I have heard that it is a bad idea to run traces through the planes. Anybody have any thoughts on this? I don't suppose anybody has written any fan-out scripts or plugins? Would it help? (I've never done it myself.) TIA, -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Arc to line connections?
I am trying to draw connections to pads with arcs, so that I can use the puller. (The normal -- not global -- puller only works with arc/line intersections, right?) The manual says I can just switch tools in the middle of a trace using the right keys (F2/F3 in the lesstif HID). This works when going from a straight line to an arc, but when I try switching from arc to line it does not work properly. It switches to the line tool, but cancels the current trace, so that I have to manually click on the same point again. When I'm using a fine grid setting, it can be quite difficult to make sure I hit the same point. Am I doing something wrong, or is this a bug? I'm using the lesstif interface and the latest release (20070912). Of course, I also don't feel like I have a good handle on the puller tool yet. Any tips on how to use it properly? I gater the idea is mostly to reduce trace lengths by using truly straight paths, rather than confining everything to 45-deg increments. Of course, I can use all-direction lines for that, so the main advantage of the puller seems to be in avoiding sharp corners. Are most folks out there still using 45-deg lines, or are we starting to transition to ugly boards with lines going every which way? Professional boards seem to use only 45-deg increments -- just judging by what I see when I open up computers and consumer products. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Exposed copper -- still need to make a pad?
I need to make an exposed area of copper (no soldermask), to act as a heat radiator. Last time I checked, the answer was to create a big SMD pad. Is this still a limitation? It sure would be nice to be able to draw arbitrary polygons and set a flag on them to clear soldermask. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Exposed copper -- still need to make a pad?
On Thu, Sep 27, 2007 at 09:44:36AM -0600, John Doty wrote: On Sep 27, 2007, at 9:28 AM, Randall Nortman wrote: I need to make an exposed area of copper (no soldermask), to act as a heat radiator. Why no soldermask? I'll bet its infrared emissivity is better than copper's, making a better radiator. In space, the radiator tape we use has a thin layer of teflon over the metal for this reason. As sayeth the datasheet, so do-eth the designer! In fact, any exposed copper is going to be covered in shiny silver stuff (tin/lead/silver, depending on process) during board fab. Would that not have pretty darned good emissivity? It would certainly have better conductivity, which is important when you're not designing for vacuum. I suspect that most of my cooling is going to be from conduction to air and subsequent convection (natural convection; no fan), though a big chunk of it will be radiation. (I did say heat radiator in my post -- probably heat sink would have been more appropriate.) -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Arc to line connections?
On Thu, Sep 27, 2007 at 02:01:44PM -0400, DJ Delorie wrote: The manual says I can just switch tools in the middle of a trace using the right keys (F2/F3 in the lesstif HID). This works when going from a straight line to an arc, but when I try switching from arc to line it does not work properly. Whenever you switch tools or layers, you always click on the LAST point, then switch tools. So, you should be finishing up the arc, starting a new arc, switching that to a line, and drawing the line. Yup, that's what I've been doing. Just to test, I started a new blank board and it worked just fine. So I started turning things off in the settings menu until I narrowed it down to Auto-enforce DRC clearance. If that is enabled, I cannot go from arc to line (but I can go from line to arc). If it is disabled, everything works just fine. However, the new topological autorouters won't be limited to 45's any more, so we may start seeing more any-way lines. Speaking of which, as I was playing with all-direction lines, I noticed that they do not enforce clearance properly. They will enforce clearance of pads, but not other traces. It happily lets me come too close to another trace with an all-direction line, and even to touch it. If I then run a DRC check (or just redraw the rat's nest) it complains about the touching copper. While I'm complaining about quirks -- here's another couple that I noticed. One I seem to be able to reproduce reliably: Set up two netlist-connected pads that aren't connected by traces yet. Start drawing a trace (45-degree) at one of the pads, connect it to the other, then hit 'U' to undo that last segmen, without ending the drawing operation. For me, it will indeed undo the segment, but the start point of the current segment (that I'm in the middle of drawing) will stay on the pad I just connected, instead of reverting to the previous starting point. (So that pad actually ends up unconnected, since it just undid the segment that connected to it, but the start point of the current segment is wrong.) It works fine if I undo before I contact another pad. I have also noticed, but cannot reliably reproduce yet, that it sometimes spontaneously inserts vias at the endpoints of segments of my traces, also possibly associated with undo operations. I might be fat-fingering the U key? I dunno, but it happened to me several times today. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Auto-enforce DRC clearance (was Arc to line connections)
[Apologies if this goes to the list twice; I sent it out the first time from the wrong address, so I think the list software will block that copy.] On Thu, Sep 27, 2007 at 03:47:18PM -0400, DJ Delorie wrote: So I started turning things off in the settings menu until I narrowed it down to Auto-enforce DRC clearance. For reference, I never use that setting. I find it invaluable, as it tells me in real time exactly how close I can bring my trace to things it's not supposed to touch. I like to pack things quite tightly. Without auto-enforce, I'd be constantly running the DRC checker and re-drawing traces. It seems like it would be quite tedious. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Alarm clocks and switching regulators
A few months ago I posted some questions about switching regulator design, and got quite a lot of useful info. One of the things briefly discussed was using a low-ESR ceramic on the input to the switcher to handle switching frequency ripple, and then big bulk electrolytics to handle 120Hz ripple from the rectifier, but with an inductor or choke between the ceramic and electrolytics to protect the bulk capacitors from the switching frequency ripple (which might age them prematurely). DJ -- I notice from looking at your alarm clock boards that you seem to have tried something like this. Would you care to share your approach and results? I'd greatly appreciate it. Looks like you have a diode in there too -- for preventing resonance? Thanks, -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Alarm clocks and switching regulators
On Mon, Sep 24, 2007 at 11:25:01AM -0400, DJ Delorie wrote: DJ -- I notice from looking at your alarm clock boards that you seem to have tried something like this. Would you care to share your approach and results? I'd greatly appreciate it. Looks like you have a diode in there too -- for preventing resonance? Yes, the diode is for limiting resonance, and also (in my thinking at least) to prevent the other regulators and circuits from leaching off the switcher's input filter. I wonder what would really happen if that diode weren't there? This is where I start bumping into the limits of my analog design knowledge. With your design, when the diode is reverse biased and shuts off, there doesn't seem to be any conduction path for the inductor -- wouldn't this cause the voltage across the inductor to spike and eventually hit the breakdown voltage of the diode, so that it conducts in reverse? And wouldn't that eventually wear out a diode not designed for it? If these are stupid newbie questions, my apologies. I am really a software guy, and much of these analog stuff is black magic to me. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Alarm clocks and switching regulators
On Mon, Sep 24, 2007 at 12:06:48PM -0400, DJ Delorie wrote: Which diode? There are a couple... I meant the one between bulk cap and inductor, on the input side. For the 15v to switcher catch diode... The inductor never has a negative flux. It's always conducting towards the switcher. If the inductor starts to forward spike it quickly exceeds Vf of the diode, and the diode conducts, drawing charge from the bulk cap. The inductor never spikes the other way, because there's no way to produce current in that direction to charge it. Right, of course, that terminal of the inductor goes negative, not positive, which will always forward-bias the diode. I was not thinking straight. But then... what about when you disconnect the power and drain the bulk cap? I guess that before you fully drain the bulk cap, you'll hit the switcher's minimum frequency and it will stop pulling current, the residual flux in the inductor will keep charging the smaller cap, which might make the switcher oscillate on and off a few times as voltage at that input pin oscillates around the minimum voltage of the switcher, but eventually things will settle down once the currents flowing through the inductor get really small. The capacitors will presumably be slowly drained by internal leakage and also leakage through the switcher. It just always makes me nervous to see inductors where one leg can be completely switched off (as your diode does here), mostly because my understanding of these things is a bit shaky. (Isn't it obvious?) I guess what really makes me nervous about your design is that I haven't seen it suggested anywhere in references on the subject. I have seen various sorts of LC filters recommended, but without that diode. The diode seems to make sense, but why then isn't it a common design? Perhaps there really is no reason to be worried about resonance, and so the diode is overkill? (I'm not criticising, just trying to understand.) For the switcher's diode... the switcher charges the inductor. When it shuts off, the inductor draws current from that diode (which is now forward biased). This allows a somewhat steady current to flow in the big inductor, which maintains a steady charge on its output cap. That much I understand. Wouldn't be undertaking switcher design if I couldn't at least grasp that. (Though I admit I had to read through the description of how buck regulators work a few times to convince myself that everything was kosher.) -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Alarm clocks and switching regulators
On Mon, Sep 24, 2007 at 10:34:58AM -0600, John Doty wrote: [...] But the truth is, D401 isn't very useful where it is. L400 is going to keep it in conduction, so it just acts like a resistor of value ~ (kT)/(qI), or ~25 milliohms at 1 amp. That's smaller than the series resistances of L400 or C402, so those are where the damping's going to be. And it's pretty good: the characteristic impedance of the filter is sqrt(L/C), or about 250 milliohms. That's about the same as the sum of the series resistances of L400 and C402, so the Q will be about 1, not a serious resonance problem. Gak! As soon as the discussion turns to characteristic impedances and Q's, my eyes glaze over. It's a mental block I have. I suppose I could go dig up one of my electronics textbooks and figure it out. You're talking about the LC filter formed by L400 and C402 -- but the presence of C400 turns this into a CLC filter and makes me worry about this being a funky multi-pole filter with strange resonance points. Because, as I've said already, analog is black magic to me, and I don't trust myself to think too hard about it. But you're saying there's nothing to worry about, even without D401? (Of course, it's even more complicated than a CLC filter, since other components are between C400 and L400: the 5V regulator, LED, and whatever might connect to J401. But I'm assuming those are all small enough current draws that they can be ignored.) Now -- here's where I break down and cry like a baby: How should I size L400 and C402 for my own design? Mine operates at ~600kHz switching frequency, and the goal is to attenuate that frequency (to, say, -3dB) upstream of the inductor, so that the bulk caps don't see it and my power supply lines don't broadcast it to the neighbors. All the equations I've been able to dig up require me to know load impedance -- that is, the impedance of my switcher and everything downstream of it. I have no clue, and there's so much stuff there it would be pretty difficult to calculate. And it will vary a lot in real life anyway, depending on what the electronics are doing moment by moment. So where do I start? (The bulk caps will be sized to handle the 120Hz ripple from my rectifier, so I just need to figure how the other two values.) I could just overkill it, of course, but I'm trying to save board space as much as possible, and L's and C's can get really big and expensive. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Alarm clocks and switching regulators
On Mon, Sep 24, 2007 at 02:36:01PM -0600, John Doty wrote: [...] What power? This isn't a minimalist design. The LM2595 is a 500 mA regulator, but other components are rated well above that. DJ seems to have wanted to keep the parts variety down here. I am dropping anywhere from 20V to 42V (peak) down to 3.3V. I am pretty much guessing on current draw: 50mA min, 150mA avg, 500mA peak. I am designing for 1A peak. I'm also expecting to see temperatures in the neighborhood of 65C. I am looking for 60V and 105C minimum specs on the capacitors on the input side. My current draw is low, so I'm not having trouble staying well within the ripple current ratings. Your calculations were extremely useful! Easy as pie, except for having to find the ESR ratings for different capacitor models -- they really like to make that difficult, it seems. And in the end I have to look at a log plot of ESR vs frequency and visually interpolate. Visual interpolation on a log plot is pretty annoying. In general, especially at the higher switching frequencies, this is what you'll see with Al or Ta electrolytics: ripple current ratings will drive you to a design with reasonably low ripple voltage and low Q at the input of the switcher. I'm using a small (2uF) ceramic capacitor at the switcher input. So I have a somewhat lower ESR but a much lower capacitance, so my ripple is more influenced by the capacitance. But my switching frequency is higher, so I see more attenuation from the same inductor value. Or, since I need to save board space, I can use a smaller inductor and still get good attenuation. My bulk capacitors are Al electrolytics. Speaking of board real estate -- yikes! But how else am I going to get ~700uF of capacitance to deal with the 120Hz ripple? (Without spending $30 each on high-tech capacitors, that is.) Of course, it has occured to me to just accept a bigger 120Hz ripple and use smaller bulk caps. It would make the switcher more efficient in general, reduce peak currents in the capacitors and transformer, and save me board space. I would think that a 620kHz switcher should be reasonably good at regulating out that 120Hz, right? I'm using one of the new emulated current mode controllers (LM25575) from National, which in theory provides excellent line regulation. (At least, that is my interpretation of what the phrase inherent line voltage feed-forward from the product literature means -- it adapts quickly to changes in line voltage by maintaining a constant current in the switched inductor.) So long as the caps keep the voltage well above the switcher's minimum frequency, I might be just fine. Thanks for all your help! -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Alarm clocks and switching regulators
On Mon, Sep 24, 2007 at 06:27:19PM -0500, John Griessen wrote: Randall Nortman wrote: I am dropping anywhere from 20V to 42V (peak) down to 3.3V. it has occured to me to just accept a bigger 120Hz ripple and use smaller bulk caps. Sure. That's a good direction to explore. Figure the absolute value you need and keep it above that by knowing how much your current draws are. Let the switcher input see 5 to 42 Volts and its constant inductor current mode will have to exercise some, and you can help it filter out ripple with attention to grounds and guard voltage zones in your layout. Make that 6-42V for my switcher - it needs at least 6V to provide its own internal Vcc. And I like 8-42V for margin. But after I wrote that, I realized that I'm also driving a low-current 5V linear regulator off the same bulk caps, and it probably won't like huge ripple. I'll check the specs and think about how much I can reasonably get away with. I guess that since it is supplying only very low current circuits, I could help it out with a relatively fat capacitor on its output (but still way smaller than big bulk caps). That should help it smooth out line ripple, no? Or I could even put in a diode and then a special bulk capacitor just for the linear regulator, which would not need to be nearly as large to deal with the ripple due to the low current draw. Keep all that primary side switching off to one side. I'm doing this on a 4-layer board, so I have both ground and 3.3v planes. My plan was to put all the power stuff in one corner of the board, and carve moats around it in the power planes, with just one fairly narrow channel in each plane to the rest of the board. I would take care to line up the moats/channels in the planes, so that the return current flows right underneath the supply current, which I gather is a good thing. (That's something I read online somewhere about split power planes and making sure that there is a return current path immediately underneath each circuit trace to minimize impedances, prevent ground loops, EMI, something wacky like that. It's all black magic to me. I just remember that if you put moats in your ground plane, you're not supposed to let any traces cross the moat.) -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Footprint for test points?
Seems a trivial thing, but what do you all use as a footprint for test points on the board? I'm just looking for something I can stick a meter probe onto easily, and maybe solder a wire onto if I need to modify the circuit in an unanticipated way. I am thinking that either a fairly fat pin (which will end up plated through) or just a circular SMT pad would be about right -- and how do I make a circular SMT pad? I guess a square pad would be fine except for aesthetics and expectations. If anybody has a ready-made footprint, I'd appreciate a pointer to it. (I searched on gedasymbols.org and didn't find any footprints -- though DJ did have an appropriate gschem symbol.) -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprint for test points?
On Sun, Sep 16, 2007 at 08:11:40PM -0400, DJ Delorie wrote: Seems a trivial thing, but what do you all use as a footprint for test points on the board? I usually just add vias wherever I need one; mine aren't official in that they're not in the schematics. Except when you have your boards fabbed with soldermask, vias end up covered. My smaller vias are often plugged up with mask, though larger ones do usually end up as holes, but the annular ring is still covered. Either way, it's hard to get a solid connection to it with a test probe. and how do I make a circular SMT pad? Create a line. Drag one end to overlap the other, creating a zero-length line. Cut to the buffer and convert to an element. Poof! Circular pad. Right, I knew this, as I use this trick to make silkscreen dots. I should have guess it would work for pads too. Thanks. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Whatever happened to the puller?
I remember a while back DJ posted some really sweet screenshots of his puller plugin for pcb, which would create nice curved traces from straight ones. Two questions: What has become of it, and (no offense intended) what exactly was the point, other than looking cool? Does it reduce RF pickup/emissions, trace coupling/inductance, or some other such effect? Does it make fabbing via toner transfer easier? Or does it just look really neat? -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: buzzing board
On Thu, Sep 13, 2007 at 08:35:35PM -0400, evan foss wrote: I have had audio amplifiers and large transistors in general buzz on their own. Are you sure it is really on standby? One good way to address this and other such possibilities would be to start de-soldering each component that is not strictly necessary to drive the OLED. Do them one at a time, and test between each one. Sounds like a fun way to spend an afternoon. If you have a spare board and components, it might be easier to start from scratch, and add one thing at a time. (Which would also help catch bad solder joints.) If you get down to just the CPU, OLED, and required support components, I would go so far as to remove the CPU and its required components, and solder on wires to drive the OLED from off-board. Then you'd have it pretty well narrowed down, I'd say. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: C++ (was Re: interesting links)
While we're having an off-topic discussion, I'll throw in my tuppence about C and C++. I have written software in both languages professionally (and personally), and during the mid/late 90's I was a serious C++ zealot. At that point, ANSI was still frantically trying to actually complete the formal language and library specification, and in the process turning up all the various ambiguities in previous specifications and implementation bugs in all of the compilers. Certain things in draft specifications were actually provably impossible to implement, IIRC. There was no compiler that was actually correct at that point, and anyway there was no complete and consistent specification to conform to. Java was an obscure project for set top boxes being worked on by some guy in some back room at Sun; nevermind Python and Ruby. And so despite the mess, everybody was using C++. (Better alternatives -- Eiffel for example -- were not marketed well enough to get any attention.) It was right around 1999/2000 (when I was also enthralled with CORBA and all the wonderful things it was going to do for the world) that I finally got seriously fed up with C++. It is a complex, non-sensical, twelve-headed dragon-horse-goat-chimera-frankenstein-beast designed by committee and assembled by vandals. It is like Perl in this regard, but unlike Perl, it masquerades as a clean, serious language, and as such eschews all of the various kludges and convenience features that Perl has added to help you deal with its ugliness. Perl is a goopy, tacky mess of glue that you can squirt into any crevice and it will hold everything together. C++ is a fragile, crystalline structure held together by tinsel and prayers. You cannot squeeze it into the space you need it to be in. You have to form the space around it. To illustrate the point, I have in my library a truly wonderful book written around that time called Large Scale C++ Software Design. It is quite a hefty book, and dense with information. It was my bible, and I thought it was one of the most insightful technical books I had ever read. Eventually I recognized that the entire book was about how to use C++ safely -- how to avoid all the dangers and pitfalls that attack you from every angle if you actually want to use all of the complex features of C++. Once I quit using C++, there were very few insights in that book that were transferrable to any other language. And therein lies the book's greatest lesson. C++ was a fantasically useful stepping stone from C, to bridge C developers into the OO world. Objective C might be better at this; I don't know, as I never really used it much. C++ is quite usable if you use it simply as a better C, and ignore 90% of what makes it different from C and just use the 10% that is actually an improvement. I am referring to basic inheritence, polymorphism, and maybe, if you're careful, exceptions and simple templates. The standard library is to be avoided at all costs, along with most of the fancier language features. Starting a new project in C++ is a questionable move at this point. It makes sense if you actually need high performance that can't be squeezed out of a higher level language, and in that case you are certainly going to be avoiding the nasty features anyway, and simply using it as a better C. But C can also be a better C, if you similarly avoid all of the things in it that are dangerous and ugly. And if you don't need really high performance, in the modern era you should almost always look to Python, Ruby, et al., or else just go back to the root of all such languages, Lisp. Admittedly, I have not done any significant amount of work in C++ since 2001-ish. Maybe things have gotten better. I don't particularly care, because I don't need C++ anymore. Who really does? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: C++ (was Re: interesting links)
On Thu, Aug 30, 2007 at 08:25:14PM -0400, Bob Paddock wrote: In today's up and coming world of multi-core processors, as anyone here looked at erlang? I looked at it a few years ago. It has a rather nice concurrency model, but it also pretty much forces you into that model, which would seem to make it a bit unpractical in the real world, where you need to interface with other things that might have different models. My general thought on that sort of thing is that when you have a clever idea for how to organize/structure/architect your code, you should implement it as a library/framework within an architecture-neutral general purpose language. That way, when you have to interface to other stuff, you can do so without resorting to ugly kludges. Good languages can be naturally extended to support whatever such architectures you like in a convenient and straightforward way. Also, such languages never gain widespread acceptance, precisely because of that fact that in order to use the language, you have to buy into the architecture it dictates. There is limited flexibility to do things differently, and in the real world that's a major problem. If you strip out the concurrency model, Erlang seems to be just another functional langauge, and why do we need another one of those? That said, the current implementations seem to be remarkably robust for such a fringe language. That, I suppose, is a testament to its simplicity. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Luxeon footprints
On Fri, Aug 10, 2007 at 08:41:05PM -0600, Jeffrey Bridge wrote: Hi guys, I have been doing bigger and bigger layouts using gschem and PCB recently, and I've gotten pretty used to working around various quirks. However, I have run into a problem which does not seem to have any solution beyond modifying the code for PCB to add some capabilities. I would like to make a footprint for any of the Lumileds LUXEON power LEDs to add to my project. They have three basic housing designs, from oldest to newest the I/III/V, the K2, and the Rebel. The Luxeon K2 requires a hexagonal soldermask hole inside of a larger filled copper area, as seen on page 14 of http://www.lumileds.com/pdfs/DS51.pdf I believe that pads can be rotated arbitrarily; you specify them by the endpoints. A regular hexagon can be created with just three rectangles, centered on the same point but rotated 60 degrees from one another. The short sides of each rectangle form opposite sides of the hexagon. That will create the pad and soldermask hole. To create the large copper area (which functions as a heatsink, I suppose), I think you will have to draw that in with polygons after placing the element, rather than make it part of the element. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Multi-page, non-hierarchical schematics?
I have a schematic split into multiple pages just for convenience and ease of editing, not so much because it's hierarchical. I'd like to use the refdes renumbering feature to generate refdeses which are unique across all the pages, but it only seems to work that way if you have the pages in a hierarchy. Unless I'm missing something. But assuming I'm not, what is the absolute simplest way to create a flat hierarchy? My understanding is that I have to draw symbols for each sub-schematic -- I suppose the symbol should just be a box with no inputs or outputs? I make connections across pages by using netname attributes -- I assume this will work within a hierarchy as well? Even just creating a box seems like a fair amount of overhead for such a simple case. Is there an easier way to do this? There are also a few parts of my schematic that are basically copy paste operations, so I'm also considering using hierarchies to handle that repetition better, but I'm a little confused about the details. The docs on hierarchy seem to be pretty lacking in general. (Not a criticism -- I'd rather the developers spent their limited time writing code than documentation, to an extent.) For example, does slotting work across sub-sheets? If I have, for example, and analog input section that includes an op-amp, and I make that a sub-sheet and then put multiple copies of it on the top-level sheet, will the individual sections be able to be lumped into different slots of a quad op-amp? Can I control that process by manually editing attributes? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Modular designs (was Re: Multi-page, non-hierarchical schematics?)
On Fri, Jul 13, 2007 at 06:36:25PM +0100, Peter TB Brett wrote: On Friday 13 July 2007 18:26:09 Randall Nortman wrote: But assuming I'm not, what is the absolute simplest way to create a flat hierarchy? (1) Create each page as a separate .sch file. (2) Use the autonumbering dialog to number your parts, with refdes starting from 100 on the first page, 200 on the second page, 300 on the third page, etc. (3) Put *all* the .sch files as arguments to the gnetlist (or gsch2pcb) invocation. If only I'd planned this all out from the start. The problem is that I'm taking an already completed project (schemated and layout), snipping out part of it and adding more on. For the part that's already done, I already have refdeses assigned and matching between schematic and layout, and I don't know of any convenient, ready-made way to renumber a .sch and .pcb in parallel (short of writing my own script to do it, which does not count as ready-made). Of course, even though the current refdes assignments are all over the map, I could still pick some number greater than any currently assigned and start from there on the new pages. It just won't be particularly clean that way -- lots of skipped numbers. But that's really only a problem if you're obsessive-compulsive like me. ;) This has actually gotten me thinking about modular designs in general -- I find myself wanting to do small runs of semi-customized boards, each of which is a mix and match of bits of boards that I've already designed. It would be nice if this modularity could be captured well in both gschem and pcb, so that I can mix and match my modules in gschem and then import that into pcb, which already knows the layout of each module. Then for each new semi-custom board I only have to draw the connections between the modules. How doable is this right now or in the near future? Seems to me that I can copy paste in both gschem and pcb, but getting the refdeses to match up would be very difficult, unless I'm missing something. Maybe actually a pretty simple script could do it -- design each module with refdeses starting at 1, then have a script which can just add an offset to each refdes in both a .sch and .pcb file and write out the new files, and tell you what the offset should be for the next file to avoid refdes conflicts. Then you load all the .sch files into gschem and set up the connections to get a netlist file, then open up pcb and load/paste each sub-layout in, then make the inter-module connections. This method creates a lot of temporary files, and a lot of manual bookkeeping, but it would work, right? Well, except for slotted parts, which would be difficult to share between modules at the layout level. I assume I'm not the only one who has wanted to make mix match boards like this -- how have other people handled it? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: liquid tin
On Thu, Jul 05, 2007 at 01:28:24AM -0400, DJ Delorie wrote: [...] Both 3.3 and 5v work fine. I'm getting about 18mV P-P ripple on the 3.3v line, at about 150Khz (the switcher's freq) plus a smaller 6MHz ripple, probably from the ATX power supply I'm using. Shorting the 3uH output inductor has no affect. Is that the secondary output inductor, after the first output inductor and capacitor? If so, I suspect that's because you don't have a secondary capacitor or any other load after the secondary inductor (not counting your scope, which I assume has very high input impedence and doesn't count as a load). If you don't allow an inductor to pass current, it will not allow a voltage to develop across its terminals, and so just looks like a conductor. Until you let it pass current by putting a load on it. V = L * dI/dt I = 0 = dI/dt = 0 = V = 0 Stick a capacitive load on there and you'll see a reduction in that ripple, I bet. (A resistive load would result in a much smaller reduction; possibly not even measurable.) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Switching regulator question
On Mon, Jun 18, 2007 at 10:48:52AM -0500, John Griessen wrote: Randall Nortman wrote: On Sun, Jun 17, 2007 at 08:53:37PM -0400, Dan McMahill wrote: [...] Personally I avoid aluminum electrolytics like the plague. And I'm in the unfortunate situation of designing for 70C ambient, natural air convection for cooling. That temp means some expensive caps, so you could design for minimizing number of high quality caps -- like a spacecraft design. How much power? Horsepower? Well that's the good news -- this is a low-power board. I am assuming a peak of about 350mA and average of 100mA. The peak is mostly due to a Zigbee wireless transceiver, and that's probably an overestimate. The switcher is putting that out at 5V, and then I have a linear regulator to take that down to 3.3V, with some analog components using 5V and all the digital stuff (incl. radio) using 3.3V. I am over-designing the power supply to provide at least 1.5A at 70C. I will take an efficiency hit by over-designing that much, but I don't think I'd feel comfortable with less margin. Do give ceramic multilayer caps a look. They are much more dense now than ten years ago, and Taiwanese and Chinese and making them high quality and low cost if you need to plan for production. A quick check on digikey shows that the biggest ceramic they stock that's rated to at least 50V (I will see 40V, with a MOV to handle transients) is 22uF, and those are $5 each. I'm going to need on the order of 100-500uF to deal with the 120Hz ripple, I think, so I think ceramic just isn't going to get me there. But I could certainly have a couple of small ceramics to help with the ripple at the switching frequency, right? How about I have some big aluminum caps front of the rectifier to do the 120Hz, then a ferrite bead, then a couple of small low-ESR ceramics right in front of the switcher? (A pi filter, in other words.) The ferrite bead would attenuate the switching ripple seen by the big caps and protect them from those ripple currents. As a plus, I would leak less switching noise upstream. Is that a dumb idea for some reason? Ferrite beads are a heck of a lot cheaper than the fancy capacitors. I am beginning to think that maybe I should step back on the basic idea of powering 3.3V logic from 24VAC in this kind of environment. What would be wrong with putting a small 4:1 pcb-mount transformer on there to get that down to 6VAC and then use a linear regulator? I still need some big caps to deal with 120Hz ripple, but I don't need to worry about the extra complexities of a switcher. A transformer designed for 115VAC shouldn't care if I drive the primary at 24VAC, should it? I suppose I would need to increase the VA rating to account for the low power factor, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Switching regulator question
On Mon, Jun 18, 2007 at 10:46:31AM -0700, Steven Michalske wrote: Putting a LC filter on the output of the bridge rectifier will help you out. I looked briefly at LC filters to handle 120Hz ripple. Requires some pretty large, expensive inductors if I'm not mistaken. Seems cheaper in both board space and money to have more capacitance. Be careful with over sizing switching power supplies, what is the minimum operating current of your design? My understanding is that with low currents that switcher will enter discontinuous mode (where inductor current goes to zero at the end of each cycle), and this will cause higher output ripple at the switching frequency and more overshoot on the voltage. This is not a big problem in my application. Is there something else that I need to be aware of? I haven't calculated minimum current, but I'm guessing 50mA. (Peak is around 350mA, designing for 1.5A. so that's a big range.) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Switching regulator question
On Sat, Jun 16, 2007 at 09:53:39PM -0400, DJ Delorie wrote: 24VAC RMS means 34V peak, HA! 24VAC means 38V peak (i.e. after the bulk caps) on my board. Had to change modules because I designed for 34V. Eeep, that concerns me. What's the Vf drop on your rectifier? I calculated a peak-to-peak voltage of 37.3V allowing for 10% head room, and then when you subtract diode drops 36V ought to do it. I'm planning to put a 40V MOV or similar on there to handle transients, of course, which will no doubt exceed the normal sine wave peaks. I wonder if your HVAC system might be wired wrong -- most of them have two ways to hook up their 24V transformer, one for 208V and one for 240V, I think. You might be running 240V into the 208V terminal. Or else your mains is 110% of nominal even after line losses, or else your rectifier has impossibly low Vf drops. Or I guess the transformer could have bad tolerances on its winding count. so I would ideally aim to have the largest input ripple possible, which coincidentally allows me to choose a smaller, cheaper input capacitor. What I did was put in four smaller caps in a row, which reduces the ripple current through each. That helps keep cost down too. http://www.delorie.com/house/furnace/pcb2/board-full.html Wow.. 4x820uF = 3.3mF total input capacitance. That's motor-start capacitor territory there. How much current are you intending to draw? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Element file format questions
I'm a big fan of drawing my footprints with either a text editor or a python script. It's been a while since I last did this, and I know that pcb keeps changing. Is the documentation at http://pcb.sourceforge.net/pcb-20070208/pcb.html correct for the 20070208 snapshot? (Or is there any compelling reason to us the CVS version?) Second question: if I want to draw a dot on the silk layer (i.e., a filled-in circle), am I to use the ElementArc command with x,y at the center, thickness equal to the desired radius, a width and height equal to half the radius, and a delta angle of 360? (Or is that angle in radians?) And lastly, what is the best practice on placing the mark and element text? Seems to me that the mark should either be in the center of the element body or centered on pin/pad 1. I've always just left the text at the origin and moved/rotated it during layout. TIA, Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Switching regulator question
On Sun, Jun 17, 2007 at 08:53:37PM -0400, Dan McMahill wrote: [...] Personally I avoid aluminum electrolytics like the plague. If you have to use them be sure to look at the ripple current rating and also figure out what temperature the cap will operate at. Aluminum electrolytics have a temp rating and a lifetime at that temp. Some are 85 deg C, 2000 hour. Think about it, 2000 hours is not much. You get a factor of 2 more for every 10 degrees you back off. Still for an 85 degree cap, you have to back off a lot. If it were me I'd want 105 deg C caps, 5000 hour so you have a better lifetime. And I'm in the unfortunate situation of designing for 70C ambient, natural air convection for cooling. And that 70C is something that I know this board is going to be subjected to, not just a well, it might get up to 60C once or twice, let's design for 70C -- it will see 70C repetatively for a few hours at a time. (These boards are going in uninsulated attics.) They may also see temps on the order of -10C; I am less certain about what the low end will be, but I'll know come winter, one way or another. I looked for plug-in power bricks that could hack that temperature range and came up empty. It's a nasty environment to design for. So yes, I'm definitely going to be giving those capacitor specs a good look. This is part of why I want to figure out how little total capacitance I can get away with, so I can afford better capacitors. How do aluminum caps fail -- open or closed? Does it buy me anything to have redundancy -- several different capacitors, maybe some aluminum and some tantalum? I will have a low-ESR ceramic or two, but it will be relatively small, meant to deal with the high frequency switching of the regulator, not the 120Hz ripple. [...] Your comment about lower input voltage giving higher efficieny is more for a linear regulator. For a switcher it will depend on many things. Yes, and that's why I'm going with a switcher, but I have noticed that looking at the efficiency curves, as a general rule you will do better with a lower differential between input and output. The effect is much more subtle than what you get with linear regulators; appropriately enough, the efficiency of those is pretty much linear with the dropout voltage. In theory, the efficiency of an ideal switcher would not depend on dropout voltage, I understand. If anybody happens to have a supplier for an ideal switcher, please forward me the datasheet. Thanks to everybody who has responded. As usually, I can always count on this group to take a question and run with it, and I end up with lots of bits of knowledge I didn't even know I needed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Switching regulator question
Anybody here knowledgeable in the field of switching power supply design? I'm designing my first one, to knock 24VAC down to 5VDC/0.5A, so it's a fairly small supply, but I don't think I'd want to do that much of a drop with a linear regulator. I'm settling on the TPS5420 integrated switcher (controller with on-chip MOSFET) from TI, which has a switching frequency of 500kHz. (Mostly chosen because of its large input range -- 24VAC RMS means 34V peak, plus I have to assume that it might be as much as 10% above nominal, then subtract the diode drops from the rectifier, so I'm designing for 36V peak.) My question (one among many) is how much do I need to filter the ripple coming out of the full-wave rectifier? Given a switching frequency of 500kHz, I would think that 120Hz ripple on the input would not bother the thing, even if it's large ripple, so long as the voltage never drops below the minimum required to still enable a 5V output (i.e., about 8V). It seems that the lower the average input voltage, the higher the average efficiency of the regulator is going to be, so I would ideally aim to have the largest input ripple possible, which coincidentally allows me to choose a smaller, cheaper input capacitor. That also means lower peak currents through the rectifier and a better power factor. But it can't be that easy. Smaller and cheaper is never better, so what am I missing? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Transformer as voltage transducer?
On Sun, May 27, 2007 at 11:16:18PM -0400, Steven Michalske wrote: [...] as for voltage monitoring, I wouldn't worry much about using the resistors. put in a fast acting fuse at a reasonable low current. How do you suppose insurance companies feel about non-UL stuff on mains power? Just in case I should happen to start a fire... If you get the one that supports the di/dt Rogowski coil like the ADE7753 then you won't have to disconnect the mains. Some thing that the electrician probably won't do with out pulling the meter. Yeah, I was looking at the Rogowski coil option, but I can't find anywhere to buy the things. Do anybody know of a supplier? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Transformer as voltage transducer?
Thanks for all the feedback so far. You have softened some of my paranoia, but also raised some other issues I hadn't thought about -- in particular the fact that transformer response is frequency-dependent, and anything too far from the 60Hz a power transformer is meant to transmit will be attenuated -- i.e., spikes, dips, and switching noise. Right? On Sun, May 27, 2007 at 01:31:31AM -0400, Darryl Gibson wrote: [...] Without knowing what the application is, it's environment, signal source, etc... it is difficult to make specific recommendations. [...] The application is a power analyzer to show me instantaneous and average true power, apparent power, power factor, RMS voltage, and line frequency, plus kWh accumulated over time. There are some great chips from Analog Devices now that integrate all this into one package with a digital output -- I just need to supply the current and voltage transducers. (I know you can get cheap devices like the Kill-A-Watt now to monitor plug loads, but I'm wanting to watch hard-wired appliances like HVAC, plus the actual main service for the whole house. And of course I want it to feed data straight to a PC and log it over time, which the Kill-A-Watt can't do.) The environment is a metal box in a garage, right next to the breaker panel. It will be cold in the winter and hot in the summer, but nothing that will seriously affect electronics, so long as my power supply is designed for it. Signal source will be CTs (current transformers -- donuts) put over the mains lines inside the breaker panel, plus whatever I settle on as voltage transducers. The voltage transducers will most likely sit outside the breaker panel, just plug into a regular three-prong outlet. I'm not sure how else I could do it without violating code in a big way. Well, if I use transformers, I could hard-wire them in, but I think I'd still be doing that outside the breaker panel. And yes, I will have a certified electrician to handle everything happening inside the breaker panel, like slipping the donuts over the mains lines. Of course, the downside of that is that he damned sure isn't going to violate code for me. So now I have to figure out if I really care about those 60Hz spikes, dips, and noise. I am thinking not, so transformers should be just fine. Then again, the reference designs for these Analog Devices chips just put a resistor divider between hot and neutral and feed it straight in without isolation. They use neutral as DC circuit ground and derive power from the hot line, so the whole circuit is tied to mains without isolation. If I did that, I would of course have to make sure that the digital interface between my measurement system and the PC that captures the data is isolated, which is pretty easy. Any thoughts on that setup? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Transformer as voltage transducer?
I would like to measure mains voltage (110-240V, 60Hz), but I want my measurement circuit to be isolated from the voltage being measured. I am going to be sampling the waveform at a high sample rate (relative to the 60Hz waveform being measured) and comparing that with the current on the same lines with (near-)simultaneous measurement. So it is important to me that the voltage waveform not be distorted or phase-shifted, and the voltage I see should be related to the source voltage by a simple linear ratio. Seems like a simple transformer will do it, in theory. But I'm not sure about how they will work in the real world. Do transformers distort the voltage waveform or phase? What happens if I put a load on the secondary of more than a few nA? What non-linearities are there? What sort of transformers are going to give me the best response? Or if the transformer idea is awful, any other ideas for isolated voltage transducers? TIA, Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: USB Digital Microscopes
I'm looking for a relatively cheap (less than about $200) USB microscope for inspecting solder joints and wasting time looking at random stuff around the house at 200x. I figure there are a few folks on this list with the same unexplainable urges, so what have you found? I've found this: http://www.thinkgeek.com/gadgets/electronic/923a/ Which seems to be made by the same folks as this: http://www.pcgears.com/default.aspx?oid=189510 Except the latter seems to have higher resolution. They are the same price, except that ThinkGeek throws in a stand. I wonder if the microscopes are actually the same, and one site or the other has the specs wrong. Might be a confusion on ThinkGeek's part about image capture resolution vs. video capture resolution. There's also the bulkier QX5 microscope made by a company apparently now owned by Intel, which cleans 640x480 resolution and sells for half the price. But the annoying thing is that neither microscope claims Linux support. Would ThinkGeek sell something that doesn't work with Linux? Aren't they marketing to, well, geeks? -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for a project
On Fri, Mar 30, 2007 at 09:05:06PM -0400, DJ Delorie wrote: I know everybody's got a long list of projects tucked away in the back corner of a desk... Is there one that you'd like a jump-start on? Clock radio with ethernet (ntp, remote alarm set, wake up to mp3s, etc). Mine is a couple of decades old, time for an upgrade. I've been thinking the same thing, except the key feature I'm after is a morning alertness test: to turn off the alarm, you have to play a game of simon, repeating some random pattern on four buttons, or maybe even doing some math or something. The point of all that is that I too often turn off the alarm without ever becoming fully awake, and something like that would force my brain to wake up a bit. And don't forget automatic weekday/weekend adjustments. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: SSRs vs. discrete triacs
On Sat, Mar 03, 2007 at 09:06:26PM -0500, DJ Delorie wrote: I need to switch 1A @ 24VAC loads, Been there. http://www.delorie.com/house/furnace/ I use an opto-triac and an alternistor. Alternistors handle the two polarities with different silicon, which helps with inductive loads, which is what I've got. No additional discretes are required, except for a 38 ohm current limiting resistor between the opto and the alternistor. Nice design. Your MCU-controlled zero-cross scheme is very nice, but not applicable in my case because I am not guaranteed that all the loads I'm switching will be in phase, so I'd need several phase detectors, and I'd rather just get zero-cross triacs (and I will pay attention to turn-on voltage -- thanks for pointing that out). On an unrelated note, how do you like the Weidmuller spring-clamp terminal blocks on that board? I had given up on terminal blocks for field connections myself -- these days I solder 3-6 of 22ga discrete wire, and then use wirenuts to make the connection in the field (and by in the field I mean not in the lab/workshop -- i.e., while lying on your back in a gravel crawlspace at 95F/98%RH with poor lighting and dirt getting into all of your bodily orifices). But those connectors look nice and are reasonably priced. The one thing they don't have that my wirenut system does is the ability to gang several wires together (e.g., shared common). Still I can always just stick a 5 length of wire in one of those connectors and fall back on my wirenut system when necessary. Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
