Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Vcc and Vss are still sensitive to load. So if the design requires both Vss and Vee be equal and opposite, then it needs regulation - zener, for example. Your absolutely right, but that's what comes next. It is the regulators how create the difference in load balance. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Hello all, As a remark on your observation Andy I would like to say in my defence that I simplified and reduced the problem/information simply to avoid wasting anyones time with details and (in my opinion) irrelevant side effects. That the two load resistors are in fact a representation of two complete sub-systems is in my opinion not relevant to the question I was asking. But maybe that was a mistake. Nevertheless I got very very great and useful feedback from this list with the information I provided. I decided that I need C1 to eliminate any DC component from the input signal and the hits for using a transformer has let me to understand my error in thinking. It was never my intention to waste anyone time by holding back information but it was my intention not to waste anyone's time by reducing the number of details ;-) What I should do in the future is be more clear about the kind of information I would like to get from this list. a. complete design b. detailed design solution c. tutorial on electronics d. coffee-machine feedback I was looking for the last one, just some feedback from other professionals to get me on track to a solution. And that's what I got, in our situation the solution is to use a transformer, thanks everyone! Cheers, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Yeap, it should be a very low power power supply. Vx is not important Vcc and Vss are. Vin can be anything from 15Khz to 28Khz so a transformer is not the most desired option. I have designed two SMPS for Vcc and Vss but there load to the rectifier are not the same, with the described result. I will try the options suggested in this list today. Robert. On 17/06/11 04:13, gene glick wrote: On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens to Vx, and don't mind adding a few parts, make a cheapo regulator with a zener and BJT? (Or maybe use TL31 instead of zener) What about a small transformer, one winding on primary, center tapped on secondary. Add a diode and a cap for each leg - and there you go! Anyway, there's lots of ways to do this. If regulated output is what you want, a little more work is required. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Thanks DJ, I had the same thought that Vx was floating somewhere unwanted, that's why I added the resistor (which didn't work). Gazing at this problem for a couple of days make me miss the obvious, just split the filter. Brilliant. I'll give it a try. Robert. On 16/06/11 20:48, DJ Delorie wrote: When you put two capacitors in series, there's no way to know what the voltage between them will be. You have three with a common central connection Vx. V1 acts to charge the node, the loads act to discharge it, so an unequal load means unequal discharging and thus nonzero average node voltage. Since D1 and D2 may have different average currents through them, Vx will adjust until the average current through R2 is the same as the net current throuth the two diodes. Can you split the filter into two filters, one for each load? or at least move C1 to the Vx side of the filter, and split it into two capacitors? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solving the light/heavy symbol problem
How we organize the data, and how the user interacts with it, need not be the same :-) I didn't read the complete threat so if I miss the point or if I repeat anyone I'm sorry. Is it not possible to make a top level program that launches the different programs (gschem, pcb, simtools, .)? The top level program can have it's own file with the meta data and cross references to the other files (the refdes maybe). The top level program can have a wizard to help new users to heavyfy the standard symbols. The top level program can have a check/lead to help setting up a simulation project/layout project/IC design project/whatever project. The top level program can call gnetlist to connect it all together. The top level program can have an import/export function to include sheets/pcb designs from other projects. This way you also have a backwards compatibility path (all additional data is stored in the TLP file), not important I know, but still... Just my €0.02 Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solving the light/heavy symbol problem
What I think users want is to have the underlying tools be more aware of the other sources of data in the design, and each other, so that the GUIs appear to be more integrated despite being individual tools and datasets underneath. This may require some high-level these are the files in your design also, but it's a slightly different problem to solve. So if I understand correctly each program in the gEDA tool chain will need a pipe/gate/threat/port/whatever through which it can communicate to a TLP or the N-1 and N+1 tool in the work flow. Something like a multi master serial communication link (I'm more a hardware engineer than a software engineer ;-) But an even different is the problem of what *design* data goes in which file. This part is not backwards compatible, because we'd want to move data out of the other files (sch, pcb, whatever) into a new container. This shouldn't be a problem, the file format of gschem is an excellent example of flexibility. If you have a TLP which can gather information from the various files and make a new file with the meta data it didn't find then your OK. For the user it doesn't matter where the information is stored as long as it is stored. For a script or a text-file junkie it might be hell. Or am I missing something? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: This morning's treat
Great! Well done! And pictures would be nice. Robert. On 23/05/11 03:57, John Doty wrote: Well, here I am in Osaka. It's Monday morning, and I just saw the prototype Soft X-ray Imager (SXI) for the ASTRO-H space mission under test. Much of the electronics, a large, complex circuit board and some mixed-signal ASICs, is of my design, using gEDA. I've been working on this for six years, now, and it's wonderful to see it all built and plugged together. So, thank you to all who made this possible. It's a beautiful morning. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB: adding information to gerber output, anyone?
Hello all, I didn't see any reply on my question so I guess the very busy and overloaded knowledge base of this list didn't find the time to look at it, so please consider this a friendly reminder ;-) Or am I asking a very silly question? (didn't find a answer by google) The question was: I was wondering if it is possible to add more information to the fabrication layer output of the gerber export (*.fab). Added: I like to do this through PCB, is there a variable I need to set? Or a command executed? So that every time the gerber is generated by PCB this information is stored automatically in the gerber fabrication layer output file. I like to add the copper thickness for that specific pcb (preferably for ever layer individually (inner/outer layer)). So far I came up with adding this information to the outline layer (but that doesn't end up in the fab-file). Thanks, Robert. Sorry for pinging again. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB: adding information to gerber output.
Hello all, I was wondering if it is possible to add more information to the fabrication layer output of the gerber export (*.fab). I like to add the copper thickness for that specific pcb (preferably for ever layer individually (inner/outer layer)). Thanks, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Time tracking
I'm using Time Tracker (Project Hamster) http://projecthamster.wordpress.com/ It's a gnome applet. Very easy to use. Billing I do through the TSV file save output. Just my $0.02 Robert. On 02/02/11 14:43, Bob Paddock wrote: On Sun, Jan 30, 2011 at 7:26 PM, Darryl Gibsonn2d...@gmail.com wrote: I'm curious what folks are using for time tracking and/or billing? Something that I just came across and am going to give a try: http://www.emacswiki.org/emacs-en/BufferTimer ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FUNDING (was: Random thoughts on the future interface of PCB)
Hello all, On Thu, 2010-12-09 at 21:55 +1100, Stephen Ecob wrote: I'm aiming to finish University in a few months.. if people would like to fund work on the toporouter, then I would be pretty keen to work on it full time. Regards, Anthony Good, we've established that money could help to improve gEDA :) What I'm *very* unsure of is whether we could raise enough to make a difference. Does anyone have any idea of how many of us make commercial use of gEDA ? As a business user I face the fact that if I choose to use commercial EDA software such as Altium then I'll pay $4K every year for a program that will make me go prematurely bald as I pull my hair out in frustration at bugs that I have no power to fix. I've chosen to use free software instead. Yes, PCB has many shortcomings - but I'm free to fix them. My business is just starting up, so cashflow is tight. At this stage I'm more inclined to contribute to gEDA by coding myself than by paying others to do it for me - but in the future I may have less time and more money. At that stage paying others to improve gEDA would make good business sense. I could easily justify $4K per year, perhaps more - businesses who use Cadence or Zuken are probably paying $20K per year. One business contributing $4K per year is almost insignificant - but 10 could achieve something worthwhile, 50 could fund a full time developer. But it's nothing more than a pipe dream unless there are others out there who think the same. Does anyone else think the same ? I think the same, but I am also in the same position (start-up, tight cashflow). I use gEDA professionally (as a freelancer) but only for a few (1 or 2) small projects a year. If my situation changes (more money, more projects) I have no objection to a donation to the gEDA project. I'm trying to contribute to the project but it's a steep learning curve. I also agree with Levente, as the cheap Dutchman that I am, I like to see where my money will be spend. Just my €0,02 Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Weird DRC error
Hello DJ, Sorry, almost but not quite. If I apply the patch the DRC error in the original file disappears, but if I move the small polygon to the larger one keeping 6 mill distance no DRC error reappears. (DRC distance is set to 10 mill). If I make the distance between the two 5 mill then I get a DRC warning. I have looked in the source code and in my opinion the following code adjustment is also needed (in addition to your patch below): In the function IsLineInPolygon() -- if (!(lp = LinePoly (Line, Line-Thickness + Bloat ))) ++ if (!(lp = LinePoly (Line, Line-Thickness + (2 * Bloat) ))) Sorry for the clumsy way of showing this. The 2 * is needed because in LinePoly it will be divided by two. If I do this then it almost works ;-) If I move the two polygons 10.01 mill apart no DRC error appears and if I move the two polygons 10.00 mill apart a DRC error does appear (?). Looking at the log window I see Rules are minspace 10.01 But I have set it to 10.00 mill. Where does the 0.01 mill come from? I will keep looking at it but if I'm barking up the wrong tree please let me know. Regards, Robert On Sun, 2010-06-20 at 00:19 -0400, DJ Delorie wrote: Try this... diff --git a/src/find.c b/src/find.c index 6fb62b6..30a0bc5 100644 --- a/src/find.c +++ b/src/find.c @@ -2747,7 +2747,8 @@ IsPolygonInPolygon (PolygonTypePtr P1, PolygonTypePtr P2) line.Point1.X = v-point[0]; line.Point1.Y = v-point[1]; - line.Thickness = 2 * Bloat; + /* Bloat is added by IsLineInPolygon, don't add it here too. */ + line.Thickness = 0; line.Clearance = 0; line.Flags = NoFlags (); for (v = v-next; v != c-head; v = v-next) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power rail net clarification
Hello Nikos, The net attribute inside a symbol has the form net=signalname:pinname,pinname,pinname Please also see: http://www.geda.seul.org/wiki/geda:na_howto In your case pin 1 and pin 3V are both connected to VCC. So probably you want something like net=3V:1 or net=3V:pwr If you instantiate a power rail you can double click on this symbol and you will get the attribute dialogue window. In this window you click the Show inherited attributes box. Now you should see the net attribute. right click on the net attribute and select promote. Now you should have two attributes, the promoted one you can edit and will prevail over the old one. I hope this helps. Regards, Robert. Hello, I just want to make sure I understand this correctly. When I instantiate a power rail, there is an inherited attribute called net with a default value of VCC:1, which I cannot change. My understanding is that if I add my own net attribute, say net=VCC:3V, that attribute will override the inherited one. I will not have this power rail connected to both the VCC:1 net and the VCC:3V net, only the VCC:3V net. Is this correct? Thanks, --Nikos Arechiga ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Weird DRC error
Ladies and Gentlemen, I need some assistance with a DRC error. The file attached produces a DRC error (Copper areas too close). However if I disconnect the large polygon from D203 (hover over the polygon and press s) the DRC error disappears. But the weird thing is that if I do not disconnect the polygon from D203 but instead I make the large point in the polygon smaller/lower the DRC error also disappears. If I disconnect the polygon from D203 (no DRC error) and I connect the two by adding a track/line over the pad the DRC error reappears. The minimum copper spacing is set to 10.0 mill and the distance between the two polygons is 15 mill. I'm lost ;-( I think I'm missing something but I don't know what. Any help is appreciated. Thanks, Robert. Additional information: version 20091103 Compiled on May 3 2010 at 10:18:24 - Compile Time Options - GUI: gtk : Gtk - The Gimp Toolkit Exporters: ps : Postscript export. eps : Encapsulated Postscript gerber : RS-274X (Gerber) export. nelma : Numerical analysis package export. bom : Exports a Bill of Materials png : GIF/JPEG/PNG export. Printers: lpr : Postscript print. DRC_test.pcb Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: BUG: gschem Segmentation fault
Hello all, I was playing around with a suggestion Kai-Martin has made in a previous post Re: gEDA-user: gsch2pcb to pcb error. Being: You can assemble frequently needed subcircuits in a special symbol and add them with one click to your sheet. So I took a fresh sheet, removed the titleblock, added sum components (include_component_as_individual_objects), added sum nets, then I did a symbol translate (=0) and saved my new symbol (rommel.sym - attached). Then I took a new sheet, included my new symbol and tried to connect a net to the one from the included symbol (does not matter which one). I can draw the net but as soon as I click once I get a segmentation fault. I attached the backtrace (using gdb) backtrace.txt My system is ubuntu (x86_64) release 10.04 (lucid) Kernel linux 2.6.32-22-generic Gnome 2.30.0 Am I doing anything wrong? Or am I missing anything? Or is this simply a bug? I had no problems with gschem before I tried to do this. Regards, Robert. rommel.sym Description: application/geda-symbol GNU gdb (GDB) 7.0 Copyright (C) 2009 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type show copying and show warranty for details. This GDB was configured as x86_64-unknown-linux-gnu. For bug reporting instructions, please see: http://www.gnu.org/software/gdb/bugs/... Reading symbols from /home/robert/local/bin/gschem...done. (gdb) run Starting program: /home/robert/local/bin/gschem [Thread debugging using libthread_db enabled] Program received signal SIGSEGV, Segmentation fault. 0x0051 in ?? () (gdb) bt #0 0x0051 in ?? () #1 0x00424743 in o_redraw (w_current=0x695250, object_list=value optimized out, draw_selected=1) at o_basic.c:211 #2 0x00424ef2 in o_redraw_rects (w_current=0x695250, rectangles=value optimized out, n_rectangles=value optimized out) at o_basic.c:100 #3 0x00444f13 in x_event_expose (widget=0x7945e0, event=0x7fffda80, w_current=0x695250) at x_event.c:73 #4 0x778fc0b8 in ?? () from /usr/lib/libgtk-x11-2.0.so.0 #5 0x74b7a5de in g_closure_invoke () from /usr/lib/libgobject-2.0.so.0 #6 0x74b8e598 in ?? () from /usr/lib/libgobject-2.0.so.0 #7 0x74b8f8b9 in g_signal_emit_valist () from /usr/lib/libgobject-2.0.so.0 #8 0x74b90033 in g_signal_emit () from /usr/lib/libgobject-2.0.so.0 #9 0x77a12e9f in ?? () from /usr/lib/libgtk-x11-2.0.so.0 #10 0x778f58c6 in gtk_main_do_event () from /usr/lib/libgtk-x11-2.0.so.0 #11 0x775508ea in ?? () from /usr/lib/libgdk-x11-2.0.so.0 #12 0x77550897 in ?? () from /usr/lib/libgdk-x11-2.0.so.0 #13 0x7754d37b in ?? () from /usr/lib/libgdk-x11-2.0.so.0 #14 0x7754f1f1 in gdk_window_process_all_updates () from /usr/lib/libgdk-x11-2.0.so.0 #15 0x7754f259 in ?? () from /usr/lib/libgdk-x11-2.0.so.0 #16 0x7752bd56 in ?? () from /usr/lib/libgdk-x11-2.0.so.0 #17 0x746c98c2 in g_main_context_dispatch () from /lib/libglib-2.0.so.0 #18 0x746cd748 in ?? () from /lib/libglib-2.0.so.0 #19 0x746cdc55 in g_main_loop_run () from /lib/libglib-2.0.so.0 #20 0x778f5af7 in gtk_main () from /usr/lib/libgtk-x11-2.0.so.0 #21 0x0041a51a in main_prog (closure=value optimized out, argc=1, argv=0x7fffe258) at gschem.c:334 #22 0x75b5da5f in ?? () from /usr/lib/libguile.so.17 #23 0x75b33d6a in ?? () from /usr/lib/libguile.so.17 #24 0x75b9a72d in scm_c_catch () from /usr/lib/libguile.so.17 #25 0x75b34207 in scm_i_with_continuation_barrier () from /usr/lib/libguile.so.17 #26 0x75b342a0 in scm_c_with_continuation_barrier () from /usr/lib/libguile.so.17 #27 0x75b99634 in scm_i_with_guile_and_parent () from /usr/lib/libguile.so.17 #28 0x75b5da15 in scm_boot_guile () from /usr/lib/libguile.so.17 #29 0x0041a0b1 in main (argc=1, argv=0x7fffe258) at gschem.c:359 (gdb) quit A debugging session is active. Inferior 1 [process 2585] will be killed. Quit anyway? (y or n) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: BUG: gschem Segmentation fault
Hello Patrick, Thanks. That's the trick. It does not segfault now. Well is it a bug or a case of not UTFM (Understanding The F** Manual)? Anyway thanks for your help. @ core developers: should I make a bug report out of this? Regards, Robert. On Wed, 2010-06-02 at 12:38 +0200, Patrick Bernaud wrote: Hello Robert, myken writes: [...] So I took a fresh sheet, removed the titleblock, added sum components (include_component_as_individual_objects), added sum nets, then I did a symbol translate (=0) and saved my new symbol (rommel.sym - attached). Then I took a new sheet, included my new symbol and tried to connect a net to the one from the included symbol (does not matter which one). I can draw the net but as soon as I click once I get a segmentation fault. You should not select the include_component_as_individual_objets options when drawing your symbol, but instead only when instantiating the composite symbol (when drawing the schematics). Still it should not segfault, so you may want to fill in a bug report if it does not get fixed in a day or two. Regards, Patrick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Unable to assign models to diodes,transistors
Please take a look here: http://geda.seul.org/wiki/geda:csygas I had trouble in the past with gEDA - SPICE because of the rule: Note that if the file holds a .MODEL, the refdes should start with U; if the file holds a .SUBCKT, the refdes should start with X. If the refdes starts with D SPICE will assume the internal model. This is what I remember, hope it helps. Regards, Robert. On Wed, 2010-05-26 at 13:34 +0530, hari venkatesh wrote: I am new user of gEDA i have seen the ngspice manual and implemented the rc circuit given in the ngspice manual. But when i tried to implement Fullwave Rectifier cicuit given in the manual, i was not getting the transient response properly. After entering $ ngspice [1]fulladder.net It is giving error unable to find defination of the model 1n4148 default assumed i have tried to give model in single line specification by selecting attribute model IS=1pA RS=10 BV=100, but still same error was comming even tried to assign model file but still same error was comming help mee References 1. http://fulladder.net/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: error: unable to find definition of model 1n750 - default assumed
in gschem add the following items to your symbol: * devive: 1N750 * model-name: 1n750 (or whatever the name of the model is called inside your spice model) Look at your spice file for something like .MODEL 1n750 d ^- this is the model-name attribute (upper and lower case do matter) and add * file: /full/path/to/your/spice/model/1N750.sp3 save and run gnetlist again. It has been a while for me since I used spice so don't shoot me for trying to help. Good luck, Robert. On Wed, 2010-05-26 at 21:36 +0530, hari venkatesh wrote: I am new to ubuntu and gEDA, am using ubuntu 9.10. I have installed the gEDA packeges from SYNAPTIC PACKAGE MANAGER. But it doesnot include Ngspice. I have installed Ngspice using sudo dpkg --force -all -i /home/user/xspice-17.0.0.1_i386.deb sudo dpkg --force -all -i /home/user/ngspice-17.0.0.1_i386.deb i want to implement fullwave rectifier which is given in ngspice manual but am getting the following error which i have given below. i have tried the attribute file , model, model-name..But no use * Spice netlister for gnetlist R1 n1 Vdd 10k V1 n0 0 SIN(0 10 50Hz) D4 0 n1 1N750 D3 Vdd n0 1N750 D2 Vdd 0 1N750 D1 n0 n1 1N750 .END Circuit: * Spice netlister for gnetlist Error on line 4 : d4 0 n1 1n750 unable to find definition of model 1n750 - default assumed Error on line 5 : d3 vdd n0 1n750 unable to find definition of model 1n750 - default assumed Error on line 6 : d2 vdd 0 1n750 unable to find definition of model 1n750 - default assumed Error on line 7 : d1 n0 n1 1n750 unable to find definition of model 1n750 - default assumed ngspice 98 - quit ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
This wiki page might be useful: http://geda.seul.org/wiki/geda:pcb-quick_reference It is more complete than the online help in the menu. I have looked at the wiki page above and found difference with my (standard) configuration. \ thin-draw toggles thin draw mode for me it only works with shift-\ or (|) thin-draw Is this an error in the wiki of in my configuration? Just trying to be helpful. Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I mark the connection point on a pad?
If you hover above a pad and hit the F key (Find Connections) all connections that are attached to that pad will be marked. It helps me to find out which pad is connected to what without the use of the schematic. I hope I understand your problem correctly. Robert. Yes, but when there are multiple lines laying on top of one another, it's hard to figure out where they go without refering back to the schematic. :) Anyway it's now a moot point. Thanks, Jim. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Is this type of footprint possible?
Hello all, I want to use a component with the attached footprint. Is it possible to make a footprint with an arc inside? Any help appreciated. Regards, Robert attachment: Wurth-elektronik-744043120.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is this type of footprint possible?
Thanks, I will try this approach, although the simplicity of Duncan's solution also appeals to me, but I don't know if I get into trouble with manufacturing (placement) tolerances using such a simple footprint. Any way, thanks for your reply. Regards, Robert. On Mon, 2010-03-29 at 18:04 +, Kai-Martin Knaak wrote: On Mon, 29 Mar 2010 11:29:34 +0200, myken-kVLBEChPVFc wrote: Is it possible to make a footprint with an arc inside? Not with real arcs, but arbitrarily close. The pads of footprints can be composed of multiple straight tracks. If they all get the same number, pcb considers them to be part of the same pad. The GUI of pcb provides no easy way to draw such complex shapes. The best bet is to draw the footprint with a vector drawing application like inkscape, save as postscript and convert to pcb with ps2edit. See the wiki for more detailed instruction: http://geda.seul.org/wiki/geda:pcb_tips#what_is_the_best_way_to_do_weird_footprints Hope, this helps, ---)kaimartin(--- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: (Solved) Compiling PCB 20001103 - missing libraries
Thanks Dan, I have found my mistake, see previous posting. Robert. -Original Message- From: Dan McMahill d...@mcmahill.net Reply-to: gEDA user mailing list geda-user@moria.seul.org To: gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: Compiling PCB 20001103 - missing libraries Date: Thu, 25 Mar 2010 23:16:30 -0400 Mailer: Thunderbird 2.0.0.24 (Windows/20100228) my...@iae.nl wrote: Hello All, I'm trying to compile and install PCB (version 20091103) and I have an question. I have created two (/home/me/tools/bin, /home/me/tools/share) directories. you shouldn't have to create those by hand. the install should do it. Then I use: ./configure --prefix=/home/me/tools/ --with-exporters=ps gerber nelma bom png make make install looks reasonable So far so good. PCB compiles fine and works great. BUT the log says: Can't scan directory '/home/me/tools/bin/../share/pcb/pcblib-newlib' opendir() returned: 'No such file or directory' is there any sort of /home/me/tools/share/pcb directory? Do I need to do something extra to install the libraries? ./configure --help does not suggest any additional option. that should have worked. can you post the log from 'make install'? You can get this with either: if your shell is tcsh/csh: make install | tee /tmp/install.log if your shell is sh/bash make install 21 | tee /tmp/install.log -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: SFlags definition question
Hello All, Sorry to bother you again with a novice question. I'm in the proces of understanding PCB so please be gentle. I have a component (DPAK) on the top (component) side of my pcb, surrounded by a polygon. I have connected one pad to the polygon by using copper trackes. I also have a polygon on the bottom (solder) side of my pcb, right beneath the one on top. I have connected the two polygons through via's with a solid connection to the plane (polygon). Now I want to free the via's of any soldermask on both sides of the pcb. So I press the K key until the clearance is OK. So far so good. Now my question: I like to fully understand how PCB works so I look in the .pcb file with a text editor and found. Via[312000 28 4000 2000 0 2000 selected,thermal(3S)] and Via[302000 261000 4000 2000 4000 2000 selected,thermal(0S,3S)] I understand that the first one has no clearance and the second one has. Question 1: is the clearance valid for both sides of the pcb? Question 2: In the documentation (pcb.pdf generated during installation) I find in section 8.8.28 Via that the last argument is an SFlags. In F.1.76 SetThermal I find that Style = 3 means a solid connection. So I do not understand what thermal(3--S--) means or (0S,3S). Can anyone help me? Where can I find this kind of information (e.g. definition of SFlags)? I hope you can help, thanks. Regards, Robert ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: SFlags definition question
I think your question concerns solder mask, not copper clearance. So you can use the Solder Mask button on the left (GTK) to make solder mask relief visible. If you need this via as thermal via for parts with thermal center pad, and you want a rectangular shape: You may use a footprint with center pad on the top, and maybe on the bottom too. I used thermal pads on the top only, but for hand soldering I needed a rectangular area free of solder mask in the bottom, so I put single rectangular pads at that location on the bottom side, with some thermal vias on it. Yes I means Solder mask. Thanks for your suggestion I will try that. Only developers should need more details. Well I'm working my way up: novice - user - power user - developer If I start absorbing details only when I start to develop it may be a bit late. Besides that I am a bit of a control freak and I really like to know what's what in my designs. On the other hand I understand that you developers do not have the time to explain every small detain to every novice that comes along claiming he wants to become a developer. But if the PCB project needs more developers they need to be grown (I read that here on the list some time ago ;-), not that I claim to be developer material but I like to understand PCB as much as possible and maybe how knows..some day.. Just point me in the right direction with my silly questions and tell me here to look (here in the sources?, here on the internet?, ?) Thanks for all your time. Regards, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: (Solved) SFlags definition question
I don't fully understand the source code and I don't know if anyone is interested but this is what I found. Apparently there are 5 types of thermals: 1. a X shape with straight spokes 2. a X shape with round spokes 3. a + shape with straight spokes 4. a + shape with round spokes 5. a solid shape In the PCB file they are represented by: 1. a nothing 2. a X 3. a + 4. a t 5. a S The thermal SFlags attribute follows the structure: thermal(layer[spoketype],layer[spoketype],layer[spoketype]) So: Via[10 10 5500 2000 0 3000 thermal(0X)] is a via with a X shape thermal with straight spokes connected to layer 0. Via[10 10 5500 2000 0 3000 thermal(1t)] is a via with a + shape thermal with round spokes connected to layer 1. Via[10 10 5500 2000 0 3000 thermal(0S,1-3+,4)] is a via with: a solid thermal connected to layer 0, a + shape with straight spokes connected to layers 1 through 3, a X shape with straight spokes connected to layer 4 Thanks everyone. Regards, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Compiling PCB 20001103 - missing libraries
Hello All, I'm trying to compile and install PCB (version 20091103) and I have an question. I have created two (/home/me/tools/bin, /home/me/tools/share) directories. Then I use: ./configure --prefix=/home/me/tools/ --with-exporters=ps gerber nelma bom png make make install So far so good. PCB compiles fine and works great. BUT the log says: Can't scan directory '/home/me/tools/bin/../share/pcb/pcblib-newlib' opendir() returned: 'No such file or directory' Do I need to do something extra to install the libraries? ./configure --help does not suggest any additional option. Thanks for any reply. Regards Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Compiling PCB 20001103 - missing libraries
Hello All, I have re-compiled pcb using the same commands and for some reason all is OK now. I have the standard footprint libraries available. I have no idea what when wrong, but sorry to waste your time with this. Regards, Robert -Original Message- From: my...@iae.nl Reply-to: gEDA user mailing list geda-user@moria.seul.org To: geda-user@moria.seul.org Subject: gEDA-user: Compiling PCB 20001103 - missing libraries Date: Thu, 25 Mar 2010 13:56:15 +0100 (CET) Mailer: SquirrelMail (version 1.2.8) Hello All, I'm trying to compile and install PCB (version 20091103) and I have an question. I have created two (/home/me/tools/bin, /home/me/tools/share) directories. Then I use: ./configure --prefix=/home/me/tools/ --with-exporters=ps gerber nelma bom png make make install So far so good. PCB compiles fine and works great. BUT the log says: Can't scan directory '/home/me/tools/bin/../share/pcb/pcblib-newlib' opendir() returned: 'No such file or directory' Do I need to do something extra to install the libraries? ./configure --help does not suggest any additional option. Thanks for any reply. Regards Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Compiling PCB 20001103 - missing libraries
Sorry all, Found the problem: classic mistake of not RTFM The INSTALL file says: After running ./configure with your selected options, run make to build PCB. You can try out the program by running cd src ./pcbtest.sh prior to installation. To install PCB after it has been built run: make install from the top level directory. ^^ Forgot to cd .. back to the top level dir. for the make install. Again sorry to waste your time. Regards, Robert -Original Message- From: myken my...@iae.nl Reply-to: gEDA user mailing list geda-user@moria.seul.org To: gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: Compiling PCB 20001103 - missing libraries Date: Thu, 25 Mar 2010 21:25:21 +0100 Mailer: Evolution 2.28.1 Hello All, I have re-compiled pcb using the same commands and for some reason all is OK now. I have the standard footprint libraries available. I have no idea what when wrong, but sorry to waste your time with this. Regards, Robert -Original Message- From: my...@iae.nl Reply-to: gEDA user mailing list geda-user@moria.seul.org To: geda-user@moria.seul.org Subject: gEDA-user: Compiling PCB 20001103 - missing libraries Date: Thu, 25 Mar 2010 13:56:15 +0100 (CET) Mailer: SquirrelMail (version 1.2.8) Hello All, I'm trying to compile and install PCB (version 20091103) and I have an question. I have created two (/home/me/tools/bin, /home/me/tools/share) directories. Then I use: ./configure --prefix=/home/me/tools/ --with-exporters=ps gerber nelma bom png make make install So far so good. PCB compiles fine and works great. BUT the log says: Can't scan directory '/home/me/tools/bin/../share/pcb/pcblib-newlib' opendir() returned: 'No such file or directory' Do I need to do something extra to install the libraries? ./configure --help does not suggest any additional option. Thanks for any reply. Regards Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is it possible to do square holes in PCB?
Hello all, I did an oval shape hole once by using three overlapping round drill holes, worked fine. maybe you can do the same with 6 small round holes: ooo ooo ooo Cheers, Robert -Original Message- From: Dave N6NZ n...@arrl.net Reply-to: gEDA user mailing list geda-user@moria.seul.org To: gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: Is it possible to do square holes in PCB? Date: Sun, 21 Feb 2010 15:08:15 -0800 Mailer: Apple Mail (2.1077) On Feb 21, 2010, at 2:01 PM, Mark Rages wrote: On Sun, Feb 21, 2010 at 1:55 PM, Anthony Shanks yamazak...@gmail.com wrote: Some parts have mounting brackets that are square, not round. Yes I know I can make a equivalent circlular hole that would fit but it wastes a lot of space doing that and it interferes with routing. Have you talked to your board house about this? I wonder what happens if you specify a reuleaux drill in the fab drawing... How large is the square that you need? At some point, this is just another routed cut-out. You end up with a corner radius the size of the router bit in use, or else you can route a little past the corner to clear the corner of your square bracket. You would have to talk to your PCB house, but I'd be thinking along the lines of agreeing on what router bit is going to be used, and then adding a layer where the tracks represent the centerline of the routing operations. Wacky board shapes done by a CNC router are nothing new, routed cut-outs fall into that category. I'm sure your PCB house has a preferred way of getting the information. They will no doubt charge you the full freight, though, I don't know of any prototype service that does non-rectangular boards, although they might exist. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem: Is it possible to draw a thicker net?
Hallo all, I'm new to this mailinglist so please be gentle. My question: Is it possible to make a net thicker in gschem (not a line but a net). I want to indicate in my schematic than the net is a high current power net. Thanks for your answers. Best regards, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: Is it possible to draw a thicker net?
Hallo Andy, Thanks for your answer. I have also found this option but it does not solve my problem. My design contains both power nets (thick nets) and normal nets (thin or normal nets) and I wish to distinguish between the two in one schematic. I know it is only cosmetic and it will have no further meaning in the process towards a PCB. But for documentation purposes I like to indicate to users the difference between to two. Sorry if my question was not clear about that. Regards, Robert. -Original Message- From: Andy Fierman andyfier...@signality.co.uk Reply-to: gEDA user mailing list geda-user@moria.seul.org To: gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: gschem: Is it possible to draw a thicker net? Date: Thu, 3 Sep 2009 21:45:02 +0100 Hi Robert, I think if you look for the system-gschemrc file (probably in /etc/gEDA/) then you'll find a section in there ; net-style string ; ; Set to thin if you want thin nets. ; Set to thick if you want thick nets. ; This mode also determines what net style gets printed ; ;(net-style thin) (net-style thick) (there are similar sections below that for bus, pin and line styles) If you net style edit this file (as root) then you'll alter the net style for all new schematics (after a quick check: it seems to apply to all schematics as they are opened). Now, if you read through this: http://geda.seul.org/wiki/geda:gsch2pcb_tutorial and look carefully at the section on Setup you'll see that you can put a gschemrc file into ~/.gEDA that will allow you to set any preferred net style for all your projects. I think it is possible to put a gschemrc file in each project that will apply just to that project but I haven't managed to make that work in a quick play. I'm sure there are people with more experience who can tell you about some of the other ways that you can customise gEDA but I hope this gets you off in the right direction. Cheers, Andy. http://signality.co.uk 2009/9/3 myken my...@iae.nl: Hallo all, I'm new to this mailinglist so please be gentle. My question: Is it possible to make a net thicker in gschem (not a line but a net). I want to indicate in my schematic than the net is a high current power net. Thanks for your answers. Best regards, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
