Re: gEDA-user: Adding inner polygons to a plane
On Fri, May 13, 2011 at 12:04:39AM +0100, Peter Clifton wrote: I can't recall exactly why, but I recall being partly opposed to Z-ordering within a single layer before. It might be because it would tend to produce big diffs in the PCB file for Z-ordering changes. Once you were opposing to me, when I was thinking about anti-object flag, and you persuaded me to do anti-layer instead. Which I now see to be a better way. Assigning numbers is another way to do it, but you do have to ensure numbers aren't duplicated, and ideally - don't have gaps.. Hmm.. You could assing polygons number and two polygons with the same number would connect and with different numbers will keep clearance between them. This is first step to make net-aware polygons and later tracks. The first step can be completly independend of nets, just assign them arbitrary identifier somehow manualy. Martin Kupec ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
Packages like Altium (which springs to mind), let you define a layer in terms of its _negative_, so you split up a power plane by defining the _boundary_ between the two (or more) regions. Negative layers are great for defining planes, especially when you want complex splits...and they don't need to be rendered. The solder mask layer is output to gerber files as a negative layer. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, 2011-05-11 at 19:19 +0100, Peter Clifton wrote: Perhaps it would be possible to support a flag on the smaller, clippiING polygon which makes it bully other polygons away from it, EAGLE does this by allowing the user to assign a numeric priority to a polygon. Polygons with higher priority get to bully. but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). I suspect that shorting the polygons together would be the exact opposite of what the user wanted most of the time. Perhaps it should create a DRC violation, with neither of the polygons rendering until the user has fixed the problem (with some kind of visual indicator to show that this is happening!). It seems to me that this would result in the behaviour of least surprise and fewer broken PCBs. Cheers, Rob signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Thu, 2011-05-12 at 14:05 +0100, Robert Spanton wrote: On Wed, 2011-05-11 at 19:19 +0100, Peter Clifton wrote: Perhaps it would be possible to support a flag on the smaller, clippiING polygon which makes it bully other polygons away from it, EAGLE does this by allowing the user to assign a numeric priority to a polygon. Polygons with higher priority get to bully. but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). I suspect that shorting the polygons together would be the exact opposite of what the user wanted most of the time. They would soon learn to stop drawing overlapping polygons though ;) Perhaps it should create a DRC violation, with neither of the polygons rendering until the user has fixed the problem (with some kind of visual indicator to show that this is happening!). It seems to me that this would result in the behaviour of least surprise and fewer broken PCBs. Shorting is not going to break anyone's PCB - its just one of many ways we could operate, and would influence how the user draws their geometry. Perhaps a simple Z-Order (perhaps file location based) would suffice, and we could add bring to front / send to back commands somewhere. Top-most polygons clip and bully lower polygons etc.. I can't recall exactly why, but I recall being partly opposed to Z-ordering within a single layer before. It might be because it would tend to produce big diffs in the PCB file for Z-ordering changes. Assigning numbers is another way to do it, but you do have to ensure numbers aren't duplicated, and ideally - don't have gaps.. Hmm.. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote: Sometimes, I want to add an inner polygon area to a plane in PCB. The area might be a power supply which only has to cover a small area; e.g. 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on top of the plane, there is no cut-out formed and I get shorts. To do what I want, I must cut a hole in the main polygon plane, then add my smaller polygon into it. This is very time consuming and changing the plane once created is very difficult. Is there a way to get PCB to support nested polygons? Not easily. For many power plane cases, these polygons won't actually be truly nested, so it is impossible to infer which polygon the user wishes to clip the other. Perhaps it would be possible to support a flag on the smaller, clippiING polygon which makes it bully other polygons away from it, but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). This class of object would not be so much a pour, but behave more like a line or arc segment. I'm guessing we would still need to retain support for clipping it against pins, pads, lines and arcs. Shouldn't take that much code to make it happen (I already implemented a similar feature once before), I just need to hear that there is general consensus that it is a sensible thing to do. Often for the kind of inner layers you describe, you want some complex boolean logic operation to produce the final shape from various sources. Packages like Altium (which springs to mind), let you define a layer in terms of its _negative_, so you split up a power plane by defining the _boundary_ between the two (or more) regions. Perhaps the way is to go more like mech-CAD systems in defining geometry based upon a hierarchy of boolean operations. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, May 11, 2011 at 11:19 AM, Peter Clifton [1]pc...@cam.ac.uk wrote: On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote: Sometimes, I want to add an inner polygon area to a plane in PCB. The � � area might be a power supply which only has to cover a small area; e.g. � � 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on � � top of the plane, there is no cut-out formed and I get shorts. To do � � what I want, I must cut a hole in the main polygon plane, then add my � � smaller polygon into it. This is very time consuming and changing the � � plane once created is very difficult. Is there a way to get PCB to � � support nested polygons? Not easily. For many power plane cases, these polygons won't actually be truly nested, so it is impossible to infer which polygon the user wishes to clip the other. Perhaps it would be possible to support a flag on the smaller, clippiING polygon which makes it bully other polygons away from it, but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). This class of object would not be so much a pour, but behave more like a line or arc segment. I'm guessing we would still need to retain support for clipping it against pins, pads, lines and arcs. Shouldn't take that much code to make it happen (I already implemented a similar feature once before), I just need to hear that there is general consensus that it is a sensible thing to do. I'm more in favor of anti-traces. They'd be equivalent to zero width traces, but still push polygon out of the way. Then you wouldn't need a nested polygon, just an anti-trace that goes around the border of the new region. References 1. mailto:pc...@cam.ac.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
One of the things I suggested for Peter's pours branch is to add another level of polygon-ness. To summarize, pours creates two layers of polygons - the layer the user creates, and the cut up polygons caused by traces, vias, etc. PCB's core sees the cut up polygons, not the user ones, so things like DRC and connectivity work properly. I suggested a layer of cut-lines between the user polys and the cut up pols, thus: Level 1: user-editable top-level polygons (whole polys) Level 2: user-editable traces which slice up polygons (sliced polys) Level 3: PCB PolygonType objects further cut up by polygon clearances etc (sliced cleared polys) (i.e. what you see in the gerbers) Level 4: output of polygon dicer (sliced, cleared, and diced polygons) (transient, used by exporters) In this example, the user would create one board-sized whole polygon, and suitable lines to slice it into the two power regions (3.3v and 1.8v) (sliced polys). These two sliced polys would then be further broken up by traces, vias, pins, etc, to make the final board. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, 2011-05-11 at 15:17 -0400, DJ Delorie wrote: One of the things I suggested for Peter's pours branch is to add another level of polygon-ness. To summarize, pours creates two layers of polygons - the layer the user creates, and the cut up polygons caused by traces, vias, etc. PCB's core sees the cut up polygons, not the user ones, so things like DRC and connectivity work properly. I suggested a layer of cut-lines between the user polys and the cut up pols, thus: Level 1: user-editable top-level polygons (whole polys) Level 2: user-editable traces which slice up polygons (sliced polys) Level 2 is the missing layer, and yes - it would be really neat to have. I once had an anti-polygons branch, this would be more like anti-tracks. In general, we probably ought to support anti-anything. Level 3: PCB PolygonType objects further cut up by polygon clearances etc (sliced cleared polys) (i.e. what you see in the gerbers) Level 4: output of polygon dicer (sliced, cleared, and diced polygons) (transient, used by exporters) Dicer? How quaint ;) GL doesn't use it, PS export doesn't use it. In fact, only gerbv and PNG really need it I think. Actually, I suppose being fair - the GL render could use the dicer. It could also use its Bentley-Ottman rasteriser (stolen from cairo), which does effectively the same job, but much faster. For now, it turns out the easiest way to render polygons efficiently is with masking, then you only need to rasterise each contour (which doesn't have holes). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
