Re: gEDA-user: Icarus verilog Synthesis
I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. For FPGA work, I am unaware of any engine that can synthesize those constructs. If you read through the XST manual from Xilinx (just for an example), I am pretty sure they tell you what can and cannot be synthesized. The commands you just listed work well for test benches or other verification code (and simulation too) but are probably not appropriate for fpga level design. Maybe VLSI is different - but I have no experience with that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
Hi, Does any one know about any book that describes how to convert a behavioral code into unoptimized gate level netlist. I know that after an unoptimized gate level netlist is got logic synthesis is applied to get an optimized netlist. I have a book called Algorithms for VLSI Design Automation. It has a chapeter on high level synthesis. But it doesnt explain my above question. I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. Regards, Ronald On 9/5/10, Ronald Mathias [1]ronnie.math...@gmail.com wrote: Hi, Thanks a lot. Regards Ronald Mathias On 9/4/10, Philipp Klaus Krause [2]...@spth.de wrote: Am 04.09.2010 06:19, schrieb Ronald Mathias: I transform the Verilog code containing behavioral statements into verilog code that contains only gate level instantiations. This is passed as input to ABC Logic synthesis tool. Finally the output generated by ABC is passed to Versatile Place and Route(VPR) program which generates the bitstream. You don't have to go down to gate level: Simple verilog, (e.g. still allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can the use vis to flatten the resulting blif-mv into blif, which can be read by abc. This is the way I currently do synthesis (for a simulated asic, directly writing the simple verilog vl2mv understands; the resulting gate level verilog is then simulated in Icarus to get timing). Philipp ___ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:ronnie.math...@gmail.com 2. mailto:p...@spth.de 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
Am 04.09.2010 06:19, schrieb Ronald Mathias: I transform the Verilog code containing behavioral statements into verilog code that contains only gate level instantiations. This is passed as input to ABC Logic synthesis tool. Finally the output generated by ABC is passed to Versatile Place and Route(VPR) program which generates the bitstream. You don't have to go down to gate level: Simple verilog, (e.g. still allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can the use vis to flatten the resulting blif-mv into blif, which can be read by abc. This is the way I currently do synthesis (for a simulated asic, directly writing the simple verilog vl2mv understands; the resulting gate level verilog is then simulated in Icarus to get timing). Philipp ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
Hi, Thanks a lot. Regards Ronald Mathias On 9/4/10, Philipp Klaus Krause [1]...@spth.de wrote: Am 04.09.2010 06:19, schrieb Ronald Mathias: I transform the Verilog code containing behavioral statements into verilog code that contains only gate level instantiations. This is passed as input to ABC Logic synthesis tool. Finally the output generated by ABC is passed to Versatile Place and Route(VPR) program which generates the bitstream. You don't have to go down to gate level: Simple verilog, (e.g. still allowed to use '+', '-', but not '*', etc) can be read by vl2mv, you can the use vis to flatten the resulting blif-mv into blif, which can be read by abc. This is the way I currently do synthesis (for a simulated asic, directly writing the simple verilog vl2mv understands; the resulting gate level verilog is then simulated in Icarus to get timing). Philipp ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:p...@spth.de 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
What are you trying to do? Are you really trying to synthesize your Verilog design, meaning you are trying to generate a bit stream to load into your FPGA? Or are you trying to compile and simulate your Verilog? Icarus Verilog is mostly a *simulator*, not a synthesizer. There were some synthesis capabilities back in the 0.8 release, but that support has been largely dropped in the 0.9 releases or current devel branch. Verilog code generator? OK, this suggests that you really are trying to *synthesize* (and not simulate) and no, not even the 0.8 release supported synthesis of user defined tasks. Ronald Mathias wrote: Hi, I have written a verilog code that makes use of a user defined task to do some computation. The task takes two parameters as input and one parameter as output. When I try to synthesize it, I get the following error: internal error: NetProc::nex_output not implemented on object type NetUTask internal error: NetProc::nex_output not implemented on object type NetUTask Does this mean that icarus verilog has not yet support for synthesis of user defined tasks? When I try to send the elaborated netlist to the verilog code generator back end, the task definition is missing from the output. Is this a bug or the verilog code generator backend is still not completely implemented ? Regards, Ronald -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
