Re: gEDA-user: random project idea
On Sat, 05 Apr 2008 09:28:43 -0500 John Griessen [EMAIL PROTECTED] wrote: Levente wrote: http://web.interware.hu/lekovacs/reflow_oven/index.html Actually, it is an electric heater. The problem is that the heat exchange is slow, and it can't maintain the slopes coming from the heat profile. I use a PT100 thermo-sensor mounted on a pice of PCB (not the PCB being reflowed.) Can you increase the number of heater rods? Well, yes. The triac can switch 20Amps on 230V that is plenty of power. I am thinking of some heat shield around the oven. That could reflect IR power to the board, increasing the efficiency. -- Levente http://web.interware.hu/lekovacs ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Sat, 29 Mar 2008 09:19:50 -0500 John Griessen [EMAIL PROTECTED] wrote: Steve Meier wrote: An interesting hobbyist project might be to modify a hot plate to be computer controlled with a thermal couple feed back loop to meet Altera's requirements. Levente has a design for a toaster controller I think he'll share. http://web.interware.hu/lekovacs/reflow_oven/index.html Actually, it is an electric heater. The problem is that the heat exchange is slow, and it can't maintain the slopes coming from the heat profile. I use a PT100 thermo-sensor mounted on a pice of PCB (not the PCB being reflowed.) The software is a quck and dirty hack, and should be rewritten. Cheers, -- Levente http://web.interware.hu/lekovacs ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Levente wrote: http://web.interware.hu/lekovacs/reflow_oven/index.html Actually, it is an electric heater. The problem is that the heat exchange is slow, and it can't maintain the slopes coming from the heat profile. I use a PT100 thermo-sensor mounted on a pice of PCB (not the PCB being reflowed.) Can you increase the number of heater rods? John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Steve Meier wrote: Isn't the switch to rohs soldering a bigger issue? There's a rumor that there is a RoHS exception for package leg pitches of 0.5mm and under, meaning all you do to get exemption is put such a part on your board... There's an email list of people documenting soldering trouble so RoHS can be argued against scientifically. [EMAIL PROTECTED] John Griessen Ecosensory Austin TX tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Steve Meier wrote: An interesting hobbyist project might be to modify a hot plate to be computer controlled with a thermal couple feed back loop to meet Altera's requirements. Levente has a design for a toaster controller I think he'll share. John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Hallo. Am 28.03.2008 um 06:51 schrieb Jesse Gordon: Can you please tell me a little more about meta-FPGA? I have no idea what it means, but I was talking with someone (who knows slightly more about fpgas then I, which still isn't much) a while back the general idea of constructing an fpga inside an fpga, such that once a high-gate-count fpga were programmed, it would function as a much smaller fpga who's internal workings would be well documented and open source, allowing hobbyists to experiment with completely free tools, and perhaps some day a real fpga company would build a native one. Well, the main reason for Meta-FPGA is the hidden bitstream formats for nearly all vendors and the commercial vendor tools in the chain. The idea point out, that it would be possible to develop out a fpga structure, which is free in all meanings. Free tools would offer a tool chain to synthesis, place and route on this free fpga structure. The commercial vendor tools still once a time in need, when the free fpga structure is synthesised, placed and routed on the commercial fpga families. Nice idea i think but until now not realized.. I would think, the main reasons are: * you need nearly 10 to 100 more gate-array to build one gate on the fpga. This means, the Meta-FPGA structure contains 1/10 to 1/100 less gate ressources then the buyed one. * practically all realizations of fpga structure, routing ressources, look-up tables etc are well patented. In fact, this prevent us to develop a free fpga structure with out violating one of this patents. Otherwise we would find a ground- breaking new structure for the fpga. I think the patent issue is a bigger show stopper. Here we are stepping in the field of real hardware, there are a lot of more patents than software developer may thinking off. I did a lot investigation in the fpga topic - and still dream of a free one! Regards, Hagen Sankowski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
High speed memory is now staggering the transmission of each data line to minimize cross talk. High end fpga's can support qdr II memory devices to clock speeds of over 500 MHz. The qdr ii has two data buses one for read and one for writing. Each bus supports a transfer on each edge of the clock. This implies data rates on these buses of over 1 GHz. It isn't the bus rate that will limit performance it is the internal clock rate. 500 MHz as opposed to over 3 GHZ. However, the fpga has all those built in multipliers hundreds of them. So for certain tasks an fpga will completely blow away a standard intel based computer. My inclination would be to build a mother board with both a standard microprocessor and an additional fpga that can be programed by the microprocessor. A customized coprocessor so to speak. Steve Meier On Thu, 2008-03-27 at 19:08 -0400, DJ Delorie wrote: My understanding is that with the GHz busses on modern mobos you need With a soft CPU, the busses can go slower. I wouldn't expect such a project to compete with PCs. I thought it was basically impossible to get it right without assistance from the CAD tool. Well, we can change the CAD tool, can't we? ;-) Is this actually practically feasible with a dumb CAD tool like pcb? You'd have to limit yourself to something that fits in our skill set, sure, but perhaps a less-than-GHz system would be doable. It would be neat to experiment with other cores and stuff besides the usual x86, arm, and mips. Imagine a picoblaze PC running something like DOS, or a nios-linux box. But it's dumb in the sense that it doesn't really contribute to the layout, It does have trace measuring, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Mar 28, 2008, at 10:10 AM, Steve Meier wrote: High speed memory is now staggering the transmission of each data line to minimize cross talk. High end fpga's can support qdr II memory devices to clock speeds of over 500 MHz. The qdr ii has two data buses one for read and one for writing. Each bus supports a transfer on each edge of the clock. This implies data rates on these buses of over 1 GHz. It isn't the bus rate that will limit performance it is the internal clock rate. 500 MHz as opposed to over 3 GHZ. when you move to serial data buses they have PLL clock multipliers that make the serial stream operate at high frequencies. so the I/O speed can be higher than the fabric speed. hardkrash However, the fpga has all those built in multipliers hundreds of them. So for certain tasks an fpga will completely blow away a standard intel based computer. My inclination would be to build a mother board with both a standard microprocessor and an additional fpga that can be programed by the microprocessor. A customized coprocessor so to speak. Steve Meier On Thu, 2008-03-27 at 19:08 -0400, DJ Delorie wrote: My understanding is that with the GHz busses on modern mobos you need With a soft CPU, the busses can go slower. I wouldn't expect such a project to compete with PCs. I thought it was basically impossible to get it right without assistance from the CAD tool. Well, we can change the CAD tool, can't we? ;-) Is this actually practically feasible with a dumb CAD tool like pcb? You'd have to limit yourself to something that fits in our skill set, sure, but perhaps a less-than-GHz system would be doable. It would be neat to experiment with other cores and stuff besides the usual x86, arm, and mips. Imagine a picoblaze PC running something like DOS, or a nios-linux box. But it's dumb in the sense that it doesn't really contribute to the layout, It does have trace measuring, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Jesse Gordon wrote: Igor2 wrote: If we are at tools, I wonder... Is there an FPGA family that I could use without using non-free software at all? Google Slipway. The author says it's not quite ready for building things that are needing reliability and he's busy on a contract job, so it's a ways off, really. John G -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Larry Doolittle wrote: Also as a curiosity, see Reinoud's MPGA, an open source meta-FPGA. That one seems to have dropped off the 'net. Does anyone have an archived copy? I may. I'lll rummage on my hard drive. I liked that concept. You could take a normal FPGA and develop one meta layer program for it with the company's tools, and hire it done if need be, the just program the meta layer as an open FPGA from then on... John G -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Hagen SANKOWSKI wrote: I think the patent issue is a bigger show stopper. Here we are stepping in the field of real hardware, there are a lot of more patents than software developer may thinking off. I did a lot investigation in the fpga topic - and still dream of a free one! FPGAs are now twenty-five years old. Hang in there, and research those old patents -- there'll be a way, but it still is a big task not easily done by amateurs all over the planet...but there's MOSIS... John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
6/6 is doable if you slightly cheat the size of the solder pads. The problem is the vias - a 12 mil hole with 6 mil rules is a 24 mil via pad, with only 39 mil on center (1mm) that leaves 15 mil between vias, which is enough for a 5/5 trace but not a 6/6 trace. So with 6/6 rules, you're limited to the outer THREE rows, not the outer FOUR. Unless there's some trick for staggering the vias to make more room? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
I have routed a 900 pin bga 1mm pitch on 4 signal layers. 30x30 using Larry's math 30/2 - 2 = 13 layers this seems pessimistic. for details see http://archives.seul.org/geda/user/Jan-2005/msg00196.html Steve M. On Thu, 2008-03-27 at 17:21 -0700, Larry Doolittle wrote: Guys - On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote: DJ Delorie wrote: http://www.xilinx.com/products/boards/ml410/index.html They have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like every connector goes directly to an FPGA pin. Maybe one fpga for the cpu core and one for the peripherals, though. I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoid more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may /work/ without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. All interesting ideas, but fundamentally not new. The bigger/faster/cheaper FPGAs get, the more interesting it gets. A few comments on details: 1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. Think carefully about the boot sequence, and how one FPGA can boot the next. Having more than one FPGA is probably a good thing. 2. For Ethernet, you don't want a PHY+MAC, just a PHY. The pin count is lower and the result is more FPGA-like. I have a demo of Gigabit-compatible IP/ARP/UDP in 200 cells plus 32 kbits RAM. I will probably even work on making it useful for real-time communications in the next year. 3. A large BGA can be useful even without a lot of board layers. Assume 1mm pitch and 5/5 space/trace. In concept, reaching all n^2 pads can take approximately n/2-2 routing layers, although that's an overestimate because many interior pads are power and ground. Practically, it takes six layers for 170 user I/O on a 256-pad BGA, and the layer count rises rapidly for those 600 to 1200 pad monsters. If you only route the outer four rows, however, you get 16*(n-4) pads with two routing layers (four physical layers with power/ground). A 676-pad package (26x26) gives you 352 routable pads like that. 4. You can do a lot with FPGA plus DDR SDRAM, outside of traditional CPU design. Just look at Elphel's model 333 camera. http://www3.elphel.com/ Ogg Theora _en_coding faster than most PC's can _de_code it. 5. I have always been impressed by Jan Gray's CPU in FPGA designs. http://fpgacpu.org/ Jan himself has moved on to other work. If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
ah it assumes all pins are io and that you can only get one trace between rows? Realistically, the center pins are power and ground with io allong the edges. so lets say for a row the center half of the pins are power and ground and you can get two traces between rows. max signal layers = (n/2 - 2) / 2 n/2 says half the pins are io -2 says on an outer surface we can touch the outer io pad with a trace. / 2 says we can place two traces between each row Steve M. On Fri, 2008-03-28 at 11:43 -0700, Steve Meier wrote: I have routed a 900 pin bga 1mm pitch on 4 signal layers. 30x30 using Larry's math 30/2 - 2 = 13 layers this seems pessimistic. for details see http://archives.seul.org/geda/user/Jan-2005/msg00196.html Steve M. On Thu, 2008-03-27 at 17:21 -0700, Larry Doolittle wrote: Guys - On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote: DJ Delorie wrote: http://www.xilinx.com/products/boards/ml410/index.html They have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like every connector goes directly to an FPGA pin. Maybe one fpga for the cpu core and one for the peripherals, though. I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoid more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may /work/ without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. All interesting ideas, but fundamentally not new. The bigger/faster/cheaper FPGAs get, the more interesting it gets. A few comments on details: 1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. Think carefully about the boot sequence, and how one FPGA can boot the next. Having more than one FPGA is probably a good thing. 2. For Ethernet, you don't want a PHY+MAC, just a PHY. The pin count is lower and the result is more FPGA-like. I have a demo of Gigabit-compatible IP/ARP/UDP in 200 cells plus 32 kbits RAM. I will probably even work on making it useful for real-time communications in the next year. 3. A large BGA can be useful even without a lot of board layers. Assume 1mm pitch and 5/5 space/trace. In concept, reaching all n^2 pads can take approximately n/2-2 routing layers, although that's an overestimate because many interior pads are power and ground. Practically, it takes six layers for 170 user I/O on a 256-pad BGA, and the layer count rises rapidly for those 600 to 1200 pad monsters. If you only route the outer four rows, however, you get 16*(n-4) pads with two routing layers (four physical layers with power/ground). A 676-pad package (26x26) gives you 352 routable pads like that. 4. You can do a lot with FPGA plus DDR SDRAM, outside of traditional CPU design. Just look at Elphel's model 333 camera. http://www3.elphel.com/ Ogg Theora _en_coding faster than most PC's can _de_code it. 5. I have always been impressed by Jan Gray's CPU in FPGA designs. http://fpgacpu.org/ Jan himself has moved on to other work. If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Again pessimistic. max signal layers = (n/2 - 2) / 2 / 2 the last / 2 says I get to work of of each edge of the device. So I should have been able to route a 900 pin fpga on 4 layers. at least as far as clearing the fpga. If we don't use via in pads we loose the two outer layers for routing to the inner io pads. max signal layers = ((n/2 - 2) / 2 / 2) + 2 and we have to make up for them with additional signal layers. Steve Meier On Fri, 2008-03-28 at 11:53 -0700, Steve Meier wrote: ah it assumes all pins are io and that you can only get one trace between rows? Realistically, the center pins are power and ground with io allong the edges. so lets say for a row the center half of the pins are power and ground and you can get two traces between rows. max signal layers = (n/2 - 2) / 2 n/2 says half the pins are io -2 says on an outer surface we can touch the outer io pad with a trace. / 2 says we can place two traces between each row Steve M. On Fri, 2008-03-28 at 11:43 -0700, Steve Meier wrote: I have routed a 900 pin bga 1mm pitch on 4 signal layers. 30x30 using Larry's math 30/2 - 2 = 13 layers this seems pessimistic. for details see http://archives.seul.org/geda/user/Jan-2005/msg00196.html Steve M. On Thu, 2008-03-27 at 17:21 -0700, Larry Doolittle wrote: Guys - On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote: DJ Delorie wrote: http://www.xilinx.com/products/boards/ml410/index.html They have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like every connector goes directly to an FPGA pin. Maybe one fpga for the cpu core and one for the peripherals, though. I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoid more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may /work/ without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. All interesting ideas, but fundamentally not new. The bigger/faster/cheaper FPGAs get, the more interesting it gets. A few comments on details: 1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. Think carefully about the boot sequence, and how one FPGA can boot the next. Having more than one FPGA is probably a good thing. 2. For Ethernet, you don't want a PHY+MAC, just a PHY. The pin count is lower and the result is more FPGA-like. I have a demo of Gigabit-compatible IP/ARP/UDP in 200 cells plus 32 kbits RAM. I will probably even work on making it useful for real-time communications in the next year. 3. A large BGA can be useful even without a lot of board layers. Assume 1mm pitch and 5/5 space/trace. In concept, reaching all n^2 pads can take approximately n/2-2 routing layers, although that's an overestimate because many interior pads are power and ground. Practically, it takes six layers for 170 user I/O on a 256-pad BGA, and the layer count rises rapidly for those 600 to 1200 pad monsters. If you only route the outer four rows, however, you get 16*(n-4) pads with two routing layers (four physical layers with power/ground). A 676-pad package (26x26) gives you 352 routable pads like that. 4. You can do a lot with FPGA plus DDR SDRAM, outside of traditional CPU design. Just look at Elphel's model 333 camera. http://www3.elphel.com/ Ogg Theora _en_coding faster than most PC's can _de_code it. 5. I have always been impressed by Jan Gray's CPU in FPGA designs. http://fpgacpu.org/ Jan himself has moved on to other work. If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. - Larry ___ geda-user mailing list
Re: gEDA-user: random project idea
Cheating? I did that board when pcb only I meant that hobby folks can rarely afford to have via-in-pad done. Unless there's some way to hand-prep each via so the bga can be soldered on. Otherwise, we need to either stick with normal rules or avoid BGAs altogether. The real issue here separation the hobbyist from the professional is the cost of the components. Boards of this nature are likely to run into the thousands of dollars each for small quantities (pcb fabrication, components and assembly). Yup. I think technology has gotten to the point where the hobbyist can make *a* motherboard, but not a leading edge one. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Steve - On Fri, Mar 28, 2008 at 10:27:28AM -0700, Steve Meier wrote: On Fri, 2008-03-28 at 10:20 -0700, Larry Doolittle wrote: OK. Just be sure to give the FPGA direct access (via PHY) to Ethernet. The same concept also applies to network performance. I'd venture to say you want four RJ-45's: two for the traditional microprocessor and two for the FPGA. Good idea add to that taking advantage of the optical networking capabilities of the fpgas. If you're willing to make the jump from $30 to $300 FPGAs, that is. The cheap ones don't have the high speed serial capability. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Cheating? I did that board when pcb only supported 8 layers so yep lie steal cheat grand larceny I did what ever I could to make it fit ;) And I am still thrilled that the difference between detection on the analog channels was less then 10 pico seconds. Far below what we could directly measure on a high end lecroy scope. Looking at the image it appears that there were as many as 8 rows deep of io from the edge. so 8 - 1 = 7 rows of inner io / 2 = 3.5 layers. for 7 rows of io 7 - 1 = 6 rows of inner io / 2 = 3 layers. So in general I agree that 7 rows of io depth can be squeezed into 3 layers, however getting to the edge of the fpga is just the start then you have to reach all the devices and the fpga itself has configuration pins scattered in such a manner as to interfere with neat orderly math. In reality there is also a relationship to board component surface area density and the number of signal layers you have to arrange traces. Fewer signal layers tends to force your components further apart. Yea about getting 6 voltage layers and 2 ground layers into the remaining 4 layers. I do recommend rethinking only one trace between rows especially for anyone using differential IO. The real issue here separation the hobbyist from the professional is the cost of the components. Boards of this nature are likely to run into the thousands of dollars each for small quantities (pcb fabrication, components and assembly). Steve M. On Fri, 2008-03-28 at 15:08 -0400, DJ Delorie wrote: Ok, you're cheating by using via-in pad ;-) I think the generic breakout (at least for us hobby types) is one trace between pads, and one between vias. So you can bring out two (signal) rows on top, two rows (through vias) to some other layer, and one more row for each additional layer. In your example, you're bringing out eight signal rows, so: two on top, two on next, and four more layers for the rest, or six signal layers. If you can get two traces between pads, that's an extra row that can come out on top. If you can get two traces between vias, it's three rows for the first non-top layer, and two rows for each layer beyond that. For your example, that's three on top, three on next, and one more layer for the next two. You should have been able to do it with only three signal layers. between:1 1/2 2 signal rows --- 1 1 1 1 2 1 1 1 3 2 1 1 4 2 2 2 5 3 2 2 6 4 3 2 7 5 4 3 8 6 5 3 9 7 6 4 108 7 4 None of this includes the power block at the center, or other power pins. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
My understanding is that the backside of the via hole pattern is filled with an epoxy which prevents the chimney effect (heat rising through the via and sucking/wicking the solder down into the via). I think that should be doable by a hobbyist. Isn't the switch to rohs soldering a bigger issue? Steve Meier On Fri, 2008-03-28 at 15:43 -0400, DJ Delorie wrote: Cheating? I did that board when pcb only I meant that hobby folks can rarely afford to have via-in-pad done. Unless there's some way to hand-prep each via so the bga can be soldered on. Otherwise, we need to either stick with normal rules or avoid BGAs altogether. The real issue here separation the hobbyist from the professional is the cost of the components. Boards of this nature are likely to run into the thousands of dollars each for small quantities (pcb fabrication, components and assembly). Yup. I think technology has gotten to the point where the hobbyist can make *a* motherboard, but not a leading edge one. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Isn't the switch to rohs soldering a bigger issue? As in we don't have to ? :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Well not yet at least not here in the US how about our European friends though? On Fri, 2008-03-28 at 16:26 -0400, DJ Delorie wrote: Isn't the switch to rohs soldering a bigger issue? As in we don't have to ? :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Also, even we in the US won't be able to get leaded bga's for ever. On Fri, 2008-03-28 at 16:26 -0400, DJ Delorie wrote: Isn't the switch to rohs soldering a bigger issue? As in we don't have to ? :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Well not yet at least not here in the US how about our European friends though? I was thinking more of hobbyists have less restrictions than commercial as far as ROHS goes. At least, that's if we can *get* non-ROHS parts. I don't mind ROHS parts as long as I can use 63/37 solder. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
I have seen rohs bga's where the balls have been removed and reballed with leaded balls. Seems like a risky extra step to avoid the temperature requirements. How hot does your hot plate get? Steve M. On Fri, 2008-03-28 at 16:34 -0400, DJ Delorie wrote: Well not yet at least not here in the US how about our European friends though? I was thinking more of hobbyists have less restrictions than commercial as far as ROHS goes. At least, that's if we can *get* non-ROHS parts. I don't mind ROHS parts as long as I can use 63/37 solder. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
I have seen rohs bga's where the balls have been removed and reballed with leaded balls. Seems like a risky extra step to avoid the temperature requirements. How hot does your hot plate get? Hot enough, I think. I haven't had a chance to see how hot it gets - I just remove the board once the solder melts. It's not like it's a controlled temperature source or anything. But as it's not controlled, lead solder gives me more elbow room. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
An interesting hobbyist project might be to modify a hot plate to be computer controlled with a thermal couple feed back loop to meet Altera's requirements. I've been thinking of having a friend machine off the cast iron top half and bolt on an aluminum disk, so that it heats faster and more evently, and adding thermocouples at that point. But the reality is, it pretty much just works for me at the moment, and it was only $20. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Fri, 28 Mar 2008 13:28:22 -0700, Steve Meier wrote: Well not yet at least not here in the US how about our European friends though? It took me quite a while to find a decent non-lead solder that produces smooth reliable connections when hand soldered. Standard SAC sucks. The guys at Balver did some metallurgy magic and came up with SN100. Never returned to lead since I got it directly from manufacturer. I managed to avoid BGAs though. ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
DJ Delorie [EMAIL PROTECTED] wrote: ATX motherboard (or any pc motherboard shape, really, like micro-atx or some laptop). PCI/PCIe slots, ISA slots, standard connectors, SDRAM - whatever. A huge FPGA in the middle. Or two or three big QFP ones. 100% synthetic circuitry, including a soft CPU, in a PC case. Sounds a lot like the Xilinx ML410: http://www.xilinx.com/products/boards/ml410/index.html Cheers, Jean-Francois ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Thu, Mar 27, 2008 at 06:36:38PM -0400, DJ Delorie wrote: ATX motherboard (or any pc motherboard shape, really, like micro-atx or some laptop). PCI/PCIe slots, ISA slots, standard connectors, SDRAM - whatever. A huge FPGA in the middle. [...] My understanding is that with the GHz busses on modern mobos you need to pay serious attention to matching trace lengths and impedances exactly for the different lines of the bus. I thought it was basically impossible to get it right without assistance from the CAD tool. Am I wrong? Is this actually practically feasible with a dumb CAD tool like pcb? No offense, really -- I love pcb! But it's dumb in the sense that it doesn't really contribute to the layout, just does a pretty good job of letting you do the layout. I've never had much luck with the autorouter even for moderately complex stuff, nevermind creating balanced busses. -- Randall ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Thu, Mar 27, 2008 at 5:36 PM, DJ Delorie [EMAIL PROTECTED] wrote: ATX motherboard (or any pc motherboard shape, really, like micro-atx or some laptop). PCI/PCIe slots, ISA slots, standard connectors, SDRAM - whatever. A huge FPGA in the middle. Or two or three big QFP ones. 100% synthetic circuitry, including a soft CPU, in a PC case. If it's designed for QFP FPGAs we might be able to get away with a four layer board, just choose pins wisely. Ok, back to sanity now... http://geekz.co.uk/lovesraymond/archive/taking-freedom-further -- Mark Rages, Engineer Midwest Telecine LLC [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
My understanding is that with the GHz busses on modern mobos you need With a soft CPU, the busses can go slower. I wouldn't expect such a project to compete with PCs. I thought it was basically impossible to get it right without assistance from the CAD tool. Well, we can change the CAD tool, can't we? ;-) Is this actually practically feasible with a dumb CAD tool like pcb? You'd have to limit yourself to something that fits in our skill set, sure, but perhaps a less-than-GHz system would be doable. It would be neat to experiment with other cores and stuff besides the usual x86, arm, and mips. Imagine a picoblaze PC running something like DOS, or a nios-linux box. But it's dumb in the sense that it doesn't really contribute to the layout, It does have trace measuring, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
http://geekz.co.uk/lovesraymond/archive/taking-freedom-further Yeah, that fits. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
DJ Delorie wrote: http://www.xilinx.com/products/boards/ml410/index.html They have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like every connector goes directly to an FPGA pin. Maybe one fpga for the cpu core and one for the peripherals, though. I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoid more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may /work/ without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. -Jesse ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Guys - On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote: DJ Delorie wrote: http://www.xilinx.com/products/boards/ml410/index.html They have a lot of support chips on that board, though. Like the south bridge, CF controller, PCI bridge, etc. I was thinking more like every connector goes directly to an FPGA pin. Maybe one fpga for the cpu core and one for the peripherals, though. I like the idea. If the main FPGA was big enough, maybe it'd only need one, but I guess we're trying to avoid more then 4 layers, and big bga=more then 4 layers. But if two fpgas were sitting right besides eachother, with about 25 pins lining up, and just connected right together, (with qfp) the run would be short, straight, and all the same length, it could be over ground-plane layer there. I think considerable fpga-fpga speeds could be attained. If the run was short enough, it may /work/ without termination. By having several such fpgas in a row, each connected likewise to the one near it, or maybe having 1 in the middle then 4 around it, one on each side, I'm sure enough pins could be attained to feed all the peripherals. It may even be doable on a 2 layer board, but four is much more then twice as good as 2. (I think it's more then twice the cost too :-) Interfacing to the ram at high speeds could be tricky, so it might be better to have the ram in parallel (wider data bus) rather then longer address space, to allow faster byte/sec without faster addresses/second. All interesting ideas, but fundamentally not new. The bigger/faster/cheaper FPGAs get, the more interesting it gets. A few comments on details: 1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. Think carefully about the boot sequence, and how one FPGA can boot the next. Having more than one FPGA is probably a good thing. 2. For Ethernet, you don't want a PHY+MAC, just a PHY. The pin count is lower and the result is more FPGA-like. I have a demo of Gigabit-compatible IP/ARP/UDP in 200 cells plus 32 kbits RAM. I will probably even work on making it useful for real-time communications in the next year. 3. A large BGA can be useful even without a lot of board layers. Assume 1mm pitch and 5/5 space/trace. In concept, reaching all n^2 pads can take approximately n/2-2 routing layers, although that's an overestimate because many interior pads are power and ground. Practically, it takes six layers for 170 user I/O on a 256-pad BGA, and the layer count rises rapidly for those 600 to 1200 pad monsters. If you only route the outer four rows, however, you get 16*(n-4) pads with two routing layers (four physical layers with power/ground). A 676-pad package (26x26) gives you 352 routable pads like that. 4. You can do a lot with FPGA plus DDR SDRAM, outside of traditional CPU design. Just look at Elphel's model 333 camera. http://www3.elphel.com/ Ogg Theora _en_coding faster than most PC's can _de_code it. 5. I have always been impressed by Jan Gray's CPU in FPGA designs. http://fpgacpu.org/ Jan himself has moved on to other work. If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. Think carefully about the boot sequence, and how one FPGA can boot the next. Having more than one FPGA is probably a good thing. What about the new flash-based FPGAs? Maybe not as big, but they seem to be instant-on. I suppose we could have a CPLD sequence the boot/reset/run sequence. Assume 1mm pitch and 5/5 space/trace. In concept, reaching all If we can fit it into 6/6 trace/space with 12 mil via holes, that's within spec for common prototype fabs (pcb-pool, specifically, which does 4 and 6 layer). Of course, with QFP, you can hand solder the chips and they easily fit in 6/6 rules. an overestimate because many interior pads are power and ground. I looked up a spartan-3 FB676, which has 300k gates. The five innermost rows (100 balls) are all power/ground. There are eight rows after that; the outer four make up 352 balls, meaning we lose only about 224 balls. It's 1mm pitch, too. Sweet. Now, if I could solder those on my hotplate... :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Randall Nortman wrote: I thought it was basically impossible to get it right without assistance from the CAD tool. PCIe keeps the signal lines differential and regular, so you have a chance. The open graphics project is slowly moving along -- they are motivated by several partners that hold the ultimate copyright to all the GPL parts and plan to make a fabless chip business of it. The scope of the idea is so big, and the goal of motherboards is always speed, so it seems not a match for open projects... but maybe Xilinx would fund it for a while :-) DJ Delorie wrote: I was thinking more like every connector goes directly to an FPGA pin. I think it would max out at 400MHz thenthat's a routed-big-design FPGA logic speed limit, right? Larry Doolittle wrote: 1. Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. [jg] I guess that's because the fpga makers seem to not want to let out their programming details -- probably because they let Mentor and Synplicity and the like do all their tools and THEY don't want it let out. JG -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Larry Doolittle [EMAIL PROTECTED] writes: Assume 1mm pitch and 5/5 space/trace. Turns out Sierra can do this, for a fee. A 7x7 4-layer board, with 5/5 rules and 12 mil holes, costs about $130ea qty5 if you don't mind waiting for it. Of course, that's a $650 investment, and you still have to buy the FPGAs and figure out how to solder them on. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote: Larry Doolittle wrote: Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. I guess that's because the fpga makers seem to not want to let out their programming details -- probably because they let Mentor and Synplicity and the like do all their tools and THEY don't want it let out. Tools are certainly part of the story. But it also strikes me as a chicken-and-egg problem. The user's don't demand or exercise the tools because of the conceptual problems and the silicon limitations. On Thu, Mar 27, 2008 at 08:59:47PM -0400, DJ Delorie wrote: What about the new flash-based FPGAs? Maybe not as big, but they seem to be instant-on. I suppose we could have a CPLD sequence the boot/reset/run sequence. Where the boot information is kept isn't as important as how to reprogram it without risk of bricking the board. If we can fit it into 6/6 trace/space with 12 mil via holes, that's within spec for common prototype fabs (pcb-pool, specifically, which does 4 and 6 layer). 6/6 is doable if you slightly cheat the size of the solder pads. Now, if I could solder [a spartan-3 FB676] on my hotplate... :-) I have seen instructions for home-soldering BGAs. I haven't tried them myself, and I don't know what the size limits are. On Thu, Mar 27, 2008 at 09:34:27PM -0500, John Griessen wrote: If anyone wants to talk shop about CPUs in FPGA, like how to add Cache, MMU, and SDRAM to a 32-bit Gray-esque processor, let's find a better list. I'm not sure about as far as a MMU linux running processor in FPGA, I think of buying that in hardware, but how hard is it to take a ethernet MAC and program it to hook up to a low power C8051 from silabs and put the fpga machine in a Actel smallest igloo fpga? The small CPU jobs are certainly practical in small FPGAs, Jan's and many others. Opencores is riddled with them. But for the motherboard concept that started this discussion, I think people would be interested in something beefier. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
On Thu, 27 Mar 2008, Larry Doolittle wrote: On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote: Larry Doolittle wrote: Self-reconfigurable FPGAs have been promised for years, but aren't ready, and probably never will be. I guess that's because the fpga makers seem to not want to let out their programming details -- probably because they let Mentor and Synplicity and the like do all their tools and THEY don't want it let out. Tools are certainly part of the story. But it also strikes me as a chicken-and-egg problem. The user's don't demand or exercise the tools because of the conceptual problems and the silicon limitations. If we are at tools, I wonder... Is there an FPGA family that I could use without using non-free software at all? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Igor2 wrote: If we are at tools, I wonder... Is there an FPGA family that I could use without using non-free software at all? I was going to ask that very question. The closest I've come to free was xilinx's ISE Impact webpack which of course is only free to use and only free for non-comercial projects. I was wondering if xilinx would ever release the information to allow people to make a completely open source truely free synthesis tool. -Jesse ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: random project idea
Jesse - On Thu, Mar 27, 2008 at 08:28:29PM -0700, Jesse Gordon wrote: Igor2 wrote: If we are at tools, I wonder... Is there an FPGA family that I could use without using non-free software at all? I was going to ask that very question. The closest I've come to free was xilinx's ISE Impact webpack which of course is only free to use and only free for non-comercial projects. I was wondering if xilinx would ever release the information to allow people to make a completely open source truely free synthesis tool. Of course, synthesis is the easy part, Icarus (almost, sort of) does that already. Place and Route is hard, especially because so little experience exists in the open source community. The real sticking point is bitstream generation, where Xilinx and Altera are traditionally anal. This question has a long history. Perhaps the most notable discussion is the 173-long thread titled FPGA openness in 2000 in comp.arch.fpga. I don't think anything important has changed since then regarding Xilinx or Altera. On the free front, we have the excellent research of Adam Megacz http://research.cs.berkeley.edu/project/slipway/ Too bad the targeted device is so pathetic. Also as a curiosity, see Reinoud's MPGA, an open source meta-FPGA. That one seems to have dropped off the 'net. Does anyone have an archived copy? - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
