Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process
[EMAIL PROTECTED] wrote: Good day! I'm just a NB in Verilog design, sorry if my question is too stupid :) I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. I became familiar with IV modelling system, but synth restrain my activity - i get strange error with the simplest module: Are you really intending to *synthesize* with Icarus Verilog? It is most common in the Xilinx flow to use Icarus Verilog for simulation then use xst for synthesis. If that is the case for you, then you do not want to use the -tfpga flag to Icarus Verilog. That will attempt to synthesize, when I think you want to only simulate. Does this link help? http://iverilog.wikia.com/wiki/User_Guide -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process
Good day! I'm just a NB in Verilog design, sorry if my question is too stupid :) I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. I became familiar with IV modelling system, but synth restrain my activity - i get strange error with the simplest module: module D (clk, reset, out, in); input clk, reset, in; output out; regout; always @ (negedge clk) if (reset) out = 1'b0; else out = in; endmodule iverilog -tfpga test.v test.v:7: sorry: Forgot to implement NetCondit::synth_sync test.v:6: error: Unable to synthesize synchronous process. 2 error(s) in post-elaboration processing. Where is my mistake? What should i read to understand my problem? Thanks! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process
On Tue, Jun 03, 2008 at 02:09:34AM +0400, [EMAIL PROTECTED] wrote: I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. Welcome! iverilog -tfpga test.v test.v:7: sorry: Forgot to implement NetCondit::synth_sync test.v:6: error: Unable to synthesize synchronous process. 2 error(s) in post-elaboration processing. Where is my mistake? What should i read to understand my problem? I guess you use the devel tree. If you really want to synthesize, you should use 0.8.6 instead. If you want to help port the synthesizer from 0.8.6 to current devel, read the source and start hacking! Synthesis in Icarus is historically weak compared to commercial tools. Steve mentioned to me privately that he might find time to think about this again in s23%%43qaazz [carrier lost] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
