Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Timothy Normand Miller wrote: Sorry about the cross-post. We're -- THIS close to getting OGD1 done, with artwork in the hands of board makers who are working on quotes, and we've discovered a problem that could make the video output unacceptable. We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. We're seeing like 900ps of jitter, which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) One option is to use the clock generators in the Lattice part, but even they have like 400ps of jitter, and they also severely limit the range of frequencies we can generate. So the best solution we can come up with is to put on some external clock generators. One for each video head. Problems: (1) more time to mod the design, (2) up to $15 each for the generators, (3) we have no idea what generators to use, how good they are, how to wire them. Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? Try the MAX3674. Jitter is less than a picosecond or two. Stick a crystal one side and you can program the thing for and output from 21.25MHz to 1360MHz. It has parallel or I2C programming. PSRR is good. http://www.maxim-ic.com/quick_view2.cfm/qv_pk/5634 -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
BTW, I just wanted to thank everyone for the help with the clock generation problem. Lots of useful information! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Random ideas: try better supply decoupling or package, stop other FPGA outputs when the clock generator is active (or at least put them far from the generator outputs). Check PCB - especially for return current paths of noisy signals. -r. On Nov 28, 2007 7:09 PM, Timothy Normand Miller [EMAIL PROTECTED] wrote: Sorry about the cross-post. We're -- THIS close to getting OGD1 done, with artwork in the hands of board makers who are working on quotes, and we've discovered a problem that could make the video output unacceptable. We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. We're seeing like 900ps of jitter, which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) One option is to use the clock generators in the Lattice part, but even they have like 400ps of jitter, and they also severely limit the range of frequencies we can generate. So the best solution we can come up with is to put on some external clock generators. One for each video head. Problems: (1) more time to mod the design, (2) up to $15 each for the generators, (3) we have no idea what generators to use, how good they are, how to wire them. Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? Unfortunately, it could take quite a long time for us to find suppliers of clock generators, get samples, wire them up and test them, etc., so we just need find out if someone out there already has the right answer or knows where to look for it. Thank you for your time! -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Sorry about the cross-post. We're -- THIS close to getting OGD1 done, with artwork in the hands of board makers who are working on quotes, and we've discovered a problem that could make the video output unacceptable. We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. We're seeing like 900ps of jitter, which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) One option is to use the clock generators in the Lattice part, but even they have like 400ps of jitter, and they also severely limit the range of frequencies we can generate. So the best solution we can come up with is to put on some external clock generators. One for each video head. Problems: (1) more time to mod the design, (2) up to $15 each for the generators, (3) we have no idea what generators to use, how good they are, how to wire them. Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? Unfortunately, it could take quite a long time for us to find suppliers of clock generators, get samples, wire them up and test them, etc., so we just need find out if someone out there already has the right answer or knows where to look for it. Thank you for your time! -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter clock
Hello Timothy, take a look at Analog Devices AD9516-0 ... 5 family, these are flexible clock generators with many outputs and low jitter performance, as far as i understood in the femti-seconds range ( 1ps jitter). I have no practical experience with them but i plan to use them in a new project. Michael Timothy Normand Miller wrote: Sorry about the cross-post. We're -- THIS close to getting OGD1 done, with artwork in the hands of board makers who are working on quotes, and we've discovered a problem that could make the video output unacceptable. We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. We're seeing like 900ps of jitter, which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) One option is to use the clock generators in the Lattice part, but even they have like 400ps of jitter, and they also severely limit the range of frequencies we can generate. So the best solution we can come up with is to put on some external clock generators. One for each video head. Problems: (1) more time to mod the design, (2) up to $15 each for the generators, (3) we have no idea what generators to use, how good they are, how to wire them. Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? Unfortunately, it could take quite a long time for us to find suppliers of clock generators, get samples, wire them up and test them, etc., so we just need find out if someone out there already has the right answer or knows where to look for it. Thank you for your time! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Timothy - On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. Welcome to the club. So the best solution we can come up with is to put on some external clock generators. One for each video head. Problems: (1) more time to mod the design, (2) up to $15 each for the generators, (3) we have no idea what generators to use, how good they are, how to wire them. Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? I live and breathe high-frequency clock jitter. A good clock subsystem has less than 1 ps rms clock jitter, at least in a limited band (e.g., 20 Hz to 20 MHz). Bad layout can screw up a design even if you use good parts. I have had positive experience with parts from ICS and AD. My experience is not specific to video. Unfortunately, it could take quite a long time for us to find suppliers of clock generators, get samples, wire them up and test them, etc., so we just need find out if someone out there already has the right answer or knows where to look for it. You haven't mumbled enough about the specific needs for me to help much yet. Frequency range, degree of programmability, signal levels, etc. Do you need a PLL, or is a programmable divider chain enough? An AD9512 is a nice part, and only US$20 each, with several programmable outputs. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. DCMs have lousy jitter, yes. Altera parts have real PLLs, though. which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) That's kind of surprising, because the DVI spec has a bitrate 10x the fundamental clock, so both the transmitter and receiver generally have to have PLLs. So the best solution we can come up with is to put on some external clock generators. Cypress makes a bunch, and some inexpensive devboards called candy boards, eg peppermint. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
Ben - On Wed, Nov 28, 2007 at 12:49:50PM -0800, Ben Jackson wrote: On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. DCMs have lousy jitter, yes. Altera parts have real PLLs, though. Even if the FPGA chip were perfect, there are so many digital signals flying around the package that ground bounce alone will kill any semblance of low jitter performance. This may be too fine a point for video work. My work involves SDR-like projects where the requirements on the order of 1ps rms. which causes artifacts on DVI monitors at resolutions as low as 1280x1024 when the cable gets beyond a certain length. (I don't recall all the details.) That's kind of surprising, because the DVI spec has a bitrate 10x the fundamental clock, so both the transmitter and receiver generally have to have PLLs. Just the receiver, right? And that cable length comment makes me suspicious something more subtle is going on. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Wed, Nov 28, 2007 at 01:02:00PM -0800, Larry Doolittle wrote: DCMs have lousy jitter, yes. Altera parts have real PLLs, though. Even if the FPGA chip were perfect, there are so many digital signals flying around the package that ground bounce alone will kill any semblance of low jitter performance. The Altera PLLs have dedicated supply (and output) pins and are located in the corners of the chip. The Xilinx DCMs are on the 2.5V VCCAUX rail shared with other things. I suppose it's worth seeing if the original board would perform better with a cleaner VCCAUX, but the nature of a DCM is inherently jittery. This may be too fine a point for video work. My work involves SDR-like projects where the requirements on the order of 1ps rms. At work I'm on a project that is generating high bandwidth signals up to 1G and our LOs are custom PLL modules (small boards with can lids) from Mini Circuits. Sounds like overkill for DVI, though. That's kind of surprising, because the DVI spec has a bitrate 10x the fundamental clock, so both the transmitter and receiver generally have to have PLLs. Just the receiver, right? And that cable length comment makes me suspicious something more subtle is going on. I've looked at receivers more closely than transmitters, but I assume that the input to the transmitter is the fundamental clock plus the wide (32? 36?) bit RGB+control plane. The serial output has the 10x bitrate, so it must make it internally. One from Conexant I just googled shows a PLL in the block diagram. My point being that the transmitter chip should be fine as long as the jitter does not impact setup-and-hold times at the input and the PLL rides over it. Is there an external loop filter to play with? Ohh it just occured to me that perhaps the problem is that the 10x clock is made from the PLL but the CLK signal on the DVI is the original clock, not a divide-by-10 of the PLL. In that case maybe there are transmitters where this is different? -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007, at 4:02 PM, Larry Doolittle wrote: That's kind of surprising, because the DVI spec has a bitrate 10x the fundamental clock, so both the transmitter and receiver generally have to have PLLs. Just the receiver, right? And that cable length comment makes me suspicious something more subtle is going on. Impedance mismatch and reflections, possibly? -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007 11:09 AM, Timothy Normand Miller [EMAIL PROTECTED] wrote: Does anyone know anything about these? Do you have experience with specific high-frequency clock generators and know how they perform and what kind of jitter they produce? These are kind of like those four pin crystal oscillators except they are six pin devices, with the extra pins for i2c programmeing. Jitter specs look good. http://www.alldatasheet.com/datasheet-pdf/pdf/195314/SILABS/SI570.html -- = Chris Albertson Redondo Beach, California ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter
On Nov 28, 2007, at 1:49 PM, Ben Jackson wrote: On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote: We've discovered that the clock generators in the Xilinx FPGA part are lousy for generating video clocks. DCMs have lousy jitter, yes. Indeed. The Spartan 3E claims +/- 100 ps jitter on the DCM's CLK0 (in- phase) output and +/- 150 ps on the CLK90, CLK180 and CLK270 (phase- shifted) outputs. The clock-doubler outputs claim +/- 1% of the clock- in period + 150 ps jitter. When doing integer division, the CLKDV outputs claim +/- 150 ps jitter. When doing non-integral division, the CLKDV output claims +/- 1% of the clock-in period + 200 ps jitter. Then when one reads the footnotes, one learns that these numbers are in addition to any input clock jitter. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
