Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
al davis wrote: On Tuesday 23 February 2010, John Griessen wrote: Would you still use gschem/gnetlist to schematically connect verilog modules? That depends on having a good translator first, right? Anything that generates a netlist. Gnucap uses language plugins to read whatever input format. Maybe someone could make a language plugin to read and write the gschem format directly. Once this is done, it will also give us a stand-alone translator, both ways, between any of the supported formats. Could you just use a top level schematic as a guide for connecting code modules to simulate with no netlist generated from gschem? Sure, but do you want to? Only as a stopgap measure. I can't dive into the translator project, but I've hinted to Mr. Wender about it -- and it sounds very much aligned with their goals the more I think about it. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: analog/code co-simulation and schematics and netlists for silicon
al davis wrote: I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. I've got a phone call to Reid Wenders of Triad scheduled this PM. Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 John Griessen Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. To be able to create a circuit layout and perform harmonic ballance simulation combined with microcontroller code simulation... Oh, and while I daydream, an integrated tool for doing FEM analysis the pcb design to improve RF circuit layout. I am only new to gEDA so forgive me if I some of this is already possible.. From the little I have seen getting the circuit information out of gEDA must be fairly straight forward - it is getting the other tools to play nicely that would be tricky. This is something that I certainly would like to look into. Geoff Australia On Wed, Feb 24, 2010 at 4:49 AM, John Griessen j...@ecosensory.com wrote: al davis wrote: I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. I've got a phone call to Reid Wenders of Triad scheduled this PM. Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 John Griessen Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote: I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. To be able to create a circuit layout and perform harmonic ballance simulation combined with microcontroller code simulation... Oh, and while I daydream, an integrated tool for doing FEM analysis the pcb design to improve RF circuit layout. I am only new to gEDA so forgive me if I some of this is already possible.. From the little I have seen getting the circuit information out of gEDA must be fairly straight forward - it is getting the other tools to play nicely that would be tricky. This is something that I certainly would like to look into. Geoff Australia Doing marine renewables, I vote for integrated computational fluid dynamics + electrical simulation - although at this point in time, I'm looking at the gEDA tools and thinking building those (including gwave!!) is a piece of cake compared to building OpenFOAM. (OpenFOAM is a GPL'd FEA package with a NIH build-system). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
On Tuesday 23 February 2010, John Griessen wrote: Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. It really doesn't work .. sorry. Gnucap (the development version) will take netlists in Spice, Spectre, or Verilog formats. The gnetlist backend only supports a small subset of what could be done. For years, I have accepted the fact that the generated netlist has some flaws and requires manual editing. I can deal with it, unhappily, but most beginners can't, and most people who might think of migrating won't even if they could. We really need a more general translator, that isn't based on the gschem format or any other tool specific format. I have a start, but need help. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 If I can get some help with Gnucap, this will happen. Actually, I do have some help now, but need more, especially people to work on user oriented issues, what most people think of as the easy part. Gnucap was designed for mixed signal from the beginning, long before there was such a thing as Verilog-AMS. What is lacking is a fully working model compiler. There is work in progress with Icarus to make this happen. The main missing piece now is a back-end for Icarus that matches the gnucap interface. That is really the only critical missing piece. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
Peter Clifton wrote: On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote: I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. My phone conversation today with Mr Wender of Triad was about verilog-ams and the possibilities it offers mostly. One way to get a model of a microprocessor running with gnucap doing analog and gates might be to use CMOS logic gate primitives that compute quickly and the usual models for analog elements and just let it all run on a server farm for a few hours. I'm not sure of the speed gnucap will simulate flip flops and nand gates at when you put enough together to make a working micro -- that's a lot of gates to sim. I'll try to spend some more time on testing the gnetlist verilog-ams back end with gnucap further, but first comes business survival. It could be months. Triad doesn't have a dedicate CAD guy to work on this kind of integration. Their sister company Viasic, (Bill Cox and gnetman), does. They're going to keep in touch about gnetlist/gnucap integration -- no promises. One thing to think about is what the NRE charges for a small chip containing a 8051 micro and custom analog peripherals would be with an open tool chain for simulation. As things are today Triad charges $200K NRE for a chip done by their staff using Cadence licenses. A DIY chip designed with gschem and verilog-ams and simulated with gnucap would have NRE charges of only $30K per chip. If a group of designs made with open tools was ready at the same time they could syndicate a wafer run and get the NRE charges down to $5K per batch per customer, (the shared slice of the cost of a single metal mask). al davis wrote: The gnetlist backend only supports a small subset of what could be done. . . We really need a more general translator, that isn't based on the gschem format or any other tool specific format. I have a start, but need help. . . What is lacking is a fully working model compiler. There is work in progress with Icarus to make this happen. The main missing piece now is a back-end for Icarus that matches the gnucap interface. Al, are you saying that Icarus verilog would run along side of gnucap once that interface is ready? Will Steve's model compiler aim at doing user definable verilog-ams models? Would you still use gschem/gnetlist to schematically connect verilog modules? That depends on having a good translator first, right? Could you just use a top level schematic as a guide for connecting code modules to simulate with no netlist generated from gschem? John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
On Tuesday 23 February 2010, John Griessen wrote: Al, are you saying that Icarus verilog would run along side of gnucap once that interface is ready? Icarus has two key parts .. A compiler, and a virtual machine. In its normal use, the compiler generates code for the virtual machine, then you run the virtual machine on that code. The icarus compiler has a provision for alternate target back ends. There are several available. -- fpga, pal, vvp, . The plan is to make a new target back end that will generate a gnucap model plugin. For gnucap, the Icarus virtual machine will not be used. In gnucap (development version, not 0.35) .. device models are not built-in, but can be loaded and unloaded at run time. This makes it possible to have a lot more models without the bloat of all of the models you are not using. (I'm not talking about the spice .model statement here .. This is the real code that implements the model.) These model plugins are standard shared-object files native to whatever system you are running on. As it stands now, some are hand coded in C++, some use the old gnucap-modelgen, and some are spice models. Gnucap can use unmodified Spice C model code as plugins, with a simple interface wrapper. The work in progress is along two lines .. One is an Icarus backend to generate a plugin. The other is to use another model compiler ADMS to generate gnucap code. You can use ADMS now to generate NGspice code, which gnucap can use as a plugin, but this is not as efficient as it should be, because of the ancient Spice interface overhead and mapping overhead. As another approach, it is possible to run the Icarus virtual machine along side of gnucap, but efficiency is not good, and you need to hack some code. It has been done. Would you still use gschem/gnetlist to schematically connect verilog modules? That depends on having a good translator first, right? Anything that generates a netlist. Gnucap uses language plugins to read whatever input format. Maybe someone could make a language plugin to read and write the gschem format directly. Once this is done, it will also give us a stand-alone translator, both ways, between any of the supported formats. Could you just use a top level schematic as a guide for connecting code modules to simulate with no netlist generated from gschem? Sure, but do you want to? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
