Re: gEDA-user: vhdl and gschem
On Friday 16 February 2007 17:48, Stuart Brorson wrote: That being said, I must say that using a schematic capture package to do Verilog or VHDL seems to defeat the purpose. Actually, VHDL and Verilog are very good as netlist languages. For automated generation, either is adequate, and VHDL has some nice features that really helpful. For manual entry, the Verilog format is clear, compact, and regular. .. far superior to the Spice format. The next real release of gnucap will use Verilog as the default netlist language, and read Spice files through a plug-in. When making a netlister, all symbols should be appropriately translated to the target format. No exceptions. This is easy to do with VHDL and Verilog, but extremely difficult to do in a useful way for Spice. Another comment on gnucap I am thinking of having the simulator core include no models at all, not even a resistor. All models are attached as plugins. There will be a development snapshot in a day or so that makes serious use of plugins, and probably 3 new plugin libraries, mostly models that you can attach as you want, without the baggage of the ones you don't. By use of a simple wrapper, it will take Spice model code (.c files) as plugins with no changes required. It will take 3f, 3e, or ngspice format. That means it is now easier to install a Spice model in gnucap than it is to install it in Spice. Commands are plugins too. The only command that is really required to be built-in is attach, but even attach can be replaced by a user, at run time. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
On Feb 18, 2007, at 4:15 PM, al davis wrote: Another comment on gnucap I am thinking of having the simulator core include no models at all, not even a resistor. All models are attached as plugins. There will be a development snapshot in a day or so that makes serious use of plugins, and probably 3 new plugin libraries, mostly models that you can attach as you want, without the baggage of the ones you don't. By use of a simple wrapper, it will take Spice model code (.c files) as plugins with no changes required. It will take 3f, 3e, or ngspice format. That means it is now easier to install a Spice model in gnucap than it is to install it in Spice. Commands are plugins too. The only command that is really required to be built-in is attach, but even attach can be replaced by a user, at run time. I really like this idea as an architectural concept. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
al davis wrote: For manual entry, the Verilog format is clear, compact, and regular. .. far superior to the Spice format. The next real release of gnucap will use Verilog as the default netlist language, and read Spice files through a plug-in. Thanks for that decision Al, I've always liked the now orientedness of verilog/iverilog. It's a natural for text definition of a network -- of wires or busses. It's a language about what's-connected-now. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
From: John Griessen [EMAIL PROTECTED] Subject: Re: gEDA-user: vhdl and gschem Date: Sun, 18 Feb 2007 18:54:46 -0600 Message-ID: [EMAIL PROTECTED] al davis wrote: For manual entry, the Verilog format is clear, compact, and regular. .. far superior to the Spice format. The next real release of gnucap will use Verilog as the default netlist language, and read Spice files through a plug-in. Thanks for that decision Al, I've always liked the now orientedness of verilog/iverilog. It's a natural for text definition of a network -- of wires or busses. It's a language about what's-connected-now. I on the other hand would have preferred VHDL. There is many reasons for it. Cheers, Magnus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
On Sunday 18 February 2007 20:01, Magnus Danielson wrote: I on the other hand would have preferred VHDL. There is many reasons for it. In the long run it really doesn't matter. The simulator core handles lists of blocks with connections. Anything more than that is handled through plug-ins. The native language will be the structural subset of Verilog-AMS. More advanced features will be too slow if they are run interpreted. Most models (modules, entities, etc.) will be compiled, and used as plug-ins. Once the system is in place, it will be trivial to also support the Spectre format, Mast and other ways to describe circuits. There can be several plugins for Spice, to mimic different versions of it. It will finally become possible to have 100% compatibility with a particular Spice, and still grow beyond it, which is something no Spice can do. For now, plug-ins are .so files. To use one you say something like attach transient.so to say you will use the transient analysis plug-in, or attach resistor.so or whatever. Soon, this will be extended so you can say attach my-transient.cc or attach my-oscillator.vams or whatever, and it will build the .so and attach it. The choice of Verilog is simply what to support first. Here's why: Consider this: == module filter (in, out); ground gnd; resistor #(.r(1K)) R1 (in, out); capacitor #(.c(1n)) C1(out, gnd); endmodule The ports could have been expressed as (.p(in), .n(out)) but I chose to use the shorter notation. == or this: == entity filter is port (terminal in, out : electrical); end entity filter; architecture v1 of filter is terminal in, out: electrical; begin r1: entity resistor generic map (r = 1K) port map (p = in, n = out); c1: entity capacitor generic map (c = 1n) port map (p = out, n = gnd); end architecture v1; == To put it in perspective, this is the old way: == .subckt filter in out r1 in out 1k c1 out 0 1n .ends == The problems with the third format cannot be seen with such a simple example, but lots of people know what they are. Of the first two If you are accustomed to the third, and need to make a change, which is the easier transition? You are teaching circuits to undergraduates, half of whom failed the introduction to programming class. Which would you rather teach? At this level, the only real difference I see between the formats is the baggage port map, generic map, entity on every line, the entity block. ... In either case, the items in the list all have the same 4 parts. (instance_name, parameters, type, connections) Both languages are consistent. So it is a simple change from one to the other. Regardless of which is first, the other will show up soon. That third format presents some real problems I would like to put behind. At least they can now be pushed out to a plug-in. As a reminder of one of the problems with the third format .. consider this: X1 a b c d e f g h i j k Clearly, this has connections a, b, c. It refers to a model named d. Parameters are being passed e=f, g is a binary that is set to true, h=i, j=k. It's not clear to you? Hmmm. For those who need it ... .. The first fomat is Verilog. The second is VHDL. The third (old way) is Spice. There are other factors, but most important is that when you look at what is important, there is no difference. The plug-ins will let you parse it any way you want, and pass on the data. I expect that the only parsing plugins that will be a mess are the multitude of Spice format plugins. The others will be trivial. I can even see being able to read gschem files directly, using a plug-in. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
On Sunday 18 February 2007 16:44, Dave McGuire wrote: I really like this idea as an architectural concept. The architectural concept is there now. The December 2006 snapshot supports plug-ins. The one that is coming extends it. What I am not sure about is how much to link in to the main executable by default. Modules that can be plug-ins can be static linked if you want. It is simply a matter of specifying in the Makefile whether to link it or not. If you choose not to link it you can attach it later. If you do link it, and want to override it, just attach the new one and it will override the built-in one. I can see it now Gnucap 2007.02.18 RCS 26.15 The Gnu Circuit Analysis Package Never trust any version less than 1.0 Copyright 1982-2002, Albert Davis Gnucap comes with ABSOLUTELY NO WARRANTY This is free software, and you are welcome to redistribute it under certain conditions according to the GNU General Public License. See the file COPYING for details. clear ^ ? bad command gnucap build build ^ ? bad command gnucap get get ^ ? bad command gnucap list list ^ ? bad command gnucap ac ac ^ ? bad command gnucap tran tran ^ ? bad command gnucap exit exit ^ ? bad command gnucap quit quit ^ ? bad command gnucap help help ^ ? bad command gnucap (actual run of gnucap, my working version, with everything moved to plugins and no plugins installed). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
On Feb 16, 2007, at 6:49 PM, Ostheller, Joel A. wrote: Yes. Pick yourself up a copy of Peter Ashenden's The Designer's guide to VHDL. Additionally you may want to get a copy of the IEEE VHDL LRM. There is no reason to use schematic capture packages to do Verilog or VHDL. Some have claimed that using it to import your VHDL/Verilog such that it auto-generates a system block diagram is an acceptable use... I usually will give them that, but not much more. I totally agree. Skip schemtics entirely when doing FPGA designs. My FPGA testbenches include bus-functional models of everything the FPGA talks to. To support this, I use either vendor-supplied models (memories and such) or I write them myself. (PLX wanted me to give them my Verilog models of their 9030 and 9656 chips, so my company said, you'll need to pay us... and that ended that discussion quite quickly.) The microcontroller or whatever talks to the FPGA, which does something interesting, and interesting outputs result, which are compared to an expected result. The automatic block diagram is interesting, if only to put on a slide for a design review, but I'd argue that you should have your block diagram draw BEFORE you start coding ... -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
Hello there, I successfully created a vhdl file from http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadder.sch http://tux.u-strasbg.fr/~chit/cours_vhdl/output.net. However, since my schematic includes some and2 and or2, the output.net includes the respective components, but if I compile the vhdl file directly, it will fails since it lacks the and2 and or2 entities. Unfortunately for such a simple schematic. Is there a method to tell gnetlist to include appropriate package name for the and2 and or2 components so that one shouldn't right his own and2 and or2 vhdl file but uses the standard vhdl code? Chitlesh -- http://clunixchit.blogspot.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
I applaude your efforts to understand the VHDL back-end. It's too bad it doesn't seem to work easily; I do think that it should just work. That being said, I must say that using a schematic capture package to do Verilog or VHDL seems to defeat the purpose. That is, these text-based logic languages have pushed schematic-based logic design aside because they are much easier to deal with once a design has grown beyond a certain (not very large) size. Maybe somebody will contradict me -- which is fine -- but in my experience nobody actually draws logic symbols anymore, except for a few random gates now and then. Rather, real logic designs are captured as Verilog or VHDL in text format, and compiled directly to programming files which are loaded into FPGAs, CPLDs, and the like. At the schematic level one just draws lots of boxes with lots of pins corresponding to the FPGA or CPLD. Therefore, using gschem to draw a logic circuit and then netlist to VHDL isn't a commonly used design flow nowadays. Instead, people just create a textual design using a text editor. Maybe that's why the VHDL netlister hasn't received much attention recently. Stuart On Fri, 16 Feb 2007, Chitlesh GOORAH wrote: Hello there, I successfully created a vhdl file from http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadder.sch http://tux.u-strasbg.fr/~chit/cours_vhdl/output.net. However, since my schematic includes some and2 and or2, the output.net includes the respective components, but if I compile the vhdl file directly, it will fails since it lacks the and2 and or2 entities. Unfortunately for such a simple schematic. Is there a method to tell gnetlist to include appropriate package name for the and2 and or2 components so that one shouldn't right his own and2 and or2 vhdl file but uses the standard vhdl code? Chitlesh -- http://clunixchit.blogspot.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
From: Chitlesh GOORAH [EMAIL PROTECTED] Subject: Re: gEDA-user: vhdl and gschem Date: Fri, 16 Feb 2007 23:36:22 +0100 Message-ID: [EMAIL PROTECTED] Hello there, I successfully created a vhdl file from http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadder.sch http://tux.u-strasbg.fr/~chit/cours_vhdl/output.net. However, since my schematic includes some and2 and or2, the output.net includes the respective components, but if I compile the vhdl file directly, it will fails since it lacks the and2 and or2 entities. Unfortunately for such a simple schematic. Is there a method to tell gnetlist to include appropriate package name for the and2 and or2 components so that one shouldn't right his own and2 and or2 vhdl file but uses the standard vhdl code? No, and it shouldn't really. You should rather include those desciptions from other schematics, given models from libraries or type them yourself. gschem/gnetlist allows you to interconnect things. You could even use it in a hierarchial fashion if you wish. Just include the VHDL files into your compilation and you will be fine. Cheers, Magnus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: vhdl and gschem
Yes. Pick yourself up a copy of Peter Ashenden's The Designer's guide to VHDL. Additionally you may want to get a copy of the IEEE VHDL LRM. There is no reason to use schematic capture packages to do Verilog or VHDL. Some have claimed that using it to import your VHDL/Verilog such that it auto-generates a system block diagram is an acceptable use... I usually will give them that, but not much more. -Original Message- From: [EMAIL PROTECTED] [mailto:geda-user- [EMAIL PROTECTED] On Behalf Of Stuart Brorson Sent: Friday, February 16, 2007 2:48 PM To: gEDA user mailing list Subject: Re: gEDA-user: vhdl and gschem I applaude your efforts to understand the VHDL back-end. It's too bad it doesn't seem to work easily; I do think that it should just work. That being said, I must say that using a schematic capture package to do Verilog or VHDL seems to defeat the purpose. That is, these text-based logic languages have pushed schematic-based logic design aside because they are much easier to deal with once a design has grown beyond a certain (not very large) size. Maybe somebody will contradict me -- which is fine -- but in my experience nobody actually draws logic symbols anymore, except for a few random gates now and then. Rather, real logic designs are captured as Verilog or VHDL in text format, and compiled directly to programming files which are loaded into FPGAs, CPLDs, and the like. At the schematic level one just draws lots of boxes with lots of pins corresponding to the FPGA or CPLD. Therefore, using gschem to draw a logic circuit and then netlist to VHDL isn't a commonly used design flow nowadays. Instead, people just create a textual design using a text editor. Maybe that's why the VHDL netlister hasn't received much attention recently. Stuart On Fri, 16 Feb 2007, Chitlesh GOORAH wrote: Hello there, I successfully created a vhdl file from http://tux.u-strasbg.fr/~chit/cours_vhdl/halfadder.sch http://tux.u-strasbg.fr/~chit/cours_vhdl/output.net. However, since my schematic includes some and2 and or2, the output.net includes the respective components, but if I compile the vhdl file directly, it will fails since it lacks the and2 and or2 entities. Unfortunately for such a simple schematic. Is there a method to tell gnetlist to include appropriate package name for the and2 and or2 components so that one shouldn't right his own and2 and or2 vhdl file but uses the standard vhdl code? Chitlesh -- http://clunixchit.blogspot.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: vhdl and gschem
Hello thre, I'm trying to make a VHDL file from a mere simple half adder schematic: http://tux.u-strasbg.fr/~chit/half_adder/adder.sch with: gnetlist -g vhdl adder.sch -o output.vhdl http://tux.u-strasbg.fr/~chit/half_adder/output.vhdl However, I don't know how to create an entity with gschem. Can any one point how to make a simple one for my adder.sch ? In my actual output.vhdl, the entity is not found. My second question about the vhdl and geda is how can I simulate that output.vhdl file with ghdl when the generated output.vhdl comes with: component 7408 or 7086 in my case. how can I make ghdl read those particular components as their respective entities and architecture (or, and)? Should I create those entities by myself or is it there something automated ? thanks Chitlesh -- http://clunixchit.blogspot.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
El dom, 11-02-2007 a las 20:03 +0100, Chitlesh GOORAH escribió: [snip] I'm trying to make a VHDL file from a mere simple half adder schematic: http://tux.u-strasbg.fr/~chit/half_adder/adder.sch with: gnetlist -g vhdl adder.sch -o output.vhdl http://tux.u-strasbg.fr/~chit/half_adder/output.vhdl However, I don't know how to create an entity with gschem. Can any one point how to make a simple one for my adder.sch ? In my actual output.vhdl, the entity is not found. Add a top-level attribute called module-name. Example: module-name=your-desired-instance-name --- adder.sch.orig 2007-02-11 17:34:55.0 +0100 +++ adder.sch 2007-02-11 20:16:55.0 +0100 @@ -43,3 +43,5 @@ netname=C } B 46500 46300 2800 2700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 46500 46100 9 10 1 0 0 0 1 +module-name=your-desired-instance-name - My second question about the vhdl and geda is how can I simulate that output.vhdl file with ghdl when the generated output.vhdl comes with: component 7408 or 7086 in my case. how can I make ghdl read those particular components as their respective entities and architecture (or, and)? Should I create those entities by myself or is it there something automated ? It seems to me that you should have the vhdl models for those components in order to use them with vhdl. Anyway I haven't used ghdl at all... Regards, Carlos ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
From: Chitlesh GOORAH [EMAIL PROTECTED] Subject: gEDA-user: vhdl and gschem Date: Sun, 11 Feb 2007 20:03:47 +0100 Message-ID: [EMAIL PROTECTED] Hi! Hello thre, I'm trying to make a VHDL file from a mere simple half adder schematic: http://tux.u-strasbg.fr/~chit/half_adder/adder.sch with: gnetlist -g vhdl adder.sch -o output.vhdl http://tux.u-strasbg.fr/~chit/half_adder/output.vhdl However, I don't know how to create an entity with gschem. Can any one point how to make a simple one for my adder.sch ? In my actual output.vhdl, the entity is not found. See comment from Carlos Nieves Ónega. However, in general what you do want to do is to design in input and output You want to go into the VHDL symbol table and use ipad-1, opad-1 and iopad-1 which will map over to VHDL in, out and inout declarations of Std_Logic type. Assign the value of these to the name you want in the entity port declaration. There still isn't vectorization which would be nice in the long run. My second question about the vhdl and geda is how can I simulate that output.vhdl file with ghdl when the generated output.vhdl comes with: component 7408 or 7086 in my case. how can I make ghdl read those particular components as their respective entities and architecture (or, and)? Should I create those entities by myself or is it there something automated ? There is even those pre-rolled for your delight. Check out: http://www.freemodelfoundry.com/ Cheers, Magnus - guilty to the original VHDL backend which fortunatly have been maintained by others ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vhdl and gschem
On 2/11/07, Magnus Danielson wrote: However, in general what you do want to do is to design in input and output You want to go into the VHDL symbol table and use ipad-1, opad-1 and iopad-1 which will map over to VHDL in, out and inout declarations of Std_Logic type. Assign the value of these to the name you want in the entity port declaration. There still isn't vectorization which would be nice in the long run. Hello, thanks for the tip, However, with gschem when I try to add a component from the sym/vhdl/ folder, gschem does not find such folder. But if I rename that sym/vhdl folder to sym/spice, gschem sees the *.sym files. Is it a bug ? 20061020 inside. There is even those pre-rolled for your delight. Check out: http://www.freemodelfoundry.com/ Thanks again for the tip :) thanks, Chitlesh -- http://clunixchit.blogspot.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
