[gem5-dev] changeset in gem5: ext: clang fix for flexible array members
changeset 0edd36ea6130 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0edd36ea6130 description: ext: clang fix for flexible array members Changes how flexible array members are defined so clang does not error out during compilation. diffstat: ext/dnet/os.h | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diffs (13 lines): diff -r 763f76d5dea7 -r 0edd36ea6130 ext/dnet/os.h --- a/ext/dnet/os.h Sun Aug 10 05:39:40 2014 -0400 +++ b/ext/dnet/os.h Wed Aug 13 06:57:19 2014 -0400 @@ -98,7 +98,8 @@ /* Support for flexible arrays. */ #undef __flexarr -#if defined(__GNUC__) ((__GNUC__ 2) || (__GNUC__ == 2 __GNUC_MINOR__ = 97)) +#if !defined(__clang__) defined(__GNUC__) \ +((__GNUC__ 2) || (__GNUC__ == 2 __GNUC_MINOR__ = 97)) /* GCC 2.97 supports C99 flexible array members. */ # define __flexarr [] #else ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: sim: remove kernel mapping check for baremeta...
changeset 3ea92bc6393b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3ea92bc6393b
description:
sim: remove kernel mapping check for baremetal workloads
Baremetal workloads are specified using the kernel parameter, but
don't always have the correct address mappings. This patch adds a
boolean flag to the system and bypasses the kernel addr mapping checks
when running in baremetal mode.
diffstat:
src/sim/System.py | 2 ++
src/sim/system.cc | 22 ++
2 files changed, 16 insertions(+), 8 deletions(-)
diffs (49 lines):
diff -r c7187ee80868 -r 3ea92bc6393b src/sim/System.py
--- a/src/sim/System.py Wed Aug 13 06:57:31 2014 -0400
+++ b/src/sim/System.py Wed Aug 13 06:57:35 2014 -0400
@@ -84,6 +84,8 @@
init_param = Param.UInt64(0, numerical value to pass into simulator)
boot_osflags = Param.String(a, boot flags to pass to the kernel)
kernel = Param.String(, file that contains the kernel code)
+kernel_addr_check = Param.Bool(True,
+whether to address check on kernel (disable for baremetal))
readfile = Param.String(, file to read startup script from)
symbolfile = Param.String(, file to get the symbols from)
load_addr_mask = Param.UInt64(0xff,
diff -r c7187ee80868 -r 3ea92bc6393b src/sim/system.cc
--- a/src/sim/system.cc Wed Aug 13 06:57:31 2014 -0400
+++ b/src/sim/system.cc Wed Aug 13 06:57:35 2014 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2014 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -274,13 +274,19 @@
* Load the kernel code into memory
*/
if (params()-kernel != ) {
-// Validate kernel mapping before loading binary
-if (!(isMemAddr((kernelStart loadAddrMask) + loadAddrOffset)
- isMemAddr((kernelEnd loadAddrMask) + loadAddrOffset))) {
-fatal(Kernel is mapped to invalid location (not memory).
- kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n,
kernelStart,
- kernelEnd, (kernelStart loadAddrMask) + loadAddrOffset,
- (kernelEnd loadAddrMask) + loadAddrOffset);
+if (params()-kernel_addr_check) {
+// Validate kernel mapping before loading binary
+if (!(isMemAddr((kernelStart loadAddrMask) +
+loadAddrOffset)
+ isMemAddr((kernelEnd loadAddrMask) +
+loadAddrOffset))) {
+fatal(Kernel is mapped to invalid location (not memory).
+ kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n,
+ kernelStart,
+ kernelEnd, (kernelStart loadAddrMask) +
+ loadAddrOffset,
+ (kernelEnd loadAddrMask) + loadAddrOffset);
+}
}
// Load program sections into memory
kernel-loadSections(physProxy, loadAddrMask, loadAddrOffset);
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[gem5-dev] changeset in gem5: util: Fix state leakage in the SortIncludes s...
changeset 84b4d6af0ecc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=84b4d6af0ecc description: util: Fix state leakage in the SortIncludes style verifier There are cases where the state of a SortIncludes object gets messed up and leaks between invocations/files. This typically happens when a file ends with an include block (dump_block() gets called at the end of __call__). In this case, the state of the class is not reset between files. This bug manifests itself as ghost includes that leak between files when applying the style hooks. This changeset adds a reset at the beginning of the __call__ method which ensures that the class is always in a clean state when processing a new file. diffstat: util/sort_includes.py | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diffs (20 lines): diff -r 68da5ef4bb6f -r 84b4d6af0ecc util/sort_includes.py --- a/util/sort_includes.py Wed Aug 13 06:57:24 2014 -0400 +++ b/util/sort_includes.py Wed Aug 13 06:57:25 2014 -0400 @@ -72,7 +72,7 @@ includes_re = tuple((a, b, re.compile(c)) for a,b,c in includes_re) def __init__(self): -self.reset() +pass def reset(self): # clear all stored headers @@ -103,6 +103,7 @@ prev = l def __call__(self, lines, filename, language): +self.reset() leading_blank = False blanks = 0 block = False ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: scons: Build the branch predictor for all CPUs
changeset c7187ee80868 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7187ee80868
description:
scons: Build the branch predictor for all CPUs
The branch predictor is normally only built when a CPU that uses a
branch predictor is built. The list of CPUs is currently incomplete as
the simple CPUs support branch predictors (for warming, branch stats,
etc). In practice, all CPU models now use branch predictors, so this
changeset removes the CPU model check and replaces it with a check for
the NULL ISA.
diffstat:
src/cpu/pred/SConscript | 23 ---
1 files changed, 12 insertions(+), 11 deletions(-)
diffs (31 lines):
diff -r 5b67e1bdf6ad -r c7187ee80868 src/cpu/pred/SConscript
--- a/src/cpu/pred/SConscript Wed Aug 13 06:57:30 2014 -0400
+++ b/src/cpu/pred/SConscript Wed Aug 13 06:57:31 2014 -0400
@@ -30,15 +30,16 @@
Import('*')
-if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS'] \
-or 'Minor' in env['CPU_MODELS']:
-SimObject('BranchPredictor.py')
+if env['TARGET_ISA'] == 'null':
+Return()
-Source('bpred_unit.cc')
-Source('2bit_local.cc')
-Source('btb.cc')
-Source('ras.cc')
-Source('tournament.cc')
-Source ('bi_mode.cc')
-DebugFlag('FreeList')
-DebugFlag('Branch')
+SimObject('BranchPredictor.py')
+
+Source('bpred_unit.cc')
+Source('2bit_local.cc')
+Source('btb.cc')
+Source('ras.cc')
+Source('tournament.cc')
+Source ('bi_mode.cc')
+DebugFlag('FreeList')
+DebugFlag('Branch')
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[gem5-dev] changeset in gem5: base: Remove unused M5_PRAGMA_NORETURN
changeset ef888b246cd0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ef888b246cd0 description: base: Remove unused M5_PRAGMA_NORETURN The M5_PRAGMA_NORETURN macro was only used in for __exit_message. Since the macro only holds a stub definition and all functions with noreturn semantics use the M5_ATTR_NORETURN, this macros is completely redundant. diffstat: src/base/compiler.hh | 1 - src/base/misc.hh | 1 - 2 files changed, 0 insertions(+), 2 deletions(-) diffs (22 lines): diff -r 4cbfdcdb2144 -r ef888b246cd0 src/base/compiler.hh --- a/src/base/compiler.hh Wed Aug 13 06:57:26 2014 -0400 +++ b/src/base/compiler.hh Wed Aug 13 06:57:27 2014 -0400 @@ -47,7 +47,6 @@ #if defined(__GNUC__) #define M5_ATTR_NORETURN __attribute__((noreturn)) -#define M5_PRAGMA_NORETURN(x) #define M5_DUMMY_RETURN #define M5_VAR_USED __attribute__((unused)) diff -r 4cbfdcdb2144 -r ef888b246cd0 src/base/misc.hh --- a/src/base/misc.hh Wed Aug 13 06:57:26 2014 -0400 +++ b/src/base/misc.hh Wed Aug 13 06:57:27 2014 -0400 @@ -71,7 +71,6 @@ VARARGS_ALLARGS); } -M5_PRAGMA_NORETURN(__exit_message) #define exit_message(prefix, code, ...)\ __exit_message(prefix, code, __FUNCTION__, __FILE__, __LINE__, \ __VA_ARGS__) ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: power: Remove unused private members to fix c...
changeset faa9dfc465ef in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=faa9dfc465ef
description:
power: Remove unused private members to fix compile-time warning
Certain versions of clang complain about unused private members if
they are not used. This changeset removes such members from the
POWER-specific ProcessInfo struct to silence the warning.
diffstat:
src/arch/power/stacktrace.cc | 1 -
src/arch/power/stacktrace.hh | 9 -
2 files changed, 0 insertions(+), 10 deletions(-)
diffs (30 lines):
diff -r 362875aec1ba -r faa9dfc465ef src/arch/power/stacktrace.cc
--- a/src/arch/power/stacktrace.cc Wed Aug 13 06:57:28 2014 -0400
+++ b/src/arch/power/stacktrace.cc Wed Aug 13 06:57:29 2014 -0400
@@ -38,7 +38,6 @@
namespace PowerISA {
ProcessInfo::ProcessInfo(ThreadContext *_tc)
-: tc(_tc)
{
panic(ProcessInfo constructor not implemented.\n);
}
diff -r 362875aec1ba -r faa9dfc465ef src/arch/power/stacktrace.hh
--- a/src/arch/power/stacktrace.hh Wed Aug 13 06:57:28 2014 -0400
+++ b/src/arch/power/stacktrace.hh Wed Aug 13 06:57:29 2014 -0400
@@ -47,15 +47,6 @@
class ProcessInfo
{
- private:
-ThreadContext *tc;
-
-int thread_info_size;
-int task_struct_size;
-int task_off;
-int pid_off;
-int name_off;
-
public:
ProcessInfo(ThreadContext *_tc);
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[gem5-dev] changeset in gem5: scons: Silence clang 3.4 warnings on Ubuntu 1...
changeset 362875aec1ba in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=362875aec1ba description: scons: Silence clang 3.4 warnings on Ubuntu 12.04 This changeset fixes three types of warnings that occur in clang 3.4 on Ubuntu 12.04: * Certain versions of libstdc++ (primarily 4.8) use struct and class interchangeably. This triggers a warning in clang. * Swig has a tendency to generate code with the register class which was deprecated in C++11. This triggers a deprecation warning in clang. * Swig sometimes generates Python wrapper code which returns uninitialized values. It's unclear if this is actually a problem (the cases might be limited to failure paths). We'll silence these warnings for now since there is little we can do about the generated code. diffstat: SConstruct | 7 ++- src/SConscript | 8 2 files changed, 14 insertions(+), 1 deletions(-) diffs (35 lines): diff -r ef888b246cd0 -r 362875aec1ba SConstruct --- a/SConstructWed Aug 13 06:57:27 2014 -0400 +++ b/SConstructWed Aug 13 06:57:28 2014 -0400 @@ -638,7 +638,12 @@ # is relying on this main.Append(CCFLAGS=['-Wno-tautological-compare', '-Wno-parentheses', - '-Wno-self-assign']) + '-Wno-self-assign', + # Some versions of libstdc++ (4.8?) seem to + # use struct hash and class hash + # interchangeably. + '-Wno-mismatched-tags', + ]) main.Append(TCMALLOC_CCFLAGS=['-fno-builtin']) diff -r ef888b246cd0 -r 362875aec1ba src/SConscript --- a/src/SConscriptWed Aug 13 06:57:27 2014 -0400 +++ b/src/SConscriptWed Aug 13 06:57:28 2014 -0400 @@ -940,6 +940,14 @@ # with non-virtual destructors new_env.Append(CXXFLAGS=['-Wdelete-non-virtual-dtor']) +swig_env.Append(CCFLAGS=[ +# Some versions of SWIG can return uninitialized values +'-Wno-sometimes-uninitialized', +# Register storage is requested in a lot of places in +# SWIG-generated code. +'-Wno-deprecated-register', +]) + werror_env = new_env.Clone() werror_env.Append(CCFLAGS='-Werror') ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: cpu: Don't forward declare RefCountingPtr
changeset 4cbfdcdb2144 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4cbfdcdb2144 description: cpu: Don't forward declare RefCountingPtr RefCountingPtr is sometimes forward declared to avoid having to include refcnt.hh. This does not work since we typically return instances of RefCountingPtr rather than references to instances. The only reason this currently works is that we include refcnt.hh in cprintf.hh, which leaks the header to most other source files. This changeset replaces such forward declarations with an include of refcnt.hh. diffstat: src/base/types.hh | 3 ++- src/cpu/static_inst_fwd.hh | 3 ++- src/sim/fault_fwd.hh | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diffs (48 lines): diff -r 84b4d6af0ecc -r 4cbfdcdb2144 src/base/types.hh --- a/src/base/types.hh Wed Aug 13 06:57:25 2014 -0400 +++ b/src/base/types.hh Wed Aug 13 06:57:26 2014 -0400 @@ -42,6 +42,8 @@ #include cassert #include ostream +#include base/refcnt.hh + /** uint64_t constant */ #define ULL(N) ((uint64_t)N##ULL) /** int64_t constant */ @@ -177,7 +179,6 @@ const PortID InvalidPortID = (PortID)-1; class FaultBase; -template class T class RefCountingPtr; typedef RefCountingPtrFaultBase Fault; #endif // __BASE_TYPES_HH__ diff -r 84b4d6af0ecc -r 4cbfdcdb2144 src/cpu/static_inst_fwd.hh --- a/src/cpu/static_inst_fwd.hhWed Aug 13 06:57:25 2014 -0400 +++ b/src/cpu/static_inst_fwd.hhWed Aug 13 06:57:26 2014 -0400 @@ -31,8 +31,9 @@ #ifndef __CPU_STATIC_INST_FWD_HH__ #define __CPU_STATIC_INST_FWD_HH__ +#include base/refcnt.hh + class StaticInst; -template class T class RefCountingPtr; typedef RefCountingPtrStaticInst StaticInstPtr; #endif // __CPU_STATIC_INST_FWD_HH__ diff -r 84b4d6af0ecc -r 4cbfdcdb2144 src/sim/fault_fwd.hh --- a/src/sim/fault_fwd.hh Wed Aug 13 06:57:25 2014 -0400 +++ b/src/sim/fault_fwd.hh Wed Aug 13 06:57:26 2014 -0400 @@ -31,8 +31,9 @@ #ifndef __SIM_FAULT_FWD_HH__ #define __SIM_FAULT_FWD_HH__ +#include base/refcnt.hh + class FaultBase; -template class T class RefCountingPtr; typedef RefCountingPtrFaultBase Fault; FaultBase * const NoFault = 0; ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: mips: Remove unused private members to fix co...
changeset 5b67e1bdf6ad in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5b67e1bdf6ad
description:
mips: Remove unused private members to fix compile-time warning
Certain versions of clang complain about unused private members if
they are not used. This changeset removes such members from the
MIPS-specific classes to silence the warning.
diffstat:
src/arch/mips/interrupts.hh | 6 --
src/arch/mips/linux/system.hh | 39 ---
src/arch/mips/stacktrace.hh | 2 --
src/arch/mips/tlb.cc | 15 ---
src/dev/mips/malta_io.hh | 3 ---
5 files changed, 0 insertions(+), 65 deletions(-)
diffs (122 lines):
diff -r faa9dfc465ef -r 5b67e1bdf6ad src/arch/mips/interrupts.hh
--- a/src/arch/mips/interrupts.hh Wed Aug 13 06:57:29 2014 -0400
+++ b/src/arch/mips/interrupts.hh Wed Aug 13 06:57:30 2014 -0400
@@ -59,7 +59,6 @@
Interrupts(Params * p) : SimObject(p)
{
-newInfoSet = false;
}
void
@@ -127,11 +126,6 @@
{
fatal(Unserialization of Interrupts Unimplemented for MIPS);
}
-
- private:
-bool newInfoSet;
-int newIpl;
-int newSummary;
};
}
diff -r faa9dfc465ef -r 5b67e1bdf6ad src/arch/mips/linux/system.hh
--- a/src/arch/mips/linux/system.hh Wed Aug 13 06:57:29 2014 -0400
+++ b/src/arch/mips/linux/system.hh Wed Aug 13 06:57:30 2014 -0400
@@ -87,45 +87,6 @@
Addr InitrdSize() const { return Param() + 0x108; }
static const int CommandLineSize = 256;
- private:
-#ifndef NDEBUG
-/** Event to halt the simulator if the kernel calls panic() */
-BreakPCEvent *kernelPanicEvent;
-
-/** Event to halt the simulator if the kernel calls die_if_kernel */
-BreakPCEvent *kernelDieEvent;
-#endif
-
-/**
- * Event to skip determine_cpu_caches() because we don't support
- * the IPRs that the code can access to figure out cache sizes
- */
-SkipFuncEvent *skipCacheProbeEvent;
-
-/** PC based event to skip the ide_delay_50ms() call */
-SkipFuncEvent *skipIdeDelay50msEvent;
-
-/**
- * PC based event to skip the dprink() call and emulate its
- * functionality
- */
-Linux::DebugPrintkEvent *debugPrintkEvent;
-
-/**
- * Skip calculate_delay_loop() rather than waiting for this to be
- * calculated
- */
-SkipDelayLoopEvent *skipDelayLoopEvent;
-
-/**
- * Event to print information about thread switches if the trace flag
- * Thread is set
- */
-PrintThreadInfo *printThreadEvent;
-
-/** Grab the PCBB of the idle process when it starts */
-IdleStartEvent *idleStartEvent;
-
public:
typedef LinuxMipsSystemParams Params;
LinuxMipsSystem(Params *p);
diff -r faa9dfc465ef -r 5b67e1bdf6ad src/arch/mips/stacktrace.hh
--- a/src/arch/mips/stacktrace.hh Wed Aug 13 06:57:29 2014 -0400
+++ b/src/arch/mips/stacktrace.hh Wed Aug 13 06:57:30 2014 -0400
@@ -45,8 +45,6 @@
private:
ThreadContext *tc;
-int thread_info_size;
-int task_struct_size;
int task_off;
int pid_off;
int name_off;
diff -r faa9dfc465ef -r 5b67e1bdf6ad src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Wed Aug 13 06:57:29 2014 -0400
+++ b/src/arch/mips/tlb.cc Wed Aug 13 06:57:30 2014 -0400
@@ -59,21 +59,6 @@
// MIPS TLB
//
-static inline mode_type
-getOperatingMode(MiscReg Stat)
-{
-if ((Stat 0x1006) != 0 || (Stat 0x18) ==0) {
-return mode_kernel;
-} else if ((Stat 0x18) == 0x8) {
-return mode_supervisor;
-} else if ((Stat 0x18) == 0x10) {
-return mode_user;
-} else {
-return mode_number;
-}
-}
-
-
TLB::TLB(const Params *p)
: BaseTLB(p), size(p-size), nlu(0)
{
diff -r faa9dfc465ef -r 5b67e1bdf6ad src/dev/mips/malta_io.hh
--- a/src/dev/mips/malta_io.hh Wed Aug 13 06:57:29 2014 -0400
+++ b/src/dev/mips/malta_io.hh Wed Aug 13 06:57:30 2014 -0400
@@ -51,9 +51,6 @@
*/
class MaltaIO : public BasicPioDevice
{
- private:
-struct tm tm;
-
protected:
class RTC : public MC146818
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[gem5-dev] RFC: New include file ordering
Hi Everyone, I have a change I'd like to make to the gem5 coding style that I believe will improve our code quality. Currently, the gem5 coding style mandates that includes are grouped four different blocks (alphabetical ordering within a block): * Python headers * C system/stdlib includes * C++ stdlib includes * M5 includes I propose that we change this to include an object's main header file first (e.g., foo.cc would include foo.hh first). This ensures that the header file does not depend on include file ordering and avoids surprises down the road when someone tries to reuse code. This kind of include file ordering is pretty common and is used at, for example, Google [1]. Comments/ideas? If everyone is happy with this change, I'll go ahead and post a patch for the style checker and update the Wiki. In order to keep the code base reasonably stable, I propose that we only apply this to new code and gradually migrate the old code. Thanks, Andreas [1] http://google-styleguide.googlecode.com/svn/trunk/cppguide.xml#Names_and_Order_of_Includes -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2324: sim: bump checkpoint version for multiple event queues
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2324/ --- Review request for Default. Repository: gem5 Description --- Changeset 10284:a50742e945c5 --- sim: bump checkpoint version for multiple event queues This patch adds a fix for older checkpoints before support for multiple event queues were added in changeset 2cce74fe359e. The change in checkpoint version should really hav ebeen part of the aforementioned changeset. Diffs - src/sim/serialize.hh 79fde1c67ed8 util/cpt_upgrader.py 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2324/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2327: arm: support 16kb vm granules
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2327/ --- Review request for Default. Repository: gem5 Description --- Changeset 10287:47e83de5d36f --- arm: support 16kb vm granules Diffs - src/arch/arm/miscregs.hh 79fde1c67ed8 src/arch/arm/table_walker.hh 79fde1c67ed8 src/arch/arm/table_walker.cc 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2327/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2325: mem: Fix address interleaving bug in DRAM controller
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2325/ --- Review request for Default. Repository: gem5 Description --- Changeset 10285:218ddd25c88c --- mem: Fix address interleaving bug in DRAM controller This patch fixes a bug in the DRAM controller address decoding. In cases where the DRAM burst size was smaller than the interleaving stripe size (e.g. LPDDR3 x32 with a 64 byte cache line) one address bit effectively got used as a channel bit when it should have been a low-order column bit. This patch adds a notion of columns per stripe, and more clearly deals with the low-order column bits and high-order column bits. The patch also relaxes the granularity check such that it is possible to use interleaving granularities other than the cache line size. The patch also adds a missing M5_CLASS_VAR_USED to the tCK member as it is only used in the debug build for now. Diffs - src/mem/dram_ctrl.hh 79fde1c67ed8 src/mem/dram_ctrl.cc 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2325/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2331: style: Add support for a style ignore list and ignore ext/
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2331/ --- Review request for Default. Repository: gem5 Description --- Changeset 10291:522c461fc667 --- style: Add support for a style ignore list and ignore ext/ There are some directories within the repository where we don't want to enforce our coding style. Specifically, we don't want the style hooks to warn whenever we update external code in the ext/ directory. Diffs - util/style.py 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2331/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2330: style: Fixup strange semantics in hg m5style
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2330/ --- Review request for Default. Repository: gem5 Description --- Changeset 10290:cb87bf7eac9b --- style: Fixup strange semantics in hg m5style The 'hg m5style' command had some rather strange semantics. When called without arguments, it applied the style checker to all added files and modified regions of modified files. However, when providing a list of files, it used that list as an ignore list instead of specifically checking those files. This patch makes the m5style command behave more like other Mercurial commands where the arguments are used to specify which files to work on instead of which files to ignore. Diffs - util/style.py 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2330/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2333: arm: Mark v7 cbz instructions as direct branches
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2333/ --- Review request for Default. Repository: gem5 Description --- Changeset 10301:b644c6b4915f --- arm: Mark v7 cbz instructions as direct branches v7 cbz/cbnz instructions were improperly marked as indirect branches. Diffs - src/arch/arm/isa/insts/branch.isa 79fde1c67ed8 src/arch/arm/isa/templates/branch.isa 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2333/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2336: arm: ISA X31 destination register fix
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2336/ --- Review request for Default. Repository: gem5 Description --- Changeset 10303:f679224ff121 --- arm: ISA X31 destination register fix This patch substituted the zero register for X31 used as a destination register. This prevents false dependencies based on X31. Diffs - src/arch/arm/intregs.hh 79fde1c67ed8 src/arch/arm/isa/formats/aarch64.isa 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2336/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 2332: cpu: Fix cached block load behavior in o3 cpu
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2332/ --- Review request for Default. Repository: gem5 Description --- Changeset 10300:bddebc19285f --- cpu: Fix cached block load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior. Diffs - src/cpu/o3/iew.hh 79fde1c67ed8 src/cpu/o3/iew_impl.hh 79fde1c67ed8 src/cpu/o3/inst_queue.hh 79fde1c67ed8 src/cpu/o3/inst_queue_impl.hh 79fde1c67ed8 src/cpu/o3/lsq.hh 79fde1c67ed8 src/cpu/o3/lsq_impl.hh 79fde1c67ed8 src/cpu/o3/lsq_unit.hh 79fde1c67ed8 src/cpu/o3/lsq_unit_impl.hh 79fde1c67ed8 src/cpu/o3/mem_dep_unit.hh 79fde1c67ed8 src/cpu/o3/mem_dep_unit_impl.hh 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2332/diff/ Testing --- Thanks, Andreas Hansson ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
