[gem5-dev] changeset in gem5: dev: Add response sanity checks in PioPort
changeset 6099331da328 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6099331da328 description: dev: Add response sanity checks in PioPort Add an assert in the PioPort that checks if a response packet from a device has the right flags set before passing it to them rest of the memory system. diffstat: src/dev/io_device.cc | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diffs (14 lines): diff -r 3499de20ab3a -r 6099331da328 src/dev/io_device.cc --- a/src/dev/io_device.cc Mon Dec 08 04:49:51 2014 -0500 +++ b/src/dev/io_device.cc Mon Dec 08 04:49:52 2014 -0500 @@ -57,7 +57,9 @@ // @todo: We need to pay for this and not just zero it out pkt-firstWordDelay = pkt-lastWordDelay = 0; -return pkt-isRead() ? device-read(pkt) : device-write(pkt); +const Tick delay(pkt-isRead() ? device-read(pkt) : device-write(pkt)); +assert(pkt-isResponse() || pkt-isError()); +return delay; } AddrRangeList ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: arm: Fix decoding of PMXEVTYPER_EL0 and PMCCF...
changeset 4e09ae443c96 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4e09ae443c96
description:
arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0
The aarch64 system register decoder is currently not decoding
PMXEVTYPER_EL0 and PMCCFILTR_EL0 correctly. This changeset updates the
decoder so that they are decoded using the values in table C5-6 in ARM
DDI 0478A.c.
diffstat:
src/arch/arm/miscregs.cc | 7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diffs (24 lines):
diff -r 6099331da328 -r 4e09ae443c96 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Mon Dec 08 04:49:52 2014 -0500
+++ b/src/arch/arm/miscregs.cc Mon Dec 08 04:49:53 2014 -0500
@@ -3177,7 +3177,7 @@
case 0:
return MISCREG_PMCCNTR_EL0;
case 1:
-return MISCREG_PMCCFILTR_EL0;
+return MISCREG_PMXEVTYPER_EL0;
case 2:
return MISCREG_PMXEVCNTR_EL0;
}
@@ -3434,6 +3434,11 @@
return MISCREG_PMEVTYPER5_EL0;
}
break;
+ case 15:
+switch (op2) {
+ case 7:
+return MISCREG_PMCCFILTR_EL0;
+}
}
break;
case 4:
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: dev: Correctly transform packets into responses
changeset 3499de20ab3a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3499de20ab3a
description:
dev: Correctly transform packets into responses
The VirtIO devices didn't correctly set the response flags in memory
packets. This changeset adds the required Packet::makeResponse()
calls.
diffstat:
src/dev/virtio/base.cc | 2 ++
src/dev/virtio/pci.cc | 4
2 files changed, 6 insertions(+), 0 deletions(-)
diffs (40 lines):
diff -r 6efb37480d87 -r 3499de20ab3a src/dev/virtio/base.cc
--- a/src/dev/virtio/base.ccFri Dec 05 22:37:03 2014 -0800
+++ b/src/dev/virtio/base.ccMon Dec 08 04:49:51 2014 -0500
@@ -426,6 +426,7 @@
if (cfgOffset + size configSize)
panic(Config read out of bounds.\n);
+pkt-makeResponse();
pkt-setData(const_castuint8_t *(cfg) + cfgOffset);
}
@@ -437,6 +438,7 @@
if (cfgOffset + size configSize)
panic(Config write out of bounds.\n);
+pkt-makeResponse();
pkt-writeData((uint8_t *)cfg + cfgOffset);
}
diff -r 6efb37480d87 -r 3499de20ab3a src/dev/virtio/pci.cc
--- a/src/dev/virtio/pci.cc Fri Dec 05 22:37:03 2014 -0800
+++ b/src/dev/virtio/pci.cc Mon Dec 08 04:49:51 2014 -0500
@@ -75,6 +75,8 @@
return 0;
}
+pkt-makeResponse();
+
switch(offset) {
case OFF_DEVICE_FEATURES:
DPRINTF(VIOPci,DEVICE_FEATURES request\n);
@@ -151,6 +153,8 @@
return 0;
}
+pkt-makeResponse();
+
switch(offset) {
case OFF_DEVICE_FEATURES:
warn(Guest tried to write device features.);
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2510: Let other objects set up memory like regions in a KVM VM.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2510/#review5652 --- Ship it! I'm still not happy with the setupMemSlot()/disableMemSlot() names, but I can't think of any better names atm, so let's go with them for now. - Andreas Sandberg On Nov. 23, 2014, 2:51 p.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2510/ --- (Updated Nov. 23, 2014, 2:51 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10551:7767dc21318d --- Let other objects set up memory like regions in a KVM VM. Diffs - src/cpu/kvm/vm.hh f9fb64a72259a2514080151b5250a04c575d443a src/cpu/kvm/vm.cc f9fb64a72259a2514080151b5250a04c575d443a Diff: http://reviews.gem5.org/r/2510/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2510: Let other objects set up memory like regions in a KVM VM.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2510/#review5653 --- src/cpu/kvm/vm.cc http://reviews.gem5.org/r/2510/#comment5046 I think this causes problems with some of the officially supported compilers. It's just a hunch, but please check. - Andreas Hansson On Nov. 23, 2014, 2:51 p.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2510/ --- (Updated Nov. 23, 2014, 2:51 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10551:7767dc21318d --- Let other objects set up memory like regions in a KVM VM. Diffs - src/cpu/kvm/vm.hh f9fb64a72259a2514080151b5250a04c575d443a src/cpu/kvm/vm.cc f9fb64a72259a2514080151b5250a04c575d443a Diff: http://reviews.gem5.org/r/2510/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] x86 SE kvm functionality (AMD vs Intel)
I have verified that x86 kvm works fine on AMD platforms, but fails on Intel platforms. Any hints about how to narrow down the cause (other than diving into gdb, which I will do). I am not an expert in KVM or how gem5 hooks up to libkvm. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)
I'm not an expert either, but I did have problems running KVM in SE mode on an Intel CPU. I didn't look into it that much, but I think things failed in the kernel somewhere. What might be happening is that the different vendors hardware virtualization mechanisms are more or less picky about various things. Something might be set up incorrectly, and one implementation gets more upset about it than the other. I believe there are tools which will help you determine whether your VM state is legal. Perhaps Andreas can tell you more about those? Gabe On Mon, Dec 8, 2014 at 4:29 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote: I have verified that x86 kvm works fine on AMD platforms, but fails on Intel platforms. Any hints about how to narrow down the cause (other than diving into gdb, which I will do). I am not an expert in KVM or how gem5 hooks up to libkvm. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2510: Let other objects set up memory like regions in a KVM VM.
On Dec. 8, 2014, 2:36 p.m., Andreas Hansson wrote: src/cpu/kvm/vm.cc, line 374 http://reviews.gem5.org/r/2510/diff/2/?file=42734#file42734line374 I think this causes problems with some of the officially supported compilers. It's just a hunch, but please check. Ugh. Yes, I think you're right. That's standard C but not C++. - Gabe --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2510/#review5653 --- On Nov. 23, 2014, 2:51 p.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2510/ --- (Updated Nov. 23, 2014, 2:51 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10551:7767dc21318d --- Let other objects set up memory like regions in a KVM VM. Diffs - src/cpu/kvm/vm.hh f9fb64a72259a2514080151b5250a04c575d443a src/cpu/kvm/vm.cc f9fb64a72259a2514080151b5250a04c575d443a Diff: http://reviews.gem5.org/r/2510/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)
Hi Mike, trace-cmd is a very handy tool to get an overview of what the kvm kernel module is doing before going into gdb. In extreme cases ftrace can be useful as well. What is the error that you are seeing? Is it still failing to enter virtualized mode? If that is the case and the hardware reason is 0x8021, that seems to be an unrecoverable exception (drivers/hv/hyperv_vmbus.h in linux kernel source code). When running in SE mode, we are trying to bring the machine state to full 64bit mode without going through legacy modes. It might be that Intel machines have a different way of going to 64bit mode than AMD machines (different CR4, different way of enabling 64bit mode page tables etc.). I remember dealing with these issue for AMD platforms by going through System Programming manual and making sure gem5 gets all the bits right as there is not much the KVM kernel model will tell about the cause of failure. Best regards, Alex From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Gabe Black via gem5-dev [gem5-dev@gem5.org] Sent: Monday, December 08, 2014 7:08 PM To: gem5 Developer List Subject: Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel) I'm not an expert either, but I did have problems running KVM in SE mode on an Intel CPU. I didn't look into it that much, but I think things failed in the kernel somewhere. What might be happening is that the different vendors hardware virtualization mechanisms are more or less picky about various things. Something might be set up incorrectly, and one implementation gets more upset about it than the other. I believe there are tools which will help you determine whether your VM state is legal. Perhaps Andreas can tell you more about those? Gabe On Mon, Dec 8, 2014 at 4:29 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote: I have verified that x86 kvm works fine on AMD platforms, but fails on Intel platforms. Any hints about how to narrow down the cause (other than diving into gdb, which I will do). I am not an expert in KVM or how gem5 hooks up to libkvm. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)
I'm pretty sure entering 64 bit mode is the same between AMD and Intel CPUs. I vaguely remember there being some subtle page table difference though, and gem5 is building the page tables in SE mode instead of the kernel. Gabe On Mon, Dec 8, 2014 at 7:44 PM, Dutu, Alexandru via gem5-dev gem5-dev@gem5.org wrote: Hi Mike, trace-cmd is a very handy tool to get an overview of what the kvm kernel module is doing before going into gdb. In extreme cases ftrace can be useful as well. What is the error that you are seeing? Is it still failing to enter virtualized mode? If that is the case and the hardware reason is 0x8021, that seems to be an unrecoverable exception (drivers/hv/hyperv_vmbus.h in linux kernel source code). When running in SE mode, we are trying to bring the machine state to full 64bit mode without going through legacy modes. It might be that Intel machines have a different way of going to 64bit mode than AMD machines (different CR4, different way of enabling 64bit mode page tables etc.). I remember dealing with these issue for AMD platforms by going through System Programming manual and making sure gem5 gets all the bits right as there is not much the KVM kernel model will tell about the cause of failure. Best regards, Alex From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Gabe Black via gem5-dev [gem5-dev@gem5.org] Sent: Monday, December 08, 2014 7:08 PM To: gem5 Developer List Subject: Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel) I'm not an expert either, but I did have problems running KVM in SE mode on an Intel CPU. I didn't look into it that much, but I think things failed in the kernel somewhere. What might be happening is that the different vendors hardware virtualization mechanisms are more or less picky about various things. Something might be set up incorrectly, and one implementation gets more upset about it than the other. I believe there are tools which will help you determine whether your VM state is legal. Perhaps Andreas can tell you more about those? Gabe On Mon, Dec 8, 2014 at 4:29 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote: I have verified that x86 kvm works fine on AMD platforms, but fails on Intel platforms. Any hints about how to narrow down the cause (other than diving into gdb, which I will do). I am not an expert in KVM or how gem5 hooks up to libkvm. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel)
I also faced problem in getting KVM CPU to run in FS mode. I figured that the following changeset causes problems: author Alexandru Dutu alexandru.d...@amd.com Sun Nov 23 18:01:08 2014 -0800 (2 weeks ago) changeset 10554 fe2e2f06a7c8 I saw the hardware reason 0x8021, but did not try to figure what was going on wrong. -- Nilay On Mon, 8 Dec 2014, Gabe Black via gem5-dev wrote: I'm pretty sure entering 64 bit mode is the same between AMD and Intel CPUs. I vaguely remember there being some subtle page table difference though, and gem5 is building the page tables in SE mode instead of the kernel. Gabe On Mon, Dec 8, 2014 at 7:44 PM, Dutu, Alexandru via gem5-dev gem5-dev@gem5.org wrote: Hi Mike, trace-cmd is a very handy tool to get an overview of what the kvm kernel module is doing before going into gdb. In extreme cases ftrace can be useful as well. What is the error that you are seeing? Is it still failing to enter virtualized mode? If that is the case and the hardware reason is 0x8021, that seems to be an unrecoverable exception (drivers/hv/hyperv_vmbus.h in linux kernel source code). When running in SE mode, we are trying to bring the machine state to full 64bit mode without going through legacy modes. It might be that Intel machines have a different way of going to 64bit mode than AMD machines (different CR4, different way of enabling 64bit mode page tables etc.). I remember dealing with these issue for AMD platforms by going through System Programming manual and making sure gem5 gets all the bits right as there is not much the KVM kernel model will tell about the cause of failure. Best regards, Alex From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Gabe Black via gem5-dev [gem5-dev@gem5.org] Sent: Monday, December 08, 2014 7:08 PM To: gem5 Developer List Subject: Re: [gem5-dev] x86 SE kvm functionality (AMD vs Intel) I'm not an expert either, but I did have problems running KVM in SE mode on an Intel CPU. I didn't look into it that much, but I think things failed in the kernel somewhere. What might be happening is that the different vendors hardware virtualization mechanisms are more or less picky about various things. Something might be set up incorrectly, and one implementation gets more upset about it than the other. I believe there are tools which will help you determine whether your VM state is legal. Perhaps Andreas can tell you more about those? Gabe On Mon, Dec 8, 2014 at 4:29 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote: I have verified that x86 kvm works fine on AMD platforms, but fails on Intel platforms. Any hints about how to narrow down the cause (other than diving into gdb, which I will do). I am not an expert in KVM or how gem5 hooks up to libkvm. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
