Re: [gem5-dev] Review Request 3699: syscall_emul: [PATCH 18/22] refactor and add functionality for dup, dup2, and pipe

2016-11-10 Thread Tony Gutierrez 

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Ship it!


Ship It!

- Tony Gutierrez


On Nov. 7, 2016, 2:09 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3699/
> ---
> 
> (Updated Nov. 7, 2016, 2:09 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:01d31dbe35c4
> ---
> syscall_emul: [PATCH 18/22] refactor and add functionality for dup, dup2, and 
> pipe
> 
> 
> Diffs
> -
> 
>   src/arch/arm/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/power/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/x86/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3699/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3689: tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

2016-11-10 Thread Brad Beckmann 

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Ship it!


Ship It!

- Brad Beckmann


On Oct. 27, 2016, 7:50 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3689/
> ---
> 
> (Updated Oct. 27, 2016, 7:50 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11706:e542abbd3730
> ---
> tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)
> 
> This patch avoids compiling ALPHA six times as part of running
> 'util/regress', and instead relis on NULL with different protocols to
> run the rubytest. All we need is the memory system, so there is really
> no need to compile the ISA over and over again.
> 
> The one downside is the removal of running 'hello' for the variuos
> ALPHA and protocol combinations, but if this is a concern we should
> rather beef up the synthetic tests for the variuos protocols.
> 
> 
> Diffs
> -
> 
>   tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simout PRE-CREATION 
>   tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt 
> PRE-CREATION 
>   util/regress c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr 
> c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout 
> c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
>  c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini 
> c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr 
> c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout 
> c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt 
> c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/config.ini
>  PRE-CREATION 
>   
>

Re: [gem5-dev] Review Request 3700: syscall_emul: [PATCH 19/22] adds basic signaling mechanism to SE mode

2016-11-10 Thread Tony Gutierrez 

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Ship it!



src/sim/se_signal.hh (line 5)


Not the correct license.


- Tony Gutierrez


On Nov. 7, 2016, 2:09 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3700/
> ---
> 
> (Updated Nov. 7, 2016, 2:09 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11708:6a7a3eee7cd0
> ---
> syscall_emul: [PATCH 19/22] adds basic signaling mechanism to SE mode
> 
> 
> Diffs
> -
> 
>   src/sim/SConscript 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/se_signal.hh PRE-CREATION 
>   src/sim/se_signal.cc PRE-CREATION 
>   src/sim/system.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3700/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3697: style: [PATCH 16/22] correct some style issues

2016-11-10 Thread Tony Gutierrez 

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Ship it!


Ship It!

- Tony Gutierrez


On Nov. 7, 2016, 2:05 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3697/
> ---
> 
> (Updated Nov. 7, 2016, 2:05 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11705:baf743047c38
> ---
> style: [PATCH 16/22] correct some style issues
> 
> 
> Diffs
> -
> 
>   src/sim/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/base/loader/object_file.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/base/loader/elf_object.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/x86/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/x86/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3697/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3702: syscall_emul: [PATCH 21/22] rewrite code related to system call exits

2016-11-10 Thread Tony Gutierrez 

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src/sim/futex_map.hh (line 5)


This is not the license we should be using. See the gpu-compute code for 
our license.



src/sim/futex_map.hh (line 66)


This comment needs more detail.



src/sim/futex_map.hh (line 91)


Newline after the return type.



src/sim/se_signal.cc (line 2)


Should this not be 2014, 2016?


- Tony Gutierrez


On Nov. 7, 2016, 2:20 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3702/
> ---
> 
> (Updated Nov. 7, 2016, 2:20 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11710:0f51ecfa24aa
> ---
> syscall_emul: [PATCH 21/22] rewrite code related to system call exits
> 
> The changeset refactors exit, exit_group, and futex related exit
> functionality.
> 
> 
> Diffs
> -
> 
>   src/sim/futex_map.hh PRE-CREATION 
>   src/sim/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/se_signal.hh PRE-CREATION 
>   src/sim/se_signal.cc PRE-CREATION 
>   src/sim/syscall_emul.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/system.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3702/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3703: syscall_emul: [PATCH 22/22] ignore system calls that are unimplemented.

2016-11-10 Thread Tony Gutierrez 

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Ship it!


This looks ok to me, but could you add more to the description explaining why 
you're targetting only these sys calls in particular?

- Tony Gutierrez


On Nov. 7, 2016, 2:57 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3703/
> ---
> 
> (Updated Nov. 7, 2016, 2:57 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11711:6fd39a6e6db8
> ---
> syscall_emul: [PATCH 22/22] ignore system calls that are unimplemented.
> 
> 
> Diffs
> -
> 
>   src/arch/x86/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3703/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3698: syscall_emul: [PATCH 17/22] refactor and add functionality to open syscall family

2016-11-10 Thread Tony Gutierrez 

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Ship it!


Ship It!

- Tony Gutierrez


On Nov. 7, 2016, 2:07 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3698/
> ---
> 
> (Updated Nov. 7, 2016, 2:07 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11706:693893fbee1f
> ---
> syscall_emul: [PATCH 17/22] refactor and add functionality to open syscall 
> family
> 
> 
> Diffs
> -
> 
>   src/arch/x86/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/kern/linux/linux.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/kern/linux/linux.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3698/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3681: syscall_emul: [patch 14/22] adds identifier system calls

2016-11-10 Thread Tony Gutierrez 

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Ship it!



src/sim/syscall_emul.cc (line 736)


Use nullptr throughout.


Minor issue, otherwise it LGTM, assuming you address Jason's comments as well.

- Tony Gutierrez


On Nov. 7, 2016, 1:56 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3681/
> ---
> 
> (Updated Nov. 7, 2016, 1:56 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11703:9a6631ad6f41
> ---
> syscall_emul: [patch 14/22] adds identifier system calls
> 
> This changeset add fields to the process object and adds the following
> three system calls: setpgid, gettid, getpid.
> 
> 
> Diffs
> -
> 
>   src/sim/syscall_emul.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/system.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/x86/linux/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/Process.py 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/process.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/syscall_emul.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3681/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3690: x86, ext: fix buf overflow in fp80 ops; pad fp80_t in fputils

2016-11-10 Thread Tony Gutierrez 


> On Nov. 9, 2016, 1:45 p.m., Bjoern A. Zeeb wrote:
> > Tested on X86 booting FreeBSD reverting my own simple workaround.
> > I can say that gem5 does no longer panic when booting FreeBSD FS with this 
> > patch applied.
> > I cannot say whether it works correctly currently.
> > However it improves the situation :)

Great. I'd like to ship this soon, but I'd like to see what Andreas S. thinks 
of it first.

Andreas, do you have any comments/concerns with this fix?


- Tony


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On Nov. 1, 2016, 12:36 p.m., Tony Gutierrez wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3690/
> ---
> 
> (Updated Nov. 1, 2016, 12:36 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11888:ed39f10e4ff3
> ---
> x86, ext: fix buf overflow in fp80 ops; pad fp80_t in fputils
> 
> the compiler seems to align the fp80_t data struct, so here we add
> explicit padding to avoid confusion.
> 
> storeFloat80() will try to write all 16B of the fp80_t to the bits[] array
> of the calling instruction. this happens because storeFloat80() points its
> local fp80_t* to the memory the caller allocated for bits[], which is only
> 10B, thus we get an overflow that is flagged by clang's asan. here we
> get the fp80 value first, the memcpy() the bits[] of fp80_t to the mem
> allocated by the caller.
> 
> 
> Diffs
> -
> 
>   ext/fputils/fpbits.h c38fcdaa5fe508dbb18cc084e758ad0ce8e2e2f4 
>   ext/fputils/include/fputils/fptypes.h 
> c38fcdaa5fe508dbb18cc084e758ad0ce8e2e2f4 
>   src/arch/x86/isa/microops/fpop.isa c38fcdaa5fe508dbb18cc084e758ad0ce8e2e2f4 
>   src/arch/x86/utility.cc c38fcdaa5fe508dbb18cc084e758ad0ce8e2e2f4 
> 
> Diff: http://reviews.gem5.org/r/3690/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Tony Gutierrez
> 
>

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Re: [gem5-dev] Review Request 3695: misc: final cleanup of the TLM modules

2016-11-10 Thread Christian Menard 

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---

(Updated Nov. 10, 2016, 5:07 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11709:a64e6cc90f4e
---
misc: final cleanup of the TLM modules

Introduce new transactor modules. These modules rerpresent the gem5 TLM ports
in the SystemC world. Common code in the examples is moved to a common dir.


Diffs (updated)
-

  util/tlm/examples/common/cli_parser.hh PRE-CREATION 
  util/tlm/examples/common/cli_parser.cc PRE-CREATION 
  util/tlm/examples/common/report_handler.hh PRE-CREATION 
  util/tlm/examples/common/report_handler.cc PRE-CREATION 
  util/tlm/examples/master_port/SConstruct PRE-CREATION 
  util/tlm/examples/master_port/main.cc PRE-CREATION 
  util/tlm/examples/master_port/tlm.py PRE-CREATION 
  util/tlm/examples/master_port/traffic_generator.cc PRE-CREATION 
  util/tlm/examples/slave_port/SConstruct PRE-CREATION 
  util/tlm/examples/slave_port/main.cc PRE-CREATION 
  util/tlm/examples/slave_port/sc_target.cc PRE-CREATION 
  util/tlm/examples/slave_port/tlm.py PRE-CREATION 
  util/tlm/gem5_master_transactor.hh PRE-CREATION 
  util/tlm/gem5_master_transactor.cc PRE-CREATION 
  util/tlm/gem5_slave_transactor.hh PRE-CREATION 
  util/tlm/gem5_slave_transactor.cc PRE-CREATION 
  util/tlm/sc_master_port.hh PRE-CREATION 
  util/tlm/sc_master_port.cc PRE-CREATION 
  util/tlm/sc_slave_port.hh PRE-CREATION 
  util/tlm/sc_slave_port.cc PRE-CREATION 
  util/tlm/sim_control.hh PRE-CREATION 
  util/tlm/sim_control.cc PRE-CREATION 

Diff: http://reviews.gem5.org/r/3695/diff/


Testing
---

Examples compile and run.


Thanks,

Christian Menard

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Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

2016-11-10 Thread Tony Gutierrez 


> On Nov. 2, 2016, 12:38 p.m., Alec Roelke wrote:
> > This doesn't work with the O3 CPU model; I wrote a simple program that 
> > performs a lr.w followed by sc.w that works with the atomic-simple, 
> > timing-simple, and minor CPU models, but with the O3 model I get this error:
> > 
> > gem5.debug: build/RISCV/mem/cache/cache.cc\:162: void 
> > Cache::satisfyRequest(PacketPtr, CacheBlk*, bool, bool): Assertion 
> > `pkt->getOffset(blkSize) + pkt->getSize() <= blkSize' failed.
> > 
> > I can't seem to track down what's causing the error.  Can anybody help me?
> 
> Ali Saidi wrote:
> the issue is that the ld + st crosses a cache line which the O3 doesn't 
> support doing this type of op when it spans two cache lines because you have 
> to track both of them.
> 
> Alec Roelke wrote:
> I see.  It sounds like fixing it would require making changes to the O3 
> model itself, is that right?  Are there changes I can make within the scope 
> of this patch, or others in the series, that will make it work?  This may 
> actually explain other errors I'm getting with the O3 model with some of the 
> other tests I'm making.

I'm not sure if you would need to necessarily modify the O3 model much, if at 
all. Certainly you will need to have your memory instructions detect an access 
that will cross a cache line boundary, split it into two, and track both. Then 
you will only consider it completed when both reqs get responses. This is done 
in a few other places in the model.


- Tony


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On Nov. 2, 2016, 12:34 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3693/
> ---
> 
> (Updated Nov. 2, 2016, 12:34 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11694:1c3068cb5c86
> ---
> riscv: [Patch 7/5] Corrected LRSC semantics
> 
> RISC-V makes use of load-reserved and store-conditional instructions to
> enable creation of lock-free concurrent data manipulation as well as
> ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO
> instructions (the latter of which do not follow LR/SC semantics). This
> patch is a correction to patch 4, which added these instructions to the
> implementation of RISC-V. It modifies locked_mem.hh and the
> implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5
> flags and return the proper values.
> 
> An important difference between gem5's LLSC semantics and RISC-V's LR/SC
> ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to
> indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V
> uses 0 to indicate success and nonzero to indicate failure where the
> value would indicate the error, but currently only 1 is reserved as a
> failure code by the ISA reference.
> 
> This is the seventh patch in the series which originally consisted of five
> patches that added the RISC-V ISA to gem5. The original five patches added
> all of the instructions and added support for more detailed CPU models and
> the sixth patch corrected the implementations of Linux constants and
> structs. There will be an eighth patch that adds some regression tests
> for the instructions.
> 
> Signed-off by: Alec Roelke
> 
> 
> Diffs
> -
> 
>   src/arch/riscv/isa/decoder.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/mem.isa PRE-CREATION 
>   src/arch/riscv/locked_mem.hh PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3693/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

2016-11-10 Thread Tony Gutierrez 

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src/arch/riscv/locked_mem.hh (line 72)


remove commented out code



src/arch/riscv/locked_mem.hh (line 84)


If you move this above the dprintf, you can use it to print the address in 
the dprint.



src/arch/riscv/locked_mem.hh (line 93)


Should you be using cacheBlockMask here, as opposed to 0xF?


- Tony Gutierrez


On Nov. 2, 2016, 12:34 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3693/
> ---
> 
> (Updated Nov. 2, 2016, 12:34 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11694:1c3068cb5c86
> ---
> riscv: [Patch 7/5] Corrected LRSC semantics
> 
> RISC-V makes use of load-reserved and store-conditional instructions to
> enable creation of lock-free concurrent data manipulation as well as
> ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO
> instructions (the latter of which do not follow LR/SC semantics). This
> patch is a correction to patch 4, which added these instructions to the
> implementation of RISC-V. It modifies locked_mem.hh and the
> implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5
> flags and return the proper values.
> 
> An important difference between gem5's LLSC semantics and RISC-V's LR/SC
> ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to
> indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V
> uses 0 to indicate success and nonzero to indicate failure where the
> value would indicate the error, but currently only 1 is reserved as a
> failure code by the ISA reference.
> 
> This is the seventh patch in the series which originally consisted of five
> patches that added the RISC-V ISA to gem5. The original five patches added
> all of the instructions and added support for more detailed CPU models and
> the sixth patch corrected the implementations of Linux constants and
> structs. There will be an eighth patch that adds some regression tests
> for the instructions.
> 
> Signed-off by: Alec Roelke
> 
> 
> Diffs
> -
> 
>   src/arch/riscv/isa/decoder.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/mem.isa PRE-CREATION 
>   src/arch/riscv/locked_mem.hh PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3693/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-11-10 Thread Cron Daemon 
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