[gem5-dev] test framework and parallelism
Hi folks. I'm integrating the systemc tests into the testing framework, and I wonder what level of parallelism there is in the framework itself, what level of parallelism the tests themselves should utilize, and how that's plumbed down. For instance, I have a verify.py script I wrote to run and verify the systemc tests. It has a lot of nice features that would be difficult to plumb through the framework so I want to keep it as its own independent entity. It has the ability to run scons to build the tests and the tests themselves in parallel which is very useful. I could make it automatically detect how much parallelism it might want to use, but that would likely be somewhat hard to do in a system dependent way, ie to make it work on macs without having one to test on, and we don't necessarily want it to run as wide as possible regardless of what else might be going on in the system, test wise or otherwise. Is there a way to tell the test framework to do things in parallel? Is there a way to allocate some amount of parallelism at the scheduler level (if a level like that exists) for a particular test, and how is that communicated to the test? Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Finding tests in the new test framework
Hi folks. I'm getting started integrating the systemc tests into the new testing framework, and I'd like to change how it finds tests to run. Currently it scans for files which starts or ends with test or tests, ends in .py, and which separate test or tests with a - or _ from the rest of the name. It looks for those files recursively relative to the current directory. That has a few problems. First, once a bug is fixed I have a CL out for, the tests/main.py (may need a better name? Not obvious that's what you're supposed to run) can be run from outside the tests directory. That means that you may end up scanning files that you don't intend, or not scanning files that you do intend. I don't think the directories you look in should be based on your current directory, although I don't immediately have another proposal. I haven't put a ton of thought into it yet, suggestions welcome. Second, it's easy to have false positives. For instance, when I attempted to run main.py from the root of the checkout, so ./tests/main.py, it picked up a file in ext/googletest, specifically ext/googletest/googlemock/scripts/generator/cpp/gmock_class_test.py. It then dutifully executed that code to look for tests. In this case that file doesn't seem to do anything, but I don't think it's unrealistic that there could be accidental undesirable side effects from something which has an unfortunate name. I think if we're going to be executing things to see what tests they define (which is reasonable IMO), we should make sure their author intended for them to be used that way. In addition to accidental name collisions, there are definitely security implications from this scheme. Let's say I've got a gem5 tree checked out which no one else can modify, but for whatever reason they can still create files within. If they make a file with the right name, they can run arbitrary code as the owner of the tree just by tucking something away deep in the file hierarchy of gem5 somewhere when they go to run the tests. This is particularly dangerous when the paths that are scanned aren't well constrained/constant. Finally, the framework seems to be written with the intention that all tests would go in the tests directory. This has been gem5's tendency historically, but I think, outside of a few potential exceptions, it's a bad practice. Tests should be alongside the things that are being tested. For instance, if I get the systemc tests hooked into the new framework, that should be in src/systemc/tests (where the tests live), not in tests/systemc or similar. That makes it important to be able to be able to run the framework on directories outside the tests directory, minimally in the src directory, and have it do the "right thing", not run errantly named files, etc. Thoughts? Suggestions? Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Fix tests/main.py so it can be run from anywhere.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15675 Change subject: tests: Fix tests/main.py so it can be run from anywhere. .. tests: Fix tests/main.py so it can be run from anywhere. tests/main.py was trying to find paths relative to itself using the string __name__ (which was __main__) when it should have been using the string __file__ which holds the name of the file being executed. Change-Id: I5ff4c42fc7d8b75ff6b96c3cde61baf731d84738 --- M tests/main.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/main.py b/tests/main.py index 509724e..779445d 100755 --- a/tests/main.py +++ b/tests/main.py @@ -10,7 +10,7 @@ import sys import os -base_dir = os.path.dirname(os.path.abspath(__name__)) +base_dir = os.path.dirname(os.path.abspath(__file__)) ext_path = os.path.join(base_dir, os.pardir, 'ext') sys.path.insert(0, base_dir) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15675 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5ff4c42fc7d8b75ff6b96c3cde61baf731d84738 Gerrit-Change-Number: 15675 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: riscv: Get rid of some ISA specific register types.
Hello Jason Lowe-Power, Alec Roelke, Alec Roelke, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14466 to look at the new patch set (#5). Change subject: riscv: Get rid of some ISA specific register types. .. riscv: Get rid of some ISA specific register types. Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100 --- M src/arch/riscv/faults.cc M src/arch/riscv/faults.hh M src/arch/riscv/isa.cc M src/arch/riscv/isa.hh M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/fp.isa M src/arch/riscv/isa/formats/standard.isa M src/arch/riscv/process.cc M src/arch/riscv/process.hh M src/arch/riscv/registers.hh M src/arch/riscv/remote_gdb.hh 11 files changed, 92 insertions(+), 96 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14466 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100 Gerrit-Change-Number: 14466 Gerrit-PatchSet: 5 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13624 )
Change subject: cpu: dev: sim: gpu-compute: Banish some ISA specific
register types.
..
cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.
Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
M src/arch/hsail/gpu_isa.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_tlb.cc
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_emul.hh
26 files changed, 478 insertions(+), 389 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh
index 425522a..fa2cde3 100644
--- a/src/arch/hsail/gpu_isa.hh
+++ b/src/arch/hsail/gpu_isa.hh
@@ -40,6 +40,7 @@
#include "arch/hsail/gpu_types.hh"
#include "base/logging.hh"
+#include "base/types.hh"
#include "gpu-compute/misc.hh"
namespace HsailISA
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index ae2911c..c2a1408 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -649,7 +649,7 @@
/** @} */
/** Records an integer register being set to a value. */
-void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
@@ -669,7 +669,7 @@
/** Records an fp register being set to an integer value. */
void
-setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
+setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5673641..2c7e022 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -88,9 +88,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
-typedef TheISA::FloatReg FloatReg;
-typedef TheISA::FloatRegBits FloatRegBits;
-typedef TheISA::MiscReg MiscReg;
using VecRegContainer = TheISA::VecRegContainer;
/** id attached to all issued requests */
@@ -189,15 +186,16 @@
// storage (which is pretty hard to imagine they would have reason
// to do).
-IntReg readIntRegOperand(const StaticInst *si, int idx) override
+RegVal
+readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isIntReg());
return thread->readIntReg(reg.index());
}
-FloatRegBits readFloatRegOperandBits(const StaticInst *si,
- int idx) override
+RegVal
+readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
@@ -207,8 +205,8 @@
/**
* Read source vector register operand.
*/
-const VecRegContainer& readVecRegOperand(const StaticInst *si,
- int idx) const override
+const VecRegContainer &
+readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
@@ -218,8 +216,8 @@
/**
* Read destination vector register operand for modification.
*/
-VecRegContainer& getWritableVecRegOperand(const StaticInst *si,
- int idx) override
+VecRegContainer &
+getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -230,8 +228,7 @@
/** @{ */
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
-readVec8BitLaneOperand(const StaticInst *si, int idx) const
-override
+readVec8BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg =
[gem5-dev] Change in gem5/gem5[master]: arch: Make the ISA register types aliases for the global types.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13623 )
Change subject: arch: Make the ISA register types aliases for the global
types.
..
arch: Make the ISA register types aliases for the global types.
The ISA specific types can thus be phased out.
Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60
Reviewed-on: https://gem5-review.googlesource.com/c/13623
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/alpha/registers.hh
M src/arch/arm/registers.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
8 files changed, 33 insertions(+), 32 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 53ade47..2bff11b 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -45,14 +45,14 @@
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
// floating point register file entry type
-typedef double FloatReg;
-typedef uint64_t FloatRegBits;
+typedef FloatRegVal FloatReg;
+typedef RegVal FloatRegBits;
// control register file contents
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 3c675cf..3e0a74e 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -59,11 +59,11 @@
using ArmISAInst::MaxInstDestRegs;
using ArmISAInst::MaxMiscDestRegs;
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
// floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
// Number of VecElem per Vector Register, computed based on the vector
length
constexpr unsigned NumVecElemPerVecReg = 4;
@@ -73,7 +73,7 @@
using VecRegContainer = VecReg::Container;
// cop-0/cop-1 system control register
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
// condition code register; must be at least 32 bits for FpCondCodes
typedef uint64_t CCReg;
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index dbac839..d2095d8 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -278,14 +278,14 @@
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
// floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
// cop-0/cop-1 system control register
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 5dd8732..527193c 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -46,11 +46,11 @@
namespace NullISA {
-typedef uint64_t IntReg;
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal IntReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
typedef uint8_t CCReg;
-typedef uint64_t MiscReg;
+typedef RegVal MiscReg;
const RegIndex ZeroReg = 0;
// dummy typedefs since we don't have vector regs
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index adbaae5..39f7d34 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -34,6 +34,7 @@
#include "arch/generic/vec_reg.hh"
#include "arch/power/generated/max_inst_regs.hh"
#include "arch/power/miscregs.hh"
+#include "base/types.hh"
namespace PowerISA {
@@ -44,12 +45,12 @@
// be detected by it. Manually add it here.
const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
-typedef uint64_t IntReg;
+typedef RegVal IntReg;
// Floating point register file entry type
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
-typedef uint64_t MiscReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
+typedef RegVal MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index bd95cf8..75f74ef 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -63,11 +63,11 @@
using RiscvISAInst::MaxInstDestRegs;
const int MaxMiscDestRegs = 1;
-typedef uint64_t IntReg;
-typedef uint64_t FloatRegBits;
-typedef double FloatReg;
+typedef RegVal IntReg;
+typedef RegVal FloatRegBits;
+typedef FloatRegVal FloatReg;
typedef uint8_t CCReg; // Not applicable to Riscv
-typedef uint64_t MiscReg;
+typedef
[gem5-dev] Change in gem5/gem5[master]: arm: Make the fp register types 64 bits.
Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13622 ) Change subject: arm: Make the fp register types 64 bits. .. arm: Make the fp register types 64 bits. This matches the other ISAs. Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c Reviewed-on: https://gem5-review.googlesource.com/c/13622 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- M src/arch/arm/registers.hh 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index e7defd1..3c675cf 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -62,8 +62,8 @@ typedef uint64_t IntReg; // floating point register file entry type -typedef uint32_t FloatRegBits; -typedef float FloatReg; +typedef uint64_t FloatRegBits; +typedef double FloatReg; // Number of VecElem per Vector Register, computed based on the vector length constexpr unsigned NumVecElemPerVecReg = 4; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13622 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c Gerrit-Change-Number: 13622 Gerrit-PatchSet: 8 Gerrit-Owner: Gabe Black Gerrit-Assignee: Giacomo Travaglini Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#4). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 386 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 4 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#3). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 386 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Access Map Pattern Matching Prefetcher
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15096 )
Change subject: mem-cache: Access Map Pattern Matching Prefetcher
..
mem-cache: Access Map Pattern Matching Prefetcher
Implementation of the Access Map Pattern Matching prefetcher
Based in the description of the following paper:
Access map pattern matching for high performance data cache prefetch.
Ishii, Y., Inaba, M., & Hiraki, K. (2011).
Journal of Instruction-Level Parallelism, 13, 1-24.
Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c
Reviewed-on: https://gem5-review.googlesource.com/c/15096
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/SConscript
A src/mem/cache/prefetch/access_map_pattern_matching.cc
A src/mem/cache/prefetch/access_map_pattern_matching.hh
4 files changed, 469 insertions(+), 0 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index a868a25..3d9c665 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -179,3 +179,37 @@
"Minimum confidence to issue prefetches")
lookahead_confidence_threshold = Param.Float(0.75,
"Minimum confidence to continue exploring lookahead entries")
+
+class AccessMapPatternMatchingPrefetcher(QueuedPrefetcher):
+type = 'AccessMapPatternMatchingPrefetcher'
+cxx_class = 'AccessMapPatternMatchingPrefetcher'
+cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
+
+start_degree = Param.Unsigned(4,
+"Initial degree (Maximum number of prefetches generated")
+hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone")
+access_map_table_entries = Param.MemorySize("256",
+"Number of entries in the access map table")
+access_map_table_assoc = Param.Unsigned(8,
+"Associativity of the access map table")
+access_map_table_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1, assoc =
Parent.access_map_table_assoc,
+size = Parent.access_map_table_entries),
+"Indexing policy of the access map table")
+access_map_table_replacement_policy =
Param.BaseReplacementPolicy(LRURP(),
+"Replacement policy of the access map table")
+high_coverage_threshold = Param.Float(0.25,
+"A prefetch coverage factor bigger than this is considered high")
+low_coverage_threshold = Param.Float(0.125,
+"A prefetch coverage factor smaller than this is considered low")
+high_accuracy_threshold = Param.Float(0.5,
+"A prefetch accuracy factor bigger than this is considered high")
+low_accuracy_threshold = Param.Float(0.25,
+"A prefetch accuracy factor smaller than this is considered low")
+high_cache_hit_threshold = Param.Float(0.875,
+"A cache hit ratio bigger than this is considered high")
+low_cache_hit_threshold = Param.Float(0.75,
+"A cache hit ratio smaller than this is considered low")
+epoch_cycles = Param.Cycles(256000, "Cycles in an epoch period")
+offchip_memory_latency = Param.Latency("30ns",
+"Memory latency used to compute the required memory bandwidth")
diff --git a/src/mem/cache/prefetch/SConscript
b/src/mem/cache/prefetch/SConscript
index ccbc2e3..b461586 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -32,6 +32,7 @@
SimObject('Prefetcher.py')
+Source('access_map_pattern_matching.cc')
Source('base.cc')
Source('queued.cc')
Source('signature_path.cc')
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.cc
b/src/mem/cache/prefetch/access_map_pattern_matching.cc
new file mode 100644
index 000..0f46eff
--- /dev/null
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.cc
@@ -0,0 +1,252 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Signature Path Prefetcher
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14737 )
Change subject: mem-cache: Signature Path Prefetcher
..
mem-cache: Signature Path Prefetcher
Related paper:
Lookahead Prefetching with Signature Path
J Kim, PV Gratz, ALN Reddy
The 2nd Data Prefetching Championship (DPC2), 2015
Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11
Reviewed-on: https://gem5-review.googlesource.com/c/14737
Reviewed-by: Nikos Nikoleris
Reviewed-by: Daniel Carvalho
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/SConscript
A src/mem/cache/prefetch/associative_set.hh
A src/mem/cache/prefetch/associative_set_impl.hh
A src/mem/cache/prefetch/signature_path.cc
A src/mem/cache/prefetch/signature_path.hh
6 files changed, 839 insertions(+), 1 deletion(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index df547ed..a868a25 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -40,6 +40,7 @@
# Mitch Hayenga
from ClockedObject import ClockedObject
+from IndexingPolicies import *
from m5.SimObject import *
from m5.params import *
from m5.proxy import *
@@ -139,3 +140,42 @@
cxx_header = "mem/cache/prefetch/tagged.hh"
degree = Param.Int(2, "Number of prefetches to generate")
+
+class SignaturePathPrefetcher(QueuedPrefetcher):
+type = 'SignaturePathPrefetcher'
+cxx_class = 'SignaturePathPrefetcher'
+cxx_header = "mem/cache/prefetch/signature_path.hh"
+
+signature_shift = Param.UInt8(3,
+"Number of bits to shift when calculating a new signature");
+signature_bits = Param.UInt16(12,
+"Size of the signature, in bits");
+signature_table_entries = Param.MemorySize("1024",
+"Number of entries of the signature table")
+signature_table_assoc = Param.Unsigned(2,
+"Associativity of the signature table")
+signature_table_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1, assoc =
Parent.signature_table_assoc,
+size = Parent.signature_table_entries),
+"Indexing policy of the signature table")
+signature_table_replacement_policy =
Param.BaseReplacementPolicy(LRURP(),
+"Replacement policy of the signature table")
+
+max_counter_value = Param.UInt8(7, "Maximum pattern counter value")
+pattern_table_entries = Param.MemorySize("4096",
+"Number of entries of the pattern table")
+pattern_table_assoc = Param.Unsigned(1,
+"Associativity of the pattern table")
+strides_per_pattern_entry = Param.Unsigned(4,
+"Number of strides stored in each pattern entry")
+pattern_table_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1, assoc = Parent.pattern_table_assoc,
+size = Parent.pattern_table_entries),
+"Indexing policy of the pattern table")
+pattern_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
+"Replacement policy of the pattern table")
+
+prefetch_confidence_threshold = Param.Float(0.5,
+"Minimum confidence to issue prefetches")
+lookahead_confidence_threshold = Param.Float(0.75,
+"Minimum confidence to continue exploring lookahead entries")
diff --git a/src/mem/cache/prefetch/SConscript
b/src/mem/cache/prefetch/SConscript
index 2665d18..ccbc2e3 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -34,6 +34,6 @@
Source('base.cc')
Source('queued.cc')
+Source('signature_path.cc')
Source('stride.cc')
Source('tagged.cc')
-
diff --git a/src/mem/cache/prefetch/associative_set.hh
b/src/mem/cache/prefetch/associative_set.hh
new file mode 100644
index 000..99b6a6d
--- /dev/null
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -0,0 +1,200 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND
[gem5-dev] Change in gem5/gem5[master]: mem-cache: allow prefetchers to emit page crossing references
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14735 )
Change subject: mem-cache: allow prefetchers to emit page crossing
references
..
mem-cache: allow prefetchers to emit page crossing references
QueuedPrefetcher takes the responsability to check for page
crossing references.
Change-Id: I0ae6bf8be465118990d9ea1cac0da8f70e69aeb1
Reviewed-on: https://gem5-review.googlesource.com/c/14735
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/tagged.cc
3 files changed, 14 insertions(+), 22 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index f48ea18..bce6fbb 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -93,14 +93,20 @@
// Block align prefetch address
addr_prio.first = blockAddress(addr_prio.first);
-PrefetchInfo new_pfi(pfi,addr_prio.first);
+if (samePage(pfi.getAddr(), addr_prio.first)) {
+PrefetchInfo new_pfi(pfi,addr_prio.first);
-pfIdentified++;
-DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
-"inserting into prefetch queue.\n", new_pfi.getAddr());
+pfIdentified++;
+DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
+"inserting into prefetch queue.\n", new_pfi.getAddr());
-// Create and insert the request
-insert(pkt, new_pfi, addr_prio.second);
+// Create and insert the request
+insert(pkt, new_pfi, addr_prio.second);
+} else {
+// Record the number of page crossing prefetches generate
+pfSpanPage += 1;
+DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
+}
}
}
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index 5d00901..caddc75 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -195,15 +195,7 @@
}
Addr new_addr = pf_addr + d * prefetch_stride;
-if (samePage(pf_addr, new_addr)) {
-DPRINTF(HWPrefetch, "Queuing prefetch to %#x.\n",
new_addr);
-addresses.push_back(AddrPriority(new_addr, 0));
-} else {
-// Record the number of page crossing prefetches generated
-pfSpanPage += degree - d + 1;
-DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
-return;
-}
+addresses.push_back(AddrPriority(new_addr, 0));
}
} else {
// Miss in table
diff --git a/src/mem/cache/prefetch/tagged.cc
b/src/mem/cache/prefetch/tagged.cc
index a360cc6..1623817 100644
--- a/src/mem/cache/prefetch/tagged.cc
+++ b/src/mem/cache/prefetch/tagged.cc
@@ -51,13 +51,7 @@
for (int d = 1; d <= degree; d++) {
Addr newAddr = blkAddr + d*(blkSize);
-if (!samePage(blkAddr, newAddr)) {
-// Count number of unissued prefetches due to page crossing
-pfSpanPage += degree - d + 1;
-return;
-} else {
-addresses.push_back(AddrPriority(newAddr,0));
-}
+addresses.push_back(AddrPriority(newAddr,0));
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0ae6bf8be465118990d9ea1cac0da8f70e69aeb1
Gerrit-Change-Number: 14735
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: virtual address support for prefetchers
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14416 )
Change subject: mem-cache: virtual address support for prefetchers
..
mem-cache: virtual address support for prefetchers
Prefetchers can be configured to operate with virtual or physical addreses.
The option can be configured through the "use_virtual_addresses" parameter
of the Prefetcher object.
Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa
Reviewed-on: https://gem5-review.googlesource.com/c/14416
Maintainer: Nikos Nikoleris
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
9 files changed, 232 insertions(+), 89 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index bae235d..df547ed 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -76,6 +76,8 @@
on_inst = Param.Bool(True, "Notify prefetcher on instruction
accesses")
prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
"Notify the hardware prefetcher on every access (not just misses)")
+use_virtual_addresses = Param.Bool(False,
+"Use virtual addresses for prefetching")
_events = []
def addEvent(self, newObject):
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 53260ae..e58d4f3 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -56,6 +56,19 @@
#include "params/BasePrefetcher.hh"
#include "sim/system.hh"
+BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr)
+ : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
+masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
+secure(pkt->isSecure())
+{
+}
+
+BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const , Addr
addr)
+ : address(addr), pc(pfi.pc), masterId(pfi.masterId),
validPC(pfi.validPC),
+secure(pfi.secure)
+{
+}
+
void
BasePrefetcher::PrefetchListener::notify(const PacketPtr )
{
@@ -67,7 +80,8 @@
lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
masterId(p->sys->getMasterId(this)),
pageBytes(p->sys->getPageBytes()),
- prefetchOnAccess(p->prefetch_on_access)
+ prefetchOnAccess(p->prefetch_on_access),
+ useVirtualAddresses(p->use_virtual_addresses)
{
}
@@ -175,7 +189,17 @@
if (pkt->cmd.isSWPrefetch()) return;
if (pkt->req->isCacheMaintenance()) return;
if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
-notify(pkt);
+
+// Verify this access type is observed by prefetcher
+if (observeAccess(pkt)) {
+if (useVirtualAddresses && pkt->req->hasVaddr()) {
+PrefetchInfo pfi(pkt, pkt->req->getVaddr());
+notify(pkt, pfi);
+} else if (!useVirtualAddresses && pkt->req->hasPaddr()) {
+PrefetchInfo pfi(pkt, pkt->req->getPaddr());
+notify(pkt, pfi);
+}
+}
}
void
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 813d1b9..63b0e1b 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -78,6 +78,96 @@
std::vector listeners;
protected:
+/**
+ * Class containing the information needed by the prefetch to train and
+ * generate new prefetch requests.
+ */
+class PrefetchInfo {
+/** The address. */
+Addr address;
+/** The program counter that generated this address. */
+Addr pc;
+/** The requestor ID that generated this address. */
+MasterID masterId;
+/** Validity bit for the PC of this address. */
+bool validPC;
+/** Whether this address targets the secure memory space. */
+bool secure;
+
+ public:
+/**
+ * Obtains the address value of this Prefetcher address.
+ * @return the addres value.
+ */
+Addr getAddr() const
+{
+return address;
+}
+
+/**
+ * Returns true if the address targets the secure memory space.
+ * @return true if the address targets the secure memory space.
+ */
+bool isSecure() const
+{
+return secure;
+}
+
+/**
+ * Returns the program counter that generated this request.
+ *
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added TLBI_ALL EL2 instruction
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15616 )
Change subject: arch-arm: Added TLBI_ALL EL2 instruction
..
arch-arm: Added TLBI_ALL EL2 instruction
This patch is adding TLBI_ALLE2(IS) operations to the arm ISA.
Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011
Signed-off-by: Giacomo Travaglini
Reviewed-by: Anouk Van Laer
Reviewed-on: https://gem5-review.googlesource.com/c/15616
Reviewed-by: Nikos Nikoleris
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/arm/isa.cc
1 file changed, 11 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d7d51b8..17c87ba 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1338,9 +1338,17 @@
tlbiOp.broadcast(tc);
return;
}
- // @todo: uncomment this to enable Virtualization
- // case MISCREG_TLBI_ALLE2IS:
- // case MISCREG_TLBI_ALLE2:
+ // AArch64 TLB Invalidate All, EL2, Inner Shareable
+ case MISCREG_TLBI_ALLE2:
+ case MISCREG_TLBI_ALLE2IS:
+{
+assert64(tc);
+scr = readMiscReg(MISCREG_SCR, tc);
+
+TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
+tlbiOp(tc);
+return;
+}
// AArch64 TLB Invalidate All, EL1
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLE1:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011
Gerrit-Change-Number: 15616
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15617 )
Change subject: arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled
..
arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled
Trying to read MPIDR(_EL1) from EL1, should return the value of
VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility
function for reading MPIDR in order to match this behaviour for both
AArch32 and AArch64.
Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3
Signed-off-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/15617
Maintainer: Andreas Sandberg
---
M src/arch/arm/isa.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
3 files changed, 40 insertions(+), 12 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 17c87ba..3d98aea 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -477,18 +477,10 @@
return val;
}
case MISCREG_MPIDR:
-cpsr = readMiscRegNoEffect(MISCREG_CPSR);
-scr = readMiscRegNoEffect(MISCREG_SCR);
-if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
-return getMPIDR(system, tc);
-} else {
-return readMiscReg(MISCREG_VMPIDR, tc);
-}
-break;
case MISCREG_MPIDR_EL1:
-// @todo in the absence of v8 virtualization support just return
MPIDR_EL1
-return getMPIDR(system, tc) & 0x;
+return readMPIDR(system, tc);
case MISCREG_VMPIDR:
+ case MISCREG_VMPIDR_EL2:
// top bit defined as RES1
return readMiscRegNoEffect(misc_reg) | 0x8000;
case MISCREG_ID_AFR0: // not implemented, so alias MIDR
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 1dc7fc0..58eb032 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -205,7 +205,37 @@
return ArmSystem::haveLPAE(tc) && ttbcr.eae;
}
-uint32_t
+MiscReg
+readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
+{
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+const ExceptionLevel current_el =
+opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+
+const bool is_secure = isSecureBelowEL3(tc);
+
+switch (current_el) {
+ case EL0:
+// Note: in MsrMrs instruction we read the register value before
+// checking access permissions. This means that EL0 entry must
+// be part of the table even if MPIDR is not accessible in user
+// mode.
+warn_once("Trying to read MPIDR at EL0\n");
+M5_FALLTHROUGH;
+ case EL1:
+if (ArmSystem::haveEL(tc, EL2) && !is_secure)
+return tc->readMiscReg(MISCREG_VMPIDR_EL2);
+else
+return getMPIDR(arm_sys, tc);
+ case EL2:
+ case EL3:
+return getMPIDR(arm_sys, tc);
+ default:
+panic("Invalid EL for reading MPIDR register\n");
+}
+}
+
+MiscReg
getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
{
// Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 3369698..01b95b3 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -250,7 +250,13 @@
bool longDescFormatInUse(ThreadContext *tc);
-uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
+/** This helper function is either returing the value of
+ * MPIDR_EL1 (by calling getMPIDR), or it is issuing a read
+ * to VMPIDR_EL2 (as it happens in virtualized systems) */
+MiscReg readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
+
+/** This helper function is returing the value of MPIDR_EL1 */
+MiscReg getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
static inline uint32_t
mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3
Gerrit-Change-Number: 15617
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch: Fix VecElem Operand generation in ISA parser
Hello Gabe Black, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15602 to look at the new patch set (#5). Change subject: arch: Fix VecElem Operand generation in ISA parser .. arch: Fix VecElem Operand generation in ISA parser Fixes include: * Change of reg_class: VecElemClass in lieau of non-existing VectorElemClass. * Removal of unused regId in operand constructor * makeRead and makeWrite are using VecElem (which is a typedef of uint32_t) as a source/destination type, regardless of the real operand type (which is specified by ctype) Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8 Signed-off-by: Giacomo Travaglini --- M src/arch/isa_parser.py 1 file changed, 20 insertions(+), 11 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15602 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8 Gerrit-Change-Number: 15602 Gerrit-PatchSet: 5 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem: Allow inserts in the begining of a packet queue
Hello Jason Lowe-Power, Daniel Carvalho, Bradley Wang, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15556 to look at the new patch set (#2). Change subject: mem: Allow inserts in the begining of a packet queue .. mem: Allow inserts in the begining of a packet queue A packet queue keeps track of packets that are scheduled to be sent at a specified time. Packets are sorted such that the packet with the earliest scheduled time is at the front of the list (unless there are other ordering requirements). Previouly, the implemented algorithm didn't allow packets to be placed at the front of the queue resulting in uneccessary delays. This change fixes the implementation of schedSendTiming. Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e Signed-off-by: Nikos Nikoleris --- M src/mem/packet_queue.cc 1 file changed, 15 insertions(+), 16 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15556 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e Gerrit-Change-Number: 15556 Gerrit-PatchSet: 2 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Bradley Wang Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Access Map Pattern Matching Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15096 to look at the new patch set (#4). Change subject: mem-cache: Access Map Pattern Matching Prefetcher .. mem-cache: Access Map Pattern Matching Prefetcher Implementation of the Access Map Pattern Matching prefetcher Based in the description of the following paper: Access map pattern matching for high performance data cache prefetch. Ishii, Y., Inaba, M., & Hiraki, K. (2011). Journal of Instruction-Level Parallelism, 13, 1-24. Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/access_map_pattern_matching.cc A src/mem/cache/prefetch/access_map_pattern_matching.hh 4 files changed, 469 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15096 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c Gerrit-Change-Number: 15096 Gerrit-PatchSet: 4 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! *** diff[simout]: SKIPPED* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: CHANGED! *
