date:20190215

[gem5-dev] SimObject Param types which are template classes

2019-02-15 Thread Gabe Black

Hi folks. I'm trying to create a SimObject out of a templated class (the
python Param type uses a specialization of it), and the pybind11 generated
code doesn't compile because the predeclaration of the class type isn't
syntactically correct since it's a template. I can work around this problem
by, for instance, subclassing it and then using that subclass (at least I
think I can, I haven't tried it yet), but it would be nice if the system
could handle it.

It's not obvious how to fix it since it's not obvious from the fully
specified type how it should be prototyped, so it's not a quick fix. Has
anyone attempted to get this to work, and/or have a solution?

Thanks!
Gabe
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: config: Make parameter conversion handle integers in other bases.

2019-02-15 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/16504



Change subject: config: Make parameter conversion handle integers in other  
bases.

..

config: Make parameter conversion handle integers in other bases.

Python's float() function/type can't handle hexadecimal notation, but
int() can. When converting the string representation of a number into
a numeric type, we can first attempt to use float() on it, and if that
fails try to use int() with an autodetected base.

Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c
---
M src/python/m5/util/convert.py
1 file changed, 13 insertions(+), 7 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 7b9cb38..87757ad 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -93,26 +93,32 @@


 # memory size configuration stuff
+def toNum(value, target_type):
+try:
+return float(value)
+except ValueError:
+pass
+try:
+return int(value, 0)
+except ValueError:
+raise ValueError("cannot convert '%s' to %s" % (value,  
target_type))

+
 def toFloat(value, target_type='float', units=None, prefixes=[]):
 assertStr(value)

 if units and not value.endswith(units):
 units = None
 if not units:
-try:
-return float(value)
-except ValueError:
-raise ValueError("cannot convert '%s' to %s" % \
- (value, target_type))
+return toNum(value, target_type)

 value = value[:-len(units)]

 prefix = next((p for p in prefixes.keys() if value.endswith(p)), None)
 if not prefix:
-return float(value)
+return toNum(value, target_type)
 value = value[:-len(prefix)]

-return float(value) * prefixes[prefix]
+return toNum(value, target_type) * prefixes[prefix]

 def toMetricFloat(value, target_type='float', units=None):
 return toFloat(value, target_type, units, metric_prefixes)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16504
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c
Gerrit-Change-Number: 16504
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: systemc: Export the tlm::tlm_global_quantum class to python.

2019-02-15 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/16503



Change subject: systemc: Export the tlm::tlm_global_quantum class to python.
..

systemc: Export the tlm::tlm_global_quantum class to python.

This way the python code can set up the global quantum without having
an sc_main function to do it.

Change-Id: I96df4dea0f1bfe9e3e86d4784bbda8f5b6b74d0b
---
M src/systemc/core/SystemC.py
M src/systemc/tlm_core/2/quantum/SConscript
A src/systemc/tlm_core/2/quantum/global_quantum_python.cc
3 files changed, 60 insertions(+), 0 deletions(-)



diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py
index 7afbd28..84424ef 100644
--- a/src/systemc/core/SystemC.py
+++ b/src/systemc/core/SystemC.py
@@ -58,6 +58,11 @@
 return SystemC_Kernel.ScMainResult(
 sc_main_result_code(), sc_main_result_str());

+def tlm_global_quantum_instance(self):
+'''Retrieve the global tlm quantum instance'''
+from _m5.systemc import tlm_global_quantum
+return tlm_global_quantum.instance()
+
 # This class represents systemc sc_object instances in python config  
files. It
 # inherits from SimObject in python, but the c++ version,  
sc_core::sc_object,

 # doesn't inherit from gem5's c++ SimObject class.
diff --git a/src/systemc/tlm_core/2/quantum/SConscript  
b/src/systemc/tlm_core/2/quantum/SConscript

index a158047..1831b5c 100644
--- a/src/systemc/tlm_core/2/quantum/SConscript
+++ b/src/systemc/tlm_core/2/quantum/SConscript
@@ -29,3 +29,5 @@

 if env['USE_SYSTEMC']:
 Source('global_quantum.cc')
+if env['USE_PYTHON']:
+Source('global_quantum_python.cc')
diff --git a/src/systemc/tlm_core/2/quantum/global_quantum_python.cc  
b/src/systemc/tlm_core/2/quantum/global_quantum_python.cc

new file mode 100644
index 000..ebc576d
--- /dev/null
+++ b/src/systemc/tlm_core/2/quantum/global_quantum_python.cc
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "systemc/core/python.hh"
+#include "systemc/ext/tlm_core/2/quantum/global_quantum.hh"
+
+namespace
+{
+
+struct InstallTlmGlobalQuantum : public ::sc_gem5::PythonInitFunc
+{
+void
+run(pybind11::module ) override
+{
+pybind11::class_(
+systemc, "tlm_global_quantum")
+.def_static("instance", ::tlm_global_quantum::instance,
+pybind11::return_value_policy::reference)
+.def("set", ::tlm_global_quantum::set)
+.def("get", ::tlm_global_quantum::get)
+.def("compute_local_quantum",
+::tlm_global_quantum::compute_local_quantum)
+;
+}
+} installTlmGlobalQuantum;
+
+} // anonymous namespace

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16503
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I96df4dea0f1bfe9e3e86d4784bbda8f5b6b74d0b
Gerrit-Change-Number: 16503
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: systemc: Export the sc_core::sc_time class to python.

2019-02-15 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/16502



Change subject: systemc: Export the sc_core::sc_time class to python.
..

systemc: Export the sc_core::sc_time class to python.

This class isn't incredibly useful in python, but it's needed to call
some other functions which are more useful.

Change-Id: I5c23cca0b50f0455423399db8b009bdf86a6ec41
---
M src/systemc/core/SConscript
M src/systemc/core/SystemC.py
A src/systemc/core/sc_time_python.cc
3 files changed, 89 insertions(+), 0 deletions(-)



diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 536c181..f086112 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -64,3 +64,4 @@
 if env['USE_PYTHON']:
 Source('python.cc')
 Source('sc_main_python.cc')
+Source('sc_time_python.cc')
diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py
index 7ab33ea..7afbd28 100644
--- a/src/systemc/core/SystemC.py
+++ b/src/systemc/core/SystemC.py
@@ -36,6 +36,12 @@
 cxx_class = 'sc_gem5::Kernel'
 cxx_header = 'systemc/core/kernel.hh'

+# The sc_time type won't exist until some setup code runs in gem5.
+try:
+from _m5.systemc import sc_time
+except:
+pass
+
 class ScMainResult(object):
 def __init__(self, code, message):
 self.code = code
diff --git a/src/systemc/core/sc_time_python.cc  
b/src/systemc/core/sc_time_python.cc

new file mode 100644
index 000..67fcb7b
--- /dev/null
+++ b/src/systemc/core/sc_time_python.cc
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "pybind11/operators.h"
+
+#include "systemc/core/python.hh"
+#include "systemc/ext/core/sc_time.hh"
+
+namespace
+{
+
+struct InstallScTime : public ::sc_gem5::PythonInitFunc
+{
+void
+run(pybind11::module ) override
+{
+pybind11::class_ sc_time(systemc, "sc_time");
+sc_time
+// Constructors (omitting nonstandard and deprecated)
+.def(pybind11::init<>())
+.def(pybind11::init())
+.def(pybind11::init())
+
+// Converters.
+.def("value", _core::sc_time::value)
+.def("to_double", _core::sc_time::to_double)
+.def("to_seconds", _core::sc_time::to_seconds)
+.def("to_string", _core::sc_time::to_string)
+.def("__repr__", _core::sc_time::to_string)
+
+// Operators.
+.def(pybind11::self == pybind11::self)
+.def(pybind11::self != pybind11::self)
+.def(pybind11::self < pybind11::self)
+.def(pybind11::self <= pybind11::self)
+.def(pybind11::self > pybind11::self)
+.def(pybind11::self >= pybind11::self)
+.def(pybind11::self += pybind11::self)
+.def(pybind11::self -= pybind11::self)
+.def(pybind11::self *= double())
+.def(pybind11::self /= double())
+;
+
+pybind11::enum_(sc_time, "sc_time_unit")
+.value("SC_FS", sc_core::SC_FS)
+.value("SC_PS", sc_core::SC_PS)
+.value("SC_NS", sc_core::SC_NS)
+.value("SC_US", sc_core::SC_US)
+.value("SC_MS", sc_core::SC_MS)
+.value("SC_SEC", sc_core::SC_SEC)
+.export_values()
+;
+}
+}

Re: [gem5-dev] [gem5-users] GPU

2019-02-15 Thread Krishna Subramanian

HI :

I built the HSAIL_X86 model for gem5. I also created the an executable
"hello" using g++ and  openCL runtimes. I was able to build the required
.asm file using the AMD High-Level-Compiler ( HLC ) provided in AMD git
repo. However when i try to run the program , i get an error : unknown HSA
Object.

*kzs0115@eelnx221:/scratch/gem5$ ./build/HSAIL_X86/gem5.opt
configs/example/apu_se.py -c
tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello -k
tests/test-progs/gpu-hello/bin/x86/gpu-hello-kernel.asm
linux/kzs0115@eelnx221:/scratch/gem5$
./build/HSAIL_X86/gem5.opt configs/example/apu_se.py -c
tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello -k
tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.brig gem5
Simulator System.  http://gem5.org gem5 is copyrighted
software; use the --copyright option for details.gem5 compiled Feb  4 2019
12:30:03gem5 started Feb 15 2019 14:25:45gem5 executing on eelnx221, pid
28614command line: ./build/HSAIL_X86/gem5.opt configs/example/apu_se.py -c
tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello -k
tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.brigGlobal
frequency set at 1 ticks per secondwarn: system.ruby.network
adopting orphan SimObject param 'int_links'warn: system.ruby.network
adopting orphan SimObject param 'ext_links'warn: DRAM device capacity (8192
Mbytes) does not match the address range assigned (512 Mbytes)fatal:
Unknown HSA object type for file:
./tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.brig.Memory
Usage: 1169144 KBytes*

I made the executable using the following commands :
*g++ -static -std=c++11 -I../../../../cl-runtime/ $(prog).cpp
$(prog)_benchmark.cc $(prog)_cl12_benchmark.cc
-L../../../../cl-runtime/dbg64b/ -lOpenCL -o $(prog)*

I built the asm using the following commands :

*clc2 --enable-hsail-extensions -cl-std=CL2.0 $oclfllvm-dis  -o
results/$fname.fe.ll results/$fname.fe.bcecho "FE complete"llvm-link
-prelink-opt -o results/$fname.linked.bc results/$fname.fe.bc  -l
$ROOT/bin/builtins-hsail.bcecho "llvm-link completed!"llvm-dis  -o
results/$fname.linked.ll results/$fname.linked.bcopt  -O3 -gpu -whole
-verify results/$fname.linked.bc -o results/$fname.opt.bcecho "opt
complete!"llvm-dis  -o results/$fname.opt.ll results/$fname.opt.bcllc  -O2
-march=hsail-64 -filetype=obj -o results/$fname.asm
results/$fname.opt.bcecho "llc complete"hsailasm  -disassemble -o
results/$fname.hsail  results/$fname.brigecho "HSAIL generated!"*

Any ideas on how to fix this ? Am i generating the .asm file incorrectly ?
If so , how do i generate it ? Thank you for your time

On Tue, Feb 12, 2019 at 1:29 PM Gutierrez, Anthony <
anthony.gutier...@amd.com> wrote:

> There are some instructions about how to build the software stack for the
> GPU model here: http://gem5.org/GPU_Models
>
> You’ll need to build the ROCr (runtime) ROCt (thunk) and HCC (clang/llvm
> compiler), and probably HIP too as most available codes are in HIP. For
> example, the Rodinia benchmarks have been hipified here:
> https://github.com/ROCm-Developer-Tools/HIP-Examples/tree/master/rodinia_3.0/hip
>
> The recommended branches are listed on the site, however most users have
> not been able to get them to run in the simulator.
>
> These are shas for each repo known to work in gem5:
>
> HCC: 7d030799dca53d39f141d60c73950966501b3ffb
> ROCr: f92eba2a8b0d5e9a8fa28a127bd1eb59f03d3eb0
> ROCt: d13b4e2e2413cb20e8cc2bcdd419f06f499f306e
> HIP: 0e3d824e8d8f1ec3e31b26fa1f2e46fd3e6d4241
>
>
> From: gem5-users  On Behalf Of Krishna
> Subramanian
> Sent: Thursday, February 7, 2019 12:26 PM
> To: gem5 Developer List ; gem5-us...@gem5.org
> Subject: [gem5-users] GPU
>
> Hi
>
> I was able to successfully run the GPU Hello included in the gem5
> distribution using the HSAIL build. However i was wondering how to write my
> own openCL/different language program and compile it all the way down to an
> executable binary on the HSAIL ( or the equivalent in GCN3). Is there any
> tutorial/methodology you can point me to if available.
>
> Thank you for your time
> Best,
> Krishna
> ___
> gem5-dev mailing list
> gem5-dev@gem5.org
> http://m5sim.org/mailman/listinfo/gem5-dev
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: base: Fix enums checkpointing

2019-02-15 Thread Giacomo Travaglini (Gerrit)

Hello Gabe Black, Jason Lowe-Power, Daniel Carvalho, Andreas Sandberg, Ciro  
Santilli,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/16382

to look at the new patch set (#2).

Change subject: base: Fix enums checkpointing
..

base: Fix enums checkpointing

Creating an extra version of string to number converters (__to_number)
in base/str.hh; it will be used by enums only when unserializing
them.  The reason not to have a single helper for both enums and
integers is that std::numeric_limits trait is not specialized for enums.
We fix this by using the std::underlying_type trait.

Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Ciro Santilli 
Signed-off-by: Giacomo Travaglini 
---
M src/base/str.hh
1 file changed, 11 insertions(+), 4 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16382
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Gerrit-Change-Number: 16382
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix fast build broken due to unused variable

2019-02-15 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/16463 )


Change subject: cpu: Fix fast build broken due to unused variable
..

cpu: Fix fast build broken due to unused variable

This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b
(fast build is striping out assertions)

Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/16463
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/cpu/o3/lsq_impl.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved



diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index abe751c..5c64377 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -685,7 +685,7 @@
 // This comming request can be either load, store or atomic.
 // Atomic request has a corresponding pointer to its atomic memory
 // operation
-bool isAtomic = !isLoad && amo_op;
+bool isAtomic M5_VAR_USED = !isLoad && amo_op;

 ThreadID tid = cpu->contextToThread(inst->contextId());
 auto cacheLineSize = cpu->cacheLineSize();

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16463
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Gerrit-Change-Number: 16463
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix fast build broken due to unused variable

2019-02-15 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/16463



Change subject: cpu: Fix fast build broken due to unused variable
..

cpu: Fix fast build broken due to unused variable

This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b
(fast build is striping out assertions)

Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/o3/lsq_impl.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index abe751c..5c64377 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -685,7 +685,7 @@
 // This comming request can be either load, store or atomic.
 // Atomic request has a corresponding pointer to its atomic memory
 // operation
-bool isAtomic = !isLoad && amo_op;
+bool isAtomic M5_VAR_USED = !isLoad && amo_op;

 ThreadID tid = cpu->contextToThread(inst->contextId());
 auto cacheLineSize = cpu->cacheLineSize();

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16463
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Gerrit-Change-Number: 16463
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: cpu: Add ISA* getter in Thread interface

2019-02-15 Thread Giacomo Travaglini (Gerrit)

Hello Anthony Gutierrez, Jason Lowe-Power, Andreas Sandberg, Giacomo  
Gabrielli,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/16462

to look at the new patch set (#2).

Change subject: cpu: Add ISA* getter in Thread interface
..

cpu: Add ISA* getter in Thread interface

This patch is adding a ISA* getter to the TC interface

Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
4 files changed, 15 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16462
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
Gerrit-Change-Number: 16462
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Giacomo Gabrielli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

2019-02-15 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded a new patch set (#13) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13515 )


Change subject: arch-arm,cpu: Add initial support for Arm SVE
..

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain 
- Gabor Dozsa 
- Giacomo Travaglini 

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/vec_reg.hh
M src/cpu/FuncUnit.py
M src/cpu/exetrace.cc
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/op_class.hh
M src/cpu/simple_thread.cc
45 files changed, 11,191 insertions(+), 61 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 13
Gerrit-Owner: Giacomo Gabrielli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Gabrielli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: cpu: Add ISA* getter in Thread interface

2019-02-15 Thread Giacomo Travaglini (Gerrit)


Hello Giacomo Gabrielli,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/16462

to review the following change.


Change subject: cpu: Add ISA* getter in Thread interface
..

cpu: Add ISA* getter in Thread interface

This patch is adding a ISA* getter to the TC interface

Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
4 files changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 9c8469c..d88c9b2 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -121,6 +121,8 @@
 return checkerCPU;
 }

+TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
+
 TheISA::Decoder *getDecoderPtr() override {
 return actualTC->getDecoderPtr();
 }
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 022e712..6dab016 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -86,6 +86,12 @@

 CheckerCPU *getCheckerCpuPtr() override { return NULL; }

+TheISA::ISA *
+getIsaPtr()
+{
+return cpu->isa[thread->threadId()];
+}
+
 TheISA::Decoder *
 getDecoderPtr() override
 {
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3dddc67..53aa9d7 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -203,6 +203,8 @@

 CheckerCPU *getCheckerCpuPtr() { return NULL; }

+TheISA::ISA *getIsaPtr() { return isa; }
+
 TheISA::Decoder *getDecoderPtr() { return  }

 System *getSystemPtr() { return system; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 6b9ff1a..2a991f6 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -57,6 +57,7 @@
 // DTB pointers.
 namespace TheISA
 {
+class ISA;
 class Decoder;
 }
 class BaseCPU;
@@ -143,6 +144,8 @@

 virtual CheckerCPU *getCheckerCpuPtr() = 0;

+virtual TheISA::ISA *getIsaPtr() = 0;
+
 virtual TheISA::Decoder *getDecoderPtr() = 0;

 virtual System *getSystemPtr() = 0;
@@ -406,6 +409,8 @@

 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }

+TheISA::ISA *getIsaPtr() { return actualTC->getIsaPtr(); }
+
 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }

 System *getSystemPtr() { return actualTC->getSystemPtr(); }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16462
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
Gerrit-Change-Number: 16462
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Gabrielli 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Cron /z/m5/regression/do-regression quick

2019-02-15 Thread Cron Daemon

* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: 
CHANGED!*** diff[simerr]: SKIPPED
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: 
CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 CHANGED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: 
CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
CHANGED!
*** stat_diff: FAILURE: Statistics mismatch* 
build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED!
Statistics mismatch* 
build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 CHANGED!
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED!
*

[gem5-dev] SimObject Param types which are template classes

[gem5-dev] Change in gem5/gem5[master]: config: Make parameter conversion handle integers in other bases.

[gem5-dev] Change in gem5/gem5[master]: systemc: Export the tlm::tlm_global_quantum class to python.

[gem5-dev] Change in gem5/gem5[master]: systemc: Export the sc_core::sc_time class to python.

Re: [gem5-dev] [gem5-users] GPU

[gem5-dev] Change in gem5/gem5[master]: base: Fix enums checkpointing

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix fast build broken due to unused variable

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix fast build broken due to unused variable

[gem5-dev] Change in gem5/gem5[master]: cpu: Add ISA* getter in Thread interface

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

[gem5-dev] Change in gem5/gem5[master]: cpu: Add ISA* getter in Thread interface

[gem5-dev] Cron /z/m5/regression/do-regression quick

12 matches

Site Navigation

Mail list logo

Footer information