date:20200217

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix CNTFRQ_EL0 permission bits

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25427 )



Change subject: arch-arm: Fix CNTFRQ_EL0 permission bits
..

arch-arm: Fix CNTFRQ_EL0 permission bits

The register is marked as being writable at EL3 only (mon).  However the
arm arm states the register is accessible at the highest implemented EL.
Which means that if EL1 is the highest EL, EL1 code should be able to
modify the register value.

Change-Id: If9884fa2232869c043c96eba320e3c69efbab517
Reviewed-by: Richard Cooper 
---
M src/arch/arm/miscregs.cc
1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index c25c24b..0b883a1 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3707,8 +3707,9 @@
 InitReg(MISCREG_HTPIDR)
   .hyp().monNonSecure();
 InitReg(MISCREG_CNTFRQ)
-  .unverifiable()
-  .reads(1).mon();
+  .reads(1)
+  .highest(system)
+  .privSecureWrite(aarch32EL3);
 InitReg(MISCREG_CNTKCTL)
   .allPrivileges().exceptUserMode();
 InitReg(MISCREG_CNTP_TVAL)
@@ -4453,7 +4454,9 @@
   .allPrivileges().exceptUserMode()
   .mapsTo(MISCREG_CNTKCTL);
 InitReg(MISCREG_CNTFRQ_EL0)
-  .reads(1).mon()
+  .reads(1)
+  .highest(system)
+  .privSecureWrite(aarch32EL3)
   .mapsTo(MISCREG_CNTFRQ);
 InitReg(MISCREG_CNTPCT_EL0)
   .reads(1)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9884fa2232869c043c96eba320e3c69efbab517
Gerrit-Change-Number: 25427
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v19.0.0.0]: arch-arm: Fix CNTFRQ_EL0 permission bits

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25428 )



Change subject: arch-arm: Fix CNTFRQ_EL0 permission bits
..

arch-arm: Fix CNTFRQ_EL0 permission bits

The register is marked as being writable at EL3 only (mon).  However the
arm arm states the register is accessible at the highest implemented EL.
Which means that if EL1 is the highest EL, EL1 code should be able to
modify the register value.

Change-Id: If9884fa2232869c043c96eba320e3c69efbab517
Reviewed-by: Richard Cooper 
---
M src/arch/arm/miscregs.cc
1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index c25c24b..0b883a1 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3707,8 +3707,9 @@
 InitReg(MISCREG_HTPIDR)
   .hyp().monNonSecure();
 InitReg(MISCREG_CNTFRQ)
-  .unverifiable()
-  .reads(1).mon();
+  .reads(1)
+  .highest(system)
+  .privSecureWrite(aarch32EL3);
 InitReg(MISCREG_CNTKCTL)
   .allPrivileges().exceptUserMode();
 InitReg(MISCREG_CNTP_TVAL)
@@ -4453,7 +4454,9 @@
   .allPrivileges().exceptUserMode()
   .mapsTo(MISCREG_CNTKCTL);
 InitReg(MISCREG_CNTFRQ_EL0)
-  .reads(1).mon()
+  .reads(1)
+  .highest(system)
+  .privSecureWrite(aarch32EL3)
   .mapsTo(MISCREG_CNTFRQ);
 InitReg(MISCREG_CNTPCT_EL0)
   .reads(1)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v19.0.0.0
Gerrit-Change-Id: If9884fa2232869c043c96eba320e3c69efbab517
Gerrit-Change-Number: 25428
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: Delete authors lists from the unittest directory.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25409 )


Change subject: tests: Delete authors lists from the unittest directory.
..

tests: Delete authors lists from the unittest directory.

Change-Id: Id4c7f5ddb932e427cb42d0698b1a048377d027c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25409
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/unittest/SConscript
M src/unittest/cprintftime.cc
M src/unittest/genini.py
M src/unittest/nmtest.cc
M src/unittest/stattest.cc
M src/unittest/symtest.cc
M src/unittest/unittest.cc
M src/unittest/unittest.hh
8 files changed, 0 insertions(+), 16 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/unittest/SConscript b/src/unittest/SConscript
index 0ca0702..3922e9e 100644
--- a/src/unittest/SConscript
+++ b/src/unittest/SConscript
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 Import('*')

diff --git a/src/unittest/cprintftime.cc b/src/unittest/cprintftime.cc
index 3192d8e..4ad347d 100644
--- a/src/unittest/cprintftime.cc
+++ b/src/unittest/cprintftime.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
  */

 #include 
diff --git a/src/unittest/genini.py b/src/unittest/genini.py
index ea2763a..2575fc0 100755
--- a/src/unittest/genini.py
+++ b/src/unittest/genini.py
@@ -24,8 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 from __future__ import print_function

diff --git a/src/unittest/nmtest.cc b/src/unittest/nmtest.cc
index 7f9dd35..8524d51 100644
--- a/src/unittest/nmtest.cc
+++ b/src/unittest/nmtest.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
  */

 #include 
diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
index daf0b86..883185a 100644
--- a/src/unittest/stattest.cc
+++ b/src/unittest/stattest.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
  */

 #include "pybind11/pybind11.h"
diff --git a/src/unittest/symtest.cc b/src/unittest/symtest.cc
index 21176b9..7534529 100644
--- a/src/unittest/symtest.cc
+++ b/src/unittest/symtest.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
  */

 #include 
diff --git a/src/unittest/unittest.cc b/src/unittest/unittest.cc
index 0cac20e..2f99eae 100644
--- a/src/unittest/unittest.cc
+++ b/src/unittest/unittest.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */

 #include "unittest/unittest.hh"
diff --git a/src/unittest/unittest.hh b/src/unittest/unittest.hh
index 2e614f1..5e9c432 100644
--- a/src/unittest/unittest.hh
+++ b/src/unittest/unittest.hh
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */

 /**

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id4c7f5ddb932e427cb42d0698b1a048377d027c2
Gerrit-Change-Number: 25409
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Tr

[gem5-dev] Change in gem5/gem5[develop]: scons: Remove authors from the main SConsctruct/SConscript files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25412 )


Change subject: scons: Remove authors from the main SConsctruct/SConscript  
files.

..

scons: Remove authors from the main SConsctruct/SConscript files.

Change-Id: I48987ea4d829e722caf16126dd82f2c580e7836a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25412
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M SConstruct
M src/SConscript
2 files changed, 0 insertions(+), 5 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index d8158fa..6a45752 100755
--- a/SConstruct
+++ b/SConstruct
@@ -39,9 +39,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-#  Nathan Binkert

 ###
 #
diff --git a/src/SConscript b/src/SConscript
index 3ffaeef..fc9df2c 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -36,8 +36,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 from __future__ import print_function


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I48987ea4d829e722caf16126dd82f2c580e7836a
Gerrit-Change-Number: 25412
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: kern: Delete authors lists from files in kern.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25413 )


Change subject: kern: Delete authors lists from files in kern.
..

kern: Delete authors lists from files in kern.

Change-Id: Ic82d0172b61b5b84241edf1112148d7383aade97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25413
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/kern/SConscript
M src/kern/kernel_stats.cc
M src/kern/kernel_stats.hh
M src/kern/linux/events.cc
M src/kern/linux/events.hh
M src/kern/linux/flag_tables.hh
M src/kern/linux/helpers.cc
M src/kern/linux/helpers.hh
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
M src/kern/linux/printk.cc
M src/kern/linux/printk.hh
M src/kern/operatingsystem.cc
M src/kern/operatingsystem.hh
M src/kern/solaris/solaris.hh
M src/kern/system_events.cc
M src/kern/system_events.hh
17 files changed, 0 insertions(+), 43 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/kern/SConscript b/src/kern/SConscript
index d079cbe..9c549a1 100644
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt

 Import('*')

diff --git a/src/kern/kernel_stats.cc b/src/kern/kernel_stats.cc
index 2d1d4fa..4a70b04 100644
--- a/src/kern/kernel_stats.cc
+++ b/src/kern/kernel_stats.cc
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- *  Nathan Binkert
  */

 #include 
diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh
index 37dbb9f..0efcccb 100644
--- a/src/kern/kernel_stats.hh
+++ b/src/kern/kernel_stats.hh
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- *  Nathan Binkert
  */

 #ifndef __KERNEL_STATS_HH__
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index f4e6944..199dfc6 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -36,9 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
  */

 #include "kern/linux/events.hh"
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index d4c77bf..ed2df23 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -36,9 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
  */

 #ifndef __KERN_LINUX_EVENTS_HH__
diff --git a/src/kern/linux/flag_tables.hh b/src/kern/linux/flag_tables.hh
index 9e5dfce..44d2507 100644
--- a/src/kern/linux/flag_tables.hh
+++ b/src/kern/linux/flag_tables.hh
@@ -38,8 +38,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
  */

 /*
diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc
index 1973a41..e1174ae 100644
--- a/src/kern/linux/helpers.cc
+++ b/src/kern/linux/helpers.cc
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 #include "kern/linux/helpers.hh"
diff --git a/src/kern/linux/helpers.hh b/src/kern/linux/helpers.hh
index cebda7d..34a0993 100644
--- a/src/kern/linux/helpers.hh
+++ b/src/kern/linux/helpers.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 #ifndef __KERN_LINUX_HELPERS_HH__
diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc
index e499776..1a8c241 100644
--- a/src/kern/linux/linu

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Delete authors lists from gpu-compute files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25414 )


Change subject: gpu-compute: Delete authors lists from gpu-compute files.
..

gpu-compute: Delete authors lists from gpu-compute files.

Change-Id: I72318eb885f9517de325ea9a9af263f36613bf6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25414
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/gpu-compute/GPUStaticInstFlags.py
M src/gpu-compute/LdsState.py
M src/gpu-compute/SConscript
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/cl_event.hh
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/exec_stage.cc
M src/gpu-compute/exec_stage.hh
M src/gpu-compute/fetch_stage.cc
M src/gpu-compute/fetch_stage.hh
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_static_inst.cc
M src/gpu-compute/gpu_static_inst.hh
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/lds_state.cc
M src/gpu-compute/lds_state.hh
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.hh
M src/gpu-compute/misc.hh
M src/gpu-compute/of_scheduling_policy.hh
M src/gpu-compute/pool_manager.cc
M src/gpu-compute/pool_manager.hh
M src/gpu-compute/rr_scheduling_policy.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/schedule_stage.hh
M src/gpu-compute/scheduler.cc
M src/gpu-compute/scheduler.hh
M src/gpu-compute/scheduling_policy.hh
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/simple_pool_manager.cc
M src/gpu-compute/simple_pool_manager.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/gpu-compute/vector_register_file.cc
M src/gpu-compute/vector_register_file.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
49 files changed, 0 insertions(+), 129 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/GPUStaticInstFlags.py  
b/src/gpu-compute/GPUStaticInstFlags.py

index 453fdce..e12db71 100644
--- a/src/gpu-compute/GPUStaticInstFlags.py
+++ b/src/gpu-compute/GPUStaticInstFlags.py
@@ -28,8 +28,6 @@
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Anthony Gutierrez

 from m5.params import *

diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index a21bde0..2cf8c3a 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -28,8 +28,6 @@
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Joe Gross

 from m5.defines import buildEnv
 from m5.params import *
diff --git a/src/gpu-compute/SConscript b/src/gpu-compute/SConscript
index 23d7fd6..b0ffebf 100644
--- a/src/gpu-compute/SConscript
+++ b/src/gpu-compute/SConscript
@@ -30,8 +30,6 @@
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Anthony Gutierrez

 Import('*')

diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index a0ac9e9..701743d 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -28,8 +28,6 @@
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Lisa Hsu

 from m5.defines import buildEnv
 from m5.params import *
diff --git a/src/gpu-compute/cl_event.hh b/src/gpu-compute/cl_event.hh
index 75297a2..9722600 100644
--- a/src/gpu-compute/cl_event.hh
+++ b/src/gpu-compute/cl_event.hh
@@ -29,8 +29,6 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

  * POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Marc Orr
  */

 #ifndef __GPU_CL_EVENT_HH__
diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index a9571ee..a15c24c 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -29,9 +29,6 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE

[gem5-dev] Change in gem5/gem5[develop]: misc: Delete authors lists from top level .md files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25417 )


Change subject: misc: Delete authors lists from top level .md files.
..

misc: Delete authors lists from top level .md files.

Change-Id: Iefa9d6bd3ce0212bb3eb6101a73aeca737df2c1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25417
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M CONTRIBUTING.md
M TESTING.md
2 files changed, 0 insertions(+), 8 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index 08619cb..6afbeac 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -1,8 +1,3 @@
-Authors: Jason Lowe-Power
- Andreas Sandberg
- Steve Reinhardt
- Bobby R. Bruce
-
 If you've made changes to gem5 that might benefit others, we strongly  
encourage

 you to contribute those changes to the public gem5 repository. There are
 several reasons to do this:
diff --git a/TESTING.md b/TESTING.md
index 6670621..17aeff9 100644
--- a/TESTING.md
+++ b/TESTING.md
@@ -1,6 +1,3 @@
-:Authors: Jason Lowe-Power
-  Sean Wilson
-
 This file explains how to use gem5's updated testing infrastructure.  
Running
 tests before submitting a patch is *incredibly important* so unexpected  
bugs

 don't creep into gem5.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25417
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iefa9d6bd3ce0212bb3eb6101a73aeca737df2c1a
Gerrit-Change-Number: 25417
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[develop]: config: Delete authors lists from config files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25416 )


Change subject: config: Delete authors lists from config files.
..

config: Delete authors lists from config files.

Change-Id: I049f2e97ad00d76341c2aeeaa02279862a8a4d71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25416
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/FileSystemConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/GPUTLBOptions.py
M configs/common/HMC.py
M configs/common/MemConfig.py
M configs/common/ObjectList.py
M configs/common/Options.py
M configs/common/SimpleOpts.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/common/__init__.py
M configs/common/cores/__init__.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/__init__.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dist/sw.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/dist_bigLITTLE.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/sc_main.py
M configs/example/se.py
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/learning_gem5/part3/test_caches.py
M configs/network/Network.py
M configs/network/__init__.py
M configs/ruby/AMD_Base_Constructor.py
M configs/ruby/CntrlBase.py
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/Ruby.py
M configs/ruby/__init__.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M configs/topologies/BaseTopology.py
M configs/topologies/Cluster.py
M configs/topologies/Crossbar.py
M configs/topologies/CrossbarGarnet.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
M configs/topologies/Mesh_westfirst.py
M configs/topologies/Pt2Pt.py
M configs/topologies/__init__.py
86 files changed, 1 insertion(+), 204 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 2961eeb..5d73fc3 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi

 from __future__ import print_function
 from __future__ import absolute_import
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 98d0adf..ff2f0da 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -35,8 +35,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Lisa Hsu

 # Configure the M5 cache hierarchy config in one place
 #
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index f8edc8b..123fea4 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -35,8 +35,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D

[gem5-dev] Change in gem5/gem5[develop]: base: Delete authors lists from files in base.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25415 )


Change subject: base: Delete authors lists from files in base.
..

base: Delete authors lists from files in base.

Change-Id: I73020efd522489ee152af890ab5e03449bc0a900
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25415
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/base/Graphics.py
M src/base/SConscript
M src/base/addr_range.hh
M src/base/addr_range.test.cc
M src/base/addr_range_map.hh
M src/base/addr_range_map.test.cc
M src/base/amo.hh
M src/base/atomicio.cc
M src/base/atomicio.hh
M src/base/atomicio.test.cc
M src/base/barrier.hh
M src/base/bitfield.cc
M src/base/bitfield.hh
M src/base/bitfield.test.cc
M src/base/bitunion.hh
M src/base/bitunion.test.cc
M src/base/bmpwriter.cc
M src/base/bmpwriter.hh
M src/base/callback.cc
M src/base/callback.hh
M src/base/callback.test.cc
M src/base/cast.hh
M src/base/channel_addr.cc
M src/base/channel_addr.hh
M src/base/channel_addr.test.cc
M src/base/chunk_generator.hh
M src/base/chunk_generator.test.cc
M src/base/circlebuf.hh
M src/base/circlebuf.test.cc
M src/base/circular_queue.hh
M src/base/circular_queue.test.cc
M src/base/compiler.hh
M src/base/condcodes.hh
M src/base/condcodes.test.cc
M src/base/coroutine.hh
M src/base/coroutine.test.cc
M src/base/cp_annotate.cc
M src/base/cp_annotate.hh
M src/base/cprintf.cc
M src/base/cprintf.hh
M src/base/cprintf.test.cc
M src/base/cprintf_formats.hh
M src/base/crc.hh
M src/base/date.cc
M src/base/debug.cc
M src/base/debug.hh
M src/base/fenv.c
M src/base/fenv.hh
M src/base/fiber.cc
M src/base/fiber.hh
M src/base/fiber.test.cc
M src/base/filters/BloomFilters.py
M src/base/filters/SConscript
M src/base/filters/base.hh
M src/base/filters/block_bloom_filter.cc
M src/base/filters/block_bloom_filter.hh
M src/base/filters/bulk_bloom_filter.cc
M src/base/filters/bulk_bloom_filter.hh
M src/base/filters/h3_bloom_filter.cc
M src/base/filters/h3_bloom_filter.hh
M src/base/filters/multi_bit_sel_bloom_filter.cc
M src/base/filters/multi_bit_sel_bloom_filter.hh
M src/base/filters/multi_bloom_filter.cc
M src/base/filters/multi_bloom_filter.hh
M src/base/filters/perfect_bloom_filter.cc
M src/base/filters/perfect_bloom_filter.hh
M src/base/flags.hh
M src/base/framebuffer.cc
M src/base/framebuffer.hh
M src/base/hostinfo.cc
M src/base/hostinfo.hh
M src/base/imgwriter.cc
M src/base/imgwriter.hh
M src/base/inet.cc
M src/base/inet.hh
M src/base/inifile.cc
M src/base/inifile.hh
M src/base/inifile.test.cc
M src/base/intmath.hh
M src/base/intmath.test.cc
M src/base/loader/dtb_file.cc
M src/base/loader/dtb_file.hh
M src/base/loader/elf_object.cc
M src/base/loader/elf_object.hh
M src/base/loader/image_file.hh
M src/base/loader/image_file_data.cc
M src/base/loader/image_file_data.hh
M src/base/loader/image_file_data.test.cc
M src/base/loader/memory_image.cc
M src/base/loader/memory_image.hh
M src/base/loader/object_file.cc
M src/base/loader/object_file.hh
M src/base/loader/raw_image.hh
M src/base/loader/small_image_file.test.hh
M src/base/loader/symtab.cc
M src/base/loader/symtab.hh
M src/base/logging.cc
M src/base/logging.hh
M src/base/match.cc
M src/base/match.hh
M src/base/match.test.cc
M src/base/output.cc
M src/base/output.hh
M src/base/pixel.cc
M src/base/pixel.hh
M src/base/pixel.test.cc
M src/base/pngwriter.cc
M src/base/pngwriter.hh
M src/base/pollevent.cc
M src/base/pollevent.hh
M src/base/random.cc
M src/base/random.hh
M src/base/refcnt.hh
M src/base/refcnt.test.cc
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/base/sat_counter.hh
M src/base/sat_counter.test.cc
M src/base/socket.cc
M src/base/socket.hh
M src/base/socket.test.cc
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/base/stats/hdf5.cc
M src/base/stats/hdf5.hh
M src/base/stats/info.hh
M src/base/stats/output.hh
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/base/stats/types.hh
M src/base/stl_helpers.hh
M src/base/str.cc
M src/base/str.hh
M src/base/str.test.cc
M src/base/time.cc
M src/base/time.hh
M src/base/trace.cc
M src/base/trace.hh
M src/base/trie.hh
M src/base/trie.test.cc
M src/base/types.cc
M src/base/types.hh
M src/base/types.test.cc
M src/base/vnc/SConscript
M src/base/vnc/Vnc.py
M src/base/vnc/vncinput.cc
M src/base/vnc/vncinput.hh
M src/base/vnc/vncserver.cc
M src/base/vnc/vncserver.hh
151 files changed, 8 insertions(+), 376 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/Graphics.py b/src/base/Graphics.py
index c42882e..c444bb9 100644
--- a/src/base/Graphics.py
+++ b/src/base/Graphics.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS S

[gem5-dev] Change in gem5/gem5[develop]: arch: Delete authors lists from generic arch files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25445 )



Change subject: arch: Delete authors lists from generic arch files.
..

arch: Delete authors lists from generic arch files.

Change-Id: I831a0f1876845f37ab12a2448e898719e74a0b55
---
M src/arch/SConscript
M src/arch/generic/BaseISA.py
M src/arch/generic/BaseInterrupts.py
M src/arch/generic/BaseTLB.py
M src/arch/generic/ISACommon.py
M src/arch/generic/SConscript
M src/arch/generic/debugfaults.hh
M src/arch/generic/decode_cache.cc
M src/arch/generic/decode_cache.hh
M src/arch/generic/interrupts.hh
M src/arch/generic/isa.hh
M src/arch/generic/linux/threadinfo.hh
M src/arch/generic/locked_mem.hh
M src/arch/generic/memhelpers.hh
M src/arch/generic/pseudo_inst.cc
M src/arch/generic/pseudo_inst.hh
M src/arch/generic/tlb.hh
M src/arch/generic/traits.hh
M src/arch/generic/types.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/isa_parser.py
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
24 files changed, 0 insertions(+), 55 deletions(-)



diff --git a/src/arch/SConscript b/src/arch/SConscript
index 0661db7..1b68f3f 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -37,8 +37,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt

 import sys
 import os
diff --git a/src/arch/generic/BaseISA.py b/src/arch/generic/BaseISA.py
index f50819b..2cc2c45 100644
--- a/src/arch/generic/BaseISA.py
+++ b/src/arch/generic/BaseISA.py
@@ -22,8 +22,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/arch/generic/BaseInterrupts.py  
b/src/arch/generic/BaseInterrupts.py

index b373d80..a5b7ad5 100644
--- a/src/arch/generic/BaseInterrupts.py
+++ b/src/arch/generic/BaseInterrupts.py
@@ -22,8 +22,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 64531b9..02776e6 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -24,9 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-#  Ivan Pizarro

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/arch/generic/ISACommon.py b/src/arch/generic/ISACommon.py
index dc2..88f9ccd 100644
--- a/src/arch/generic/ISACommon.py
+++ b/src/arch/generic/ISACommon.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Rekai Gonzalez

 from m5.params import *
 from m5.proxy import *
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index ec46b07..e3c2567 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -35,8 +35,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 Import('*')

diff --git a/src/arch/generic/debugfaults.hh  
b/src/arch/generic/debugfaults.hh

index 1c8d882..7d62d3f 100644
--- a/src/arch/generic/debugfaults.hh
+++ b/src/arch/generic/debugfaults.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */

 #ifndef __ARCH_GENERIC_DEBUGFAULTS_HH__
diff --git a/src/arch/generic/decode_cache.cc  
b/src/arch/generic/decode_cache.cc

index 0f7a9d9..341cb70 100644
--- a/src/arch/generic/decode_cache.cc
+++ b/src/arch/generic/decode_cache.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:

[gem5-dev] Change in gem5/gem5[develop]: tests: Delete authors lists from test files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25454 )



Change subject: tests: Delete authors lists from test files.
..

tests: Delete authors lists from test files.

Change-Id: Id3628d34adccf8cc1044195b7209f3b01f061c93
---
M tests/SConscript
M tests/configs/alpha_generic.py
M tests/configs/arm_generic.py
M tests/configs/base_config.py
M tests/configs/checkpoint.py
M tests/configs/dram-lowp.py
M tests/configs/learning-gem5-p1-simple.py
M tests/configs/learning-gem5-p1-two-level.py
M tests/configs/memcheck.py
M tests/configs/memtest-filter.py
M tests/configs/memtest-ruby.py
M tests/configs/memtest.py
M tests/configs/minor-timing-mp.py
M tests/configs/minor-timing.py
M tests/configs/o3-timing-checker.py
M tests/configs/o3-timing-mp-ruby.py
M tests/configs/o3-timing-mp.py
M tests/configs/o3-timing-mt.py
M tests/configs/o3-timing-ruby.py
M tests/configs/o3-timing.py
M tests/configs/pc-o3-timing.py
M tests/configs/pc-simple-atomic.py
M tests/configs/pc-simple-timing-ruby.py
M tests/configs/pc-simple-timing.py
M tests/configs/pc-switcheroo-full.py
M tests/configs/realview-minor-dual.py
M tests/configs/realview-minor.py
M tests/configs/realview-o3-checker.py
M tests/configs/realview-o3-dual.py
M tests/configs/realview-o3.py
M tests/configs/realview-simple-atomic-checkpoint.py
M tests/configs/realview-simple-atomic-dual.py
M tests/configs/realview-simple-atomic.py
M tests/configs/realview-simple-timing-dual-ruby.py
M tests/configs/realview-simple-timing-dual.py
M tests/configs/realview-simple-timing-ruby.py
M tests/configs/realview-simple-timing.py
M tests/configs/realview-switcheroo-atomic.py
M tests/configs/realview-switcheroo-full.py
M tests/configs/realview-switcheroo-noncaching-timing.py
M tests/configs/realview-switcheroo-o3.py
M tests/configs/realview-switcheroo-timing.py
M tests/configs/realview64-minor-dual.py
M tests/configs/realview64-minor.py
M tests/configs/realview64-o3-checker.py
M tests/configs/realview64-o3-dual.py
M tests/configs/realview64-o3.py
M tests/configs/realview64-simple-atomic-checkpoint.py
M tests/configs/realview64-simple-atomic-dual.py
M tests/configs/realview64-simple-atomic.py
M tests/configs/realview64-simple-timing-dual-ruby.py
M tests/configs/realview64-simple-timing-dual.py
M tests/configs/realview64-simple-timing-ruby.py
M tests/configs/realview64-simple-timing.py
M tests/configs/realview64-switcheroo-atomic.py
M tests/configs/realview64-switcheroo-full.py
M tests/configs/realview64-switcheroo-o3.py
M tests/configs/realview64-switcheroo-timing.py
M tests/configs/rubytest-ruby.py
M tests/configs/simple-atomic-dummychecker.py
M tests/configs/simple-atomic-mp-ruby.py
M tests/configs/simple-atomic-mp.py
M tests/configs/simple-atomic.py
M tests/configs/simple-timing-mp-ruby.py
M tests/configs/simple-timing-mp.py
M tests/configs/simple-timing-ruby.py
M tests/configs/simple-timing.py
M tests/configs/switcheroo.py
M tests/configs/t1000-simple-atomic.py
M tests/configs/tgen-dram-ctrl.py
M tests/configs/tgen-simple-mem.py
M tests/configs/tsunami-minor-dual.py
M tests/configs/tsunami-minor.py
M tests/configs/tsunami-o3-dual.py
M tests/configs/tsunami-o3.py
M tests/configs/tsunami-simple-atomic-dual.py
M tests/configs/tsunami-simple-atomic.py
M tests/configs/tsunami-simple-timing-dual.py
M tests/configs/tsunami-simple-timing.py
M tests/configs/tsunami-switcheroo-full.py
M tests/configs/twosys-tsunami-simple-atomic.py
M tests/configs/x86_generic.py
M tests/diff-out
M tests/gem5/__init__.py
M tests/gem5/cpu_tests/run.py
M tests/gem5/cpu_tests/test.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/fs/linux/arm/test.py
M tests/gem5/hello_se/test_hello_se.py
M tests/gem5/learning_gem5/part1_test.py
M tests/gem5/learning_gem5/part2_test.py
M tests/gem5/learning_gem5/part3_test.py
M tests/gem5/m5_util/test_exit.py
M tests/gem5/memory/memtest-run.py
M tests/gem5/memory/simple-run.py
M tests/gem5/memory/test.py
M tests/gem5/suite.py
M tests/gem5/test_build/test_build.py
M tests/gem5/verifier.py
M tests/jenkins/presubmit.sh
M tests/legacy-configs/run.py
M tests/long/fs/10.linux-boot/test.py
M tests/long/fs/80.solaris-boot/test.py
M tests/long/se/10.mcf/test.py
M tests/long/se/70.twolf/test.py
M tests/quick/fs/10.linux-boot/test.py
M tests/quick/fs/80.netperf-stream/test.py
M tests/quick/se/00.hello.mp/test.py
M tests/quick/se/01.hello-2T-smt/test.py
M tests/quick/se/02.insttest/test.py
M tests/quick/se/30.eon/test.py
M tests/quick/se/50.memtest/test.py
M tests/quick/se/50.vortex/test.py
M tests/quick/se/51.memcheck/test.py
M tests/quick/se/60.rubytest/test.py
M tests/quick/se/70.tgen/test.py
M tests/quick/se/80.dram-closepage/test.py
M tests/quick/se/80.dram-openpage/test.py
M tests/run.py
M tests/test-progs/asmtest/src/riscv/isa/macros/mt/test_macros_mt.h
M tests/test-progs/asmtest/src/riscv/isa/macros/mt/test_macros_mt_ecall.h
M tests/test-progs/as

[gem5-dev] Change in gem5/gem5[develop]: arch: Delete authors lists from the null arch files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25446 )



Change subject: arch: Delete authors lists from the null arch files.
..

arch: Delete authors lists from the null arch files.

Change-Id: Ief42708d8961a5c33db5e8a603ee8fff8df8b198
---
M src/arch/null/SConscript
M src/arch/null/SConsopts
M src/arch/null/cpu_dummy.cc
M src/arch/null/cpu_dummy.hh
M src/arch/null/isa_traits.hh
M src/arch/null/locked_mem.hh
M src/arch/null/registers.hh
M src/arch/null/remote_gdb.hh
M src/arch/null/types.hh
M src/arch/null/utility.hh
10 files changed, 0 insertions(+), 20 deletions(-)



diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index e64b69c..41457e2 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -34,8 +34,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 Import('*')

diff --git a/src/arch/null/SConsopts b/src/arch/null/SConsopts
index e377564..a799754 100644
--- a/src/arch/null/SConsopts
+++ b/src/arch/null/SConsopts
@@ -34,8 +34,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 Import('*')

diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
index 4c78bf7..df30b81 100644
--- a/src/arch/null/cpu_dummy.cc
+++ b/src/arch/null/cpu_dummy.cc
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 /**
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
index 6f6311b..7e183eb 100644
--- a/src/arch/null/cpu_dummy.hh
+++ b/src/arch/null/cpu_dummy.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_CPU_DUMMY_HH__
diff --git a/src/arch/null/isa_traits.hh b/src/arch/null/isa_traits.hh
index d15f83c..6a9c2ea 100644
--- a/src/arch/null/isa_traits.hh
+++ b/src/arch/null/isa_traits.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_ISA_TRAITS_HH__
diff --git a/src/arch/null/locked_mem.hh b/src/arch/null/locked_mem.hh
index f5ecaf7..e1e9cde 100644
--- a/src/arch/null/locked_mem.hh
+++ b/src/arch/null/locked_mem.hh
@@ -36,8 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
  */

 #ifndef __ARCH_NULL_LOCKED_MEM_HH__
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 0ad0ea4..db02afc 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_REGISTERS_HH__
diff --git a/src/arch/null/remote_gdb.hh b/src/arch/null/remote_gdb.hh
index dddebce..4df9cc8 100644
--- a/src/arch/null/remote_gdb.hh
+++ b/src/arch/null/remote_gdb.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_REMOTE_GDB_HH__
diff --git a/src/arch/null/types.hh b/src/arch/null/types.hh
index b62b8f2..3fa7479 100644
--- a/src/arch/null/types.hh
+++ b/src/arch/null/types.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_TYPES_HH__
diff --git a/src/arch/null/utility.hh b/src/arch/null/utility.hh
index f1e347d..82b9be6 100644
--- a/src/arch/null/utility

[gem5-dev] Change in gem5/gem5[develop]: power: Delete the authors lists from the power ISA.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25450 )



Change subject: power: Delete the authors lists from the power ISA.
..

power: Delete the authors lists from the power ISA.

Change-Id: Ib661723a9fcc09dd6e1e68a7c38a99e6d404dc46
---
M src/arch/power/PowerISA.py
M src/arch/power/PowerInterrupts.py
M src/arch/power/PowerTLB.py
M src/arch/power/SConscript
M src/arch/power/SConsopts
M src/arch/power/decoder.cc
M src/arch/power/decoder.hh
M src/arch/power/faults.hh
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/insts/condition.cc
M src/arch/power/insts/condition.hh
M src/arch/power/insts/floating.cc
M src/arch/power/insts/floating.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
M src/arch/power/insts/misc.cc
M src/arch/power/insts/misc.hh
M src/arch/power/insts/static_inst.cc
M src/arch/power/insts/static_inst.hh
M src/arch/power/interrupts.cc
M src/arch/power/interrupts.hh
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/basic.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/condition.isa
M src/arch/power/isa/formats/formats.isa
M src/arch/power/isa/formats/fp.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/misc.isa
M src/arch/power/isa/formats/unimp.isa
M src/arch/power/isa/formats/unknown.isa
M src/arch/power/isa/formats/util.isa
M src/arch/power/isa/includes.isa
M src/arch/power/isa/main.isa
M src/arch/power/isa/operands.isa
M src/arch/power/isa_traits.hh
M src/arch/power/kernel_stats.hh
M src/arch/power/linux/linux.cc
M src/arch/power/linux/linux.hh
M src/arch/power/linux/process.cc
M src/arch/power/linux/process.hh
M src/arch/power/locked_mem.hh
M src/arch/power/microcode_rom.hh
M src/arch/power/miscregs.hh
M src/arch/power/mmapped_ipr.hh
M src/arch/power/pagetable.cc
M src/arch/power/pagetable.hh
M src/arch/power/process.cc
M src/arch/power/process.hh
M src/arch/power/pseudo_inst.hh
M src/arch/power/registers.hh
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
M src/arch/power/stacktrace.cc
M src/arch/power/stacktrace.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/power/types.hh
M src/arch/power/utility.cc
M src/arch/power/utility.hh
M src/arch/power/vtophys.cc
M src/arch/power/vtophys.hh
69 files changed, 0 insertions(+), 187 deletions(-)



diff --git a/src/arch/power/PowerISA.py b/src/arch/power/PowerISA.py
index 82efb9a..81abd9c 100644
--- a/src/arch/power/PowerISA.py
+++ b/src/arch/power/PowerISA.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 from m5.objects.BaseISA import BaseISA

diff --git a/src/arch/power/PowerInterrupts.py  
b/src/arch/power/PowerInterrupts.py

index f7e7e57..443e7ae 100644
--- a/src/arch/power/PowerInterrupts.py
+++ b/src/arch/power/PowerInterrupts.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.objects.BaseInterrupts import BaseInterrupts

diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index 5c582b4..7f9a271 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Timothy M. Jones

 from m5.SimObject import SimObject
 from m5.params import *
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 473c312..b4878fd 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Timothy M. Jones

 Import('*')

diff --git a/src/arch/power/SConsopts b/src/arch/power/SConsopts
index d762c2d..851f2ba 100644
--- a/src/arch/power/SConsopts
+++ b/src/arch/power/SConsopts
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Timothy M. Jones

 Import('

[gem5-dev] Change in gem5/gem5[develop]: hsail: Delete the author list from gpu_isa.hh.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25448 )



Change subject: hsail: Delete the author list from gpu_isa.hh.
..

hsail: Delete the author list from gpu_isa.hh.

Change-Id: I9c90fef4420286dbda7157d8961b4cf3c79a7c27
---
M src/arch/hsail/gpu_isa.hh
1 file changed, 0 insertions(+), 2 deletions(-)



diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh
index 86af905..75063cb 100644
--- a/src/arch/hsail/gpu_isa.hh
+++ b/src/arch/hsail/gpu_isa.hh
@@ -29,8 +29,6 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

  * POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Anthony Gutierrez
  */

 #ifndef __ARCH_HSAIL_GPU_ISA_HH__

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25448
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9c90fef4420286dbda7157d8961b4cf3c79a7c27
Gerrit-Change-Number: 25448
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
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[gem5-dev] Change in gem5/gem5[develop]: mips: Delete authors lists from mips files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25449 )



Change subject: mips: Delete authors lists from mips files.
..

mips: Delete authors lists from mips files.

Change-Id: I56c054c64fe3d1e39ed5d315b8ac78de2e993dc5
---
M src/arch/mips/MipsISA.py
M src/arch/mips/MipsInterrupts.py
M src/arch/mips/MipsSystem.py
M src/arch/mips/MipsTLB.py
M src/arch/mips/SConscript
M src/arch/mips/SConsopts
M src/arch/mips/bare_iron/system.cc
M src/arch/mips/bare_iron/system.hh
M src/arch/mips/decoder.cc
M src/arch/mips/decoder.hh
M src/arch/mips/dsp.cc
M src/arch/mips/dsp.hh
M src/arch/mips/dt_constants.hh
M src/arch/mips/faults.cc
M src/arch/mips/faults.hh
M src/arch/mips/idle_event.cc
M src/arch/mips/idle_event.hh
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/isa/base.isa
M src/arch/mips/isa/bitfields.isa
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/basic.isa
M src/arch/mips/isa/formats/branch.isa
M src/arch/mips/isa/formats/control.isa
M src/arch/mips/isa/formats/dsp.isa
M src/arch/mips/isa/formats/formats.isa
M src/arch/mips/isa/formats/fp.isa
M src/arch/mips/isa/formats/int.isa
M src/arch/mips/isa/formats/mem.isa
M src/arch/mips/isa/formats/mt.isa
M src/arch/mips/isa/formats/noop.isa
M src/arch/mips/isa/formats/tlbop.isa
M src/arch/mips/isa/formats/trap.isa
M src/arch/mips/isa/formats/unimp.isa
M src/arch/mips/isa/formats/unknown.isa
M src/arch/mips/isa/formats/util.isa
M src/arch/mips/isa/includes.isa
M src/arch/mips/isa/main.isa
M src/arch/mips/isa/operands.isa
M src/arch/mips/isa_traits.hh
M src/arch/mips/kernel_stats.hh
M src/arch/mips/linux/aligned.hh
M src/arch/mips/linux/linux.cc
M src/arch/mips/linux/linux.hh
M src/arch/mips/linux/process.cc
M src/arch/mips/linux/process.hh
M src/arch/mips/linux/system.cc
M src/arch/mips/linux/system.hh
M src/arch/mips/linux/thread_info.hh
M src/arch/mips/locked_mem.hh
M src/arch/mips/microcode_rom.hh
M src/arch/mips/mmapped_ipr.hh
M src/arch/mips/mt.hh
M src/arch/mips/mt_constants.hh
M src/arch/mips/pagetable.cc
M src/arch/mips/pagetable.hh
M src/arch/mips/pra_constants.hh
M src/arch/mips/process.cc
M src/arch/mips/process.hh
M src/arch/mips/pseudo_inst.hh
M src/arch/mips/registers.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/mips/stacktrace.cc
M src/arch/mips/stacktrace.hh
M src/arch/mips/system.cc
M src/arch/mips/system.hh
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/mips/types.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
M src/arch/mips/vtophys.cc
M src/arch/mips/vtophys.hh
77 files changed, 0 insertions(+), 221 deletions(-)



diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index 180d9e6..5194e18 100644
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 from m5.params import *
 from m5.proxy import *
diff --git a/src/arch/mips/MipsInterrupts.py  
b/src/arch/mips/MipsInterrupts.py

index 1065701..fdd7fc7 100644
--- a/src/arch/mips/MipsInterrupts.py
+++ b/src/arch/mips/MipsInterrupts.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.objects.BaseInterrupts import BaseInterrupts

diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index 7a5d8fd..fefc582 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jaidev Patwardhan

 from m5.defines import buildEnv
 from m5.params import *
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 62996cc..d43b6d7 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jaidev Patwardhan
-#  Korey Sewell

 from m5.SimObject import SimObject
 from m5.params import *
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index d30c28d..0e69778 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -25,10 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

[gem5-dev] Change in gem5/gem5[develop]: tests: Delete some test files which are specific to Alpha.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25458 )



Change subject: tests: Delete some test files which are specific to Alpha.
..

tests: Delete some test files which are specific to Alpha.

Change-Id: Idbffab70abdbb59817c6e002e26b8cb0fa96a4e2
---
D tests/configs/alpha_generic.py
D tests/configs/tsunami-minor-dual.py
D tests/configs/tsunami-minor.py
D tests/configs/tsunami-o3-dual.py
D tests/configs/tsunami-o3.py
D tests/configs/tsunami-simple-atomic-dual.py
D tests/configs/tsunami-simple-atomic.py
D tests/configs/tsunami-simple-timing-dual.py
D tests/configs/tsunami-simple-timing.py
D tests/configs/tsunami-switcheroo-full.py
D tests/configs/twosys-tsunami-simple-atomic.py
D tests/test-progs/hello/bin/alpha/linux/hello
12 files changed, 0 insertions(+), 581 deletions(-)



diff --git a/tests/configs/alpha_generic.py b/tests/configs/alpha_generic.py
deleted file mode 100644
index 0cef339..000
--- a/tests/configs/alpha_generic.py
+++ /dev/null
@@ -1,99 +0,0 @@
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import ABCMeta, abstractmethod
-import m5
-from m5.objects import *
-from m5.proxy import *
-m5.util.addToPath('../configs/')
-from common import FSConfig, SysPaths
-from common.Caches import *
-from base_config import *
-
-class LinuxAlphaSystemBuilder(object):
-"""Mix-in that implements create_system.
-
-This mix-in is intended as a convenient way of adding an
-Alpha-specific create_system method to a class deriving from one of
-the generic base systems.
-"""
-def __init__(self):
-"""
-Arguments:
-  machine_type -- String describing the platform to simulate
-"""
-pass
-
-def create_system(self):
-system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
-system.kernel = SysPaths.binary('vmlinux')
-self.init_system(system)
-return system
-
-class LinuxAlphaFSSystem(LinuxAlphaSystemBuilder,
- BaseFSSystem):
-"""Basic Alpha full system builder."""
-
-def __init__(self, **kwargs):
-"""Initialize an Alpha system that supports full system simulation.
-
-Note: Keyword arguments that are not listed below will be
-passed to the BaseFSSystem.
-
-Keyword Arguments:
-  -
-"""
-BaseSystem.__init__(self, **kwargs)
-LinuxAlphaSystemBuilder.__init__(self)
-
-class LinuxAlphaFSSystemUniprocessor(LinuxAlphaSystemBuilder,
- BaseFSSystemUniprocessor):
-"""Basic Alpha full system builder for uniprocessor systems.
-
-Note: This class is a specialization of the AlphaFSSystem and is
-only really needed to provide backwards compatibility for existing
-test cases.
-"""
-
-def __init__(self, **kwargs):
-BaseFSSyste

[gem5-dev] Change in gem5/gem5[develop]: riscv: Delete authors lists from riscv files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25451 )



Change subject: riscv: Delete authors lists from riscv files.
..

riscv: Delete authors lists from riscv files.

Change-Id: I94135c8f0e1baee741d6470cb80b4da5e5f8e673
---
M src/arch/riscv/RiscvISA.py
M src/arch/riscv/RiscvInterrupts.py
M src/arch/riscv/RiscvSystem.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/SConsopts
M src/arch/riscv/bare_metal/system.cc
M src/arch/riscv/bare_metal/system.hh
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/idle_event.cc
M src/arch/riscv/idle_event.hh
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/amo.cc
M src/arch/riscv/insts/amo.hh
M src/arch/riscv/insts/compressed.cc
M src/arch/riscv/insts/compressed.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/mem.hh
M src/arch/riscv/insts/standard.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/static_inst.cc
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/insts/unknown.hh
M src/arch/riscv/interrupts.cc
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/main.isa
M src/arch/riscv/isa/operands.isa
M src/arch/riscv/isa_traits.hh
M src/arch/riscv/kernel_stats.hh
M src/arch/riscv/linux/linux.cc
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/process.cc
M src/arch/riscv/linux/process.hh
M src/arch/riscv/locked_mem.hh
M src/arch/riscv/microcode_rom.hh
M src/arch/riscv/mmapped_ipr.hh
M src/arch/riscv/pagetable.cc
M src/arch/riscv/pagetable.hh
M src/arch/riscv/pra_constants.hh
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M src/arch/riscv/pseudo_inst.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
M src/arch/riscv/stacktrace.cc
M src/arch/riscv/stacktrace.hh
M src/arch/riscv/system.cc
M src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/riscv/types.hh
M src/arch/riscv/utility.hh
M src/arch/riscv/vtophys.hh
70 files changed, 12 insertions(+), 227 deletions(-)



diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index dfb42c4..3869174 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -37,10 +37,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg
-#  Sven Karlsson
-#  Alec Roelke

 from m5.objects.BaseISA import BaseISA

diff --git a/src/arch/riscv/RiscvInterrupts.py  
b/src/arch/riscv/RiscvInterrupts.py

index 7e63ded..c3ad370 100644
--- a/src/arch/riscv/RiscvInterrupts.py
+++ b/src/arch/riscv/RiscvInterrupts.py
@@ -26,10 +26,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-#  Sven Karlsson
-#  Alec Roelke

 from m5.objects.BaseInterrupts import BaseInterrupts

diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index ea1defd..7be9ff9 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -26,9 +26,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Alec Roelke
-#  Robert Scheffel

 from m5.params import *

diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index b24fffb..4bcaf67 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jaidev Patwardhan
-#  Korey Sewell

 from m5.SimObject import SimObject
 from m5.params import *
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 25adb53..21c084b 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -38,10 +38,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T

[gem5-dev] Change in gem5/gem5[develop]: system: Delete authors lists from system source files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25455 )



Change subject: system: Delete authors lists from system source files.
..

system: Delete authors lists from system source files.

Change-Id: I899bd4d04ad1cbf5ab32d57df88e2a146d2e2e4e
---
M system/arm/bootloader/arm/boot.S
M system/arm/bootloader/arm/makefile
M system/arm/dt/Makefile
M system/arm/dt/armv7.dts
M system/arm/dt/armv8.dts
M system/arm/dt/armv8_big_little.dts
M system/arm/dt/platforms/vexpress_gem5_v1.dtsi
M system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
10 files changed, 0 insertions(+), 22 deletions(-)



diff --git a/system/arm/bootloader/arm/boot.S  
b/system/arm/bootloader/arm/boot.S

index 4870ecc..0439eca 100644
--- a/system/arm/bootloader/arm/boot.S
+++ b/system/arm/bootloader/arm/boot.S
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
  */

 /*
diff --git a/system/arm/bootloader/arm/makefile  
b/system/arm/bootloader/arm/makefile

index b6e4f32..e8be5f7 100644
--- a/system/arm/bootloader/arm/makefile
+++ b/system/arm/bootloader/arm/makefile
@@ -32,9 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi
-#  Prakash Ramrakhyani


 # Need to have CROSS_COMPILE set to /path/to/bin/arm-unknown-linux-gnu-
diff --git a/system/arm/dt/Makefile b/system/arm/dt/Makefile
index 1bb6870..fb7ac30 100644
--- a/system/arm/dt/Makefile
+++ b/system/arm/dt/Makefile
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 CPP?=cpp
 DTC?=dtc
diff --git a/system/arm/dt/armv7.dts b/system/arm/dt/armv7.dts
index 96b37ec..adfd968 100644
--- a/system/arm/dt/armv7.dts
+++ b/system/arm/dt/armv7.dts
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 /dts-v1/;
diff --git a/system/arm/dt/armv8.dts b/system/arm/dt/armv8.dts
index e221e6a..a4007b9 100644
--- a/system/arm/dt/armv8.dts
+++ b/system/arm/dt/armv8.dts
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 /dts-v1/;
diff --git a/system/arm/dt/armv8_big_little.dts  
b/system/arm/dt/armv8_big_little.dts

index 347cfe3..63c90ec 100644
--- a/system/arm/dt/armv8_big_little.dts
+++ b/system/arm/dt/armv8_big_little.dts
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- *  Gabor Dozsa
  */

 /dts-v1/;
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi

index d9c3877..91e82c0 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 /include/ "vexpress_gem5_v1_base.dtsi"
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi

index 61a0104..a84e8e3 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 / {
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi

index 9e4ccbd..6c4dddc 100644
---

[gem5-dev] Change in gem5/gem5[develop]: util: Remove ALPHA from the regress script.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25460 )



Change subject: util: Remove ALPHA from the regress script.
..

util: Remove ALPHA from the regress script.

The default architecture will now be ARM.

Change-Id: Ib2bda3d4ce1fc25f1fec1c9f62eeb9b81032017b
---
M util/regress
1 file changed, 1 insertion(+), 2 deletions(-)



diff --git a/util/regress b/util/regress
index 1e89bd1..1f1404c 100755
--- a/util/regress
+++ b/util/regress
@@ -38,7 +38,7 @@
 add_option('-v', '--verbose', action='store_true', default=False,
help='echo commands before executing')
 add_option('--builds',
-   default='ALPHA,' \
+   default='ARM,' \
'MIPS,' \
'NULL,' \
'NULL_MOESI_hammer,' \
@@ -48,7 +48,6 @@
'POWER,' \
'SPARC,' \
'X86,X86_MESI_Two_Level,' \
-   'ARM,' \
'RISCV,' \
'HSAIL_X86',
help="comma-separated build targets to test  
(default: '%default')")


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25460
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2bda3d4ce1fc25f1fec1c9f62eeb9b81032017b
Gerrit-Change-Number: 25460
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
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[gem5-dev] Change in gem5/gem5[develop]: util: Delete authors lists from files in util.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25457 )



Change subject: util: Delete authors lists from files in util.
..

util: Delete authors lists from files in util.

Change-Id: I2a165d3130c1464a73823046e4c7b03ba0355459
---
M util/SConscript
M util/batch/batch.py
M util/batch/job.py
M util/batch/send.py
M util/ccdrv/Makefile
M util/ccdrv/devtime.c
M util/checkpoint_aggregator.py
M util/checktrace.sh
M util/compile
M util/cpt_upgrader.py
M util/cpt_upgraders/arm-gem5-gic-ext.py
M util/cpt_upgraders/arm-hdlcd-upgrade.py
M util/cscope-index.py
M util/cxx_config/Makefile
M util/cxx_config/main.cc
M util/cxx_config/stats.cc
M util/cxx_config/stats.hh
M util/decode_inst_dep_trace.py
M util/decode_inst_trace.py
M util/decode_packet_trace.py
M util/dist/gem5-dist.sh
M util/dist/test/simple_bootscript.rcS
M util/dist/test/test-2nodes-AArch64.sh
M util/emacs/m5-c-style.el
M util/encode_inst_dep_trace.py
M util/encode_packet_trace.py
M util/gen_arm_fs_files.py
M util/git-commit-msg.py
M util/git-pre-commit.py
M util/hgstyle.py
M util/m5/Makefile.aarch64
M util/m5/Makefile.alpha
M util/m5/Makefile.arm
M util/m5/Makefile.sparc
M util/m5/Makefile.thumb
M util/m5/Makefile.x86
M util/m5/jni/gem5Op.java
M util/m5/jni_gem5Op.c
M util/m5/lua_gem5Op.c
M util/m5/m5.c
M util/m5/m5_mmap.c
M util/m5/m5_mmap.h
M util/m5/m5op_alpha.S
M util/m5/m5op_arm.S
M util/m5/m5op_arm_A64.S
M util/m5/m5op_sparc.S
M util/m5/m5op_x86.S
M util/maint/create_patches.sh
M util/maint/list_changes.py
M util/maint/upstream_msg_filter.sed
M util/memtest-soak.py
M util/minorview.py
M util/minorview/__init__.py
M util/minorview/blobs.py
M util/minorview/colours.py
M util/minorview/minor.pic
M util/minorview/model.py
M util/minorview/parse.py
M util/minorview/point.py
M util/minorview/view.py
M util/o3-pipeview.py
M util/oprofile-top.py
M util/pbs/job.py
M util/pbs/pbs.py
M util/pbs/send.py
M util/plot_dram/PlotPowerStates.py
M util/plot_dram/dram_lat_mem_rd_plot.py
M util/plot_dram/dram_sweep_plot.py
M util/plot_dram/lowp_dram_sweep_plot.py
M util/protolib.py
M util/qdo
M util/regress
M util/rundiff
M util/statetrace/SConscript
M util/statetrace/SConstruct
M util/statetrace/arch/amd64/tracechild.cc
M util/statetrace/arch/amd64/tracechild.hh
M util/statetrace/arch/arm/tracechild.cc
M util/statetrace/arch/arm/tracechild.hh
M util/statetrace/arch/i686/tracechild.cc
M util/statetrace/arch/i686/tracechild.hh
M util/statetrace/arch/sparc/tracechild.cc
M util/statetrace/arch/sparc/tracechild.hh
M util/statetrace/base/arch_check.h
M util/statetrace/base/regstate.hh
M util/statetrace/base/statetrace.cc
M util/statetrace/base/tracechild.cc
M util/statetrace/base/tracechild.hh
M util/stats/__init__.py
M util/stats/barchart.py
M util/stats/categories.py
M util/stats/chart.py
M util/stats/db.py
M util/stats/dbinit.py
M util/stats/display.py
M util/stats/flags.py
M util/stats/info.py
M util/stats/output.py
M util/stats/print.py
M util/stats/profile.py
M util/stats/stats.py
M util/style.py
M util/style/__init__.py
M util/style/file_types.py
M util/style/repo.py
M util/style/sort_includes.py
M util/style/style.py
M util/style/verifiers.py
M util/systemc/gem5_within_systemc/Makefile
M util/systemc/gem5_within_systemc/main.cc
M util/systemc/gem5_within_systemc/sc_gem5_control.cc
M util/systemc/gem5_within_systemc/sc_gem5_control.hh
M util/systemc/gem5_within_systemc/sc_logger.cc
M util/systemc/gem5_within_systemc/sc_logger.hh
M util/systemc/gem5_within_systemc/sc_module.cc
M util/systemc/gem5_within_systemc/sc_module.hh
M util/systemc/gem5_within_systemc/stats.cc
M util/systemc/gem5_within_systemc/stats.hh
M util/systemc/systemc_within_gem5/systemc_sc_main/SConscript
M util/systemc/systemc_within_gem5/systemc_sc_main/config.py
M util/systemc/systemc_within_gem5/systemc_sc_main/sc_main.cc
M util/systemc/systemc_within_gem5/systemc_simple_object/SConscript
M util/systemc/systemc_within_gem5/systemc_simple_object/SystemC_Example.py
M util/systemc/systemc_within_gem5/systemc_simple_object/config.py
M util/systemc/systemc_within_gem5/systemc_simple_object/feeder.cc
M util/systemc/systemc_within_gem5/systemc_simple_object/feeder.hh
M util/systemc/systemc_within_gem5/systemc_simple_object/printer.cc
M util/systemc/systemc_within_gem5/systemc_simple_object/printer.hh
M util/tap/Makefile
M util/tap/tap.cc
M util/term/Makefile
M util/tlm/SConstruct
M util/tlm/conf/tgen.cfg
M util/tlm/conf/tlm_elastic_slave.py
M util/tlm/conf/tlm_master.py
M util/tlm/conf/tlm_slave.py
M util/tlm/examples/common/SConscript
M util/tlm/examples/common/cli_parser.cc
M util/tlm/examples/common/cli_parser.hh
M util/tlm/examples/common/report_handler.cc
M util/tlm/examples/common/report_handler.hh
M util/tlm/examples/master_port/SConscript
M util/tlm/examples/master_port/main.cc
M util/tlm/examples/master_port/traffic_generator.cc
M util/tlm/examples/master_port/traffic_generat

[gem5-dev] Change in gem5/gem5[develop]: misc: Remove arch-alpha from the MAINTAINERS file.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25461 )



Change subject: misc: Remove arch-alpha from the MAINTAINERS file.
..

misc: Remove arch-alpha from the MAINTAINERS file.

This architecture no longer exists in gem5, and so doesn't need a
maintainer.

Change-Id: I41cfba1e60d24fd4016953addfb7933993bce98b
---
M MAINTAINERS
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/MAINTAINERS b/MAINTAINERS
index 6ee1e93..949657d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25,7 +25,6 @@

 arch: General architecture-specific components
   Gabe Black 
-arch-alpha:
 arch-arm:
   Andreas Sandberg 
   Giacomo Travaglini 

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[gem5-dev] Change in gem5/gem5[develop]: misc: Delete authors lists from shared include files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25456 )



Change subject: misc: Delete authors lists from shared include files.
..

misc: Delete authors lists from shared include files.

Change-Id: I65d3d2e8df9799d9d3dc61734265a62b4dc9d67f
---
M include/gem5/asm/generic/m5op_flags.h
M include/gem5/asm/generic/m5ops.h
M include/gem5/m5ops.h
3 files changed, 0 insertions(+), 11 deletions(-)



diff --git a/include/gem5/asm/generic/m5op_flags.h  
b/include/gem5/asm/generic/m5op_flags.h

index de44e00..0304b88 100644
--- a/include/gem5/asm/generic/m5op_flags.h
+++ b/include/gem5/asm/generic/m5op_flags.h
@@ -36,10 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
- *  Andreas Sandberg
  */

 #ifndef __GEM5_ASM_GENERIC_M5OP_FLAGS_H__
diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

index 2d7d074..d0ee337 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -36,10 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
- *  Andreas Sandberg
  */

 #ifndef __GEM5_ASM_GENERIC_M5OPS_H__
diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h
index 72223d1..8a35666 100644
--- a/include/gem5/m5ops.h
+++ b/include/gem5/m5ops.h
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
  */

 #ifndef __GEM5_M5OP_H__

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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove mention of ALPHA from the SConstruct.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25463 )



Change subject: scons: Remove mention of ALPHA from the SConstruct.
..

scons: Remove mention of ALPHA from the SConstruct.

I've arbitrarily chosen to make ARM the default ISA for now, since I
think it's the best supported ISA with X86 somewhere a little behind
it. As a compromise, I change all mention of ALPHA (or even ALPHA_SE!)
in comments to be X86 instead, so it gets some attention too.

Change-Id: I1d8edc7925ca2d94f11b26e2c0b9314216e9b97d
---
M SConstruct
1 file changed, 10 insertions(+), 10 deletions(-)



diff --git a/SConstruct b/SConstruct
index 6a45752..2ecbaf6 100755
--- a/SConstruct
+++ b/SConstruct
@@ -46,7 +46,7 @@
 #
 # While in this directory ('gem5'), just type 'scons' to build the default
 # configuration (see below), or type 'scons build//'
-# to build some other configuration (e.g., 'build/ALPHA/gem5.opt' for
+# to build some other configuration (e.g., 'build/X86/gem5.opt' for
 # the optimized full-system version).
 #
 # You can build gem5 in a different directory as long as there is a
@@ -58,15 +58,15 @@
 #
 #   The following two commands are equivalent.  The '-u' option tells
 #   scons to search up the directory tree for this SConstruct file.
-#   % cd /gem5 ; scons build/ALPHA/gem5.debug
-#   % cd /gem5/build/ALPHA; scons -u gem5.debug
+#   % cd /gem5 ; scons build/X86/gem5.debug
+#   % cd /gem5/build/X86; scons -u gem5.debug
 #
 #   The following two commands are equivalent and demonstrate building
 #   in a directory outside of the source tree.  The '-C' option tells
 #   scons to chdir to the specified directory to find this SConstruct
 #   file.
-#   % cd /gem5 ; scons /local/foo/build/ALPHA/gem5.debug
-#   % cd /local/foo/build/ALPHA; scons -C /gem5 gem5.debug
+#   % cd /gem5 ; scons /local/foo/build/X86/gem5.debug
+#   % cd /local/foo/build/X86; scons -C /gem5 gem5.debug
 #
 # You can use 'scons -H' to print scons options.  If you're in this
 # 'gem5' directory (or use -u or -C to tell scons where to find this
@@ -196,7 +196,7 @@
 ###

 # Find default configuration & binary.
-Default(environ.get('M5_DEFAULT_BINARY', 'build/ALPHA/gem5.debug'))
+Default(environ.get('M5_DEFAULT_BINARY', 'build/ARM/gem5.debug'))

 # helper function: find last occurrence of element in list
 def rfind(l, elt, offs = -1):
@@ -227,8 +227,8 @@

 # Each target must have 'build' in the interior of the path; the
 # directory below this will determine the build parameters.  For
-# example, for target 'foo/bar/build/ALPHA_SE/arch/alpha/blah.do' we
-# recognize that ALPHA_SE specifies the configuration because it
+# example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
+# recognize that X86 specifies the configuration because it
 # follow 'build' in the build path.

 # The funky assignment to "[:]" is needed to replace the list contents
@@ -274,7 +274,7 @@

 #
 # Set up global sticky variables... these are common to an entire build
-# tree (not specific to a particular build like ALPHA_SE)
+# tree (not specific to a particular build like X86)
 #

 global_vars_file = joinpath(build_root, 'variables.global')
@@ -1151,7 +1151,7 @@
 env['BUILDDIR'] = variant_path

 # variant_dir is the tail component of build path, and is used to
-# determine the build parameters (e.g., 'ALPHA_SE')
+# determine the build parameters (e.g., 'X86')
 (build_root, variant_dir) = splitpath(variant_path)

 # Set env variables according to the build directory config.

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[gem5-dev] Change in gem5/gem5[develop]: sparc: Delete authors lists from sparc files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25452 )



Change subject: sparc: Delete authors lists from sparc files.
..

sparc: Delete authors lists from sparc files.

Change-Id: Iac3f9bb546121c73e6e73a0377d2a917c40df5f8
---
M src/arch/sparc/SConscript
M src/arch/sparc/SConsopts
M src/arch/sparc/SparcISA.py
M src/arch/sparc/SparcInterrupts.py
M src/arch/sparc/SparcNativeTrace.py
M src/arch/sparc/SparcSystem.py
M src/arch/sparc/SparcTLB.py
M src/arch/sparc/asi.cc
M src/arch/sparc/asi.hh
M src/arch/sparc/decoder.cc
M src/arch/sparc/decoder.hh
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/sparc/handlers.hh
M src/arch/sparc/insts/SConscript
M src/arch/sparc/insts/blockmem.cc
M src/arch/sparc/insts/blockmem.hh
M src/arch/sparc/insts/branch.cc
M src/arch/sparc/insts/branch.hh
M src/arch/sparc/insts/integer.cc
M src/arch/sparc/insts/integer.hh
M src/arch/sparc/insts/mem.cc
M src/arch/sparc/insts/mem.hh
M src/arch/sparc/insts/micro.cc
M src/arch/sparc/insts/micro.hh
M src/arch/sparc/insts/nop.cc
M src/arch/sparc/insts/nop.hh
M src/arch/sparc/insts/priv.cc
M src/arch/sparc/insts/priv.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/insts/static_inst.hh
M src/arch/sparc/insts/trap.cc
M src/arch/sparc/insts/trap.hh
M src/arch/sparc/insts/unimp.hh
M src/arch/sparc/insts/unknown.hh
M src/arch/sparc/interrupts.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/isa/base.isa
M src/arch/sparc/isa/bitfields.isa
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/formats/basic.isa
M src/arch/sparc/isa/formats/branch.isa
M src/arch/sparc/isa/formats/formats.isa
M src/arch/sparc/isa/formats/integerop.isa
M src/arch/sparc/isa/formats/mem/basicmem.isa
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/isa/formats/mem/mem.isa
M src/arch/sparc/isa/formats/mem/swap.isa
M src/arch/sparc/isa/formats/mem/util.isa
M src/arch/sparc/isa/formats/nop.isa
M src/arch/sparc/isa/formats/priv.isa
M src/arch/sparc/isa/formats/trap.isa
M src/arch/sparc/isa/formats/unimp.isa
M src/arch/sparc/isa/formats/unknown.isa
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/isa/main.isa
M src/arch/sparc/isa/operands.isa
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/kernel_stats.hh
M src/arch/sparc/linux/linux.cc
M src/arch/sparc/linux/linux.hh
M src/arch/sparc/linux/process.cc
M src/arch/sparc/linux/process.hh
M src/arch/sparc/linux/syscalls.cc
M src/arch/sparc/locked_mem.hh
M src/arch/sparc/microcode_rom.hh
M src/arch/sparc/miscregs.hh
M src/arch/sparc/mmapped_ipr.hh
M src/arch/sparc/nativetrace.cc
M src/arch/sparc/nativetrace.hh
M src/arch/sparc/pagetable.cc
M src/arch/sparc/pagetable.hh
M src/arch/sparc/process.cc
M src/arch/sparc/process.hh
M src/arch/sparc/pseudo_inst.hh
M src/arch/sparc/registers.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/remote_gdb.hh
M src/arch/sparc/solaris/process.cc
M src/arch/sparc/solaris/process.hh
M src/arch/sparc/solaris/solaris.cc
M src/arch/sparc/solaris/solaris.hh
M src/arch/sparc/sparc_traits.hh
M src/arch/sparc/stacktrace.hh
M src/arch/sparc/system.cc
M src/arch/sparc/system.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/sparc/tlb_map.hh
M src/arch/sparc/types.hh
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/sparc/vtophys.cc
M src/arch/sparc/vtophys.hh
96 files changed, 1 insertion(+), 257 deletions(-)



diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index afffd8a..709911d 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-#  Steve Reinhardt

 Import('*')

diff --git a/src/arch/sparc/SConsopts b/src/arch/sparc/SConsopts
index c356062..41aa275 100644
--- a/src/arch/sparc/SConsopts
+++ b/src/arch/sparc/SConsopts
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 Import('*')

diff --git a/src/arch/sparc/SparcISA.py b/src/arch/sparc/SparcISA.py
index 5f8f3ce..235fdcc 100644
--- a/src/arch/sparc/SparcISA.py
+++ b/src/arch/sparc/SparcISA.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 from m5.objects.BaseISA import BaseISA

diff --git a/src/arch/sparc/SparcInterrupts.py  
b/src/arch/sparc/SparcInterrupts.py

index 04979ad..4bacfe0

[gem5-dev] Change in gem5/gem5[develop]: util: Delete some Alpha related files from the m5 utility.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25459 )



Change subject: util: Delete some Alpha related files from the m5 utility.
..

util: Delete some Alpha related files from the m5 utility.

Change-Id: I5d751996d09459e79427851e80a4826e18f9db27
---
D util/m5/Makefile.alpha
D util/m5/m5op_alpha.S
2 files changed, 0 insertions(+), 180 deletions(-)



diff --git a/util/m5/Makefile.alpha b/util/m5/Makefile.alpha
deleted file mode 100644
index d9013be..000
--- a/util/m5/Makefile.alpha
+++ /dev/null
@@ -1,50 +0,0 @@
-# Copyright (c) 2005-2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-### If we are not compiling on an alpha, we must use cross tools ###
-ifneq ($(shell uname -m), alpha)
-CROSS_COMPILE?=alpha-unknown-linux-gnu-
-endif
-CC=$(CROSS_COMPILE)gcc
-AS=$(CROSS_COMPILE)as
-LD=$(CROSS_COMPILE)ld
-
-CFLAGS=-O2 -I../../include
-OBJS=m5.o m5op_alpha.o m5_mmap.o
-
-all: m5
-
-%.o: %.S
-   $(CC) $(CFLAGS) -o $@ -c $<
-
-%.o: %.c
-   $(CC)  $(CFLAGS) -o $@ -c $<
-
-m5: $(OBJS)
-   $(CC) -o $@ $(OBJS)
-
-clean:
-   rm -f *.o m5
diff --git a/util/m5/m5op_alpha.S b/util/m5/m5op_alpha.S
deleted file mode 100644
index 255dfb4..000
--- a/util/m5/m5op_alpha.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define m5_op 0x01
-
-#include 
-
-#define INST(op, ra, rb, func) \
-.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
-
-#define LEAF(func)\
-.align 3; \
-.globl  func; \
-.entfunc; \
-func:
-
-#define RET   \
-ret ($26)
-
-#define END(func) \
-.end func
-
-#define SIMPLE_OP(_f, _o)   \
-LEAF(_f)\
-_o; \
-RET;\
-END(_f)
-
-#define ARM(reg) IN

[gem5-dev] Change in gem5/gem5[develop]: misc: Remove mention of ALPHA from the README.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25462 )



Change subject: misc: Remove mention of ALPHA from the README.
..

misc: Remove mention of ALPHA from the README.

Change-Id: Ic0faf22e5ed94cf7e7591175a808c4696de29e25
---
M README
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/README b/README
index 44a97ba..e24e7a3 100644
--- a/README
+++ b/README
@@ -14,9 +14,9 @@
 for more details concerning the minimum versions of the aforementioned  
tools.


 Once you have all dependencies resolved, type 'scons
-build//gem5.opt' where ARCH is one of ALPHA, ARM, NULL, MIPS,
-POWER, SPARC, or X86. This will build an optimized version of the gem5
-binary (gem5.opt) for the the specified architecture. See
+build//gem5.opt' where ARCH is one of ARM, NULL, MIPS, POWER, SPARC,
+or X86. This will build an optimized version of the gem5 binary (gem5.opt)
+for the the specified architecture. See
 http://www.gem5.org/documentation/general_docs/building for more details  
and

 options.


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[gem5-dev] Change in gem5/gem5[develop]: arch, arch-arm: Use BaseISA in RenameMode interface

2020-02-17 Thread Giacomo Travaglini (Gerrit)


Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/25429

to review the following change.


Change subject: arch, arch-arm: Use BaseISA in RenameMode interface
..

arch, arch-arm: Use BaseISA in RenameMode interface

Please note: we are still templatizing the RenameMode class to avoid
virtual methods

Change-Id: I4afd99f45eaa45be9e032b67e106884a21c83234
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/isa.hh
M src/arch/generic/traits.hh
2 files changed, 9 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 9016196..cd420e4 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -778,9 +778,11 @@
 struct RenameMode
 {
 static Enums::VecRegRenameMode
-init(const ArmISA::ISA* isa)
+init(const BaseISA* isa)
 {
-return isa->vecRegRenameMode();
+auto arm_isa = dynamic_cast(isa);
+assert(arm_isa);
+return arm_isa->vecRegRenameMode();
 }

 static Enums::VecRegRenameMode
@@ -794,7 +796,7 @@
 }

 static bool
-equalsInit(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)
+equalsInit(const BaseISA* isa1, const BaseISA* isa2)
 {
 return init(isa1) == init(isa2);
 }
diff --git a/src/arch/generic/traits.hh b/src/arch/generic/traits.hh
index c95c5ab..bc9d85e 100644
--- a/src/arch/generic/traits.hh
+++ b/src/arch/generic/traits.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -42,6 +42,7 @@
 #ifndef __ARCH_COMMON_TRAITS_HH__
 #define __ARCH_COMMON_TRAITS_HH__

+#include "arch/generic/isa.hh"
 #include "arch/types.hh"
 #include "enums/VecRegRenameMode.hh"

@@ -53,7 +54,7 @@
 template 
 struct RenameMode
 {
-static Enums::VecRegRenameMode init(const ISA*) { return Enums::Full; }
+static Enums::VecRegRenameMode init(const BaseISA*) { return  
Enums::Full; }


 static Enums::VecRegRenameMode
 mode(const TheISA::PCState&)
@@ -63,7 +64,7 @@
  * Compare the initial rename mode of two instances of the ISA.
  * Result is true by definition, as the default mode is Full.
  * */
-static bool equalsInit(const ISA*, const ISA*) { return true; }
+static bool equalsInit(const BaseISA*, const BaseISA*) { return true; }
 };

 #endif /* __ARCH_COMMON_TRAITS_HH__ */

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I4afd99f45eaa45be9e032b67e106884a21c83234
Gerrit-Change-Number: 25429
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix vector renaming bug

2020-02-17 Thread Giacomo Travaglini (Gerrit)


Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/25430

to review the following change.


Change subject: cpu: Fix vector renaming bug
..

cpu: Fix vector renaming bug

The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/25009

moved initialization of vecMode out of initializing list.
In this way regFile gets initialized with an invalid initial renaming
mode.

Change-Id: Ib7bab9eaac0f5850fd3b3151584132f809a641e1
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/cpu/o3/cpu.cc
1 file changed, 3 insertions(+), 6 deletions(-)



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 31334a3..0454413 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -103,6 +103,9 @@
   iew(this, params),
   commit(this, params),

+  /* It is mandatory that all SMT threads use the same renaming mode as
+   * they are sharing registers and rename */
+  vecMode(RenameMode::init(params->isa[0])),
   regFile(params->numPhysIntRegs,
   params->numPhysFloatRegs,
   params->numPhysVecRegs,
@@ -132,12 +135,6 @@
   system(params->system),
   lastRunningCycle(curCycle())
 {
-auto *the_isa = dynamic_cast(params->isa[0]);
-assert(the_isa);
-/* It is mandatory that all SMT threads use the same renaming mode as
- * they are sharing registers and rename */
-vecMode = RenameMode::init(the_isa);
-
 if (!params->switched_out) {
 _status = Running;
 } else {

--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Mark ExecContext::tcBase() as const

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24523 )


Change subject: cpu: Mark ExecContext::tcBase() as const
..

cpu: Mark ExecContext::tcBase() as const

Change-Id: Ia3965c05a1b00e0a9738ddbccb4dc0b651f78e5e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24523
Tested-by: kokoro 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/simple/exec_context.hh
5 files changed, 10 insertions(+), 10 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 85ad544..81b3999 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, 2013, 2016-2019 ARM Limited
+ * Copyright (c) 2011, 2013, 2016-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -919,7 +919,7 @@
 void setThreadState(ImplState *state) { thread = state; }

 /** Returns the thread context. */
-ThreadContext *tcBase() { return thread->getTC(); }
+ThreadContext *tcBase() const { return thread->getTC(); }

   public:
 /** Returns whether or not the eff. addr. source registers are ready.  
*/

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 775381c..7d3d339 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, 2016-2018 ARM Limited
+ * Copyright (c) 2011, 2016-2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -595,7 +595,7 @@

 void dumpAndExit();

-ThreadContext *tcBase() override { return tc; }
+ThreadContext *tcBase() const override { return tc; }
 SimpleThread *threadBase() { return thread; }

 InstResult unverifiedResult;
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index a96ccfc..c1af767 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016-2018 ARM Limited
+ * Copyright (c) 2014, 2016-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -311,7 +311,7 @@
 /** @} */

 /** Returns a pointer to the ThreadContext. */
-virtual ThreadContext *tcBase() = 0;
+virtual ThreadContext *tcBase() const = 0;

 /**
  * @{
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 2b1b530..327c0b2 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2014, 2016-2018, 2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -390,7 +390,7 @@
 thread.syscall(fault);
 }

-ThreadContext *tcBase() override { return thread.getTC(); }
+ThreadContext *tcBase() const override { return thread.getTC(); }

 /* @todo, should make stCondFailures persistent somewhere */
 unsigned int readStCondFailures() const override { return 0; }
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 04be1a0..5924ada 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018 ARM Limited
+ * Copyright (c) 2014-2018, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -505,7 +505,7 @@
 }

 /** Returns a pointer to the ThreadContext. */
-ThreadContext *tcBase() override { return thread->getTC(); }
+ThreadContext *tcBase() const override { return thread->getTC(); }

 bool
 readPredicate() const override

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia3965c05a1b00e0a9738ddbccb4dc0b651f78e5e
Gerrit-Change-Number: 24523
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmKVM build

2020-02-17 Thread Giacomo Travaglini (Gerrit)


Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/25464

to review the following change.


Change subject: arch-arm: Fix ArmKVM build
..

arch-arm: Fix ArmKVM build

BaseInterrupts don't have a checkRaw method.
This was breaking gem5 compilation on a Arm machine

Change-Id: I8717b1bcf64ed14e8a0f63a9dcaca6041dbea4d3
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 8 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 80576a2..24f7be8 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -45,6 +45,7 @@
 #include 
 #include 

+#include "arch/arm/interrupts.hh"
 #include "arch/registers.hh"
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
@@ -270,8 +271,9 @@
 Tick
 ArmKvmCPU::kvmRun(Tick ticks)
 {
-bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+auto interrupt = static_cast(interrupts[0]);
+const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+const bool simIRQ(interrupt->checkRaw(INT_IRQ));

 if (fiqAsserted != simFIQ) {
 fiqAsserted = simFIQ;
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index 7659650..c99e853 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -41,6 +41,7 @@

 #include 

+#include "arch/arm/interrupts.hh"
 #include "debug/KvmInt.hh"
 #include "params/BaseArmKvmCPU.hh"

@@ -88,8 +89,9 @@
 Tick
 BaseArmKvmCPU::kvmRun(Tick ticks)
 {
-const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+auto interrupt = static_cast(interrupts[0]);
+const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+const bool simIRQ(interrupt->checkRaw(INT_IRQ));

 if (!vm.hasKernelIRQChip()) {
 if (fiqAsserted != simFIQ) {

--
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[gem5-dev] Change in gem5/gem5[develop]: misc: pass ThreadContext on ISA clear

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25465 )



Change subject: misc: pass ThreadContext on ISA clear
..

misc: pass ThreadContext on ISA clear

This patch changes the clear API for the ISAs to pass the ThreadContext
issuing the call. This allows the ISA to carry out maintainance
operations on the TC state.

Change-Id: I40d6cf39c321521a221146aa0fd8f2cf665d39c6
---
M src/arch/arm/isa.hh
M src/arch/mips/isa.hh
M src/arch/power/isa.hh
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.hh
M src/arch/x86/isa.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.hh
8 files changed, 24 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 9016196..b5f6d7c 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -465,9 +465,10 @@
 }

   public:
-void clear();
+void clear(ThreadContext *tc) { clear(); }

   protected:
+void clear();
 void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
 void clear64(const ArmISAParams *p);
 void initID32(const ArmISAParams *p);
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index df0936d..80450fb 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -74,8 +74,12 @@
 std::vector bankType;

   public:
+void clear(ThreadContext *tc) { clear(); }
+
+  protected:
 void clear();

+  public:
 void configCP();

 unsigned getVPENum(ThreadID tid) const;
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index d5706b5..c82dd73 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -58,10 +58,18 @@
 typedef PowerISAParams Params;

 void
+clear(ThreadContext *tc)
+{
+clear();
+}
+
+  protected:
+void
 clear()
 {
 }

+  public:
 RegVal
 readMiscRegNoEffect(int misc_reg) const
 {
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 1c08700..41c136c 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -73,8 +73,12 @@
   public:
 typedef RiscvISAParams Params;

+void clear(ThreadContext *tc) { clear(); }
+
+  protected:
 void clear();

+  public:
 RegVal readMiscRegNoEffect(int misc_reg) const;
 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
 void setMiscRegNoEffect(int misc_reg, RegVal val);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index ba3f514..141464c 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -167,7 +167,7 @@

   public:

-void clear();
+void clear(ThreadContext *tc) { clear(); }

 void serialize(CheckpointOut &cp) const override;
 void unserialize(CheckpointIn &cp) override;
@@ -178,6 +178,7 @@
 using BaseISA::startup;

   protected:
+void clear();
 bool isHyperPriv() { return hpstate.hpriv; }
 bool isPriv() { return hpstate.hpriv || pstate.priv; }
 bool isNonPriv() { return !isPriv(); }
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index b404077..f8a587c 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -56,11 +56,12 @@
 void updateHandyM5Reg(Efer efer, CR0 cr0,
 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
 ThreadContext *tc);
+void clear();

   public:
 typedef X86ISAParams Params;

-void clear();
+void clear(ThreadContext *tc) { clear(); }

 ISA(Params *p);
 const Params *params() const;
diff --git a/src/cpu/o3/thread_context_impl.hh  
b/src/cpu/o3/thread_context_impl.hh

index e05721b..0605871 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -200,7 +200,7 @@
 void
 O3ThreadContext::clearArchRegs()
 {
-cpu->isa[thread->threadId()]->clear();
+cpu->isa[thread->threadId()]->clear(this);
 }

 template 
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 7f799d8..6732ce5 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -299,7 +299,7 @@
 for (auto &pred_reg: vecPredRegs)
 pred_reg.reset();
 ccRegs.fill(0);
-isa->clear();
+isa->clear(this);
 }

 //

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: ArmISA::clear, inval TLB cached miscregs

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25466 )



Change subject: arch-arm: ArmISA::clear, inval TLB cached miscregs
..

arch-arm: ArmISA::clear, inval TLB cached miscregs

ArmISA::clear resets the value of the architecture registers. Some of
these are cached in ArmTLB, including SCTLR. This patch invalidates the
cached copies on clear; this fixes a bug when resetting CPU cores by which
the cached SCTLR was used and SCTLR.M was set, resulting in non-arch
compliant reset behaviour and a PA being treated as a VA on translation.

Change-Id: I8d4eeeaf807325bd7b300a7a317abfa40ad23c87
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ed90b0e..e7dd81b 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -123,6 +123,15 @@
 }

 void
+ISA::clear(ThreadContext *tc)
+{
+clear();
+// Invalidate cached copies of miscregs in the TLBs
+getITBPtr(tc)->invalidateMiscReg();
+getDTBPtr(tc)->invalidateMiscReg();
+}
+
+void
 ISA::clear()
 {
 const Params *p(params());
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index b5f6d7c..988a25c 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -465,7 +465,7 @@
 }

   public:
-void clear(ThreadContext *tc) { clear(); }
+void clear(ThreadContext *tc);

   protected:
 void clear();

--
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: PL031, fix AMBA ID and clock names

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25432 )



Change subject: dev-arm: PL031, fix AMBA ID and clock names
..

dev-arm: PL031, fix AMBA ID and clock names

This patch fixes the AMBA ID of the PL031 RTC. It also adds the
"clock-names" property to its auto-DTB generation. This fixes and
enables correct probing from Linux.

Change-Id: I331bfa81664f57a35f21f35d658772eb40380e35
---
M src/dev/arm/RealView.py
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 2de99ca..3d87be8 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -489,7 +489,7 @@
 type = 'PL031'
 cxx_header = "dev/arm/rtc_pl031.hh"
 time = Param.Time('01/01/2009', "System time to use ('Now' for actual  
time)")

-amba_id = 0x00341031
+amba_id = 0x00041031

 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
@@ -498,6 +498,7 @@
 node.appendCompatible(["arm,pl031", "arm,primecell"])
 clock = state.phandle(self.clk_domain.unproxy(self))
 node.append(FdtPropertyWords("clocks", clock))
+node.append(FdtPropertyStrings("clock-names", ["apb_pclk"]))

 yield node


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[gem5-dev] Change in gem5/gem5[develop]: misc: Delete authors lists from documentation related files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25405 )


Change subject: misc: Delete authors lists from documentation related files.
..

misc: Delete authors lists from documentation related files.

Change-Id: I6cd78336687c2516a90dba7c56154b03a709f791
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25405
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/doc/inside-minor.doxygen
M src/doc/se-files.txt
M src/doxygen/stl.hh
3 files changed, 0 insertions(+), 7 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/doc/inside-minor.doxygen b/src/doc/inside-minor.doxygen
index e55f61c..9db3d68 100644
--- a/src/doc/inside-minor.doxygen
+++ b/src/doc/inside-minor.doxygen
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andrew Bardsley

 namespace Minor
 {
diff --git a/src/doc/se-files.txt b/src/doc/se-files.txt
index e5f3805..bf1f1cf 100644
--- a/src/doc/se-files.txt
+++ b/src/doc/se-files.txt
@@ -24,8 +24,6 @@
 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-Authors: Brandon Potter
-
  
===


 This file exists to educate users and notify them that some filesystem open
diff --git a/src/doxygen/stl.hh b/src/doxygen/stl.hh
index fd9f681..bf537ef 100644
--- a/src/doxygen/stl.hh
+++ b/src/doxygen/stl.hh
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- *  Nathan Binkert
  */

 /**

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6cd78336687c2516a90dba7c56154b03a709f791
Gerrit-Change-Number: 25405
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Delete authors lists from proto.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25407 )


Change subject: misc: Delete authors lists from proto.
..

misc: Delete authors lists from proto.

Change-Id: I3ec4f28c82de2f006518ca276f761813d08d7977
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25407
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/proto/SConscript
M src/proto/inst.proto
M src/proto/inst_dep_record.proto
M src/proto/packet.proto
M src/proto/protoio.cc
M src/proto/protoio.hh
6 files changed, 1 insertion(+), 13 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/proto/SConscript b/src/proto/SConscript
index 665d164..9ca38f7 100644
--- a/src/proto/SConscript
+++ b/src/proto/SConscript
@@ -34,8 +34,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 Import('*')

diff --git a/src/proto/inst.proto b/src/proto/inst.proto
index ef44dfe..478a736 100644
--- a/src/proto/inst.proto
+++ b/src/proto/inst.proto
@@ -32,8 +32,6 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Ali Saidi

 syntax = "proto2";

diff --git a/src/proto/inst_dep_record.proto  
b/src/proto/inst_dep_record.proto

index 808837e..0666f40 100644
--- a/src/proto/inst_dep_record.proto
+++ b/src/proto/inst_dep_record.proto
@@ -32,8 +32,6 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Radhika Jagtap

 syntax = "proto2";

@@ -81,4 +79,4 @@
   optional uint64 pc = 10;
   optional uint64 v_addr = 11;
   optional uint32 asid = 12;
-}
\ No newline at end of file
+}
diff --git a/src/proto/packet.proto b/src/proto/packet.proto
index 1fb7e2f..e8536f2 100644
--- a/src/proto/packet.proto
+++ b/src/proto/packet.proto
@@ -32,8 +32,6 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Andreas Hansson

 syntax = "proto2";

diff --git a/src/proto/protoio.cc b/src/proto/protoio.cc
index d2ce459..93c5749 100644
--- a/src/proto/protoio.cc
+++ b/src/proto/protoio.cc
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #include "proto/protoio.hh"
diff --git a/src/proto/protoio.hh b/src/proto/protoio.hh
index 27bb336..cb2f6ff 100644
--- a/src/proto/protoio.hh
+++ b/src/proto/protoio.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3ec4f28c82de2f006518ca276f761813d08d7977
Gerrit-Change-Number: 25407
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Delete authors lists from the python directory.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25408 )


Change subject: python: Delete authors lists from the python directory.
..

python: Delete authors lists from the python directory.

Change-Id: Ia147b90016f56a8ddd0c77b15746f74f50aba7e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25408
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/python/SConscript
M src/python/importer.py
M src/python/m5/SimObject.py
M src/python/m5/__init__.py
M src/python/m5/config.py
M src/python/m5/core.py
M src/python/m5/debug.py
M src/python/m5/event.py
M src/python/m5/ext/__init__.py
M src/python/m5/internal/__init__.py
M src/python/m5/internal/params.py
M src/python/m5/main.py
M src/python/m5/objects/__init__.py
M src/python/m5/options.py
M src/python/m5/params.py
M src/python/m5/proxy.py
M src/python/m5/simulate.py
M src/python/m5/stats/__init__.py
M src/python/m5/ticks.py
M src/python/m5/trace.py
M src/python/m5/util/__init__.py
M src/python/m5/util/attrdict.py
M src/python/m5/util/convert.py
M src/python/m5/util/dot_writer.py
M src/python/m5/util/dot_writer_ruby.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
M src/python/m5/util/pybind.py
M src/python/m5/util/smartdict.py
M src/python/m5/util/terminal_formatter.py
M src/python/marshal.cc
M src/python/pybind11/core.cc
M src/python/pybind11/core.hh
M src/python/pybind11/debug.cc
M src/python/pybind11/event.cc
M src/python/pybind11/pybind.hh
M src/python/pybind11/stats.cc
37 files changed, 0 insertions(+), 95 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/SConscript b/src/python/SConscript
index 8264e38..cf52ee1 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-#  Nathan Binkert

 Import('*')

diff --git a/src/python/importer.py b/src/python/importer.py
index 20d168e..c29fb7b 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 from __future__ import print_function
 from __future__ import absolute_import
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 37a13a3..b76db5c 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -37,11 +37,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-#  Nathan Binkert
-#  Andreas Hansson
-#  Andreas Sandberg

 from __future__ import print_function
 from __future__ import absolute_import
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 8cad3b8..309764d 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 from __future__ import print_function
 from __future__ import absolute_import
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
index c28f667..926ea14 100644
--- a/src/python/m5/config.py
+++ b/src/python/m5/config.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 import os
 from os.path import isdir, isfile, join as joinpath
diff --git a/src/python/m5/core.py b/src/python/m5/core.py
index c8c57fc..34d54bc 100644
--- a/src/python/m5/core.py
+++ b/src/python/m5/core.py
@@ -35,8 +35,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 from __future__ import print_function
 from __future__ import absolute_import
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index d2892f7..a3d5e35 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -23,8 +23,6 @@
 # THEORY OF

[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: Delete authors lists from learning_gem5.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25406 )


Change subject: learning-gem5: Delete authors lists from learning_gem5.
..

learning-gem5: Delete authors lists from learning_gem5.

Change-Id: I42b6241057dab661aeaad695d48f62f70f163832
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25406
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/learning_gem5/part2/HelloObject.py
M src/learning_gem5/part2/SConscript
M src/learning_gem5/part2/SimpleCache.py
M src/learning_gem5/part2/SimpleMemobj.py
M src/learning_gem5/part2/SimpleObject.py
M src/learning_gem5/part2/goodbye_object.cc
M src/learning_gem5/part2/goodbye_object.hh
M src/learning_gem5/part2/hello_object.cc
M src/learning_gem5/part2/hello_object.hh
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.cc
M src/learning_gem5/part2/simple_memobj.hh
M src/learning_gem5/part2/simple_object.cc
M src/learning_gem5/part2/simple_object.hh
M src/learning_gem5/part3/MSI-cache.sm
M src/learning_gem5/part3/MSI-dir.sm
M src/learning_gem5/part3/MSI-msg.sm
18 files changed, 0 insertions(+), 36 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/learning_gem5/part2/HelloObject.py  
b/src/learning_gem5/part2/HelloObject.py

index 42f1be3..91b4125 100644
--- a/src/learning_gem5/part2/HelloObject.py
+++ b/src/learning_gem5/part2/HelloObject.py
@@ -24,8 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/learning_gem5/part2/SConscript  
b/src/learning_gem5/part2/SConscript

index 1a01d6d..c709f03 100644
--- a/src/learning_gem5/part2/SConscript
+++ b/src/learning_gem5/part2/SConscript
@@ -24,8 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power

 Import('*')

diff --git a/src/learning_gem5/part2/SimpleCache.py  
b/src/learning_gem5/part2/SimpleCache.py

index 7a02630..bd5ebfc 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -24,8 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power

 from m5.params import *
 from m5.proxy import *
diff --git a/src/learning_gem5/part2/SimpleMemobj.py  
b/src/learning_gem5/part2/SimpleMemobj.py

index 3769468..aee81c4 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -24,8 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/learning_gem5/part2/SimpleObject.py  
b/src/learning_gem5/part2/SimpleObject.py

index ee7e9ae..23fcf5f 100644
--- a/src/learning_gem5/part2/SimpleObject.py
+++ b/src/learning_gem5/part2/SimpleObject.py
@@ -24,8 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jason Lowe-Power

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/learning_gem5/part2/goodbye_object.cc  
b/src/learning_gem5/part2/goodbye_object.cc

index 3eaa5ad..d27de74 100644
--- a/src/learning_gem5/part2/goodbye_object.cc
+++ b/src/learning_gem5/part2/goodbye_object.cc
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Jason Lowe-Power
  */

 #include "learning_gem5/part2/goodbye_object.hh"
diff --git a/src/learning_gem5/part2/goodbye_object.hh  
b/src/learning_gem5/part2/goodbye_object.hh

index 0a2453c..1e6546b 100644
--- a/src/learning_gem5/part2/goodbye_object.hh
+++ b/src/learning_gem5/part2/goodbye_object.hh
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) A

[gem5-dev] Change in gem5/gem5[release-staging-v19.0.0.0]: arch-arm: Fix ArmKVM build

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25431 )


Change subject: arch-arm: Fix ArmKVM build
..

arch-arm: Fix ArmKVM build

BaseInterrupts don't have a checkRaw method.
This was breaking gem5 compilation on a Arm machine

Change-Id: I8717b1bcf64ed14e8a0f63a9dcaca6041dbea4d3
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25431
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 8 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 80576a2..24f7be8 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -45,6 +45,7 @@
 #include 
 #include 

+#include "arch/arm/interrupts.hh"
 #include "arch/registers.hh"
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
@@ -270,8 +271,9 @@
 Tick
 ArmKvmCPU::kvmRun(Tick ticks)
 {
-bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+auto interrupt = static_cast(interrupts[0]);
+const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+const bool simIRQ(interrupt->checkRaw(INT_IRQ));

 if (fiqAsserted != simFIQ) {
 fiqAsserted = simFIQ;
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index 7659650..c99e853 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -41,6 +41,7 @@

 #include 

+#include "arch/arm/interrupts.hh"
 #include "debug/KvmInt.hh"
 #include "params/BaseArmKvmCPU.hh"

@@ -88,8 +89,9 @@
 Tick
 BaseArmKvmCPU::kvmRun(Tick ticks)
 {
-const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+auto interrupt = static_cast(interrupts[0]);
+const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+const bool simIRQ(interrupt->checkRaw(INT_IRQ));

 if (!vm.hasKernelIRQChip()) {
 if (fiqAsserted != simFIQ) {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v19.0.0.0
Gerrit-Change-Id: I8717b1bcf64ed14e8a0f63a9dcaca6041dbea4d3
Gerrit-Change-Number: 25431
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Use a int to store fgetc return value

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25384 )


Change subject: base: Use a int to store fgetc return value
..

base: Use a int to store fgetc return value

The stdio fgetc returns the character read as an unsigned char cast to
an int.
The reason why it gets casted from unsigned char to int is because EOF
is defined as a negative value (usually -1).

At the moment in the atomicio.test we store the int in a char.

However the C standard states that the sign of a char is implementation
specific. This makes the test non portable: an architecture/ABI which
which is considering a char as a unsigned char won't compile since a
unsigned value will always be != -1 (EOF).

This is the error message you would get on a aarch64 host /w gcc/5.4.0

build/ARM/base/atomicio.test.cc:121:48:
error: comparison is always true due to limited range of data type
[-Werror=type-limits]

Change-Id: I120e44b5204d98e643f19b8dd6fa2762342a6e64
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25384
Reviewed-by: Ciro Santilli 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/atomicio.test.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Ciro Santilli: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/atomicio.test.cc b/src/base/atomicio.test.cc
index 29dacac..1801d2c 100644
--- a/src/base/atomicio.test.cc
+++ b/src/base/atomicio.test.cc
@@ -115,9 +115,9 @@

 EXPECT_EQ(file_contents.size(), size);

-char c;
+int c;
 for (unsigned int i = 0; (c = fgetc(file)) != EOF; i++) {
-EXPECT_EQ(file_contents[i], c);
+EXPECT_EQ(file_contents[i], (unsigned char)c);
 }

 fclose(file);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I120e44b5204d98e643f19b8dd6fa2762342a6e64
Gerrit-Change-Number: 25384
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Be more verbose on load/store construction

2020-02-17 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/24044 )


Change subject: arch-arm: Be more verbose on load/store construction
..

arch-arm: Be more verbose on load/store construction

This is achieved by using keyword arguments to improve readibility.
Some of the building helpers are using native types and can be annoying
for a reader to understand what those sequences of number and boolean
mean. It is also easier in this way to commit mistakes.

Change-Id: I63081d09a1f621550c5b6522b8107f349939b21d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Ciro Santilli 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24044
Tested-by: kokoro 
---
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str64.isa
2 files changed, 144 insertions(+), 130 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 16c0d93..17789df 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -390,82 +390,93 @@
 LoadPost64(mnem, NameBase + "_POST", size, sign,  
flavor=flavor).emit()
 LoadReg64(mnem, NameBase + "_REG", size, sign,  
flavor=flavor).emit()


+LoadPre64("ldraa", "LDRAA_PRE", size=8, sign=False,  
flavor="authDA").emit()
+LoadImm64("ldraa", "LDRAA_REG", size=8, sign=False,  
flavor="authDA").emit()
+LoadPre64("ldrab", "LDRAB_PRE", size=8, sign=False,  
flavor="authDB").emit()
+LoadImm64("ldrab", "LDRAB_REG", size=8, sign=False,  
flavor="authDB").emit()


-LoadPre64("ldraa", "LDRAA_PRE", 8, False, flavor="authDA").emit()
-LoadImm64("ldraa", "LDRAA_REG", 8, False, flavor="authDA").emit()
-LoadPre64("ldrab", "LDRAB_PRE", 8, False, flavor="authDB").emit()
-LoadImm64("ldrab", "LDRAB_REG", 8, False, flavor="authDB").emit()
+buildLoads64("ldrb", "LDRB64", size=1, sign=False)
+buildLoads64("ldrsb", "LDRSBW64", size=1, sign=True)
+buildLoads64("ldrsb", "LDRSBX64", size=1, sign=True, flavor="widen")
+buildLoads64("ldrh", "LDRH64", size=2, sign=False)
+buildLoads64("ldrsh", "LDRSHW64", size=2, sign=True)
+buildLoads64("ldrsh", "LDRSHX64", size=2, sign=True, flavor="widen")
+buildLoads64("ldrsw", "LDRSW64", size=4, sign=True, flavor="widen")
+buildLoads64("ldr", "LDRW64", size=4, sign=False)
+buildLoads64("ldr", "LDRX64", size=8, sign=False)
+buildLoads64("ldr", "LDRBFP64", size=1, sign=False, flavor="fp")
+buildLoads64("ldr", "LDRHFP64", size=2, sign=False, flavor="fp")
+buildLoads64("ldr", "LDRSFP64", size=4, sign=False, flavor="fp")
+buildLoads64("ldr", "LDRDFP64", size=8, sign=False, flavor="fp")

-buildLoads64("ldrb", "LDRB64", 1, False)
-buildLoads64("ldrsb", "LDRSBW64", 1, True)
-buildLoads64("ldrsb", "LDRSBX64", 1, True, flavor="widen")
-buildLoads64("ldrh", "LDRH64", 2, False)
-buildLoads64("ldrsh", "LDRSHW64", 2, True)
-buildLoads64("ldrsh", "LDRSHX64", 2, True, flavor="widen")
-buildLoads64("ldrsw", "LDRSW64", 4, True, flavor="widen")
-buildLoads64("ldr", "LDRW64", 4, False)
-buildLoads64("ldr", "LDRX64", 8, False)
-buildLoads64("ldr", "LDRBFP64", 1, False, flavor="fp")
-buildLoads64("ldr", "LDRHFP64", 2, False, flavor="fp")
-buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp")
-buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp")
-
-LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit()
-LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit()
-LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,
+LoadImm64("prfm", "PRFM64_IMM", size=8, flavor="mprefetch").emit()
+LoadReg64("prfm", "PRFM64_REG", size=8, flavor="mprefetch").emit()
+LoadLit64("prfm", "PRFM64_LIT", size=8, literal=True,
   flavor="mprefetch").emit()
-LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit()
+LoadImm64("prfum", "PRFUM64_IMM", size=8, flavor="mprefetch").emit()

-LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit()
-LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit()
-LoadImm64("ldursb", "LDURSBX64_IMM", 1, True, flavor="widen").emit()
-LoadImm64("ldurh", "LDURH64_IMM", 2, False).emit()
-LoadImm64("ldursh", "LDURSHW64_IMM", 2, True).emit()
-LoadImm64("ldursh", "LDURSHX64_IMM", 2, True, flavor="widen").emit()
-LoadImm64("ldursw", "LDURSW64_IMM", 4, True, flavor="widen").emit()
-LoadImm64("ldur", "LDURW64_IMM", 4, False).emit()
-LoadImm64("ldur", "LDURX64_IMM", 8, False).emit()
-LoadImm64("ldur", "LDURBFP64_IMM", 1, flavor="fp").emit()
-LoadImm64("ldur", "LDURHFP64_IMM", 2, flavor="fp").emit()
-LoadImm64("ldur", "LDURSFP64_IMM", 4, flavor="fp").emit()
-LoadImm64("ldur", "LDURDFP64_IMM", 8, flavor="fp").emit()
+LoadImm64("ldurb", "LDURB64_IMM

[gem5-dev] Change in gem5/gem5[develop]: sim-se: Extend MemState API to use VMAs

2020-02-17 Thread Matthew Poremba (Gerrit)

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25483 )



Change subject: sim-se: Extend MemState API to use VMAs
..

sim-se: Extend MemState API to use VMAs

Extend the MemState API to handle all memory tracking functions and
utilize virtual memory areas. This is intended to reduce the footprint
of the process class and is utilized in a subsequent patch.

This touches the process class for each ISA because the constructor for
MemState has changed.

Change-Id: I3ef10657e5f8e8f0e328bdf0aa15a27b1dde39bf
Signed-off-by: Brandon Potter 
---
M src/arch/alpha/process.cc
M src/arch/arm/process.cc
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/riscv/process.cc
M src/arch/sparc/process.hh
M src/arch/x86/process.cc
M src/mem/se_translating_port_proxy.cc
M src/sim/SConscript
A src/sim/mem_state.cc
M src/sim/mem_state.hh
A src/sim/mem_state_impl.hh
M src/sim/process.cc
M src/sim/process.hh
14 files changed, 922 insertions(+), 56 deletions(-)



diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 02a6899..c4c50a6 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -67,8 +67,9 @@
 // Set pointer for next thread stack.  Reserve 8M for main stack.
 Addr next_thread_stack_base = stack_base - max_stack_size;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end, params->system, pTable);
 }

 void
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 19ee32b..f348167 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -81,8 +81,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x4000L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end, params->system, pTable);
 }

 ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
@@ -95,8 +96,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x40L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end, params->system, pTable);
 }

 void
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index a62c1de..451b6a1 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -71,8 +71,9 @@
 // Set up region for mmaps.  Start it 1GB above the top of the heap.
 Addr mmap_end = brk_point + 0x4000L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end, params->system, pTable);
 }

 void
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index fdef2fa..954c8b2 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -69,8 +69,9 @@
 // Set up region for mmaps. For now, start at bottom of kuseg space.
 Addr mmap_end = 0x7000L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end, params->system, pTable);
 }

 void
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index ce49836..702c77f 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -77,8 +77,9 @@
 const Addr next_thread_stack_base = stack_base - max_stack_size;
 const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
 const Addr mmap_end = 0x4000L;
-memState = make_shared(brk_point, stack_base, max_stack_size,
-next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+max_stack_size, next_thread_stack_base, mmap_end,  
params->system,

+pTable);
 }

 RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile  
*objFile) :

@@ -89,8 +90,9 @@

[gem5-dev] Change in gem5/gem5[develop]: arch: Delete authors lists from generic arch files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25445 )


Change subject: arch: Delete authors lists from generic arch files.
..

arch: Delete authors lists from generic arch files.

Change-Id: I831a0f1876845f37ab12a2448e898719e74a0b55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25445
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/SConscript
M src/arch/generic/BaseISA.py
M src/arch/generic/BaseInterrupts.py
M src/arch/generic/BaseTLB.py
M src/arch/generic/ISACommon.py
M src/arch/generic/SConscript
M src/arch/generic/debugfaults.hh
M src/arch/generic/decode_cache.cc
M src/arch/generic/decode_cache.hh
M src/arch/generic/interrupts.hh
M src/arch/generic/isa.hh
M src/arch/generic/linux/threadinfo.hh
M src/arch/generic/locked_mem.hh
M src/arch/generic/memhelpers.hh
M src/arch/generic/pseudo_inst.cc
M src/arch/generic/pseudo_inst.hh
M src/arch/generic/tlb.hh
M src/arch/generic/traits.hh
M src/arch/generic/types.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/isa_parser.py
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
24 files changed, 0 insertions(+), 55 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/SConscript b/src/arch/SConscript
index 0661db7..1b68f3f 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -37,8 +37,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt

 import sys
 import os
diff --git a/src/arch/generic/BaseISA.py b/src/arch/generic/BaseISA.py
index f50819b..2cc2c45 100644
--- a/src/arch/generic/BaseISA.py
+++ b/src/arch/generic/BaseISA.py
@@ -22,8 +22,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/arch/generic/BaseInterrupts.py  
b/src/arch/generic/BaseInterrupts.py

index b373d80..a5b7ad5 100644
--- a/src/arch/generic/BaseInterrupts.py
+++ b/src/arch/generic/BaseInterrupts.py
@@ -22,8 +22,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 64531b9..02776e6 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -24,9 +24,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-#  Ivan Pizarro

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/arch/generic/ISACommon.py b/src/arch/generic/ISACommon.py
index dc2..88f9ccd 100644
--- a/src/arch/generic/ISACommon.py
+++ b/src/arch/generic/ISACommon.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Rekai Gonzalez

 from m5.params import *
 from m5.proxy import *
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index ec46b07..e3c2567 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -35,8 +35,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 Import('*')

diff --git a/src/arch/generic/debugfaults.hh  
b/src/arch/generic/debugfaults.hh

index 1c8d882..7d62d3f 100644
--- a/src/arch/generic/debugfaults.hh
+++ b/src/arch/generic/debugfaults.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */

 #ifndef __ARCH_GENERIC_DEBUGFAULTS_HH__
diff --git a/src/arch/generic/decode_cache.cc  
b/src/arch/generic/decode_cache.cc

index 0f7a9d9..341cb70 100644
--- a/src/arch/generic/decode_cache.cc
+++ b/src/arch/generic/de

[gem5-dev] Change in gem5/gem5[develop]: arch: Delete authors lists from the null arch files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25446 )


Change subject: arch: Delete authors lists from the null arch files.
..

arch: Delete authors lists from the null arch files.

Change-Id: Ief42708d8961a5c33db5e8a603ee8fff8df8b198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25446
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/null/SConscript
M src/arch/null/SConsopts
M src/arch/null/cpu_dummy.cc
M src/arch/null/cpu_dummy.hh
M src/arch/null/isa_traits.hh
M src/arch/null/locked_mem.hh
M src/arch/null/registers.hh
M src/arch/null/remote_gdb.hh
M src/arch/null/types.hh
M src/arch/null/utility.hh
10 files changed, 0 insertions(+), 20 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index e64b69c..41457e2 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -34,8 +34,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 Import('*')

diff --git a/src/arch/null/SConsopts b/src/arch/null/SConsopts
index e377564..a799754 100644
--- a/src/arch/null/SConsopts
+++ b/src/arch/null/SConsopts
@@ -34,8 +34,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 Import('*')

diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
index 4c78bf7..df30b81 100644
--- a/src/arch/null/cpu_dummy.cc
+++ b/src/arch/null/cpu_dummy.cc
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 /**
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
index 6f6311b..7e183eb 100644
--- a/src/arch/null/cpu_dummy.hh
+++ b/src/arch/null/cpu_dummy.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_CPU_DUMMY_HH__
diff --git a/src/arch/null/isa_traits.hh b/src/arch/null/isa_traits.hh
index d15f83c..6a9c2ea 100644
--- a/src/arch/null/isa_traits.hh
+++ b/src/arch/null/isa_traits.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_ISA_TRAITS_HH__
diff --git a/src/arch/null/locked_mem.hh b/src/arch/null/locked_mem.hh
index f5ecaf7..e1e9cde 100644
--- a/src/arch/null/locked_mem.hh
+++ b/src/arch/null/locked_mem.hh
@@ -36,8 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
  */

 #ifndef __ARCH_NULL_LOCKED_MEM_HH__
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 0ad0ea4..db02afc 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_REGISTERS_HH__
diff --git a/src/arch/null/remote_gdb.hh b/src/arch/null/remote_gdb.hh
index dddebce..4df9cc8 100644
--- a/src/arch/null/remote_gdb.hh
+++ b/src/arch/null/remote_gdb.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Hansson
  */

 #ifndef __ARCH_NULL_REMOTE_GDB_HH__
diff --git a/src/arch/null/types.hh b/src/arch/null/types.hh
index b62b8f2..3fa7479 100644
--- a/src/arch/null/types.hh
+++ b/src/arch/null/types.hh
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE US

[gem5-dev] Change in gem5/gem5[develop]: systemc: Delete authors lists from systemc files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25410 )


Change subject: systemc: Delete authors lists from systemc files.
..

systemc: Delete authors lists from systemc files.

Change-Id: I6c6219732029d5a9db1d317c130086cf2d16a272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25410
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/systemc/SConscript
M src/systemc/SConsopts
M src/systemc/Tlm.py
M src/systemc/channel/SConscript
M src/systemc/channel/messages.cc
M src/systemc/channel/sc_clock.cc
M src/systemc/channel/sc_event_queue.cc
M src/systemc/channel/sc_in_resolved.cc
M src/systemc/channel/sc_inout_resolved.cc
M src/systemc/channel/sc_mutex.cc
M src/systemc/channel/sc_out_resolved.cc
M src/systemc/channel/sc_semaphore.cc
M src/systemc/channel/sc_signal.cc
M src/systemc/channel/sc_signal_resolved.cc
M src/systemc/core/SConscript
M src/systemc/core/SystemC.py
M src/systemc/core/channel.cc
M src/systemc/core/channel.hh
M src/systemc/core/event.cc
M src/systemc/core/event.hh
M src/systemc/core/kernel.cc
M src/systemc/core/kernel.hh
M src/systemc/core/list.hh
M src/systemc/core/messages.cc
M src/systemc/core/module.cc
M src/systemc/core/module.hh
M src/systemc/core/object.cc
M src/systemc/core/object.hh
M src/systemc/core/port.cc
M src/systemc/core/port.hh
M src/systemc/core/process.cc
M src/systemc/core/process.hh
M src/systemc/core/process_types.hh
M src/systemc/core/python.cc
M src/systemc/core/python.hh
M src/systemc/core/sc_attr.cc
M src/systemc/core/sc_event.cc
M src/systemc/core/sc_export.cc
M src/systemc/core/sc_interface.cc
M src/systemc/core/sc_join.cc
M src/systemc/core/sc_main.cc
M src/systemc/core/sc_main_fiber.cc
M src/systemc/core/sc_main_fiber.hh
M src/systemc/core/sc_main_python.cc
M src/systemc/core/sc_module.cc
M src/systemc/core/sc_module_name.cc
M src/systemc/core/sc_object.cc
M src/systemc/core/sc_port.cc
M src/systemc/core/sc_prim.cc
M src/systemc/core/sc_process_handle.cc
M src/systemc/core/sc_sensitive.cc
M src/systemc/core/sc_simcontext.cc
M src/systemc/core/sc_spawn.cc
M src/systemc/core/sc_time.cc
M src/systemc/core/sc_time_python.cc
M src/systemc/core/sched_event.cc
M src/systemc/core/sched_event.hh
M src/systemc/core/scheduler.cc
M src/systemc/core/scheduler.hh
M src/systemc/core/sensitivity.cc
M src/systemc/core/sensitivity.hh
M src/systemc/core/time.cc
M src/systemc/core/time.hh
M src/systemc/dt/SConscript
M src/systemc/dt/bit/SConscript
M src/systemc/dt/bit/messages.cc
M src/systemc/dt/fx/SConscript
M src/systemc/dt/fx/messages.cc
M src/systemc/dt/int/SConscript
M src/systemc/dt/int/messages.cc
M src/systemc/dt/misc/SConscript
M src/systemc/dt/sc_mempool.cc
M src/systemc/ext/channel/_channel.hh
M src/systemc/ext/channel/_using.hh
M src/systemc/ext/channel/messages.hh
M src/systemc/ext/channel/sc_buffer.hh
M src/systemc/ext/channel/sc_clock.hh
M src/systemc/ext/channel/sc_event_queue.hh
M src/systemc/ext/channel/sc_fifo.hh
M src/systemc/ext/channel/sc_fifo_in.hh
M src/systemc/ext/channel/sc_fifo_in_if.hh
M src/systemc/ext/channel/sc_fifo_out.hh
M src/systemc/ext/channel/sc_fifo_out_if.hh
M src/systemc/ext/channel/sc_in.hh
M src/systemc/ext/channel/sc_in_resolved.hh
M src/systemc/ext/channel/sc_in_rv.hh
M src/systemc/ext/channel/sc_inout.hh
M src/systemc/ext/channel/sc_inout_resolved.hh
M src/systemc/ext/channel/sc_inout_rv.hh
M src/systemc/ext/channel/sc_mutex.hh
M src/systemc/ext/channel/sc_mutex_if.hh
M src/systemc/ext/channel/sc_out.hh
M src/systemc/ext/channel/sc_out_resolved.hh
M src/systemc/ext/channel/sc_out_rv.hh
M src/systemc/ext/channel/sc_semaphore.hh
M src/systemc/ext/channel/sc_semaphore_if.hh
M src/systemc/ext/channel/sc_signal.hh
M src/systemc/ext/channel/sc_signal_in_if.hh
M src/systemc/ext/channel/sc_signal_inout_if.hh
M src/systemc/ext/channel/sc_signal_resolved.hh
M src/systemc/ext/channel/sc_signal_rv.hh
M src/systemc/ext/core/_core.hh
M src/systemc/ext/core/_using.hh
M src/systemc/ext/core/messages.hh
M src/systemc/ext/core/sc_attr.hh
M src/systemc/ext/core/sc_event.hh
M src/systemc/ext/core/sc_export.hh
M src/systemc/ext/core/sc_interface.hh
M src/systemc/ext/core/sc_join.hh
M src/systemc/ext/core/sc_main.hh
M src/systemc/ext/core/sc_module.hh
M src/systemc/ext/core/sc_module_name.hh
M src/systemc/ext/core/sc_object.hh
M src/systemc/ext/core/sc_port.hh
M src/systemc/ext/core/sc_prim.hh
M src/systemc/ext/core/sc_process_handle.hh
M src/systemc/ext/core/sc_sensitive.hh
M src/systemc/ext/core/sc_simcontext.hh
M src/systemc/ext/core/sc_spawn.hh
M src/systemc/ext/core/sc_time.hh
M src/systemc/ext/dt/_dt.hh
M src/systemc/ext/dt/_using.hh
M src/systemc/ext/dt/bit/_bit.hh
M src/systemc/ext/dt/bit/_using.hh
M src/systemc/ext/dt/bit/messages.hh
M src/systemc/ext/dt/fx/_fx.hh
M src/systemc/ext/dt/fx/_using.hh
M src/systemc/ext/dt/fx/messages.hh
M src/systemc/ext/dt/in

[gem5-dev] Change in gem5/gem5[develop]: sim: Delete authors lists from files in sim.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25411 )


Change subject: sim: Delete authors lists from files in sim.
..

sim: Delete authors lists from files in sim.

Change-Id: I09a6117772c092157bf83701cf853145bb88ccf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25411
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/sim/ClockDomain.py
M src/sim/ClockedObject.py
M src/sim/DVFSHandler.py
M src/sim/InstTracer.py
M src/sim/Process.py
M src/sim/RedirectPath.py
M src/sim/Root.py
M src/sim/SConscript
M src/sim/SubSystem.py
M src/sim/System.py
M src/sim/TickedObject.py
M src/sim/VoltageDomain.py
M src/sim/arguments.cc
M src/sim/arguments.hh
M src/sim/async.cc
M src/sim/async.hh
M src/sim/aux_vector.hh
M src/sim/backtrace.hh
M src/sim/backtrace_glibc.cc
M src/sim/backtrace_none.cc
M src/sim/byteswap.hh
M src/sim/byteswap.test.cc
M src/sim/clock_domain.cc
M src/sim/clock_domain.hh
M src/sim/clocked_object.cc
M src/sim/clocked_object.hh
M src/sim/core.cc
M src/sim/core.hh
M src/sim/cxx_config.cc
M src/sim/cxx_config.hh
M src/sim/cxx_config_ini.cc
M src/sim/cxx_config_ini.hh
M src/sim/cxx_manager.cc
M src/sim/cxx_manager.hh
M src/sim/debug.cc
M src/sim/debug.hh
M src/sim/drain.cc
M src/sim/drain.hh
M src/sim/dvfs_handler.cc
M src/sim/dvfs_handler.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/eventq_impl.hh
M src/sim/faults.cc
M src/sim/faults.hh
M src/sim/fd_array.cc
M src/sim/fd_array.hh
M src/sim/fd_entry.cc
M src/sim/fd_entry.hh
M src/sim/full_system.hh
M src/sim/futex_map.hh
M src/sim/global_event.cc
M src/sim/global_event.hh
M src/sim/guest_abi.hh
M src/sim/guest_abi.test.cc
M src/sim/init.cc
M src/sim/init.hh
M src/sim/init_signals.cc
M src/sim/init_signals.hh
M src/sim/initparam_keys.hh
M src/sim/insttracer.hh
M src/sim/linear_solver.cc
M src/sim/linear_solver.hh
M src/sim/main.cc
M src/sim/mathexpr.cc
M src/sim/mathexpr.hh
M src/sim/microcode_rom.cc
M src/sim/microcode_rom.hh
M src/sim/port.cc
M src/sim/port.hh
M src/sim/power/MathExprPowerModel.py
M src/sim/power/PowerModel.py
M src/sim/power/PowerModelState.py
M src/sim/power/SConscript
M src/sim/power/ThermalDomain.py
M src/sim/power/ThermalModel.py
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/mathexpr_powermodel.hh
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_entity.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.cc
M src/sim/power/thermal_node.hh
M src/sim/probe/Probe.py
M src/sim/probe/SConscript
M src/sim/probe/mem.hh
M src/sim/probe/pmu.hh
M src/sim/probe/probe.cc
M src/sim/probe/probe.hh
M src/sim/process.cc
M src/sim/process.hh
M src/sim/process_impl.hh
M src/sim/pseudo_inst.cc
M src/sim/pseudo_inst.hh
M src/sim/py_interact.cc
M src/sim/py_interact.hh
M src/sim/python.cc
M src/sim/redirect_path.cc
M src/sim/redirect_path.hh
M src/sim/root.cc
M src/sim/root.hh
M src/sim/serialize.cc
M src/sim/serialize.hh
M src/sim/sim_events.cc
M src/sim/sim_events.hh
M src/sim/sim_exit.hh
M src/sim/sim_object.cc
M src/sim/sim_object.hh
M src/sim/simulate.cc
M src/sim/simulate.hh
M src/sim/stat_control.cc
M src/sim/stat_control.hh
M src/sim/stat_register.cc
M src/sim/stat_register.hh
M src/sim/stats.hh
M src/sim/sub_system.cc
M src/sim/sub_system.hh
M src/sim/syscall_debug_macros.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_desc.hh
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/syscall_emul_buf.hh
M src/sim/syscall_return.hh
M src/sim/system.cc
M src/sim/system.hh
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
M src/sim/voltage_domain.cc
M src/sim/voltage_domain.hh
M src/sim/vptr.hh
135 files changed, 5 insertions(+), 352 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/ClockDomain.py b/src/sim/ClockDomain.py
index 4d2b249..aad4736 100644
--- a/src/sim/ClockDomain.py
+++ b/src/sim/ClockDomain.py
@@ -32,10 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Vasileios Spiliopoulos
-#  Akash Bagdia
-#  Stephan Diestelhorst

 from m5.params import *
 from m5.SimObject import SimObject
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 2d61718..3819093 100644
--- a/src/sim/ClockedObject.py
+++ b/src/sim/ClockedObject.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS

[gem5-dev] Change in gem5/gem5[develop]: dev, mips: Delete a large binary file from src/dev/mips.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25404 )


Change subject: dev,mips: Delete a large binary file from src/dev/mips.
..

dev,mips: Delete a large binary file from src/dev/mips.

This file doesn't seem to actually get referred to by anything in gem5,
and additionally MIPS FS mode has a ways to go before it can be used.
If this file is really necessary for running MIPS, it can be retrieved
from the history in the future.

Change-Id: I3a86fc928a4be1c9159f0fafb986dfb06d09bb7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25404
Reviewed-by: Bobby R. Bruce 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
D src/dev/mips/console
1 file changed, 0 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/mips/console b/src/dev/mips/console
deleted file mode 100644
index ec2721c..000
--- a/src/dev/mips/console
+++ /dev/null
Binary files differ

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25404
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a86fc928a4be1c9159f0fafb986dfb06d09bb7b
Gerrit-Change-Number: 25404
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mips: Delete authors lists from mips files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25449 )


Change subject: mips: Delete authors lists from mips files.
..

mips: Delete authors lists from mips files.

Change-Id: I56c054c64fe3d1e39ed5d315b8ac78de2e993dc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25449
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/mips/MipsISA.py
M src/arch/mips/MipsInterrupts.py
M src/arch/mips/MipsSystem.py
M src/arch/mips/MipsTLB.py
M src/arch/mips/SConscript
M src/arch/mips/SConsopts
M src/arch/mips/bare_iron/system.cc
M src/arch/mips/bare_iron/system.hh
M src/arch/mips/decoder.cc
M src/arch/mips/decoder.hh
M src/arch/mips/dsp.cc
M src/arch/mips/dsp.hh
M src/arch/mips/dt_constants.hh
M src/arch/mips/faults.cc
M src/arch/mips/faults.hh
M src/arch/mips/idle_event.cc
M src/arch/mips/idle_event.hh
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/isa/base.isa
M src/arch/mips/isa/bitfields.isa
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/basic.isa
M src/arch/mips/isa/formats/branch.isa
M src/arch/mips/isa/formats/control.isa
M src/arch/mips/isa/formats/dsp.isa
M src/arch/mips/isa/formats/formats.isa
M src/arch/mips/isa/formats/fp.isa
M src/arch/mips/isa/formats/int.isa
M src/arch/mips/isa/formats/mem.isa
M src/arch/mips/isa/formats/mt.isa
M src/arch/mips/isa/formats/noop.isa
M src/arch/mips/isa/formats/tlbop.isa
M src/arch/mips/isa/formats/trap.isa
M src/arch/mips/isa/formats/unimp.isa
M src/arch/mips/isa/formats/unknown.isa
M src/arch/mips/isa/formats/util.isa
M src/arch/mips/isa/includes.isa
M src/arch/mips/isa/main.isa
M src/arch/mips/isa/operands.isa
M src/arch/mips/isa_traits.hh
M src/arch/mips/kernel_stats.hh
M src/arch/mips/linux/aligned.hh
M src/arch/mips/linux/linux.cc
M src/arch/mips/linux/linux.hh
M src/arch/mips/linux/process.cc
M src/arch/mips/linux/process.hh
M src/arch/mips/linux/system.cc
M src/arch/mips/linux/system.hh
M src/arch/mips/linux/thread_info.hh
M src/arch/mips/locked_mem.hh
M src/arch/mips/microcode_rom.hh
M src/arch/mips/mmapped_ipr.hh
M src/arch/mips/mt.hh
M src/arch/mips/mt_constants.hh
M src/arch/mips/pagetable.cc
M src/arch/mips/pagetable.hh
M src/arch/mips/pra_constants.hh
M src/arch/mips/process.cc
M src/arch/mips/process.hh
M src/arch/mips/pseudo_inst.hh
M src/arch/mips/registers.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/mips/stacktrace.cc
M src/arch/mips/stacktrace.hh
M src/arch/mips/system.cc
M src/arch/mips/system.hh
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/mips/types.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
M src/arch/mips/vtophys.cc
M src/arch/mips/vtophys.hh
77 files changed, 0 insertions(+), 221 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index 180d9e6..5194e18 100644
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 from m5.params import *
 from m5.proxy import *
diff --git a/src/arch/mips/MipsInterrupts.py  
b/src/arch/mips/MipsInterrupts.py

index 1065701..fdd7fc7 100644
--- a/src/arch/mips/MipsInterrupts.py
+++ b/src/arch/mips/MipsInterrupts.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.objects.BaseInterrupts import BaseInterrupts

diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index 7a5d8fd..fefc582 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jaidev Patwardhan

 from m5.defines import buildEnv
 from m5.params import *
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 62996cc..d43b6d7 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jaidev Pat

[gem5-dev] Change in gem5/gem5[develop]: sparc: Delete authors lists from sparc files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25452 )


Change subject: sparc: Delete authors lists from sparc files.
..

sparc: Delete authors lists from sparc files.

Change-Id: Iac3f9bb546121c73e6e73a0377d2a917c40df5f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25452
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/sparc/SConscript
M src/arch/sparc/SConsopts
M src/arch/sparc/SparcISA.py
M src/arch/sparc/SparcInterrupts.py
M src/arch/sparc/SparcNativeTrace.py
M src/arch/sparc/SparcSystem.py
M src/arch/sparc/SparcTLB.py
M src/arch/sparc/asi.cc
M src/arch/sparc/asi.hh
M src/arch/sparc/decoder.cc
M src/arch/sparc/decoder.hh
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/sparc/handlers.hh
M src/arch/sparc/insts/SConscript
M src/arch/sparc/insts/blockmem.cc
M src/arch/sparc/insts/blockmem.hh
M src/arch/sparc/insts/branch.cc
M src/arch/sparc/insts/branch.hh
M src/arch/sparc/insts/integer.cc
M src/arch/sparc/insts/integer.hh
M src/arch/sparc/insts/mem.cc
M src/arch/sparc/insts/mem.hh
M src/arch/sparc/insts/micro.cc
M src/arch/sparc/insts/micro.hh
M src/arch/sparc/insts/nop.cc
M src/arch/sparc/insts/nop.hh
M src/arch/sparc/insts/priv.cc
M src/arch/sparc/insts/priv.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/insts/static_inst.hh
M src/arch/sparc/insts/trap.cc
M src/arch/sparc/insts/trap.hh
M src/arch/sparc/insts/unimp.hh
M src/arch/sparc/insts/unknown.hh
M src/arch/sparc/interrupts.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/isa/base.isa
M src/arch/sparc/isa/bitfields.isa
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/formats/basic.isa
M src/arch/sparc/isa/formats/branch.isa
M src/arch/sparc/isa/formats/formats.isa
M src/arch/sparc/isa/formats/integerop.isa
M src/arch/sparc/isa/formats/mem/basicmem.isa
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/isa/formats/mem/mem.isa
M src/arch/sparc/isa/formats/mem/swap.isa
M src/arch/sparc/isa/formats/mem/util.isa
M src/arch/sparc/isa/formats/nop.isa
M src/arch/sparc/isa/formats/priv.isa
M src/arch/sparc/isa/formats/trap.isa
M src/arch/sparc/isa/formats/unimp.isa
M src/arch/sparc/isa/formats/unknown.isa
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/isa/main.isa
M src/arch/sparc/isa/operands.isa
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/kernel_stats.hh
M src/arch/sparc/linux/linux.cc
M src/arch/sparc/linux/linux.hh
M src/arch/sparc/linux/process.cc
M src/arch/sparc/linux/process.hh
M src/arch/sparc/linux/syscalls.cc
M src/arch/sparc/locked_mem.hh
M src/arch/sparc/microcode_rom.hh
M src/arch/sparc/miscregs.hh
M src/arch/sparc/mmapped_ipr.hh
M src/arch/sparc/nativetrace.cc
M src/arch/sparc/nativetrace.hh
M src/arch/sparc/pagetable.cc
M src/arch/sparc/pagetable.hh
M src/arch/sparc/process.cc
M src/arch/sparc/process.hh
M src/arch/sparc/pseudo_inst.hh
M src/arch/sparc/registers.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/remote_gdb.hh
M src/arch/sparc/solaris/process.cc
M src/arch/sparc/solaris/process.hh
M src/arch/sparc/solaris/solaris.cc
M src/arch/sparc/solaris/solaris.hh
M src/arch/sparc/sparc_traits.hh
M src/arch/sparc/stacktrace.hh
M src/arch/sparc/system.cc
M src/arch/sparc/system.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/sparc/tlb_map.hh
M src/arch/sparc/types.hh
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/sparc/vtophys.cc
M src/arch/sparc/vtophys.hh
96 files changed, 1 insertion(+), 257 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index afffd8a..709911d 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-#  Steve Reinhardt

 Import('*')

diff --git a/src/arch/sparc/SConsopts b/src/arch/sparc/SConsopts
index c356062..41aa275 100644
--- a/src/arch/sparc/SConsopts
+++ b/src/arch/sparc/SConsopts
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert

 Import('*')

diff --git a/src/arch/sparc/SparcISA.py b/src/arch/sparc/SparcISA.py
index 5f8f3ce..235fdcc 100644
--- a/src/arch/sparc/SparcISA.py
+++ b/src/arch/sparc/SparcISA.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF

[gem5-dev] Change in gem5/gem5[develop]: hsail: Delete the author list from gpu_isa.hh.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25448 )


Change subject: hsail: Delete the author list from gpu_isa.hh.
..

hsail: Delete the author list from gpu_isa.hh.

Change-Id: I9c90fef4420286dbda7157d8961b4cf3c79a7c27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25448
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/hsail/gpu_isa.hh
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh
index 86af905..75063cb 100644
--- a/src/arch/hsail/gpu_isa.hh
+++ b/src/arch/hsail/gpu_isa.hh
@@ -29,8 +29,6 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

  * POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Anthony Gutierrez
  */

 #ifndef __ARCH_HSAIL_GPU_ISA_HH__

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25448
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9c90fef4420286dbda7157d8961b4cf3c79a7c27
Gerrit-Change-Number: 25448
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
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[gem5-dev] Change in gem5/gem5[develop]: power: Delete the authors lists from the power ISA.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25450 )


Change subject: power: Delete the authors lists from the power ISA.
..

power: Delete the authors lists from the power ISA.

Change-Id: Ib661723a9fcc09dd6e1e68a7c38a99e6d404dc46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25450
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/power/PowerISA.py
M src/arch/power/PowerInterrupts.py
M src/arch/power/PowerTLB.py
M src/arch/power/SConscript
M src/arch/power/SConsopts
M src/arch/power/decoder.cc
M src/arch/power/decoder.hh
M src/arch/power/faults.hh
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/insts/condition.cc
M src/arch/power/insts/condition.hh
M src/arch/power/insts/floating.cc
M src/arch/power/insts/floating.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
M src/arch/power/insts/misc.cc
M src/arch/power/insts/misc.hh
M src/arch/power/insts/static_inst.cc
M src/arch/power/insts/static_inst.hh
M src/arch/power/interrupts.cc
M src/arch/power/interrupts.hh
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/basic.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/condition.isa
M src/arch/power/isa/formats/formats.isa
M src/arch/power/isa/formats/fp.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/misc.isa
M src/arch/power/isa/formats/unimp.isa
M src/arch/power/isa/formats/unknown.isa
M src/arch/power/isa/formats/util.isa
M src/arch/power/isa/includes.isa
M src/arch/power/isa/main.isa
M src/arch/power/isa/operands.isa
M src/arch/power/isa_traits.hh
M src/arch/power/kernel_stats.hh
M src/arch/power/linux/linux.cc
M src/arch/power/linux/linux.hh
M src/arch/power/linux/process.cc
M src/arch/power/linux/process.hh
M src/arch/power/locked_mem.hh
M src/arch/power/microcode_rom.hh
M src/arch/power/miscregs.hh
M src/arch/power/mmapped_ipr.hh
M src/arch/power/pagetable.cc
M src/arch/power/pagetable.hh
M src/arch/power/process.cc
M src/arch/power/process.hh
M src/arch/power/pseudo_inst.hh
M src/arch/power/registers.hh
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
M src/arch/power/stacktrace.cc
M src/arch/power/stacktrace.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/power/types.hh
M src/arch/power/utility.cc
M src/arch/power/utility.hh
M src/arch/power/vtophys.cc
M src/arch/power/vtophys.hh
69 files changed, 0 insertions(+), 187 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/PowerISA.py b/src/arch/power/PowerISA.py
index 82efb9a..81abd9c 100644
--- a/src/arch/power/PowerISA.py
+++ b/src/arch/power/PowerISA.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 from m5.objects.BaseISA import BaseISA

diff --git a/src/arch/power/PowerInterrupts.py  
b/src/arch/power/PowerInterrupts.py

index f7e7e57..443e7ae 100644
--- a/src/arch/power/PowerInterrupts.py
+++ b/src/arch/power/PowerInterrupts.py
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black

 from m5.objects.BaseInterrupts import BaseInterrupts

diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index 5c582b4..7f9a271 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Timothy M. Jones

 from m5.SimObject import SimObject
 from m5.params import *
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 473c312..b4878fd 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -25,8 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Timothy M. Jones

 Import('*')

diff --git a/src/arch/power/SConsopts b/src/arch/power/SConsopts
index d762c2d..851f2ba 100644
--- a/src/arch/power/SConsopts
+++ b/src/arch/power/SConsopts
@@ -25,8 +25,6 @

[gem5-dev] Change in gem5/gem5[develop]: riscv: Delete authors lists from riscv files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25451 )


Change subject: riscv: Delete authors lists from riscv files.
..

riscv: Delete authors lists from riscv files.

Change-Id: I94135c8f0e1baee741d6470cb80b4da5e5f8e673
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25451
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/riscv/RiscvISA.py
M src/arch/riscv/RiscvInterrupts.py
M src/arch/riscv/RiscvSystem.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/SConsopts
M src/arch/riscv/bare_metal/system.cc
M src/arch/riscv/bare_metal/system.hh
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/idle_event.cc
M src/arch/riscv/idle_event.hh
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/amo.cc
M src/arch/riscv/insts/amo.hh
M src/arch/riscv/insts/compressed.cc
M src/arch/riscv/insts/compressed.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/mem.hh
M src/arch/riscv/insts/standard.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/static_inst.cc
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/insts/unknown.hh
M src/arch/riscv/interrupts.cc
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/main.isa
M src/arch/riscv/isa/operands.isa
M src/arch/riscv/isa_traits.hh
M src/arch/riscv/kernel_stats.hh
M src/arch/riscv/linux/linux.cc
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/process.cc
M src/arch/riscv/linux/process.hh
M src/arch/riscv/locked_mem.hh
M src/arch/riscv/microcode_rom.hh
M src/arch/riscv/mmapped_ipr.hh
M src/arch/riscv/pagetable.cc
M src/arch/riscv/pagetable.hh
M src/arch/riscv/pra_constants.hh
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M src/arch/riscv/pseudo_inst.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
M src/arch/riscv/stacktrace.cc
M src/arch/riscv/stacktrace.hh
M src/arch/riscv/system.cc
M src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/riscv/types.hh
M src/arch/riscv/utility.hh
M src/arch/riscv/vtophys.hh
70 files changed, 12 insertions(+), 227 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index dfb42c4..3869174 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -37,10 +37,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg
-#  Sven Karlsson
-#  Alec Roelke

 from m5.objects.BaseISA import BaseISA

diff --git a/src/arch/riscv/RiscvInterrupts.py  
b/src/arch/riscv/RiscvInterrupts.py

index 7e63ded..c3ad370 100644
--- a/src/arch/riscv/RiscvInterrupts.py
+++ b/src/arch/riscv/RiscvInterrupts.py
@@ -26,10 +26,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-#  Sven Karlsson
-#  Alec Roelke

 from m5.objects.BaseInterrupts import BaseInterrupts

diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index ea1defd..7be9ff9 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -26,9 +26,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Alec Roelke
-#  Robert Scheffel

 from m5.params import *

diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index b24fffb..4bcaf67 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -25,9 +25,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Jaidev Patwardhan
-#  Korey Sewell

 from m5.SimObject import SimObject
 from m5.par

[gem5-dev] Change in gem5/gem5[develop]: tests: Delete authors lists from test files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25454 )


Change subject: tests: Delete authors lists from test files.
..

tests: Delete authors lists from test files.

Change-Id: Id3628d34adccf8cc1044195b7209f3b01f061c93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25454
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/SConscript
M tests/configs/alpha_generic.py
M tests/configs/arm_generic.py
M tests/configs/base_config.py
M tests/configs/checkpoint.py
M tests/configs/dram-lowp.py
M tests/configs/learning-gem5-p1-simple.py
M tests/configs/learning-gem5-p1-two-level.py
M tests/configs/memcheck.py
M tests/configs/memtest-filter.py
M tests/configs/memtest-ruby.py
M tests/configs/memtest.py
M tests/configs/minor-timing-mp.py
M tests/configs/minor-timing.py
M tests/configs/o3-timing-checker.py
M tests/configs/o3-timing-mp-ruby.py
M tests/configs/o3-timing-mp.py
M tests/configs/o3-timing-mt.py
M tests/configs/o3-timing-ruby.py
M tests/configs/o3-timing.py
M tests/configs/pc-o3-timing.py
M tests/configs/pc-simple-atomic.py
M tests/configs/pc-simple-timing-ruby.py
M tests/configs/pc-simple-timing.py
M tests/configs/pc-switcheroo-full.py
M tests/configs/realview-minor-dual.py
M tests/configs/realview-minor.py
M tests/configs/realview-o3-checker.py
M tests/configs/realview-o3-dual.py
M tests/configs/realview-o3.py
M tests/configs/realview-simple-atomic-checkpoint.py
M tests/configs/realview-simple-atomic-dual.py
M tests/configs/realview-simple-atomic.py
M tests/configs/realview-simple-timing-dual-ruby.py
M tests/configs/realview-simple-timing-dual.py
M tests/configs/realview-simple-timing-ruby.py
M tests/configs/realview-simple-timing.py
M tests/configs/realview-switcheroo-atomic.py
M tests/configs/realview-switcheroo-full.py
M tests/configs/realview-switcheroo-noncaching-timing.py
M tests/configs/realview-switcheroo-o3.py
M tests/configs/realview-switcheroo-timing.py
M tests/configs/realview64-minor-dual.py
M tests/configs/realview64-minor.py
M tests/configs/realview64-o3-checker.py
M tests/configs/realview64-o3-dual.py
M tests/configs/realview64-o3.py
M tests/configs/realview64-simple-atomic-checkpoint.py
M tests/configs/realview64-simple-atomic-dual.py
M tests/configs/realview64-simple-atomic.py
M tests/configs/realview64-simple-timing-dual-ruby.py
M tests/configs/realview64-simple-timing-dual.py
M tests/configs/realview64-simple-timing-ruby.py
M tests/configs/realview64-simple-timing.py
M tests/configs/realview64-switcheroo-atomic.py
M tests/configs/realview64-switcheroo-full.py
M tests/configs/realview64-switcheroo-o3.py
M tests/configs/realview64-switcheroo-timing.py
M tests/configs/rubytest-ruby.py
M tests/configs/simple-atomic-dummychecker.py
M tests/configs/simple-atomic-mp-ruby.py
M tests/configs/simple-atomic-mp.py
M tests/configs/simple-atomic.py
M tests/configs/simple-timing-mp-ruby.py
M tests/configs/simple-timing-mp.py
M tests/configs/simple-timing-ruby.py
M tests/configs/simple-timing.py
M tests/configs/switcheroo.py
M tests/configs/t1000-simple-atomic.py
M tests/configs/tgen-dram-ctrl.py
M tests/configs/tgen-simple-mem.py
M tests/configs/tsunami-minor-dual.py
M tests/configs/tsunami-minor.py
M tests/configs/tsunami-o3-dual.py
M tests/configs/tsunami-o3.py
M tests/configs/tsunami-simple-atomic-dual.py
M tests/configs/tsunami-simple-atomic.py
M tests/configs/tsunami-simple-timing-dual.py
M tests/configs/tsunami-simple-timing.py
M tests/configs/tsunami-switcheroo-full.py
M tests/configs/twosys-tsunami-simple-atomic.py
M tests/configs/x86_generic.py
M tests/diff-out
M tests/gem5/__init__.py
M tests/gem5/cpu_tests/run.py
M tests/gem5/cpu_tests/test.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/fs/linux/arm/test.py
M tests/gem5/hello_se/test_hello_se.py
M tests/gem5/learning_gem5/part1_test.py
M tests/gem5/learning_gem5/part2_test.py
M tests/gem5/learning_gem5/part3_test.py
M tests/gem5/m5_util/test_exit.py
M tests/gem5/memory/memtest-run.py
M tests/gem5/memory/simple-run.py
M tests/gem5/memory/test.py
M tests/gem5/suite.py
M tests/gem5/test_build/test_build.py
M tests/gem5/verifier.py
M tests/jenkins/presubmit.sh
M tests/legacy-configs/run.py
M tests/long/fs/10.linux-boot/test.py
M tests/long/fs/80.solaris-boot/test.py
M tests/long/se/10.mcf/test.py
M tests/long/se/70.twolf/test.py
M tests/quick/fs/10.linux-boot/test.py
M tests/quick/fs/80.netperf-stream/test.py
M tests/quick/se/00.hello.mp/test.py
M tests/quick/se/01.hello-2T-smt/test.py
M tests/quick/se/02.insttest/test.py
M tests/quick/se/30.eon/test.py
M tests/quick/se/50.memtest/test.py
M tests/quick/se/50.vortex/test.py
M tests/quick/se/51.memcheck/test.py
M tests/quick/se/60.rubytest/test.py
M tests/quick/se/70.tgen/test.py
M tests/quick/se/80.dram-closepage/test.py
M tests/quick/se/80.dram-openpage/test.py
M tests/run

[gem5-dev] Change in gem5/gem5[develop]: misc: Delete authors lists from shared include files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25456 )


Change subject: misc: Delete authors lists from shared include files.
..

misc: Delete authors lists from shared include files.

Change-Id: I65d3d2e8df9799d9d3dc61734265a62b4dc9d67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25456
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M include/gem5/asm/generic/m5op_flags.h
M include/gem5/asm/generic/m5ops.h
M include/gem5/m5ops.h
3 files changed, 0 insertions(+), 11 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/include/gem5/asm/generic/m5op_flags.h  
b/include/gem5/asm/generic/m5op_flags.h

index de44e00..0304b88 100644
--- a/include/gem5/asm/generic/m5op_flags.h
+++ b/include/gem5/asm/generic/m5op_flags.h
@@ -36,10 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
- *  Andreas Sandberg
  */

 #ifndef __GEM5_ASM_GENERIC_M5OP_FLAGS_H__
diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

index 2d7d074..d0ee337 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -36,10 +36,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
- *  Andreas Sandberg
  */

 #ifndef __GEM5_ASM_GENERIC_M5OPS_H__
diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h
index 72223d1..8a35666 100644
--- a/include/gem5/m5ops.h
+++ b/include/gem5/m5ops.h
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *  Ali Saidi
  */

 #ifndef __GEM5_M5OP_H__

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65d3d2e8df9799d9d3dc61734265a62b4dc9d67f
Gerrit-Change-Number: 25456
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: system: Delete authors lists from system source files.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25455 )


Change subject: system: Delete authors lists from system source files.
..

system: Delete authors lists from system source files.

Change-Id: I899bd4d04ad1cbf5ab32d57df88e2a146d2e2e4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25455
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M system/arm/bootloader/arm/boot.S
M system/arm/bootloader/arm/makefile
M system/arm/dt/Makefile
M system/arm/dt/armv7.dts
M system/arm/dt/armv8.dts
M system/arm/dt/armv8_big_little.dts
M system/arm/dt/platforms/vexpress_gem5_v1.dtsi
M system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
10 files changed, 0 insertions(+), 22 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/system/arm/bootloader/arm/boot.S  
b/system/arm/bootloader/arm/boot.S

index 4870ecc..0439eca 100644
--- a/system/arm/bootloader/arm/boot.S
+++ b/system/arm/bootloader/arm/boot.S
@@ -33,8 +33,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
  */

 /*
diff --git a/system/arm/bootloader/arm/makefile  
b/system/arm/bootloader/arm/makefile

index b6e4f32..e8be5f7 100644
--- a/system/arm/bootloader/arm/makefile
+++ b/system/arm/bootloader/arm/makefile
@@ -32,9 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi
-#  Prakash Ramrakhyani


 # Need to have CROSS_COMPILE set to /path/to/bin/arm-unknown-linux-gnu-
diff --git a/system/arm/dt/Makefile b/system/arm/dt/Makefile
index 1bb6870..fb7ac30 100644
--- a/system/arm/dt/Makefile
+++ b/system/arm/dt/Makefile
@@ -23,8 +23,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg

 CPP?=cpp
 DTC?=dtc
diff --git a/system/arm/dt/armv7.dts b/system/arm/dt/armv7.dts
index 96b37ec..adfd968 100644
--- a/system/arm/dt/armv7.dts
+++ b/system/arm/dt/armv7.dts
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 /dts-v1/;
diff --git a/system/arm/dt/armv8.dts b/system/arm/dt/armv8.dts
index e221e6a..a4007b9 100644
--- a/system/arm/dt/armv8.dts
+++ b/system/arm/dt/armv8.dts
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 /dts-v1/;
diff --git a/system/arm/dt/armv8_big_little.dts  
b/system/arm/dt/armv8_big_little.dts

index 347cfe3..63c90ec 100644
--- a/system/arm/dt/armv8_big_little.dts
+++ b/system/arm/dt/armv8_big_little.dts
@@ -24,9 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- *  Gabor Dozsa
  */

 /dts-v1/;
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi

index d9c3877..91e82c0 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
  */

 /include/ "vexpress_gem5_v1_base.dtsi"
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi

index 61a0104..a84e8e3 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

[gem5-dev] No more "Authors" in source files

2020-02-17 Thread Gabe Black

Hi everybody. This was brought up for discussion a while ago, but the
consensus was to remove Authors from source files since it was frequently
unclear when to update the list, and they were frequently out of date or
incomplete. Who contributed what is accurately recorded by git, and the
history shows what parts of what files were written by which authors.

Most of the Authors lists have been removed (
https://gem5-review.googlesource.com/c/public/gem5/+/25457/1 still needs
a +2!), and when making new files in the future, please do not include one.

Thanks!
Gabe
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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove mention of ALPHA from the SConstruct.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25463 )


Change subject: scons: Remove mention of ALPHA from the SConstruct.
..

scons: Remove mention of ALPHA from the SConstruct.

I've arbitrarily chosen to make ARM the default ISA for now, since I
think it's the best supported ISA with X86 somewhere a little behind
it. As a compromise, I change all mention of ALPHA (or even ALPHA_SE!)
in comments to be X86 instead, so it gets some attention too.

Change-Id: I1d8edc7925ca2d94f11b26e2c0b9314216e9b97d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25463
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M SConstruct
1 file changed, 10 insertions(+), 10 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 6a45752..2ecbaf6 100755
--- a/SConstruct
+++ b/SConstruct
@@ -46,7 +46,7 @@
 #
 # While in this directory ('gem5'), just type 'scons' to build the default
 # configuration (see below), or type 'scons build//'
-# to build some other configuration (e.g., 'build/ALPHA/gem5.opt' for
+# to build some other configuration (e.g., 'build/X86/gem5.opt' for
 # the optimized full-system version).
 #
 # You can build gem5 in a different directory as long as there is a
@@ -58,15 +58,15 @@
 #
 #   The following two commands are equivalent.  The '-u' option tells
 #   scons to search up the directory tree for this SConstruct file.
-#   % cd /gem5 ; scons build/ALPHA/gem5.debug
-#   % cd /gem5/build/ALPHA; scons -u gem5.debug
+#   % cd /gem5 ; scons build/X86/gem5.debug
+#   % cd /gem5/build/X86; scons -u gem5.debug
 #
 #   The following two commands are equivalent and demonstrate building
 #   in a directory outside of the source tree.  The '-C' option tells
 #   scons to chdir to the specified directory to find this SConstruct
 #   file.
-#   % cd /gem5 ; scons /local/foo/build/ALPHA/gem5.debug
-#   % cd /local/foo/build/ALPHA; scons -C /gem5 gem5.debug
+#   % cd /gem5 ; scons /local/foo/build/X86/gem5.debug
+#   % cd /local/foo/build/X86; scons -C /gem5 gem5.debug
 #
 # You can use 'scons -H' to print scons options.  If you're in this
 # 'gem5' directory (or use -u or -C to tell scons where to find this
@@ -196,7 +196,7 @@
 ###

 # Find default configuration & binary.
-Default(environ.get('M5_DEFAULT_BINARY', 'build/ALPHA/gem5.debug'))
+Default(environ.get('M5_DEFAULT_BINARY', 'build/ARM/gem5.debug'))

 # helper function: find last occurrence of element in list
 def rfind(l, elt, offs = -1):
@@ -227,8 +227,8 @@

 # Each target must have 'build' in the interior of the path; the
 # directory below this will determine the build parameters.  For
-# example, for target 'foo/bar/build/ALPHA_SE/arch/alpha/blah.do' we
-# recognize that ALPHA_SE specifies the configuration because it
+# example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
+# recognize that X86 specifies the configuration because it
 # follow 'build' in the build path.

 # The funky assignment to "[:]" is needed to replace the list contents
@@ -274,7 +274,7 @@

 #
 # Set up global sticky variables... these are common to an entire build
-# tree (not specific to a particular build like ALPHA_SE)
+# tree (not specific to a particular build like X86)
 #

 global_vars_file = joinpath(build_root, 'variables.global')
@@ -1151,7 +1151,7 @@
 env['BUILDDIR'] = variant_path

 # variant_dir is the tail component of build path, and is used to
-# determine the build parameters (e.g., 'ALPHA_SE')
+# determine the build parameters (e.g., 'X86')
 (build_root, variant_dir) = splitpath(variant_path)

 # Set env variables according to the build directory config.

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Gerrit-Change-Id: I1d8edc7925ca2d94f11b26e2c0b9314216e9b97d
Gerrit-Change-Number: 25463
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove arch-alpha from the MAINTAINERS file.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25461 )


Change subject: misc: Remove arch-alpha from the MAINTAINERS file.
..

misc: Remove arch-alpha from the MAINTAINERS file.

This architecture no longer exists in gem5, and so doesn't need a
maintainer.

Change-Id: I41cfba1e60d24fd4016953addfb7933993bce98b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25461
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M MAINTAINERS
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/MAINTAINERS b/MAINTAINERS
index 6ee1e93..949657d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25,7 +25,6 @@

 arch: General architecture-specific components
   Gabe Black 
-arch-alpha:
 arch-arm:
   Andreas Sandberg 
   Giacomo Travaglini 

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Gerrit-Change-Number: 25461
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove mention of ALPHA from the README.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25462 )


Change subject: misc: Remove mention of ALPHA from the README.
..

misc: Remove mention of ALPHA from the README.

Change-Id: Ic0faf22e5ed94cf7e7591175a808c4696de29e25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25462
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M README
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/README b/README
index 44a97ba..e24e7a3 100644
--- a/README
+++ b/README
@@ -14,9 +14,9 @@
 for more details concerning the minimum versions of the aforementioned  
tools.


 Once you have all dependencies resolved, type 'scons
-build//gem5.opt' where ARCH is one of ALPHA, ARM, NULL, MIPS,
-POWER, SPARC, or X86. This will build an optimized version of the gem5
-binary (gem5.opt) for the the specified architecture. See
+build//gem5.opt' where ARCH is one of ARM, NULL, MIPS, POWER, SPARC,
+or X86. This will build an optimized version of the gem5 binary (gem5.opt)
+for the the specified architecture. See
 http://www.gem5.org/documentation/general_docs/building for more details  
and

 options.


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Gerrit-Change-Id: Ic0faf22e5ed94cf7e7591175a808c4696de29e25
Gerrit-Change-Number: 25462
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Delete some test files which are specific to Alpha.

2020-02-17 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25458 )


Change subject: tests: Delete some test files which are specific to Alpha.
..

tests: Delete some test files which are specific to Alpha.

Change-Id: Idbffab70abdbb59817c6e002e26b8cb0fa96a4e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25458
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
D tests/configs/alpha_generic.py
D tests/configs/tsunami-minor-dual.py
D tests/configs/tsunami-minor.py
D tests/configs/tsunami-o3-dual.py
D tests/configs/tsunami-o3.py
D tests/configs/tsunami-simple-atomic-dual.py
D tests/configs/tsunami-simple-atomic.py
D tests/configs/tsunami-simple-timing-dual.py
D tests/configs/tsunami-simple-timing.py
D tests/configs/tsunami-switcheroo-full.py
D tests/configs/twosys-tsunami-simple-atomic.py
D tests/test-progs/hello/bin/alpha/linux/hello
12 files changed, 0 insertions(+), 581 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/alpha_generic.py b/tests/configs/alpha_generic.py
deleted file mode 100644
index 0cef339..000
--- a/tests/configs/alpha_generic.py
+++ /dev/null
@@ -1,99 +0,0 @@
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import ABCMeta, abstractmethod
-import m5
-from m5.objects import *
-from m5.proxy import *
-m5.util.addToPath('../configs/')
-from common import FSConfig, SysPaths
-from common.Caches import *
-from base_config import *
-
-class LinuxAlphaSystemBuilder(object):
-"""Mix-in that implements create_system.
-
-This mix-in is intended as a convenient way of adding an
-Alpha-specific create_system method to a class deriving from one of
-the generic base systems.
-"""
-def __init__(self):
-"""
-Arguments:
-  machine_type -- String describing the platform to simulate
-"""
-pass
-
-def create_system(self):
-system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
-system.kernel = SysPaths.binary('vmlinux')
-self.init_system(system)
-return system
-
-class LinuxAlphaFSSystem(LinuxAlphaSystemBuilder,
- BaseFSSystem):
-"""Basic Alpha full system builder."""
-
-def __init__(self, **kwargs):
-"""Initialize an Alpha system that supports full system simulation.
-
-Note: Keyword arguments that are not listed below will be
-passed to the BaseFSSystem.
-
-Keyword Arguments:
-  -
-"""
-BaseSystem.__init__(self, **kwargs)
-LinuxAlphaSystemBuilder.__init__(self)
-
-class LinuxAlphaFSSystemUniprocessor(LinuxAlphaSystemBuilder,
- BaseFSSystemUniprocessor):
-"""Basic Alpha full system builder for

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