[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: merged changes from RISCV-test upstream repo.
Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28729 ) Change subject: arch-riscv,tests: merged changes from RISCV-test upstream repo. .. arch-riscv,tests: merged changes from RISCV-test upstream repo. Change-Id: Ied7c34fedc99657e667bddaf3f3521e5a8f96a6e --- M tests/test-progs/asmtest/src/riscv/env/encoding.h M tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h M tests/test-progs/asmtest/src/riscv/env/v/entry.S M tests/test-progs/asmtest/src/riscv/env/v/riscv_test.h M tests/test-progs/asmtest/src/riscv/env/v/vm.c M tests/test-progs/asmtest/src/riscv/isa/macros/scalar/test_macros.h M tests/test-progs/asmtest/src/riscv/isa/rv64mi/access.S M tests/test-progs/asmtest/src/riscv/isa/rv64mi/breakpoint.S M tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S M tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag M tests/test-progs/asmtest/src/riscv/isa/rv64si/csr.S M tests/test-progs/asmtest/src/riscv/isa/rv64si/dirty.S A tests/test-progs/asmtest/src/riscv/isa/rv64si/icache-alias.S M tests/test-progs/asmtest/src/riscv/isa/rv64si/ma_fetch.S M tests/test-progs/asmtest/src/riscv/isa/rv64si/scall.S M tests/test-progs/asmtest/src/riscv/isa/rv64ua/lrsc.S M tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag M tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmin.S M tests/test-progs/asmtest/src/riscv/isa/rv64ud/structural.S M tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmin.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/jalr.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sll.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/slli.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/slliw.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sllw.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sra.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sraiw.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/sraw.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srl.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srli.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srliw.S M tests/test-progs/asmtest/src/riscv/isa/rv64ui/srlw.S 32 files changed, 1,781 insertions(+), 165 deletions(-) diff --git a/tests/test-progs/asmtest/src/riscv/env/encoding.h b/tests/test-progs/asmtest/src/riscv/env/encoding.h index c109ce1..769b0d0 100644 --- a/tests/test-progs/asmtest/src/riscv/env/encoding.h +++ b/tests/test-progs/asmtest/src/riscv/env/encoding.h @@ -1,4 +1,4 @@ -// See LICENSE for license details. +/* See LICENSE for license details. */ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H @@ -12,7 +12,7 @@ #define MSTATUS_HPIE0x0040 #define MSTATUS_MPIE0x0080 #define MSTATUS_SPP 0x0100 -#define MSTATUS_HPP 0x0600 +#define MSTATUS_VS 0x0600 #define MSTATUS_MPP 0x1800 #define MSTATUS_FS 0x6000 #define MSTATUS_XS 0x00018000 @@ -32,6 +32,7 @@ #define SSTATUS_UPIE0x0010 #define SSTATUS_SPIE0x0020 #define SSTATUS_SPP 0x0100 +#define SSTATUS_VS 0x0600 #define SSTATUS_FS 0x6000 #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x0004 @@ -40,6 +41,9 @@ #define SSTATUS_UXL 0x0003 #define SSTATUS64_SD0x8000 +#define USTATUS_UIE 0x0001 +#define USTATUS_UPIE0x0010 + #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET(1<<29) #define DCSR_FULLRESET (1<<28) @@ -95,12 +99,15 @@ #define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 +#define MIP_USIP(1 << IRQ_U_SOFT) #define MIP_SSIP(1 << IRQ_S_SOFT) #define MIP_HSIP(1 << IRQ_H_SOFT) #define MIP_MSIP(1 << IRQ_M_SOFT) +#define MIP_UTIP(1 << IRQ_U_TIMER) #define MIP_STIP(1 << IRQ_S_TIMER) #define MIP_HTIP(1 << IRQ_H_TIMER) #define MIP_MTIP(1 << IRQ_M_TIMER) +#define MIP_UEIP(1 << IRQ_U_EXT) #define MIP_SEIP(1 << IRQ_S_EXT) #define MIP_HEIP(1 << IRQ_H_EXT) #define MIP_MEIP(1 << IRQ_M_EXT) @@ -138,12 +145,15 @@ #define PMP_NA4 0x10 #define PMP_NAPOT 0x18 +#define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 #define IRQ_S_TIMER 5 #define IRQ_H_TIMER 6 #define IRQ_M_TIMER 7 +#define IRQ_U_EXT8 #define IRQ_S_EXT9 #define IRQ_H_EXT10 #define IRQ_M_EXT11 @@ -156,16 +166,16 @@ #define EXT_IO_BASE0x4000 #define DRAM_BASE 0x8000 -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Acc
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: base,sim: allow m5writeFile with stdout/stderr.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28727 )
Change subject: base,sim: allow m5writeFile with stdout/stderr.
..
base,sim: allow m5writeFile with stdout/stderr.
If m5writeFile opens stdout/stderr, no file is registered in
OutputDirectory and thus we don't want to search for it on close.
In order to write multiple times to stdout/stderr in a reasonable way,
we also want to prevent seeking. Thus, don't seek if the offset is 0, in
which case this would be a noop anyway (we just opened the file without
append).
Finally, it is helpful for debugging if the stream is flushed on every
write.
Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
---
M src/base/output.cc
M src/sim/pseudo_inst.cc
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/base/output.cc b/src/base/output.cc
index ec94a13..47b8aa7 100644
--- a/src/base/output.cc
+++ b/src/base/output.cc
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -142,6 +143,11 @@
void
OutputDirectory::close(OutputStream *file)
{
+if (file == &stdout || file == &stderr) {
+file->stream()->flush();
+return;
+}
+
auto i = files.find(file->name());
if (i == files.end())
fatal("Attempted to close an unregistred file stream");
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index c65fdc0..b11a5a4 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2010-2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -425,8 +426,10 @@
if (!os)
panic("could not open file %s\n", filename);
-// seek to offset
-os->seekp(offset);
+if (offset != 0) {
+// seek to offset
+os->seekp(offset);
+}
// copy out data and write to file
char *buf = new char[len];
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
Gerrit-Change-Number: 28727
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run p tests.
Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28730 ) Change subject: arch-riscv,tests: run p tests. .. arch-riscv,tests: run p tests. This commit enables the p tests (using physical memory) of the test suite. We use the pseudo instruction m5writefile to report success/failure to a dedicated file and m5exit to shutdown. The test based on timer ticks has been disabled, because RISC-V has no timer yet. Change-Id: I0f0e6d6c20210a02411aac0b8d4e85c27f0d904d --- M tests/test-progs/asmtest/src/riscv/Makefile M tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h M tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag M tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S M tests/test-progs/asmtest/src/riscv/isa/rv64si/Makefrag 5 files changed, 31 insertions(+), 8 deletions(-) diff --git a/tests/test-progs/asmtest/src/riscv/Makefile b/tests/test-progs/asmtest/src/riscv/Makefile index c1fe47d..7b54251 100644 --- a/tests/test-progs/asmtest/src/riscv/Makefile +++ b/tests/test-progs/asmtest/src/riscv/Makefile @@ -45,6 +45,11 @@ define compile_template +$$($(1)_p_tests): $(1)-p-%: $(1)/%.S + mkdir -p $(bin_dir) + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $(bin_dir)/$$@ +$(1)_p_env_tests += $$($(1)_p_tests) + $$($(1)_ps_tests): $(1)-ps-%: $(1)/%.S mkdir -p $(bin_dir) $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/ps -I$(src_dir)/macros/scalar -I$(src_dir)/macros/mt -T$(src_dir)/../env/ps/link.ld $$< -o $(bin_dir)/$$@ @@ -73,12 +78,15 @@ $(eval $(call compile_template,rv64uamt,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64samt,-march=rv64g -mabi=lp64)) +p_env_tests_dump = $(addsuffix .dump, $(p_env_tests)) ps_env_tests_dump = $(addsuffix .dump, $(ps_env_tests)) # # Targets -all: ps +all: p ps +# build tests with p environment +p: $(p_env_tests_dump) # build tests with ps environment ps:$(ps_env_tests_dump) diff --git a/tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h b/tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h index 2b9aad3..661b2c5 100644 --- a/tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h +++ b/tests/test-progs/asmtest/src/riscv/env/p/riscv_test.h @@ -188,7 +188,19 @@ /* some unhandlable exception occurred */ \ 1:ori TESTNUM, TESTNUM, 1337; \ write_tohost: \ -sw TESTNUM, tohost, t5; \ +mv a1, TESTNUM; \ +/* 1 = success; otherwise (a0 >> 1) is the failed test */ \ +srl a1, a1, 1; \ +la a0, tohost_data; \ +sb a1, 0(a0); \ +/* write exit code (binary) to file */ \ +li a1, 1; \ +li a2, 0; \ +la a3, tohost_file; \ +.long 0x9E7B; \ +/* shutdown gem5 */ \ +li a0, 0; \ +.long 0x427B; \ j write_tohost; \ reset_vector: \ INIT_XREG; \ @@ -253,7 +265,11 @@ // Data Section Macro //--- -#define EXTRA_DATA +#define EXTRA_DATA \ +tohost_file:\ +.asciz "exitcode"; \ +tohost_data:\ +.byte 0; #define RVTEST_DATA_BEGIN \ EXTRA_DATA \ diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag index b0ddefe..c81c24e 100644 --- a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag @@ -13,7 +13,6 @@ scall \ sbreak \ -rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests)) -
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: run v tests.
Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28731 )
Change subject: arch-riscv,tests: run v tests.
..
arch-riscv,tests: run v tests.
This commit enables the v tests (using virtual memory) in the test
suite. As for the p tests, success/failure is reported by m5writefile to
a dedicated file. Additionally, failed asserts are reported via the
m5writefile to stdout.
Change-Id: I4fcb8b9cdf0d58460fb90de869fba8c6c8c428a1
---
M tests/test-progs/asmtest/src/riscv/Makefile
M tests/test-progs/asmtest/src/riscv/env/v/vm.c
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/tests/test-progs/asmtest/src/riscv/Makefile
b/tests/test-progs/asmtest/src/riscv/Makefile
index 7b54251..4a22ae5 100644
--- a/tests/test-progs/asmtest/src/riscv/Makefile
+++ b/tests/test-progs/asmtest/src/riscv/Makefile
@@ -55,6 +55,11 @@
$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/ps
-I$(src_dir)/macros/scalar -I$(src_dir)/macros/mt
-T$(src_dir)/../env/ps/link.ld $$< -o $(bin_dir)/$$@
$(1)_ps_env_tests += $$($(1)_ps_tests)
+$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
+ mkdir -p $(bin_dir)
+ $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ |
md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v
-I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld
$(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $(bin_dir)/$$@
+$(1)_v_env_tests += $$($(1)_v_tests)
+
$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
$(1): $$($(1)_tests_dump)
@@ -80,15 +85,18 @@
p_env_tests_dump = $(addsuffix .dump, $(p_env_tests))
ps_env_tests_dump = $(addsuffix .dump, $(ps_env_tests))
+v_env_tests_dump = $(addsuffix .dump, $(v_env_tests))
#
# Targets
-all: p ps
+all: p ps v
# build tests with p environment
p: $(p_env_tests_dump)
# build tests with ps environment
ps:$(ps_env_tests_dump)
+# build tests with v environment
+v: $(v_env_tests_dump)
#
# Clean up
diff --git a/tests/test-progs/asmtest/src/riscv/env/v/vm.c
b/tests/test-progs/asmtest/src/riscv/env/v/vm.c
index 6bf05f7..5352dca 100644
--- a/tests/test-progs/asmtest/src/riscv/env/v/vm.c
+++ b/tests/test-progs/asmtest/src/riscv/env/v/vm.c
@@ -17,47 +17,47 @@
void trap_entry();
void pop_tf(trapframe_t*);
-volatile uint64_t tohost;
-volatile uint64_t fromhost;
-
-static void do_tohost(uint64_t tohost_value)
-{
- while (tohost)
-fromhost = 0;
- tohost = tohost_value;
-}
-
#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)
#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r"
(addr) : "memory")
+static const char *stdoutFile = "stdout";
+static const char *exitcodeFile = "exitcode";
+
static uint64_t lfsr63(uint64_t x)
{
uint64_t bit = (x ^ (x >> 1)) & 1;
return (x >> 1) | (bit << 62);
}
-static void cputchar(int x)
+static void cputchar(const char *file, int x)
{
- do_tohost(0x0101 | (unsigned char)x);
+ volatile char c = x;
+ register word_t a0 asm("a0") = (uintptr_t)(&c);
+ register word_t a1 asm("a1") = 1;
+ register word_t a2 asm("a2") = 0;
+ register word_t a3 asm("a3") = (uintptr_t)file;
+ asm volatile (".long 0x9E7B" : : "r"(a0), "r"(a1), "r"(a2), "r"(a3));
}
static void cputstring(const char* s)
{
while (*s)
-cputchar(*s++);
+cputchar(stdoutFile, *s++);
}
static void terminate(int code)
{
- do_tohost(code);
+ cputchar(exitcodeFile, code >> 1);
+ register word_t a0 asm("a0") = 0;
+ asm volatile (".long 0x427B" : : "r"(a0));
while (1);
}
void wtf()
{
- terminate(841);
+ terminate(255 << 1);
}
#define stringify1(x) #x
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: I4fcb8b9cdf0d58460fb90de869fba8c6c8c428a1
Gerrit-Change-Number: 28731
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: added .gitignore.
Nils Asmussen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28728 ) Change subject: arch-riscv,tests: added .gitignore. .. arch-riscv,tests: added .gitignore. Change-Id: I4377468acf906fbe1f3ca2baa5f0c2aa2941b501 --- A tests/test-progs/asmtest/.gitignore 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/tests/test-progs/asmtest/.gitignore b/tests/test-progs/asmtest/.gitignore new file mode 100644 index 000..84ff6ec --- /dev/null +++ b/tests/test-progs/asmtest/.gitignore @@ -0,0 +1,2 @@ +bin/* +dump/* -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28728 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I4377468acf906fbe1f3ca2baa5f0c2aa2941b501 Gerrit-Change-Number: 28728 Gerrit-PatchSet: 1 Gerrit-Owner: Nils Asmussen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Updated resources bucket url to version 20
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28708 ) Change subject: misc: Updated resources bucket url to version 20 .. misc: Updated resources bucket url to version 20 This will fix this v20.0.0.0 of gem5 to the v20 gem5 resources bucket subdirectory. Change-Id: I0c1f1a2c28c18e684bcb009d1650f9e9d2950a93 --- M ext/testlib/config.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ext/testlib/config.py b/ext/testlib/config.py index 348d0a8..189f7c1 100644 --- a/ext/testlib/config.py +++ b/ext/testlib/config.py @@ -220,7 +220,7 @@ os.pardir)) defaults.result_path = os.path.join(os.getcwd(), '.testing-results') defaults.list_only_failed = False -defaults.resource_url = 'http://dist.gem5.org/dist/develop' +defaults.resource_url = 'http://dist.gem5.org/dist/v20' def define_constants(constants): ''' -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28708 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I0c1f1a2c28c18e684bcb009d1650f9e9d2950a93 Gerrit-Change-Number: 28708 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Updated version to 20.0.0.0
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28707 ) Change subject: misc: Updated version to 20.0.0.0 .. misc: Updated version to 20.0.0.0 Change-Id: I5ba4a6e728b2daccea898685d3c27b0f7c7a02cd --- M src/base/version.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/base/version.cc b/src/base/version.cc index 7182b55..c5fbca0 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -26,4 +26,4 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -const char *gem5Version = "[develop]"; +const char *gem5Version = "20.0.0.0"; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28707 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I5ba4a6e728b2daccea898685d3c27b0f7c7a02cd Gerrit-Change-Number: 28707 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: scons: Update python-config flags for python3.8
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28687 )
Change subject: scons: Update python-config flags for python3.8
..
scons: Update python-config flags for python3.8
Starting in python 3.8 the python3-config utility requires the --embed
flag to output -lpython3.8. Without this flag, gem5 won't link to the
python library.
More details: https://bugs.python.org/issue36721
https://github.com/python/cpython/pull/13500
Change-Id: Id9c63577dcd2defa7ae62cc32e042c4a245e7082
Signed-off-by: Jason Lowe-Power
---
M SConstruct
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/SConstruct b/SConstruct
index ba4affa..31b3503 100755
--- a/SConstruct
+++ b/SConstruct
@@ -683,8 +683,14 @@
# Read the linker flags and split them into libraries and other link
# flags. The libraries are added later through the call the CheckLib.
-py_ld_flags = readCommand([python_config, '--ldflags'],
-exception='').split()
+# Note: starting in Python 3.8 the --embed flag is required to get the
+# -lpython3.8 linker flag
+py_ld_flags = readCommand([python_config, '--ldflags', '--embed'],
+ exception='').split()
+if py_ld_flags[0] == "Usage:":
+# If --embed isn't detected then we're running python <3.8
+py_ld_flags = readCommand([python_config, '--ldflags'],
+ exception='').split()
py_libs = []
for lib in py_ld_flags:
if not lib.startswith('-l'):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Id9c63577dcd2defa7ae62cc32e042c4a245e7082
Gerrit-Change-Number: 28687
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28667 )
Change subject: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
..
mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.
Issue-On: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28667
Reviewed-by: Timothy Hayes
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M src/mem/ruby/SConscript
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
R src/mem/ruby/structures/RubyPrefetcher.cc
R src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
M src/mem/ruby/structures/SConscript
M src/mem/slicc/symbols/StateMachine.py
11 files changed, 19 insertions(+), 15 deletions(-)
Approvals:
Timothy Hayes: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index 61d6c52..0bd893e 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -121,7 +121,7 @@
clk_domain = system.cpu[i].clk_domain
# Ruby prefetcher
-prefetcher = RubyPrefetcher.Prefetcher(
+prefetcher = RubyPrefetcher(
num_streams=16,
unit_filter = 256,
nonunit_filter = 256,
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index 8d2e01f..3ddf8ef 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -78,7 +78,7 @@
start_index_bit = block_size_bits,
is_icache = False)
-prefetcher = RubyPrefetcher.Prefetcher()
+prefetcher = RubyPrefetcher()
# the ruby random tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 8c22ae4..fc90f8a 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -126,7 +126,7 @@
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
-MakeInclude('structures/Prefetcher.hh')
+MakeInclude('structures/RubyPrefetcher.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')
MakeInclude('structures/WireBuffer.hh')
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 3639ef2..4de4a29 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,7 +46,7 @@
Cycles response_latency := 2;
bool send_evictions;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
bool enable_prefetch := "False";
// From this node's L0 cache to the network
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 7c83478..3e3580f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -30,7 +30,7 @@
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
Cycles l1_response_latency := 2;
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..6ab0f3f 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -246,7 +246,7 @@
bool isSet(Addr);
}
-structure (Prefetcher, external = "yes") {
+structure (RubyPrefetcher, external = "yes") {
void observeMiss(Addr, RubyRequestType);
void observePfHit(Addr);
void observePfMiss(Addr);
diff --git a/src/mem/ruby/structures/Prefetcher.cc
b/src/mem/ruby/structures/RubyPrefetcher.cc
similarity index 99%
rename from src/mem/ruby/structures/Prefetcher.cc
rename to src/mem/ruby/structures/RubyPrefetcher.cc
index 0602115..8646b99 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -38,7 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "mem/ruby/structures/Prefetcher.hh"
+#include "mem/ruby/structures/RubyPrefetcher.hh"
#in
[gem5-dev] Patchset to optionally reduce the size of stats.txt
At https://gem5-review.googlesource.com/c/public/gem5/+/28630/1 I have created a patchset to optionally reduce the size of stats.txt by making some simple reductions that users can enable from the command line (namely: remove alignment spaces, dumping only stats under selected SimObject subtrees, and dumping names only on first dump) The reductions are described in detail with examples in the commit messages, and further discussion is present at: https://gem5.atlassian.net/browse/GEM5-508 Jason felt that it would be good to also gather feedback from the dev mailing list since stats are so widely used, so of course, let me know if you have any opinions on this. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix possible MOESI_CMP deadlock
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21929 )
Change subject: mem-ruby: fix possible MOESI_CMP deadlock
..
mem-ruby: fix possible MOESI_CMP deadlock
Freeing the L2 block only after local invalidates are acked in the OLSF
state may lead to a deadlock.
Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21929
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 3c7763f..9894107 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -1910,6 +1910,9 @@
i_allocateTBE;
t_recordFwdXID;
ee_sendLocalInv;
+gg_clearLocalSharers;
+checkCacheNoSharersNoOwner;
+rr_deallocateL2CacheBlock;
m_popRequestQueue;
}
@@ -1921,10 +1924,7 @@
transition(OLSF, All_Acks, I) {
c_sendDataFromTBEToFwdGETX;
-gg_clearLocalSharers;
s_deallocateTBE;
-checkCacheNoSharersNoOwner;
-rr_deallocateL2CacheBlock;
n_popTriggerQueue;
wa_wakeUpDependents;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21929
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Gerrit-Change-Number: 21929
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: Timothy Hayes
Gerrit-Reviewer: kokoro
Gerrit-CC: Ciro Santilli
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MOESI_CMP_directory functional reads
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21927 )
Change subject: mem-ruby: fix MOESI_CMP_directory functional reads
..
mem-ruby: fix MOESI_CMP_directory functional reads
This patch properly sets the access permissions in all controllers.
'Busy' was used for all transient states, which is incorrect in lots of
cases when we still hold a valid copy of the line and are able to handle
a functional read.
In the L2 controller these states were split to differentiate the access
permissions:
IFGXX -> IFGXX, IFGXXD
IGMO -> IGMO, IGMOU
IGMIOF -> IGMIOF, IGMIOFD
Same for the dir. controller:
IS -> IS, IS_M
MM -> MM, MM_M
The dir. controllers also has the states WBI/WBS for lines that have
been queued for a writeback. In these states we hold the data in the TBE
for replying to functional reads until the memory acks the write and we
move to I or S.
Other minor changes includes updated debug messages and asserts.
Change-Id: Ie4f6eac3b4d2641ec91ac6b168a0a017f61c0d6f
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21927
Maintainer: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Tested-by: kokoro
---
M configs/ruby/MOESI_CMP_directory.py
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
6 files changed, 220 insertions(+), 106 deletions(-)
Approvals:
Pouya Fotouhi: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MOESI_CMP_directory.py
b/configs/ruby/MOESI_CMP_directory.py
index 2b7770a..315d62b 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -211,6 +211,7 @@
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
+dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
for i, dma_port in enumerate(dma_ports):
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index d7b175c..a29fb5c 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -74,19 +74,20 @@
I, AccessPermission:Invalid, desc="Idle";
S, AccessPermission:Read_Only, desc="Shared";
O, AccessPermission:Read_Only, desc="Owned";
-M, AccessPermission:Read_Only, desc="Modified (dirty)";
-M_W, AccessPermission:Read_Only, desc="Modified (dirty)";
+M, AccessPermission:Read_Write, desc="Modified (dirty)";
+M_W, AccessPermission:Read_Write, desc="Modified (dirty)";
MM, AccessPermission:Read_Write, desc="Modified (dirty and locally
modified)";
MM_W, AccessPermission:Read_Write, desc="Modified (dirty and locally
modified)";
// Transient States
+// Notice we still have a valid copy of the block in most states
IM, AccessPermission:Busy, "IM", desc="Issued GetX";
+IS, AccessPermission:Busy, "IS", desc="Issued GetS";
SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have
an old copy of the line";
OM, AccessPermission:Read_Only, "SM", desc="Issued GetX, received
data";
-IS, AccessPermission:Busy, "IS", desc="Issued GetS";
-SI, AccessPermission:Busy, "OI", desc="Issued PutS, waiting for ack";
-OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
-MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
+SI, AccessPermission:Read_Only, "OI", desc="Issued PutS, waiting for
ack";
+OI, AccessPermission:Read_Only, "OI", desc="Issued PutO, waiting for
ack";
+MI, AccessPermission:Read_Write, "MI", desc="Issued PutX, waiting for
ack";
II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Fwd_GETS or
Fwd_GETX, waiting for ack";
}
@@ -225,13 +226,13 @@
AccessPermission getAccessPermission(Addr addr) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- DPRINTF(RubySlicc, "%s\n",
L1Cache_State_to_permission(tbe.TBEState));
+ DPRINTF(RubySlicc, "%s,%s\n", tbe.TBEState,
L1Cache_State_to_permission(tbe.TBEState));
return L1Cache_State_to_permission(tbe.TBEState);
}
Entry cache_entry := getCacheEntry(addr);
if(is_valid(cache_entry)) {
- DPRINTF(RubySlicc, "%s\n",
L1Cache_State_to_permission(cache_entry.CacheState));
+ DPRINTF(RubySlicc, "%s,%s\n", cache_entry.CacheState,
L1Cache_State_to_permission(cache_entry.CacheState));
return L1Cache_State_to_permission(cache_entry.CacheState);
}
@@ -270,8 +271,10 @@
}
TBE tbe := TBEs[addr];
-num_functional_writes
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fixed MOESI_CMP_directory resource tracking
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21928 )
Change subject: mem-ruby: Fixed MOESI_CMP_directory resource tracking
..
mem-ruby: Fixed MOESI_CMP_directory resource tracking
Fixes a few resource allocation issues in the directory controller:
- Added TBE resource checks on allocation.
- Now also allocating a TBE when issuing read requests to the controller
to allow for a better response to backpressure. Without the TBE as a
limiting factor, the directory can have an unbounded amount of
outstanding memory requests.
- Also allocating a TBE for forwarded requests.
Change-Id: I17016668bd64a50a4354baad5d181e6d3802ac46
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21928
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
2 files changed, 31 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index ff1f91b..3b09cbf 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -459,6 +459,9 @@
action(d_sendDataMsg, "d", desc="Send data to requestor") {
peek(memQueue_in, MemoryMsg) {
+ // Not using tbe here, but we must have allocated on a memory
+ // request
+ assert(is_valid(tbe));
enqueue(responseNetwork_out, ResponseMsg, 1) {
out_msg.addr := address;
out_msg.Sender := machineID;
@@ -596,6 +599,7 @@
action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch
request") {
peek(requestQueue_in, RequestMsg) {
+ assert(is_valid(tbe));
enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
out_msg.addr := address;
out_msg.Type := MemoryRequestType:MEMORY_READ;
@@ -713,6 +717,7 @@
}
action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+check_allocate(TBEs);
peek (requestQueue_in, RequestMsg) {
assert(is_valid(tbe) == false);
TBEs.allocate(address);
@@ -738,12 +743,14 @@
// TRANSITIONS
transition(I, GETX, MM_M) {
allocDirEntry;
+v_allocateTBE;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
transition(I, DMA_READ, XI_M) {
allocDirEntry;
+v_allocateTBE;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
@@ -772,6 +779,7 @@
transition(XI_M, Memory_Data_DMA, I) {
d_sendDataMsg; // ack count may be zero
deallocDirEntry;
+w_deallocateTBE;
q_popMemQueue;
}
@@ -796,6 +804,7 @@
}
transition(S, GETX, MM_M) {
+v_allocateTBE;
qf_queueMemoryFetchRequest;
g_sendInvalidations;
i_popIncomingRequestQueue;
@@ -818,11 +827,19 @@
transition(I, GETS, IS_M) {
allocDirEntry;
+v_allocateTBE;
qf_queueMemoryFetchRequest;
i_popIncomingRequestQueue;
}
- transition({S, SS}, {GETS, DMA_READ}, SS) {
+ transition(S, {GETS, DMA_READ}, SS) {
+v_allocateTBE;
+qf_queueMemoryFetchRequest;
+n_incrementOutstanding;
+i_popIncomingRequestQueue;
+ }
+
+ transition(SS, {GETS, DMA_READ}) {
qf_queueMemoryFetchRequest;
n_incrementOutstanding;
i_popIncomingRequestQueue;
@@ -888,22 +905,26 @@
}
transition(M, GETS, MO) {
+v_allocateTBE;
f_forwardRequest;
i_popIncomingRequestQueue;
}
transition(M, PUTX, MI) {
+v_allocateTBE;
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
// happens if M->O transition happens on-chip
transition(M, PUTO, MI) {
+v_allocateTBE;
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
transition(M, PUTO_SHARERS, MIS) {
+v_allocateTBE;
a_sendWriteBackAck;
i_popIncomingRequestQueue;
}
@@ -924,12 +945,14 @@
}
transition({MM, MO}, Exclusive_Unblock, M) {
+w_deallocateTBE;
cc_clearSharers;
e_ownerIsUnblocker;
j_popIncomingUnblockQueue;
}
transition(MO, Unblock, O) {
+w_deallocateTBE;
m_addUnlockerToSharers;
j_popIncomingUnblockQueue;
}
@@ -943,11 +966,13 @@
}
transition(IS, Unblock, S) {
+w_deallocateTBE;
m_addUnlockerToSharers;
j_popIncomingUnblockQueue;
}
transition(IS, Exclusive_Unblock, M) {
+w_deallocateTBE;
cc_clearSharers;
e_ownerIsUnblocker;
j_popIncomingUnblockQueue;
@@ -960,6 +985,7 @@
}
transition(SS, Last_Unblock, S) {
+w_deallocateTBE;
m_addUnlockerToSharers;
o_decrementOutstanding;
j_popIncomingUnblockQueue;
@@ -980,7 +1006,6 @@
transition(MI, Dirty_Writeback,
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removed unused checkCoherence
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21924 )
Change subject: mem-ruby: removed unused checkCoherence
..
mem-ruby: removed unused checkCoherence
Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21924
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
5 files changed, 0 insertions(+), 20 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fc1f7f3..ff574b5 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -128,7 +128,6 @@
void writeCallbackScFail(Addr, DataBlock);
bool llscCheckMonitor(Addr);
- void checkCoherence(Addr);
void evictionCallback(Addr);
void recordRequestType(SequencerRequestType);
bool checkResourceAvailable(CacheResourceType, Addr);
@@ -148,7 +147,6 @@
Cycles, Cycles, Cycles);
void writeCallback(Addr, MachineType, DataBlock,
Cycles, Cycles, Cycles, bool);
- void checkCoherence(Addr);
void evictionCallback(Addr);
void recordCPReadCallBack(MachineID, MachineID);
void recordCPWriteCallBack(MachineID, MachineID);
@@ -169,7 +167,6 @@
Cycles, Cycles, Cycles, bool);
void invCallback(Addr);
void wbCallback(Addr);
- void checkCoherence(Addr);
void evictionCallback(Addr);
}
diff --git a/src/mem/ruby/system/GPUCoalescer.cc
b/src/mem/ruby/system/GPUCoalescer.cc
index 93275cb..a7b658e 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -976,13 +976,6 @@
<< "]";
}
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-GPUCoalescer::checkCoherence(Addr addr)
-{
-}
void
GPUCoalescer::recordRequestType(SequencerRequestType requestType) {
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 1321173..3230ef1 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -176,7 +176,6 @@
bool empty() const;
void print(std::ostream& out) const;
-void checkCoherence(Addr address);
void markRemoved();
void removeRequest(GPUCoalescerRequest* request);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index de7941a..aa134f4 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -738,14 +738,6 @@
<< "]";
}
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-Sequencer::checkCoherence(Addr addr)
-{
-}
-
void
Sequencer::recordRequestType(SequencerRequestType requestType) {
DPRINTF(RubyStats, "Recorded statistic: %s\n",
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index bb93607..ebca568 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -124,7 +124,6 @@
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
-void checkCoherence(Addr address);
void markRemoved();
void evictionCallback(Addr address);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Gerrit-Change-Number: 21924
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Missing transition in MOESI_CMP_directory
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21925 )
Change subject: mem-ruby: Missing transition in MOESI_CMP_directory
..
mem-ruby: Missing transition in MOESI_CMP_directory
Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21925
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 70035e2..64d67be 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -695,7 +695,7 @@
i_popIncomingRequestQueue;
}
- transition({I, S}, PUTO) {
+ transition({I, S}, {PUTO, PUTO_SHARERS}) {
b_sendWriteBackNack;
i_popIncomingRequestQueue;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Gerrit-Change-Number: 21925
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Deallocating unused entries in MOESI_CMP dir
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27847 )
Change subject: mem-ruby: Deallocating unused entries in MOESI_CMP dir
..
mem-ruby: Deallocating unused entries in MOESI_CMP dir
Invalid entries are never removed from the directory the Directory
controller. This patch fixes this by deallocating the entries
when they become invalid.
Change-Id: I616686a78c5eddb7748192bf94bb691a4f158cbc
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27847
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Pouya Fotouhi
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 78 insertions(+), 35 deletions(-)
Approvals:
Pouya Fotouhi: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 7faa8e0..e8d0863 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -138,70 +138,97 @@
Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+assert(is_valid(dir_entry));
+return dir_entry;
+ }
-if (is_valid(dir_entry)) {
- return dir_entry;
-}
-
-dir_entry := static_cast(Entry, "pointer",
+ Entry allocateDirectoryEntry(Addr addr), return_by_pointer="yes" {
+Entry dir_entry := static_cast(Entry, "pointer",
directory.allocate(addr, new Entry));
return dir_entry;
}
+ void deallocateDirectoryEntry(Addr addr) {
+// Always going to transition from a valid state to I when deallocating
+// Owners and shares must be clear
+assert(getDirectoryEntry(addr).DirectoryState != State:I);
+assert(getDirectoryEntry(addr).Owner.count() == 0);
+assert(getDirectoryEntry(addr).Sharers.count() == 0);
+
+directory.deallocate(addr);
+
+// disable coherence checker
+// sequencer.checkCoherence(addr);
+ }
+
State getState(TBE tbe, Addr addr) {
-return getDirectoryEntry(addr).DirectoryState;
+Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+if (is_valid(dir_entry)) {
+ return dir_entry.DirectoryState;
+}
+else {
+ return State:I;
+}
}
void setState(TBE tbe, Addr addr, State state) {
if (directory.isPresent(addr)) {
- if (state == State:I) {
-assert(getDirectoryEntry(addr).Owner.count() == 0);
-assert(getDirectoryEntry(addr).Sharers.count() == 0);
- }
+ Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
- if (state == State:S) {
-assert(getDirectoryEntry(addr).Owner.count() == 0);
- }
+ if (is_valid(dir_entry)) {
- if (state == State:O) {
-assert(getDirectoryEntry(addr).Owner.count() == 1);
-
assert(getDirectoryEntry(addr).Sharers.isSuperset(getDirectoryEntry(addr).Owner)
== false);
- }
+assert(state != State:I);
- if (state == State:M) {
-assert(getDirectoryEntry(addr).Owner.count() == 1);
-assert(getDirectoryEntry(addr).Sharers.count() == 0);
- }
+if (state == State:S) {
+ assert(dir_entry.Owner.count() == 0);
+}
- if ((state != State:SS) && (state != State:OO)) {
-assert(getDirectoryEntry(addr).WaitingUnblocks == 0);
- }
+if (state == State:O) {
+ assert(dir_entry.Owner.count() == 1);
+ assert(dir_entry.Sharers.isSuperset(dir_entry.Owner) == false);
+}
- if ( (getDirectoryEntry(addr).DirectoryState != State:I) && (state
== State:I) ) {
-getDirectoryEntry(addr).DirectoryState := state;
- // disable coherence checker
-// sequencer.checkCoherence(addr);
- }
- else {
-getDirectoryEntry(addr).DirectoryState := state;
+if (state == State:M) {
+ assert(dir_entry.Owner.count() == 1);
+ assert(dir_entry.Sharers.count() == 0);
+}
+
+if ((state != State:SS) && (state != State:OO)) {
+ assert(dir_entry.WaitingUnblocks == 0);
+}
+
+dir_entry.DirectoryState := state;
+
+ } else {
+assert(state == State:I);
}
}
}
AccessPermission getAccessPermission(Addr addr) {
if (directory.isPresent(addr)) {
- DPRINTF(RubySlicc, "%s\n",
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
- return
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+ Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+ if (is_valid(dir_entry)) {
+DPRINTF(RubySlicc, "%s\n",
Directory_State_to_permission(dir_entry.DirectoryState));
+return Directory_State_to_permissio
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add deallocate to DirectoryMemory
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21920 )
Change subject: mem-ruby: Add deallocate to DirectoryMemory
..
mem-ruby: Add deallocate to DirectoryMemory
Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21920
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/DirectoryMemory.cc
M src/mem/ruby/structures/DirectoryMemory.hh
3 files changed, 21 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..fc1f7f3 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -197,6 +197,7 @@
structure (DirectoryMemory, external = "yes") {
AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
AbstractCacheEntry lookup(Addr);
+ void deallocate(Addr);
bool isPresent(Addr);
void invalidateBlock(Addr);
void recordRequestType(DirectoryRequestType);
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc
b/src/mem/ruby/structures/DirectoryMemory.cc
index e2ee0fc..c6e3ccf 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -127,6 +127,7 @@
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
+assert(m_entries[idx] == NULL);
entry->changePermission(AccessPermission_Read_Only);
m_entries[idx] = entry;
@@ -134,6 +135,20 @@
}
void
+DirectoryMemory::deallocate(Addr address)
+{
+assert(isPresent(address));
+uint64_t idx;
+DPRINTF(RubyCache, "Removing entry for address: %#x\n", address);
+
+idx = mapAddressToLocalIdx(address);
+assert(idx < m_num_entries);
+assert(m_entries[idx] != NULL);
+delete m_entries[idx];
+m_entries[idx] = NULL;
+}
+
+void
DirectoryMemory::print(ostream& out) const
{
}
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh
b/src/mem/ruby/structures/DirectoryMemory.hh
index f879b29..3dd0e95 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017,2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -79,6 +79,9 @@
AbstractCacheEntry *lookup(Addr address);
AbstractCacheEntry *allocate(Addr address, AbstractCacheEntry*
new_entry);
+// Explicitly free up this address
+void deallocate(Addr address);
+
void print(std::ostream& out) const;
void recordRequestType(DirectoryRequestType requestType);
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Gerrit-Change-Number: 21920
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Check on PerfectCacheMemory deallocate
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21921 )
Change subject: mem-ruby: Check on PerfectCacheMemory deallocate
..
mem-ruby: Check on PerfectCacheMemory deallocate
Allowing deallocate to be called for non-existing blocks may hide
potential bugs.
Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21921
Reviewed-by: Pouya Fotouhi
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/structures/PerfectCacheMemory.hh
1 file changed, 14 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh
b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 363e3e8..9898995 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -138,7 +150,8 @@
inline void
PerfectCacheMemory::deallocate(Addr address)
{
-m_map.erase(makeLineAddress(address));
+auto num_erased M5_VAR_USED = m_map.erase(makeLineAddress(address));
+assert(num_erased == 1);
}
// Returns with the physical address of the conflicting cache line
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Gerrit-Change-Number: 21921
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed invalid transition from MOESI_CMP dir
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27848 )
Change subject: mem-ruby: Removed invalid transition from MOESI_CMP dir
..
mem-ruby: Removed invalid transition from MOESI_CMP dir
When memory data is received we always have a valid directory
entry or are in a transient state.
Change-Id: I0e9120e320c157fd306909458cbc446275a4f738
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27848
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index e8d0863..6f868b4 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -905,7 +905,7 @@
j_popIncomingUnblockQueue;
}
- transition({I, S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS},
Memory_Data) {
+ transition({S, O, M, IS, SS, OO, MO, MM, MI, MIS, OS, OSS}, Memory_Data)
{
d_sendDataMsg;
q_popMemQueue;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0e9120e320c157fd306909458cbc446275a4f738
Gerrit-Change-Number: 27848
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removed checkCoherence from MOESI_CMP_directory
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21923 )
Change subject: mem-ruby: removed checkCoherence from MOESI_CMP_directory
..
mem-ruby: removed checkCoherence from MOESI_CMP_directory
The implementation is empty and this is not used by other protocols
Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21923
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
3 files changed, 0 insertions(+), 11 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index b8d8ab4..d7b175c 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -215,7 +215,6 @@
((cache_entry.CacheState != State:O) && (state == State:O)) ) {
cache_entry.CacheState := state;
-sequencer.checkCoherence(addr);
}
else {
cache_entry.CacheState := state;
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 5dfc6a9..0faa03f 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -522,13 +522,6 @@
(state == State:SLS)) {
assert(is_valid(cache_entry));
assert(L2cache.isTagPresent(addr));
-
- if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
- ((cache_entry.CacheState != State:S) && (state == State:S)) ||
- ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
-// disable Coherence Checker for now
-// sequencer.checkCoherence(addr);
- }
} else if ( (state == State:ILS) ||
(state == State:ILX) ||
(state == State:ILO) ||
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 6f868b4..70035e2 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -156,9 +156,6 @@
assert(getDirectoryEntry(addr).Sharers.count() == 0);
directory.deallocate(addr);
-
-// disable coherence checker
-// sequencer.checkCoherence(addr);
}
State getState(TBE tbe, Addr addr) {
--
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Gerrit-Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Gerrit-Change-Number: 21923
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Deallocating unused entries in MOESI_CMP L2
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21922 )
Change subject: mem-ruby: Deallocating unused entries in MOESI_CMP L2
..
mem-ruby: Deallocating unused entries in MOESI_CMP L2
Invalid entries are never removed from the directories in the L2
controller. This patch fixes this by deallocating the entries
when they become invalid. The NP (not present) state was removed
since it's now equivalent to Invalid.
Change-Id: Id807b341a2aadb06008491545aca614d5a09b8df
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21922
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 80 insertions(+), 67 deletions(-)
Approvals:
Pouya Fotouhi: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 18e3b89..5dfc6a9 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -66,14 +66,13 @@
state_declaration(State, desc="L2 Cache states",
default="L2Cache_State_I") {
// Stable states
-NP, AccessPermission:Invalid, desc="Not Present";
I, AccessPermission:Invalid, desc="Invalid";
-ILS, AccessPermission:Invalid, desc="Idle/NP, but local sharers exist";
-ILX, AccessPermission:Invalid, desc="Idle/NP, but local exclusive
exists";
-ILO, AccessPermission:Invalid, desc="Idle/NP, but local owner exists";
-ILOX, AccessPermission:Invalid, desc="Idle/NP, but local owner exists
and chip is exclusive";
-ILOS, AccessPermission:Invalid, desc="Idle/NP, but local owner exists
and local sharers as well";
-ILOSX, AccessPermission:Invalid, desc="Idle/NP, but local owner
exists, local sharers exist, chip is exclusive ";
+ILS, AccessPermission:Invalid, desc="Not present, but local sharers
exist";
+ILX, AccessPermission:Invalid, desc="Not present, but local exclusive
exists";
+ILO, AccessPermission:Invalid, desc="Not present, but local owner
exists";
+ILOX, AccessPermission:Invalid, desc="Not present, but local owner
exists and chip is exclusive";
+ILOS, AccessPermission:Invalid, desc="Not present, but local owner
exists and local sharers as well";
+ILOSX, AccessPermission:Invalid, desc="Not present, but local owner
exists, local sharers exist, chip is exclusive ";
S, AccessPermission:Read_Only, desc="Shared, no local sharers";
O, AccessPermission:Read_Only, desc="Owned, no local sharers";
OLS, AccessPermission:Read_Only, desc="Owned with local sharers";
@@ -324,11 +323,22 @@
void copyDirToCache(Entry cache_entry, Addr addr) {
assert(is_valid(cache_entry));
DirEntry dir_entry := getDirEntry(addr);
+assert(is_valid(dir_entry));
cache_entry.Sharers := dir_entry.Sharers;
cache_entry.Owner := dir_entry.Owner;
cache_entry.OwnerValid := dir_entry.OwnerValid;
}
+ bool isDirEntryClean(DirEntry dir_entry) {
+assert(is_valid(dir_entry));
+return (dir_entry.Sharers.count() == 0) &&
+ (dir_entry.OwnerValid == false);
+ }
+
+ bool isCacheEntryClean(Entry cache_entry) {
+return (cache_entry.Sharers.count() == 0) &&
+ (cache_entry.OwnerValid == false);
+ }
void recordLocalSharerInDir(Entry cache_entry, Addr addr, MachineID
shar_id) {
if (is_valid(cache_entry)) {
@@ -478,7 +488,6 @@
}
State getState(TBE tbe, Entry cache_entry, Addr addr) {
-
if (is_valid(tbe)) {
return tbe.TBEState;
} else if (is_valid(cache_entry)) {
@@ -487,7 +496,7 @@
DirEntry dir_entry := getDirEntry(addr);
return dir_entry.DirState;
} else {
- return State:NP;
+ return State:I;
}
}
@@ -496,45 +505,46 @@
}
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
+// Consistency checks
+
+// Either on the the cache, directory, or invalid
assert((localDirectory.isTagPresent(addr) &&
L2cache.isTagPresent(addr)) == false);
+if (state == State:I) {
+ assert(L2cache.isTagPresent(addr) == false);
+ assert(is_valid(cache_entry) == false);
+ assert(localDirectory.isTagPresent(addr) == false);
+} else if ( (state == State:M) ||
+(state == State:O) ||
+(state == State:S) ||
+(state == State:OLS) ||
+(state == State:OLSX) ||
+(state == State:SLS)) {
+ assert(is_valid(cache_entry));
+ assert(L2cache.isTagPresent(addr));
+
+ if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
+ ((cache_entry.CacheState != State:S) && (state == State:S)) ||
+ ((cache_entry.CacheState !=
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix MOESI_CMP_directory DMA handling
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21926 )
Change subject: mem-ruby: Fix MOESI_CMP_directory DMA handling
..
mem-ruby: Fix MOESI_CMP_directory DMA handling
This patch fixes some issues in the directory controller regarding DMA
handling:
1) Junk data messages were being sent immediately in response to DMA reads
for a line in the S state (one or more sharers, clean). Now, data is
fetched from memory directly and forwarded to the device. Some existing
transitions for handling GETS requests are reused, since it's essentially
the same behavior (except we don't update the list of sharers for DMAs)
2) DMA writes for lines in the I or S states would always overwrite the
whole line. We now check if it's only a partial line write, in which case
we fetch the line from memory, update it, and writeback.
3) Fixed incorrect DMA msg size
Some existing functions were renamed for clarity.
Change-Id: I759344ea4136cd11c3a52f9eaab2e8ce678edd04
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21926
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Pouya Fotouhi
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
2 files changed, 109 insertions(+), 58 deletions(-)
Approvals:
Pouya Fotouhi: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 64d67be..0dfbdb8 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -76,8 +76,9 @@
OS, AccessPermission:Busy, desc="Blocked on a writeback";
OSS, AccessPermission:Busy, desc="Blocked on a writeback, but don't
remove from sharers when received";
-XI_M, AccessPermission:Busy, desc="In a stable state, going to I,
waiting for the memory controller";
-XI_U, AccessPermission:Busy, desc="In a stable state, going to I,
waiting for an unblock";
+XI_M, AccessPermission:Busy, desc="Blocked, going to I, waiting for
the memory controller";
+XI_M_U, AccessPermission:Busy, desc="Blocked, going to XI_U, waiting
for the memory controller";
+XI_U, AccessPermission:Busy, desc="Blocked, going to I, waiting for an
unblock";
OI_D, AccessPermission:Busy, desc="In O, going to I, waiting for data";
OD, AccessPermission:Busy, desc="In O, waiting for dma ack from L2";
@@ -96,10 +97,12 @@
Exclusive_Unblock, desc="The processor become the exclusive owner (E
or M) of the line";
Clean_Writeback, desc="The final message as part of a PutX/PutS, no
data";
Dirty_Writeback, desc="The final message as part of a PutX/PutS,
contains data";
-Memory_Data, desc="Fetched data from memory arrives";
+Memory_Data_DMA, desc="Fetched data from memory arrives; original
requestor is DMA";
+Memory_Data_Cache, desc="Fetched data from memory arrives; original
requestor is Cache";
Memory_Ack,desc="Writeback Ack from memory arrives";
DMA_READ, desc="DMA Read";
-DMA_WRITE, desc="DMA Write";
+DMA_WRITE_LINE,desc="DMA Write full line";
+DMA_WRITE_PARTIAL, desc="DMA Write partial line";
DMA_ACK, desc="DMA Ack";
Data, desc="Data to directory";
}
@@ -128,6 +131,8 @@
bool isPresent(Addr);
}
+ int blockSize, default="RubySystem::getBlockSizeBytes()";
+
// ** OBJECTS **
TBETable TBEs, template="",
constructor="m_number_of_TBEs";
@@ -264,6 +269,9 @@
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
out_port(memQueue_out, MemoryMsg, requestToMemory);
+ // For inserting internal unblocks only
+ out_port(unblockNetwork_out_internal, ResponseMsg, responseToDir);
+
// ** IN_PORTS **
in_port(unblockNetwork_in, ResponseMsg, responseToDir, rank=2) {
@@ -316,8 +324,13 @@
trigger(Event:DMA_READ, makeLineAddress(in_msg.addr),
TBEs[makeLineAddress(in_msg.addr)]);
} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
- trigger(Event:DMA_WRITE, makeLineAddress(in_msg.addr),
+ if (in_msg.Len == blockSize) {
+assert(makeLineAddress(in_msg.addr) == in_msg.addr);
+trigger(Event:DMA_WRITE_LINE, in_msg.addr, TBEs[in_msg.addr]);
+ } else {
+trigger(Event:DMA_WRITE_PARTIAL, makeLineAddress(in_msg.addr),
TBEs[makeLineAddress(in_msg.addr)]);
+ }
} else {
error("Invalid message");
}
@@ -330,7 +343,12 @@
if (memQueue_in.isReady(clockEdge())) {
peek(memQueue_in, MemoryMsg) {
if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
- trigger(Event:Memory_Data, in_msg.addr, TBEs[in_msg.addr]);
+
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: util: Port git hooks to python3
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28588 )
Change subject: util: Port git hooks to python3
..
util: Port git hooks to python3
This involves changing:
* git-commit
* git-pre-commit
* style verifiers
JIRA: https://gem5.atlassian.net/browse/GEM5-473
Change-Id: I7bd0b54469f942bf927c8be1fd94d12f67594d48
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28588
Maintainer: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M util/git-commit-msg.py
M util/git-pre-commit.py
M util/style/file_types.py
M util/style/region.py
M util/style/repo.py
M util/style/sort_includes.py
M util/style/style.py
M util/style/verifiers.py
8 files changed, 78 insertions(+), 66 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index 23270bc..92e8100 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2.7
+#!/usr/bin/env python
#
# Copyright (c) 2019 Inria
# All rights reserved
diff --git a/util/git-pre-commit.py b/util/git-pre-commit.py
index 1510949..b6d124a 100755
--- a/util/git-pre-commit.py
+++ b/util/git-pre-commit.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2.7
+#!/usr/bin/env python
#
# Copyright (c) 2016 ARM Limited
# All rights reserved
@@ -35,6 +35,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from __future__ import print_function
+
from tempfile import TemporaryFile
import os
import subprocess
@@ -66,7 +68,7 @@
for status, fname in git.status(filter="MA", cached=True):
if args.verbose:
-print "Checking %s..." % fname
+print("Checking {}...".format(fname))
if check_ignores(fname):
continue
if status == "M":
@@ -77,7 +79,7 @@
# Show they appropriate object and dump it to a file
status = git.file_from_index(fname)
f = TemporaryFile()
-f.write(status)
+f.write(status.encode())
verifiers = [ v(ui, opts, base=repo_base) for v in all_verifiers ]
for v in verifiers:
@@ -93,22 +95,25 @@
if failing_files:
if len(failing_files) > len(staged_mismatch):
-print >> sys.stderr
-print >> sys.stderr, "Style checker failed for the following
files:"
+print("\n", file=sys.stderr)
+print("Style checker failed for the following files:",
file=sys.stderr)
for f in failing_files:
if f not in staged_mismatch:
-print >> sys.stderr, "\t%s" % f
-print >> sys.stderr
-print >> sys.stderr, \
-"Please run the style checker manually to fix the offending
files.\n" \
-"To check your modifications, run: util/style.py -m"
+print("\t{}".format(f), file=sys.stderr)
+print("\n", file=sys.stderr)
+print(
+"Please run the style checker manually to fix "
+"the offending files.\n"
+"To check your modifications, run: util/style.py -m",
+file=sys.stderr)
-print >> sys.stderr
+print("\n", file=sys.stderr)
if staged_mismatch:
-print >> sys.stderr, \
-"It looks like you have forgotten to stage your fixes for commit
in\n"\
-"the following files: "
+print(
+"It looks like you have forgotten to stage your "
+"fixes for commit in\n"
+"the following files: ", file=sys.stderr)
for f in staged_mismatch:
-print >> sys.stderr, "\t%s" % f
-print >> sys.stderr, "Please `git --add' them"
+print("\t%s".format(f), file=sys.stderr)
+print("Please `git --add' them", file=sys.stderr)
sys.exit(1)
diff --git a/util/style/file_types.py b/util/style/file_types.py
index 4ffa7e0..2577492 100644
--- a/util/style/file_types.py
+++ b/util/style/file_types.py
@@ -77,7 +77,7 @@
)
# the list of all languages that we detect
-all_languages = frozenset(lang_types.itervalues())
+all_languages = frozenset(lang_types.values())
all_languages |= frozenset(lang for start,lang in lang_prefixes)
all_languages |= frozenset(lang for start,lang in hash_bang)
diff --git a/util/style/region.py b/util/style/region.py
index f4e12c5..ce00680 100644
--- a/util/style/region.py
+++ b/util/style/region.py
@@ -57,8 +57,8 @@
args = tuple(arg)
if len(args) != 2:
-raise AttributeError, \
-"Only one or two arguments allowed, %d provided" % (alen, )
+raise(AttributeError, \
+"Only one or two arguments allowed, %d provided" % (alen,
))
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: util: Make cpt_upgraders python3 compatible
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28587 )
Change subject: util: Make cpt_upgraders python3 compatible
..
util: Make cpt_upgraders python3 compatible
It won't be possible to build gem5 in a python3 only environment
otherwise since the cpt_upgrader.py script is automatically run at the
end of compilation
Change-Id: Iea4217e5cd64ca44b99aa0db5dabfdced7aeb3ea
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28587
Maintainer: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M util/cpt_upgrader.py
M util/cpt_upgraders/arm-hdlcd-upgrade.py
M util/cpt_upgraders/arm-miscreg-teehbr.py
M util/cpt_upgraders/arm-sve.py
M util/cpt_upgraders/armv8.py
M util/cpt_upgraders/x86-add-tlb.py
6 files changed, 44 insertions(+), 40 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 4ac7dbf..96dcaf6 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -1,6 +1,6 @@
-#!/usr/bin/env python2.7
+#!/usr/bin/env python
-# Copyright (c) 2012-2013,2015-2016 ARM Limited
+# Copyright (c) 2012-2013,2015-2016, 2020 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -68,8 +68,9 @@
# upgrader. This can be especially valuable when maintaining private
# upgraders in private branches.
+from __future__ import print_function
-import ConfigParser
+from six.moves import configparser
import glob, types, sys, os
import os.path as osp
@@ -79,8 +80,8 @@
if not verbose_print:
return
for arg in args:
-print arg,
-print
+print(arg, end=' ')
+print("\n")
class Upgrader:
tag_set = set()
@@ -89,7 +90,7 @@
legacy = {}
def __init__(self, filename):
self.filename = filename
-execfile(filename, {}, self.__dict__)
+exec(open(filename).read(), {}, self.__dict__)
if not hasattr(self, 'tag'):
self.tag = osp.basename(filename)[:-3]
@@ -99,7 +100,7 @@
self.depends = [self.depends]
if not isinstance(self.depends, list):
-print "Error: 'depends' for %s is the wrong type" % self.tag
+print("Error: 'depends' for {} is the wrong
type".format(self.tag))
sys.exit(1)
if hasattr(self, 'fwd_depends'):
@@ -109,23 +110,25 @@
self.fwd_depends = []
if not isinstance(self.fwd_depends, list):
-print "Error: 'fwd_depends' for %s is the wrong type" %
self.tag
+print("Error: 'fwd_depends' for {} is the wrong type".format(
+self.tag))
sys.exit(1)
if hasattr(self, 'upgrader'):
if not isinstance(self.upgrader, types.FunctionType):
-print "Error: 'upgrader' for %s is %s, not function" \
-% (self.tag, type(self))
+print("Error: 'upgrader' for {} is {}, not
function".format(
+self.tag, type(self)))
sys.exit(1)
Upgrader.tag_set.add(self.tag)
elif hasattr(self, 'downgrader'):
if not isinstance(self.downgrader, types.FunctionType):
-print "Error: 'downgrader' for %s is %s, not function" \
-% (self.tag, type(self))
+print("Error: 'downgrader' for {} is {}, not
function".format(
+self.tag, type(self)))
sys.exit(1)
Upgrader.untag_set.add(self.tag)
else:
-print "Error: no upgrader or downgrader method for", self.tag
+print("Error: no upgrader or downgrader method for".format(
+self.tag))
sys.exit(1)
if hasattr(self, 'legacy_version'):
@@ -170,14 +173,14 @@
for tag, upg in Upgrader.by_tag.items():
for fd in upg.fwd_depends:
if fd not in Upgrader.by_tag:
-print "Error: '%s' cannot (forward) depend on "\
- "nonexistent tag '%s'" % (fd, tag)
+print("Error: '{}' cannot (forward) depend on "
+ "nonexistent tag '{}'".format(fd, tag))
sys.exit(1)
Upgrader.by_tag[fd].depends.append(tag)
for dep in upg.depends:
if dep not in Upgrader.by_tag:
-print "Error: '%s' cannot depend on "\
- "nonexistent tag '%s'" % (tag, dep)
+print("Error: '{}' cannot depend on "
+ "nonexistent tag '{}'".format(tag, dep))
sys.exit(1)
def process_file(path, **kwargs):
@@ -191,7 +194,7 @@
import shutil
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: python: Manually convert float to int when using %x
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28607 ) Change subject: python: Manually convert float to int when using %x .. python: Manually convert float to int when using %x This is required by python3.5 which is not allowing a floating point value to be printed in hex and will trigger a TypeError assertion: TypeError: %X format: an integer is required, not float Change-Id: I2033366751924579cc87e7fccda8fdb33a31412d Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28607 Reviewed-by: Bobby R. Bruce Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/m5/util/dot_writer.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/m5/util/dot_writer.py b/src/python/m5/util/dot_writer.py index e6de3f3..c66108d 100644 --- a/src/python/m5/util/dot_writer.py +++ b/src/python/m5/util/dot_writer.py @@ -267,7 +267,7 @@ return dot_rgb_to_html(r, g, b) def dot_rgb_to_html(r, g, b): -return "#%.2x%.2x%.2x" % (r, g, b) +return "#%.2x%.2x%.2x" % (int(r), int(g), int(b)) # We need to create all of the clock domains. We abuse the alpha channel to get # the correct domain colouring. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28607 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I2033366751924579cc87e7fccda8fdb33a31412d Gerrit-Change-Number: 28607 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
