[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add doorbell interface class
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34377 )
Change subject: dev-arm: Add doorbell interface class
..
dev-arm: Add doorbell interface class
JIRA: https://gem5.atlassian.net/browse/GEM5-768
Change-Id: I0d264a74cbf8ca0f780314ad01fb0dd0765a0464
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34377
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
A src/dev/arm/Doorbell.py
M src/dev/arm/SConscript
A src/dev/arm/doorbell.hh
3 files changed, 111 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/Doorbell.py b/src/dev/arm/Doorbell.py
new file mode 100644
index 000..9a8e690
--- /dev/null
+++ b/src/dev/arm/Doorbell.py
@@ -0,0 +1,44 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class Doorbell(SimObject):
+type = 'Doorbell'
+abstract = True
+cxx_header = "dev/arm/doorbell.hh"
+set_address = Param.Addr("Doorbell set address")
+clear_address = Param.Addr("Doorbell clear address")
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index 46ff259..cc3efcf 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -40,6 +40,7 @@
if env['TARGET_ISA'] == 'arm':
SimObject('AbstractNVM.py')
SimObject('Display.py')
+SimObject('Doorbell.py')
SimObject('FlashDevice.py')
SimObject('GenericTimer.py')
SimObject('Gic.py')
diff --git a/src/dev/arm/doorbell.hh b/src/dev/arm/doorbell.hh
new file mode 100644
index 000..0f786cf
--- /dev/null
+++ b/src/dev/arm/doorbell.hh
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * docu
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Define a ParentMem object for DTB autogen
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34376 )
Change subject: dev-arm: Define a ParentMem object for DTB autogen
..
dev-arm: Define a ParentMem object for DTB autogen
A memory willing to autogenerate child nodes can do that directly in
the generateDeviceTree method. However sometimes portions of memory
(child nodes) are tagged for specific applications. Hardcoding the
child node in the parent memory class is not flexible, so we delegate
this to the application model, which is registering the generator
helper via the ParentMem interface
JIRA: https://gem5.atlassian.net/browse/GEM5-768
Change-Id: I5fa5bac0decf5399dbaa3804569998dc5e6d7bc0
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34376
Tested-by: kokoro
Reviewed-by: Richard Cooper
---
M src/dev/arm/RealView.py
1 file changed, 36 insertions(+), 1 deletion(-)
Approvals:
Richard Cooper: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 5397de5..d35f7ce 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -543,7 +543,40 @@
yield node
-class MmioSRAM(SimpleMemory):
+class ParentMem(SimpleMemory):
+"""
+This is a base abstract class for child node generation
+A memory willing to autogenerate child nodes can do that
+directly in the generateDeviceTree method.
+However sometimes portions of memory (child nodes) are tagged
+for specific applications. Hardcoding the child node in the
+parent memory class is not flexible, so we delegate this
+to the application model, which is registering the generator
+helper via the ParentMem interface.
+"""
+def __init__(self, *args, **kwargs):
+super(ParentMem, self).__init__(*args, **kwargs)
+self._generators = []
+
+def addSubnodeGenerator(self, gen):
+"""
+This is the method a client application would use to
+register a child generator in the memory object.
+"""
+self._generators.append(gen)
+
+def generateSubnodes(self, node, state):
+"""
+This is the method the memory would use to instantiate
+the child nodes via the previously registered generators.
+"""
+for subnode_gen in self._generators:
+node.append(subnode_gen(state))
+
+class MmioSRAM(ParentMem):
+def __init__(self, *args, **kwargs):
+super(MmioSRAM, self).__init__(**kwargs)
+
def generateDeviceTree(self, state):
node = FdtNode("sram@%x" % long(self.range.start))
node.appendCompatible(["mmio-sram"])
@@ -559,6 +592,8 @@
state.addrCells(self.range.start) +
state.sizeCells(self.range.size()) ))
+self.generateSubnodes(node, state)
+
yield node
class FVPBasePwrCtrl(BasicPioDevice):
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34376
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5fa5bac0decf5399dbaa3804569998dc5e6d7bc0
Gerrit-Change-Number: 34376
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: kvm, arm: Add parameter to force simulation of Gicv2
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36795 )
Change subject: kvm, arm: Add parameter to force simulation of Gicv2
..
kvm, arm: Add parameter to force simulation of Gicv2
By setting simulate_gic to True it will be possible to prevent
the simulation from using the host interrupt controller
Signed-off-by: Giacomo Travaglini
Change-Id: I7c7df798e07bfaddbc2f1e7dd981b6aff621a9d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36795
Reviewed-by: Andreas Sandberg
Reviewed-by: Hsuan Hsu
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/kvm/KvmGic.py
M src/arch/arm/kvm/gic.cc
2 files changed, 5 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Hsuan Hsu: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py
index 9796908..ce85ecb 100644
--- a/src/arch/arm/kvm/KvmGic.py
+++ b/src/arch/arm/kvm/KvmGic.py
@@ -41,3 +41,6 @@
class MuxingKvmGic(GicV2):
type = 'MuxingKvmGic'
cxx_header = "arch/arm/kvm/gic.hh"
+
+simulate_gic = Param.Bool(False,
+"Forcing the simulation to use the gem5 GIC instead of the host
GIC")
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 6767833..feb764f 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -170,7 +170,8 @@
kernelGic(nullptr),
usingKvm(false)
{
-if (auto vm = system.getKvmVM()) {
+auto vm = system.getKvmVM();
+if (vm && !p.simulate_gic) {
kernelGic = new KvmKernelGicV2(*vm, p.cpu_addr, p.dist_addr,
p.it_lines);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36795
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7c7df798e07bfaddbc2f1e7dd981b6aff621a9d1
Gerrit-Change-Number: 36795
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: System is expecting a kvm_vm param for KvmVM
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31217 ) Change subject: tests: System is expecting a kvm_vm param for KvmVM .. tests: System is expecting a kvm_vm param for KvmVM Signed-off-by: Giacomo Travaglini Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31217 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- M tests/gem5/configs/base_config.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/gem5/configs/base_config.py b/tests/gem5/configs/base_config.py index fbedbaf..5623db8 100644 --- a/tests/gem5/configs/base_config.py +++ b/tests/gem5/configs/base_config.py @@ -133,7 +133,7 @@ Arguments: system -- System to work on. """ -system.vm = KvmVM() +system.kvm_vm = KvmVM() def init_system(self, system): """Initialize a system. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31217 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16 Gerrit-Change-Number: 31217 Gerrit-PatchSet: 6 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: misc: create C declarations for the _addr and _semi m5ops
Ciro Santilli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/36896 ) Change subject: misc: create C declarations for the _addr and _semi m5ops .. misc: create C declarations for the _addr and _semi m5ops Symbols such as m5_exit_addr are already present in the libm5.a, but were not previously exposed in a header. This commit allows external C programs to use those versions of the functions as well. Change-Id: I925e3af7bd6cb23e06fb744d453153323afb9310 --- M include/gem5/m5ops.h 1 file changed, 7 insertions(+), 0 deletions(-) diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h index fddbf53..377d648 100644 --- a/include/gem5/m5ops.h +++ b/include/gem5/m5ops.h @@ -35,6 +35,8 @@ #include +#include + void m5_arm(uint64_t address); void m5_quiesce(void); void m5_quiesce_ns(uint64_t ns); @@ -68,6 +70,11 @@ void m5_se_syscall(); void m5_se_page_fault(); +#define M5OP(name, func) __typeof__(name) name ## _addr; \ + __typeof__(name) name ## _semi; +M5OP_FOREACH +#undef M5OP + #ifdef __cplusplus } #endif -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36896 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I925e3af7bd6cb23e06fb744d453153323afb9310 Gerrit-Change-Number: 36896 Gerrit-PatchSet: 1 Gerrit-Owner: Ciro Santilli Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: ARM full system boot that uses the HDLCD?
Gabe, last time I touched HDLCD a while back, it worked on fs.py with this setup: https://stackoverflow.com/questions/50364863/how-to-get-graphical-gui-output-and-user-touch-keyboard-mouse-input-in-a-ful/50364864#50364864 I suppose the other main in-tree arm scripts would also work. From: Gabe Black via gem5-dev Sent: Friday, October 30, 2020 1:41 AM To: gem5 Developer List Cc: Gabe Black Subject: [gem5-dev] ARM full system boot that uses the HDLCD? Hey ARM folks. I want to take a look at optimizing the HDLCD framebuffer output, VNC output, etc., since that's a big bottleneck when, for instance, running Fast Model simulation. Is there a simple config I can run without using fast model, etc, which I can use to test the HDLCD and those video features? I'll check how much performance gain there is later on, but for now I just want to make sure I don't break anything. Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Instantiate SCMI in VExpress_GEM5 platforms
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/34380 ) Change subject: dev-arm: Instantiate SCMI in VExpress_GEM5 platforms .. dev-arm: Instantiate SCMI in VExpress_GEM5 platforms JIRA: https://gem5.atlassian.net/browse/GEM5-768 Change-Id: If5c03aed43f6a521c657e0c9b1dfa95fa4c72413 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34380 Tested-by: kokoro Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- M src/dev/arm/RealView.py 1 file changed, 39 insertions(+), 0 deletions(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index d35f7ce..bf8e0e6 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -53,6 +53,7 @@ from m5.objects.SimpleMemory import SimpleMemory from m5.objects.GenericTimer import * from m5.objects.Gic import * +from m5.objects.MHU import MHU, Scp2ApDoorbell, Ap2ScpDoorbell from m5.objects.EnergyCtrl import EnergyCtrl from m5.objects.ClockedObject import ClockedObject from m5.objects.SubSystem import SubSystem @@ -61,6 +62,7 @@ from m5.objects.PS2 import * from m5.objects.VirtIOMMIO import MmioVirtIO from m5.objects.Display import Display, Display1080p +from m5.objects.Scmi import * from m5.objects.SMMUv3 import SMMUv3 from m5.objects.PciDevice import PciLegacyIoBar, PciIoBar @@ -607,6 +609,23 @@ type = 'FVPBasePwrCtrl' cxx_header = 'dev/arm/fvp_base_pwr_ctrl.hh' +class GenericMHU(MHU): +lowp_scp2ap = Scp2ApDoorbell( +set_address=0x10020008, clear_address=0x10020010, +interrupt=ArmSPI(num=68)) +highp_scp2ap = Scp2ApDoorbell( +set_address=0x10020028, clear_address=0x10020030, +interrupt=ArmSPI(num=67)) +sec_scp2ap = Scp2ApDoorbell( +set_address=0x10020208, clear_address=0x10020210, +interrupt=ArmSPI(num=69)) +lowp_ap2scp = Ap2ScpDoorbell( +set_address=0x10020108, clear_address=0x10020110) +highp_ap2scp = Ap2ScpDoorbell( +set_address=0x10020128, clear_address=0x10020130) +sec_ap2scp = Ap2ScpDoorbell( +set_address=0x10020308, clear_address=0x10020310) + class RealView(Platform): type = 'RealView' cxx_header = "dev/arm/realview.hh" @@ -912,6 +931,7 @@ 0x1000-0x13ff: gem5-specific peripherals (Off-chip, CS5) 0x1000-0x1000: gem5 energy controller 0x1001-0x1001: gem5 pseudo-ops + 0x1002-0x1002: gem5 MHU 0x1400-0x17ff: Reserved (Off-chip, PSRAM, CS1) 0x1800-0x1bff: Reserved (Off-chip, Peripherals, CS2) @@ -1188,6 +1208,25 @@ # system. cur_sys.m5ops_base = 0x1001 +def attachScmi(self, bus): +# Generate and attach the mailbox +self.mailbox = GenericMHU(pio_addr=0x1002) +self._attach_device(self.mailbox, bus) + +# Generate and attach the SCMI platform +_scmi_comm = ScmiCommunication( +agent_channel = ScmiAgentChannel( +shmem=self.non_trusted_sram, +shmem_range=AddrRange(0x2e00, size=0x200), +doorbell=self.mailbox.highp_ap2scp), +platform_channel = ScmiPlatformChannel( +shmem=self.non_trusted_sram, +shmem_range=AddrRange(0x2e00, size=0x200), +doorbell=self.mailbox.highp_scp2ap)) + +self.scmi = ScmiPlatform(comms=[ _scmi_comm ]) +self._attach_device(self.scmi, bus) + def generateDeviceTree(self, state): # Generate using standard RealView function dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34380 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If5c03aed43f6a521c657e0c9b1dfa95fa4c72413 Gerrit-Change-Number: 34380 Gerrit-PatchSet: 11 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement Arm MHU (Message Handling Unit)
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34378 )
Change subject: dev-arm: Implement Arm MHU (Message Handling Unit)
..
dev-arm: Implement Arm MHU (Message Handling Unit)
JIRA: https://gem5.atlassian.net/browse/GEM5-768
Change-Id: I895eba1a3421746a602e6a4f88916da9054169a8
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34378
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
A src/dev/arm/css/MHU.py
A src/dev/arm/css/SConscript
A src/dev/arm/css/Scp.py
A src/dev/arm/css/mhu.cc
A src/dev/arm/css/mhu.hh
A src/dev/arm/css/scp.hh
6 files changed, 669 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
new file mode 100644
index 000..878ca22
--- /dev/null
+++ b/src/dev/arm/css/MHU.py
@@ -0,0 +1,113 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Doorbell import Doorbell
+from m5.params import *
+from m5.proxy import *
+from m5.util.fdthelper import *
+
+class MhuDoorbell(Doorbell):
+type = 'MhuDoorbell'
+abstract = True
+cxx_header = "dev/arm/css/mhu.hh"
+
+class Scp2ApDoorbell(MhuDoorbell):
+type = 'Scp2ApDoorbell'
+cxx_header = "dev/arm/css/mhu.hh"
+
+interrupt = Param.ArmInterruptPin("Interrupt Pin")
+
+class Ap2ScpDoorbell(MhuDoorbell):
+type = 'Ap2ScpDoorbell'
+cxx_header = "dev/arm/css/mhu.hh"
+
+# Message Handling Unit
+class MHU(BasicPioDevice):
+type = 'MHU'
+cxx_header = "dev/arm/css/mhu.hh"
+pio_size = Param.Unsigned(0x1000, "MHU pio size")
+
+lowp_scp2ap = Param.Scp2ApDoorbell(
+"Low Priority doorbell channel for communications "
+"from the System Control Processor (SCP) to the "
+"Application Processor (AP)")
+highp_scp2ap = Param.Scp2ApDoorbell(
+"High Priority doorbell channel for communications "
+"from the System Control Processor (SCP) to the "
+"Application Processor (AP)")
+sec_scp2ap = Param.Scp2ApDoorbell(
+"Secure doorbell channel for communications "
+"from the System Control Processor (SCP) to the "
+"Application Processor (AP)")
+
+lowp_ap2scp = Param.Ap2ScpDoorbell(
+"Low Priority doorbell channel for communications "
+"from the Application Processor (AP) to the "
+"System Control Processor (SCP)")
+highp_ap2scp = Param.Ap2ScpDoorbell(
+"High Priority doorbell channel for communications "
+"from the Application Processor (AP) to the "
+"System Control Processor (SCP)")
+sec_ap2scp = Param.Ap2ScpDoorbell(
+"Secure doorbell channel for comm
[gem5-dev] Change in gem5/gem5[develop]: configs: Do not require default options for caches
Davide Basilio Bartolini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36897 )
Change subject: configs: Do not require default options for caches
..
configs: Do not require default options for caches
This change is useful when using custom simulation scripts that do not
rely on configs/common/Options.py.
Without this change, the custom script always needed to provide some
value for cache sizes and HW prefetchers configuration; with this change
it is possible to provide no value and use what is defined in the core
configuration as default.
Change-Id: I21051be91daf29e3c1878385b9cbcd6c71386038
---
M configs/common/CacheConfig.py
1 file changed, 27 insertions(+), 32 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 05c38e0..bd80c1a 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -48,6 +48,30 @@
from common.Caches import *
from common import ObjectList
+def _get_hwp(hwp_option):
+if hwp_option == None:
+return NULL
+
+hwpClass = ObjectList.hwp_list.get(hwp_option)
+return hwpClass()
+
+def _get_cache_opts(level, options):
+opts = {}
+
+size_attr = '{}_size'.format(level)
+if hasattr(options, size_attr):
+opts['size'] = getattr(options, size_attr)
+
+assoc_attr = '{}_assoc'.format(level)
+if hasattr(options, assoc_attr):
+opts['assoc'] = getattr(options, assoc_attr)
+
+prefetcher_attr = '{}_hwp_type'.format(level)
+if hasattr(options, prefetcher_attr):
+opts['prefetcher'] = _get_hwp(getattr(options, prefetcher_attr))
+
+return opts
+
def config_cache(options, system):
if options.external_memory_system and (options.caches or
options.l2cache):
print("External caches and internal caches are exclusive
options.\n")
@@ -98,30 +122,19 @@
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs.
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
- size=options.l2_size,
- assoc=options.l2_assoc)
+ **_get_cache_opts('l2', options))
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
-if options.l2_hwp_type:
-hwpClass = ObjectList.hwp_list.get(options.l2_hwp_type)
-if system.l2.prefetcher != "Null":
-print("Warning: l2-hwp-type is set (", hwpClass, "), but",
- "the current l2 has a default Hardware Prefetcher",
- "of type", type(system.l2.prefetcher), ", using the",
- "specified by the flag option.")
-system.l2.prefetcher = hwpClass()
if options.memchecker:
system.memchecker = MemChecker()
for i in range(options.num_cpus):
if options.caches:
-icache = icache_class(size=options.l1i_size,
- assoc=options.l1i_assoc)
-dcache = dcache_class(size=options.l1d_size,
- assoc=options.l1d_assoc)
+icache = icache_class(**_get_cache_opts('l1i', options))
+dcache = dcache_class(**_get_cache_opts('l1d', options))
# If we have a walker cache specified, instantiate two
# instances here
@@ -147,24 +160,6 @@
# Let CPU connect to monitors
dcache = dcache_mon
-if options.l1d_hwp_type:
-hwpClass = ObjectList.hwp_list.get(options.l1d_hwp_type)
-if dcache.prefetcher != m5.params.NULL:
-print("Warning: l1d-hwp-type is set (", hwpClass, "),
but",
- "the current l1d has a default Hardware
Prefetcher",
- "of type", type(dcache.prefetcher), ", using
the",
- "specified by the flag option.")
-dcache.prefetcher = hwpClass()
-
-if options.l1i_hwp_type:
-hwpClass = ObjectList.hwp_list.get(options.l1i_hwp_type)
-if icache.prefetcher != m5.params.NULL:
-print("Warning: l1i-hwp-type is set (", hwpClass, "),
but",
- "the current l1i has a default Hardware
Prefetcher",
- "of type", type(icache.prefetcher), ", using
the",
- "specified by the flag option.")
-icache.prefetcher = hwpClass()
-
# When connecting the caches, the clock is also inherited
# from the CPU in question
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36897
To
[gem5-dev] Status of Compiler-Checks tests
Hi all, We noticed that a recent change https://gem5-review.googlesource.com/c/public/gem5/+/35856 broke the Build on GCC 5.4: build/ARM/dev/reg_bank.test.cc:29:32: error: unknown option after '#pragma GCC diagnostic' kind [-Werror=pragmas] #pragma GCC diagnostic ignored "-Wdeprecated-copy" ^ cc1plus: all warnings being treated as errors The option was apparently only added to GCC 9: https://gcc.gnu.org/gcc-9/changes.html I then searched a bit and found out about Compiler-Checks under http://jenkins.gem5.org/ which is awesome, but unfortunately hasn't passed in a month and not run in 12 days. So I wanted to check what's the status of that setup? That is a very good way to prevent this kind of build break. Even more awesome would be if we could add a build with the minimum supported GCC version to precommits. Let me know if there's anything I can do to help to get that up and running. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: Status of Compiler-Checks tests
Hey Ciro, Due to us officially dropping support for Python2 in the next release, the develop branch was failing on the compilation tests due to the fact the Docker Image's we were running them on weren't configured correctly (some were purely Python2). So I paused the compiler tests while I fixed this. Once I'd fixed the Docker images, I re-ran the compiler tests on one of our beefy servers at UC Davis and found some compilation bugs, so I went ahead and fixed them too. The changes to the Dockerfiles and the compilation fixes can be found here: https://gem5-review.googlesource.com/c/public/gem5/+/36715. I've been busy this past week so not had much time to address the comments on this chain, but will do later today or tomorrow (I didn't see the point in turning the compiler tests back on while these fixes have yet to be merged). I'll look into the compiler bug you've described in this email and see if I can submit a fix on top of the relation chian. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Mon, Nov 2, 2020 at 6:10 AM Ciro Santilli wrote: > Hi all, > > We noticed that a recent change > https://gem5-review.googlesource.com/c/public/gem5/+/35856 broke the > Build on GCC 5.4: > > build/ARM/dev/reg_bank.test.cc:29:32: error: unknown option after > '#pragma GCC diagnostic' kind [-Werror=pragmas] > #pragma GCC diagnostic ignored "-Wdeprecated-copy" > ^ > cc1plus: all warnings being treated as errors > > The option was apparently only added to GCC 9: > https://gcc.gnu.org/gcc-9/changes.html > > I then searched a bit and found out about Compiler-Checks under > http://jenkins.gem5.org/ which is awesome, but unfortunately hasn't > passed in a month and not run in 12 days. > > So I wanted to check what's the status of that setup? That is a very good > way to prevent this kind of build break. > > Even more awesome would be if we could add a build with the minimum > supported GCC version to precommits. > > Let me know if there's anything I can do to help to get that up and > running. > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make CPUID vendor string a param
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36156 )
Change subject: arch-x86: Make CPUID vendor string a param
..
arch-x86: Make CPUID vendor string a param
Modern libraries such as ROCm, MPI, and libnuma use files in Linux'
sysfs to determine the system topology such as number of CPUs, cache
size, cache associativity, etc. If Linux does not recognize the vendor
string returned by CPUID in x86 it will do a generic initialization
which does not include creating these files. In the case of ROCm
(specifically ROCt) this causes failures when getting device properties.
This can be solved by setting the vendor string to, for example,
AuthenticAMD (as qemu does) so that Linux will create the relevant sysfs
files. Unfortunately, simply changing the string in cpuid.cc to
AuthenticAMD causes simulation slowdown and may not be desirable to all
users. This change creates a parameter, defaulting to M5 Simulator as it
currently is, which can be set in python configuration files to change
the vendor string. Example of how to configure this is:
for i in range(len(self.cpus)):
for j in range(len(self.cpus[i].isa)):
self.cpus[i].isa[j].vendor_string = "AuthenticAMD"
Change-Id: I8de26d5a145867fa23518718a799dd96b5b9bffa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36156
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/X86ISA.py
M src/arch/x86/cpuid.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
4 files changed, 37 insertions(+), 15 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
index d73d99a..1503f5f 100644
--- a/src/arch/x86/X86ISA.py
+++ b/src/arch/x86/X86ISA.py
@@ -34,8 +34,12 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.BaseISA import BaseISA
+from m5.params import *
class X86ISA(BaseISA):
type = 'X86ISA'
cxx_class = 'X86ISA::ISA'
cxx_header = "arch/x86/isa.hh"
+
+vendor_string = Param.String("M5 Simulator",
+ "Vendor string for CPUID instruction")
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 64d4544..8c9f29c 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -28,6 +28,7 @@
#include "arch/x86/cpuid.hh"
+#include "arch/x86/isa.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
@@ -67,8 +68,6 @@
NumExtendedCpuidFuncs
};
-static const int vendorStringSize = 13;
-static const char vendorString[vendorStringSize] = "M5 Simulator";
static const int nameStringSize = 48;
static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
@@ -93,12 +92,15 @@
// The extended functions
switch (funcNum) {
case VendorAndLargestExtFunc:
-assert(vendorStringSize >= 12);
-result = CpuidResult(
-0x8000 + NumExtendedCpuidFuncs - 1,
-stringToRegister(vendorString),
-stringToRegister(vendorString + 4),
-stringToRegister(vendorString + 8));
+{
+ ISA *isa = dynamic_cast(tc->getIsaPtr());
+ const char *vendor_string =
isa->getVendorString().c_str();
+ result = CpuidResult(
+ 0x8000 + NumExtendedCpuidFuncs - 1,
+ stringToRegister(vendor_string),
+ stringToRegister(vendor_string + 4),
+ stringToRegister(vendor_string + 8));
+}
break;
case FamilyModelSteppingBrandFeatures:
result = CpuidResult(0x00020f51, 0x0405,
@@ -151,12 +153,15 @@
// The standard functions
switch (funcNum) {
case VendorAndLargestStdFunc:
-assert(vendorStringSize >= 12);
-result = CpuidResult(
-NumStandardCpuidFuncs - 1,
-stringToRegister(vendorString),
-stringToRegister(vendorString + 4),
-stringToRegister(vendorString + 8));
+{
+ ISA *isa = dynamic_cast(tc->getIsaPtr());
+ const char *vendor_string =
isa->getVendorString().c_str();
+ result = CpuidResult(
+ NumExtendedCpuidFuncs - 1,
+ stringToRegister(vendor_string),
+ stringToRegister(vendor_string + 4),
+ stringToRegister(vendor_string + 8));
+}
break;
case FamilyModelStepping:
res
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix VExpressFastmodel timer configs
Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36379 )
Change subject: dev-arm: Fix VExpressFastmodel timer configs
..
dev-arm: Fix VExpressFastmodel timer configs
generic_timer is no longer in the return value of _on_chip_devices. We
should correct the _on_chip_devices. Furthermore, to prevent the timer
conflict with the fastmodel, we should remove unwanted timer.
Change-Id: I6ec7f9749546df3e8f125a5b96e7ed83cab2ea56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36379
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/dev/arm/VExpressFastmodel.py
2 files changed, 28 insertions(+), 6 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index 65d57a1..0b0fa8d 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -34,6 +34,7 @@
from m5.objects.Gic import ArmPPI
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
+from m5.util.fdthelper import FdtNode, FdtPropertyWords
class FastModelCortexA76(IrisBaseCPU):
type = 'FastModelCortexA76'
@@ -348,6 +349,21 @@
walk_cache_latency = Param.UInt64(0, "Walk cache latency for TA
(Timing "\
"Annotation), expressed in simulation ticks")
+def generateDeviceTree(self, state):
+node = FdtNode("timer")
+
+node.appendCompatible(["arm,cortex-a15-timer",
+ "arm,armv7-timer",
+ "arm,armv8-timer"])
+node.append(FdtPropertyWords("interrupts", [
+1, int(self.cntpsirq.num), 0xf08,
+1, int(self.cntpnsirq.num), 0xf08,
+1, int(self.cntvirq.num), 0xf08,
+1, int(self.cnthpirq.num), 0xf08,
+]))
+
+yield node
+
class FastModelScxEvsCortexA76x1(SystemC_ScModule):
type = 'FastModelScxEvsCortexA76x1'
cxx_class
= 'FastModel::ScxEvsCortexA76'
diff --git a/src/dev/arm/VExpressFastmodel.py
b/src/dev/arm/VExpressFastmodel.py
index 015f6d4..a6b9b34 100644
--- a/src/dev/arm/VExpressFastmodel.py
+++ b/src/dev/arm/VExpressFastmodel.py
@@ -26,6 +26,7 @@
from m5.objects.FastModelGIC import FastModelGIC, SCFastModelGIC
from m5.objects.Gic import ArmSPI
from m5.objects.RealView import VExpress_GEM5_Base, HDLcd
+from m5.objects.SubSystem import SubSystem
class VExpressFastmodel(VExpress_GEM5_Base):
gic = FastModelGIC(
@@ -39,14 +40,19 @@
pxl_clk=VExpress_GEM5_Base.dcc.osc_pxl, pio_addr=0x2b00,
interrupt=ArmSPI(num=95))
-def __init__(self, *args, **kwargs):
-super(VExpressFastmodel, self).__init__(*args, **kwargs)
+# Remove original timer to prevent from possible conflict with
Fastmodel
+# timer.
+generic_timer = SubSystem()
+generic_timer_mem = SubSystem()
+sys_counter = SubSystem()
def _on_chip_devices(self):
-devices = super(VExpressFastmodel, self)._on_chip_devices()
-devices += [ self.gic, self.hdlcd ]
-devices.remove(self.generic_timer)
-return devices
+return [
+self.gic,
+self.hdlcd,
+self.system_watchdog,
+self.trusted_watchdog,
+]
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
if boot_loader is None:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36379
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ec7f9749546df3e8f125a5b96e7ed83cab2ea56
Gerrit-Change-Number: 36379
Gerrit-PatchSet: 10
Gerrit-Owner: Yu-hsin Wang
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add dtb-gen to fs_bigLITTLE.py
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36955 )
Change subject: configs: Add dtb-gen to fs_bigLITTLE.py
..
configs: Add dtb-gen to fs_bigLITTLE.py
Change-Id: I1956e98d0fa507cc342e926b61d69fb967a64556
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 29f5c6b..76de0eb 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -213,6 +213,8 @@
"only parameters of its children.")
parser.add_argument("--vio-9p", action="store_true",
help=Options.vio_9p_help)
+parser.add_argument("--dtb-gen", action="store_true",
+help="Doesn't run simulation, it generates a DTB
only")
return parser
def build(options):
@@ -367,6 +369,10 @@
sys.exit(event.getCode())
+def generateDtb(root):
+root.system.generateDtb(os.path.join(m5.options.outdir, "system.dtb"))
+
+
def main():
parser = argparse.ArgumentParser(
description="Generic ARM big.LITTLE configuration")
@@ -375,7 +381,10 @@
root = build(options)
root.apply_config(options.param)
instantiate(options)
-run()
+if options.dtb_gen:
+ generateDtb(root)
+else:
+ run()
if __name__ == "__m5_main__":
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36955
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1956e98d0fa507cc342e926b61d69fb967a64556
Gerrit-Change-Number: 36955
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: Add a unit test for the "addr" call type in the m5 util.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27751 )
Change subject: util: Add a unit test for the "addr" call type in the m5
util.
..
util: Add a unit test for the "addr" call type in the m5 util.
This verifies that the slightly more complex --addr command line option
behaves as expected.
Also, like the inst and semi call type unit tests, it will either
attempt to successfully perform a call to the "sum" m5 op if it's told
it's running under gem5, or it will attempt to catch itself failing to
run that command by using mprotect to block its access to the mmap-ed
region and then looks at the siginfo_t to make sure the attempted access
was to the right place, etc.
It also will attempt to verify the details of the mmap if possible by
looking up information about its own mmap-ings in /proc. If the file it
would expect to find the mappings in doesn't exist, it prints a warning
and gives up. If it does, it looks through it to find the line
corresponding to the m5 ops, and then checks some details of the mapping
like its size and its offset in the target file. The offset would
correspond to the physical address if using the real /dev/mem.
Change-Id: Icc14cd9ac02eae93c56f1f2aa78fd67d8540a2f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27751
Reviewed-by: Giacomo Travaglini
Maintainer: Gabe Black
Tested-by: kokoro
---
M util/m5/src/call_type/addr.test.cc
1 file changed, 429 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/call_type/addr.test.cc
b/util/m5/src/call_type/addr.test.cc
index 42b7341..60921e4 100644
--- a/util/m5/src/call_type/addr.test.cc
+++ b/util/m5/src/call_type/addr.test.cc
@@ -26,9 +26,438 @@
*/
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "args.hh"
#include "call_type.hh"
+#include "dispatch_table.hh"
+#include "m5_mmap.h"
+
+class DefaultCallType : public CallType
+{
+ private:
+DispatchTable dt;
+
+ public:
+DefaultCallType() : CallType("default") {}
+
+bool initCalled = false;
+void init() override { initCalled = true; }
+
+bool isDefault() const override { return true; }
+void printDesc(std::ostream &os) const override {}
+const DispatchTable &getDispatch() const override { return dt; }
+};
+
+DefaultCallType defaultCallType;
+
+#if defined(M5OP_ADDR)
+const bool DefaultAddrDefined = true;
+constexpr uint64_t DefaultAddress = M5OP_ADDR;
+#else
+const bool DefaultAddrDefined = false;
+constexpr uint64_t DefaultAddress = 0;
+#endif
+
+class AddrCallTypeTest : public testing::Test
+{
+ protected:
+CallType *ct = nullptr;
+
+void
+SetUp() override
+{
+m5_mmap_dev = "/dev/zero";
+m5op_addr = 2;
+}
+
+void
+TearDown() override
+{
+unmap_m5_mem();
+}
+};
+
+TEST_F(AddrCallTypeTest, EmptyArgs)
+{
+// Addr should not be selected if there are no arguments.
+Args empty({});
+defaultCallType.initCalled = false;
+ct = CallType::detect(empty);
+EXPECT_EQ(ct, &defaultCallType);
+EXPECT_TRUE(defaultCallType.initCalled);
+}
+
+TEST_F(AddrCallTypeTest, OneArgMismatch)
+{
+// Addr should not be selected if --addr isn't the first argument.
+Args one_arg({"one"});
+defaultCallType.initCalled = false;
+ct = CallType::detect(one_arg);
+EXPECT_EQ(ct, &defaultCallType);
+EXPECT_TRUE(defaultCallType.initCalled);
+EXPECT_EQ(one_arg.size(), 1);
+}
+
+TEST_F(AddrCallTypeTest, OneArgSelected)
+{
+// Addr should be selected if --addr is the first argument.
+Args selected({"--addr=3"});
+defaultCallType.initCalled = false;
+ct = CallType::detect(selected);
+EXPECT_NE(ct, &defaultCallType);
+EXPECT_NE(ct, nullptr);
+EXPECT_FALSE(defaultCallType.initCalled);
+EXPECT_EQ(m5op_addr, 3);
+}
+
+TEST_F(AddrCallTypeTest, SplitSelected)
+{
+Args split({"--addr", "3"});
+defaultCallType.initCalled = false;
+ct = CallType::detect(split);
+EXPECT_NE(ct, &defaultCallType);
+EXPECT_NE(ct, nullptr);
+EXPECT_FALSE(defaultCallType.initCalled);
+EXPECT_EQ(m5op_addr, 3);
+}
+
+TEST_F(AddrCallTypeTest, OneArgSelectedExtra)
+{
+Args selected_extra({"--addr=3", "foo"});
+defaultCallType.initCalled = false;
+ct = CallType::detect(selected_extra);
+EXPECT_NE(ct, &defaultCallType);
+EXPECT_NE(ct, nullptr);
+EXPECT_FALSE(defaultCallType.initCalled);
+EXPECT_EQ(m5op_addr, 3);
+}
+
+TEST_F(AddrCallTypeTest, SplitSelectedExtra)
+{
+Args split_extra({"--addr", "3", "foo"});
+defaultCallType.initCalled = false;
+ct = CallType::detect(split_extra);
+EXPECT_NE(ct, &defaultCallType);
+EXPECT_NE(ct, nullptr);
+
[gem5-dev] Change in gem5/gem5[develop]: dev: Convert the x86 i8237 DMA controller to use RegBank.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36815 )
Change subject: dev: Convert the x86 i8237 DMA controller to use RegBank.
..
dev: Convert the x86 i8237 DMA controller to use RegBank.
This gets rid of the requirement to only modify one byte register at a
time, and builds some structure around individual DMA channels.
The one small feature of the i8237 that was implemented is still
implemented, but now with a method of the i8237.
Change-Id: Ibc2b2d75f2a3b860da3f28ae649c6f1a099bdf7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36815
Reviewed-by: Matthew Poremba
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/dev/x86/i8237.cc
M src/dev/x86/i8237.hh
2 files changed, 162 insertions(+), 85 deletions(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/x86/i8237.cc b/src/dev/x86/i8237.cc
index 05d08c8..a7f641f 100644
--- a/src/dev/x86/i8237.cc
+++ b/src/dev/x86/i8237.cc
@@ -28,110 +28,137 @@
#include "dev/x86/i8237.hh"
+#include "base/cprintf.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-Tick
-X86ISA::I8237::read(PacketPtr pkt)
+namespace X86ISA
{
-assert(pkt->getSize() == 1);
-Addr offset = pkt->getAddr() - pioAddr;
-switch (offset) {
- case 0x0:
-panic("Read from i8237 channel 0 current address
unimplemented.\n");
- case 0x1:
-panic("Read from i8237 channel 0 remaining "
-"word count unimplemented.\n");
- case 0x2:
-panic("Read from i8237 channel 1 current address
unimplemented.\n");
- case 0x3:
-panic("Read from i8237 channel 1 remaining "
-"word count unimplemented.\n");
- case 0x4:
-panic("Read from i8237 channel 2 current address
unimplemented.\n");
- case 0x5:
-panic("Read from i8237 channel 2 remaining "
-"word count unimplemented.\n");
- case 0x6:
-panic("Read from i8237 channel 3 current address
unimplemented.\n");
- case 0x7:
-panic("Read from i8237 channel 3 remaining "
-"word count unimplemented.\n");
- case 0x8:
-panic("Read from i8237 status register unimplemented.\n");
- default:
-panic("Read from undefined i8237 register %d.\n", offset);
-}
+
+namespace
+{
+
+I8237::Register::ReadFunc
+readUnimpl(const std::string &label)
+{
+return [label](I8237::Register ®) -> uint8_t {
+panic("Read from i8237 %s unimplemented.", label);
+};
+}
+
+I8237::Register::WriteFunc
+writeUnimpl(const std::string &label)
+{
+return [label](I8237::Register ®, const uint8_t &value) {
+panic("Write to i8237 %s unimplemented.", label);
+};
+}
+
+} // anonymous namespace
+
+I8237::Channel::ChannelAddrReg::ChannelAddrReg(Channel &channel) :
+Register(csprintf("channel %d current address", channel.number))
+{
+reader(readUnimpl(name()));
+writer(writeUnimpl(name()));
+}
+
+I8237::Channel::ChannelRemainingReg::ChannelRemainingReg(Channel
&channel) :
+Register(csprintf("channel %d remaining word count", channel.number))
+{
+reader(readUnimpl(name()));
+writer(writeUnimpl(name()));
+}
+
+I8237::WriteOnlyReg::WriteOnlyReg(const std::string &new_name, Addr
offset) :
+Register(new_name)
+{
+reader([offset](I8237::Register ®) -> uint8_t {
+panic("Illegal read from i8237 register %d.", offset);
+});
+}
+
+I8237::I8237(const Params &p) : BasicPioDevice(p, 16),
latency(p.pio_latency),
+regs("registers", pioAddr), channels{{{0}, {1}, {2}, {3}}},
+statusCommandReg("status/command"),
+requestReg("request", 0x9),
+setMaskBitReg("set mask bit", 0xa),
+modeReg("mode", 0xb),
+clearFlipFlopReg("clear flip-flop", 0xc),
+temporaryMasterClearReg("temporary/maskter clear"),
+clearMaskReg("clear mask", 0xe),
+writeMaskReg("write mask", 0xf)
+{
+// Add the channel address and remaining registers.
+for (auto &channel: channels)
+regs.addRegisters({ channel.addrReg, channel.remainingReg });
+
+// Add the other registers individually.
+regs.addRegisters({
+statusCommandReg.
+reader(readUnimpl("status register")).
+writer(writeUnimpl("command register")),
+
+requestReg.
+writer(writeUnimpl("request register")),
+
+setMaskBitReg.
+writer(this, &I8237::setMaskBit),
+
+modeReg.
+writer(writeUnimpl("mode register")),
+
+clearFlipFlopReg.
+writer(writeUnimpl("clear LSB/MSB flip-flop register")),
+
+temporaryMasterClearReg.
+reader(readUnimpl("temporary register")).
+writer(writeUnimpl("master clear register")),
+
+clearMaskReg.
+writer(writeUnimpl("clear mask regist
[gem5-dev] successful build setup on arm system
Hi, I am back to testing on an arm SBC. Does anyone know the recipe for a successful build on an arm box? GCC9 and clang 10 builds both die with obscure internal compiler errors. This is on an ubuntu 20.04 setup, compiling the develop branch. scons CC=clang CXX=clang++ build/ARM/gem5.opt -j4 I needed quite a few compiler warning overrides to get the clang10 build going. the above build command works fine on an x86_64 box. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: ARM full system boot that uses the HDLCD?
Thanks Ciro. Looking at that, my guess is that the kernel I'm using doesn't have HDLCD drivers, so it never sets that up and never tells it to start processing frames. That should hopefully be fairly easy to fix :-). Gabe On Mon, Nov 2, 2020 at 2:50 AM Ciro Santilli via gem5-dev wrote: > Gabe, last time I touched HDLCD a while back, it worked on fs.py with this > setup: > https://stackoverflow.com/questions/50364863/how-to-get-graphical-gui-output-and-user-touch-keyboard-mouse-input-in-a-ful/50364864#50364864 > I suppose the other main in-tree arm scripts would also work. > -- > *From:* Gabe Black via gem5-dev > *Sent:* Friday, October 30, 2020 1:41 AM > *To:* gem5 Developer List > *Cc:* Gabe Black > *Subject:* [gem5-dev] ARM full system boot that uses the HDLCD? > > Hey ARM folks. I want to take a look at optimizing the HDLCD framebuffer > output, VNC output, etc., since that's a big bottleneck when, for instance, > running Fast Model simulation. > > Is there a simple config I can run without using fast model, etc, which I > can use to test the HDLCD and those video features? I'll check how much > performance gain there is later on, but for now I just want to make sure I > don't break anything. > > Gabe > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Clean up the __init__s in (Sub)OperandList.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35818 )
Change subject: arch: Clean up the __init__s in (Sub)OperandList.
..
arch: Clean up the __init__s in (Sub)OperandList.
These had a lot of for loops and ifs and nesting. Python lets you avoid
that, which makes the code easier to read and more intuitive to
understand.
Change-Id: I576bf1de9e5b2268717a535ca42f2db669d83ed2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35818
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/isa_parser/operand_list.py
1 file changed, 51 insertions(+), 75 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser/operand_list.py
b/src/arch/isa_parser/operand_list.py
index 86de5a5..12a23d9 100755
--- a/src/arch/isa_parser/operand_list.py
+++ b/src/arch/isa_parser/operand_list.py
@@ -101,59 +101,42 @@
self.append(op_desc)
self.sort()
+
# enumerate source & dest register operands... used in building
# constructor later
-self.numSrcRegs = 0
-self.numDestRegs = 0
-self.numFPDestRegs = 0
-self.numIntDestRegs = 0
-self.numVecDestRegs = 0
-self.numVecPredDestRegs = 0
-self.numCCDestRegs = 0
-self.numMiscDestRegs = 0
-self.memOperand = None
+regs = list(filter(lambda i: i.isReg(), self.items))
+mem = list(filter(lambda i: i.isMem(), self.items))
+srcs = list(filter(lambda r: r.is_src, regs))
+dests = list(filter(lambda r: r.is_dest, regs))
+
+for idx, reg in enumerate(srcs):
+reg.src_reg_idx = idx
+for idx, reg in enumerate(dests):
+reg.dest_reg_idx = idx
+
+self.numSrcRegs = len(srcs)
+self.numDestRegs = len(dests)
+self.numFPDestRegs = sum(r.isFloatReg() for r in dests)
+self.numIntDestRegs = sum(r.isIntReg() for r in dests)
+self.numVecDestRegs = sum(r.isVecReg() for r in dests)
+self.numVecPredDestRegs = sum(r.isVecPredReg() for r in dests)
+self.numCCDestRegs = sum(r.isCCReg() for r in dests)
+self.numMiscDestRegs = sum(r.isControlReg() for r in dests)
+
+if len(mem) > 1:
+error("Code block has more than one memory operand")
+
+self.memOperand = mem[0] if mem else None
# Flags to keep track if one or more operands are to be
read/written
# conditionally.
-self.predRead = False
-self.predWrite = False
+self.predRead = any(i.hasReadPred() for i in self.items)
+self.predWrite = any(i.hasWritePred() for i in self.items)
-for op_desc in self.items:
-if op_desc.isReg():
-if op_desc.is_src:
-op_desc.src_reg_idx = self.numSrcRegs
-self.numSrcRegs += 1
-if op_desc.is_dest:
-op_desc.dest_reg_idx = self.numDestRegs
-self.numDestRegs += 1
-if op_desc.isFloatReg():
-self.numFPDestRegs += 1
-elif op_desc.isIntReg():
-self.numIntDestRegs += 1
-elif op_desc.isVecReg():
-self.numVecDestRegs += 1
-elif op_desc.isVecPredReg():
-self.numVecPredDestRegs += 1
-elif op_desc.isCCReg():
-self.numCCDestRegs += 1
-elif op_desc.isControlReg():
-self.numMiscDestRegs += 1
-elif op_desc.isMem():
-if self.memOperand:
-error("Code block has more than one memory operand.")
-self.memOperand = op_desc
-
-# Check if this operand has read/write predication. If true,
then
-# the microop will dynamically index source/dest registers.
-self.predRead = self.predRead or op_desc.hasReadPred()
-self.predWrite = self.predWrite or op_desc.hasWritePred()
-
-if parser.maxInstSrcRegs < self.numSrcRegs:
-parser.maxInstSrcRegs = self.numSrcRegs
-if parser.maxInstDestRegs < self.numDestRegs:
-parser.maxInstDestRegs = self.numDestRegs
-if parser.maxMiscDestRegs < self.numMiscDestRegs:
-parser.maxMiscDestRegs = self.numMiscDestRegs
+parser.maxInstSrcRegs = max(parser.maxInstSrcRegs, self.numSrcRegs)
+parser.maxInstDestRegs = max(parser.maxInstDestRegs,
self.numDestRegs)
+parser.maxMiscDestRegs = max(parser.maxInstDestRegs,
+ self.numMiscDestRegs)
# now make a final pass to finalize op_desc fields that may depend
# on the r
