[gem5-dev] Change in gem5/gem5[develop]: mem,sim: Get the page size from the page table in SE mode.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34172 )
Change subject: mem,sim: Get the page size from the page table in SE mode.
..
mem,sim: Get the page size from the page table in SE mode.
The page table already knows the size of a page without having to
directly use any ISA specific constants.
Change-Id: I68b575e194697065620a2097d972076886766f74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34172
Tested-by: kokoro
Reviewed-by: Bobby R. Bruce
Maintainer: Gabe Black
---
M src/mem/multi_level_page_table.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
M src/sim/mem_state.cc
M src/sim/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
7 files changed, 41 insertions(+), 39 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/multi_level_page_table.hh
b/src/mem/multi_level_page_table.hh
index 68a32b1..3d9ca9b 100644
--- a/src/mem/multi_level_page_table.hh
+++ b/src/mem/multi_level_page_table.hh
@@ -192,8 +192,8 @@
public:
MultiLevelPageTable(const std::string &__name, uint64_t _pid,
-System *_sys, Addr pageSize) :
-EmulationPageTable(__name, _pid, pageSize), system(_sys)
+System *_sys, Addr _pageSize) :
+EmulationPageTable(__name, _pid, _pageSize), system(_sys)
{}
~MultiLevelPageTable() {}
@@ -204,7 +204,7 @@
if (shared)
return;
-_basePtr = prepTopTable(system, pageSize);
+_basePtr = prepTopTable(system, _pageSize);
}
Addr basePtr() { return _basePtr; }
@@ -216,8 +216,8 @@
Final entry;
-for (int64_t offset = 0; offset < size; offset += pageSize) {
-walk(system, pageSize, _basePtr,
+for (int64_t offset = 0; offset < size; offset += _pageSize) {
+walk(system, _pageSize, _basePtr,
vaddr + offset, true, &entry);
entry.reset(paddr + offset, true, flags & Uncacheable,
@@ -236,16 +236,16 @@
Final old_entry, new_entry;
-for (int64_t offset = 0; offset < size; offset += pageSize) {
+for (int64_t offset = 0; offset < size; offset += _pageSize) {
// Unmap the original mapping.
-walk(system, pageSize, _basePtr, vaddr + offset,
+walk(system, _pageSize, _basePtr, vaddr +
offset,
false, &old_entry);
old_entry.present(false);
old_entry.write(system->physProxy);
// Map the new one.
-walk(system, pageSize, _basePtr, new_vaddr +
offset,
-true, &new_entry);
+walk(system, _pageSize, _basePtr,
+new_vaddr + offset, true, &new_entry);
new_entry.reset(old_entry.paddr(), true,
old_entry.uncacheable(),
old_entry.readonly());
new_entry.write(system->physProxy);
@@ -259,8 +259,8 @@
Final entry;
-for (int64_t offset = 0; offset < size; offset += pageSize) {
-walk(system, pageSize, _basePtr,
+for (int64_t offset = 0; offset < size; offset += _pageSize) {
+walk(system, _pageSize, _basePtr,
vaddr + offset, false, &entry);
fatal_if(!entry.present(),
"PageTable::unmap: Address %#x not mapped.", vaddr);
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 5318f35..d088d29 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -62,9 +62,9 @@
pTable.emplace(vaddr, Entry(paddr, flags));
}
-size -= pageSize;
-vaddr += pageSize;
-paddr += pageSize;
+size -= _pageSize;
+vaddr += _pageSize;
+paddr += _pageSize;
}
}
@@ -84,9 +84,9 @@
pTable.emplace(new_vaddr, old_it->second);
pTable.erase(old_it);
-size -= pageSize;
-vaddr += pageSize;
-new_vaddr += pageSize;
+size -= _pageSize;
+vaddr += _pageSize;
+new_vaddr += _pageSize;
}
}
@@ -108,8 +108,8 @@
auto it = pTable.find(vaddr);
assert(it != pTable.end());
pTable.erase(it);
-size -= pageSize;
-vaddr += pageSize;
+size -= _pageSize;
+vaddr += _pageSize;
}
}
@@ -119,7 +119,7 @@
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
-for (int64_t offset = 0; offset < size; offset += pageSize)
+for (int64_t offset = 0; offset < size; offset += _pageSize)
if (pTable.find(vaddr + offset) != pTable.end())
return false;
@@ -158,7 +158,7 @@
if (!translate(req->getVaddr(), paddr))
return Fault(new GenericP
[gem5-dev] Change in gem5/gem5[develop]: base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37175 )
Change subject: base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
..
base: Fix `AddrRange::addIntlvBits(Addr)` and new test.
The methods `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` should be the inverse of one another,
but the latter did not insert the blanks for filling the removed bits in
the correct positions. Since the masks are ordered increasingly by the
position of the least significant bit of each mask, the lowest bit that
has to be inserted at each iteration is always `intlv_bit`, not needing
to be shifted to the left or right. The bits that need to be copied
from the input address are `intlv_bit-1..0` at each iteration.
A new `AddrRangeTest.AddRemoveInterleavBitsAcrossContiguousRange` test
has been added to include a case in which the previous code fails but
the corrected code passes.
This function is not used anywhere other than the tests and the class
`ChannelAddr`. However, it is needed to implement efficiently multibank
caches in the classic mode.
Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Signed-off-by: Isaac Sánchez Barrera
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index e333b32..8a811d4 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -523,9 +523,10 @@
const int intlv_bit = masks_lsb[i];
if (intlv_bit > 0) {
// on every iteration we add one bit from the input
-// address, and therefore the lowest invtl_bit has
-// also shifted to the left by i positions.
-a = insertBits(a << 1, intlv_bit + i - 1, 0, a);
+// address, but the lowest invtl_bit in the iteration is
+// always in the right position because they are sorted
+// increasingly from the LSB
+a = insertBits(a << 1, intlv_bit - 1, 0, a);
} else {
a <<= 1;
}
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 34921d8..13b32a5 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -784,6 +784,34 @@
}
}
+TEST(AddrRangeTest, AddRemoveInterleavBitsAcrossContiguousRange)
+{
+/*
+ * This purpose of this test is to ensure that removing then adding
+ * interleaving bits has no net effect.
+ * E.g.:
+ * addr_range.addIntlvBits(add_range.removeIntlvBits(an_address))
should
+ * always return an_address.
+ */
+Addr start = 0x0;
+Addr end = 0x1;
+std::vector masks;
+masks.push_back(1 << 2);
+masks.push_back(1 << 3);
+masks.push_back(1 << 4);
+uint8_t intlv_match = 0x7;
+AddrRange r(start, end, masks, intlv_match);
+
+for (Addr i = 0; i < 0xFFF; i++) {
+Addr removedBits = r.removeIntlvBits(i);
+/*
+ * As intlv_match = 0x7, all the interleaved bits should be set.
+ */
+EXPECT_EQ(i | (1 << 2) | (1 << 3) | (1 << 4),
+ r.addIntlvBits(removedBits));
+}
+}
+
TEST(AddrRangeTest, InterleavingAddressesGetOffset)
{
Addr start = 0x0002;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37175
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Gerrit-Change-Number: 37175
Gerrit-PatchSet: 1
Gerrit-Owner: Isaac Sánchez Barrera
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add support for interleaved caches.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37176 )
Change subject: mem-cache: Add support for interleaved caches.
..
mem-cache: Add support for interleaved caches.
Add a specialization in the indexing policies and the tag table to allow
for interleaved caches (for example, multibank caches).
The new interleaved set-associative indexing policy makes use of the
address range of the cache, so the `BaseTags` class has a new parameter
with the address range from the parent cache as a default value. The
address manipulation for getting the tag and set or reconstructing the
original address is done with the `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` methods, so this new indexing policy
requires that its cache has one single address range.
Change-Id: I706fa27523b8a33604f18572f0b7e3e88286bbba
Signed-off-by: Isaac Sánchez Barrera
---
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/indexing_policies/IndexingPolicies.py
M src/mem/cache/tags/indexing_policies/SConscript
A src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
A src/mem/cache/tags/indexing_policies/intlv_set_associative.hh
5 files changed, 231 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index ce086fa..1f0abb1 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -71,6 +71,9 @@
entry_size = Param.Int(Parent.cache_line_size,
"Indexing entry size in bytes")
+# The addr_ranges of the cache might be needed by some indexing
policies
+addr_ranges = VectorParam.AddrRange(Parent.addr_ranges, "Address
ranges")
+
class BaseSetAssoc(BaseTags):
type = 'BaseSetAssoc'
cxx_header = "mem/cache/tags/base_set_assoc.hh"
@@ -82,6 +85,9 @@
replacement_policy = Param.BaseReplacementPolicy(
Parent.replacement_policy, "Replacement policy")
+class IntlvSetAssocTags(BaseSetAssoc):
+indexing_policy = IntlvSetAssociative()
+
class SectorTags(BaseTags):
type = 'SectorTags'
cxx_header = "mem/cache/tags/sector_tags.hh"
diff --git a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
index 7414ddf..237b938 100644
--- a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
+++ b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
@@ -51,3 +51,10 @@
type = 'SkewedAssociative'
cxx_class = 'SkewedAssociative'
cxx_header = "mem/cache/tags/indexing_policies/skewed_associative.hh"
+
+class IntlvSetAssociative(SetAssociative):
+type = 'IntlvSetAssociative'
+cxx_class = 'IntlvSetAssociative'
+cxx_header
= "mem/cache/tags/indexing_policies/intlv_set_associative.hh"
+
+addr_ranges = VectorParam.AddrRange(Parent.addr_ranges, "address
ranges")
diff --git a/src/mem/cache/tags/indexing_policies/SConscript
b/src/mem/cache/tags/indexing_policies/SConscript
index 98c9202..581fd0e 100644
--- a/src/mem/cache/tags/indexing_policies/SConscript
+++ b/src/mem/cache/tags/indexing_policies/SConscript
@@ -30,5 +30,6 @@
SimObject('IndexingPolicies.py')
Source('base.cc')
+Source('intlv_set_associative.cc')
Source('set_associative.cc')
Source('skewed_associative.cc')
diff --git a/src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
b/src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
new file mode 100644
index 000..8a0d326
--- /dev/null
+++ b/src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2020 Barcelona Supercomputing Center (BSC)
+ * Copyright (c) 2018 Inria
+ * Copyright (c) 2012-2014,2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the di
[gem5-dev] Change in gem5/gem5[develop]: tests: Update guest binaries used by regressions
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/37177 ) Change subject: tests: Update guest binaries used by regressions .. tests: Update guest binaries used by regressions The new tarball (aarch-system-20200611.tar.bz2) contains the m5_exit_addr.squashfs.arm64 disk image to be used by KVM regressions This disk image is based on a memory mapped m5 exit Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890 Signed-off-by: Giacomo Travaglini --- M tests/gem5/fs/linux/arm/test.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem5/fs/linux/arm/test.py b/tests/gem5/fs/linux/arm/test.py index 33ca33e..482dd1d 100644 --- a/tests/gem5/fs/linux/arm/test.py +++ b/tests/gem5/fs/linux/arm/test.py @@ -88,7 +88,7 @@ #'realview64-o3-checker', ] -tarball = 'aarch-system-201901106.tar.bz2' +tarball = 'aarch-system-20200611.tar.bz2' url = config.resource_url + "/arm/" + tarball filepath = os.path.dirname(os.path.abspath(__file__)) path = joinpath(config.bin_path, 'arm') -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37177 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890 Gerrit-Change-Number: 37177 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: misc: Convert MAINTAINERS to YAML
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37035 ) Change subject: misc: Convert MAINTAINERS to YAML .. misc: Convert MAINTAINERS to YAML Convert MAINTAINERS to YAML and rename it to MAINTAINERS.yaml. Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37035 Reviewed-by: Hoa Nguyen Maintainer: Jason Lowe-Power Tested-by: kokoro --- D MAINTAINERS A MAINTAINERS.yaml 2 files changed, 303 insertions(+), 147 deletions(-) Approvals: Hoa Nguyen: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/MAINTAINERS b/MAINTAINERS deleted file mode 100644 index 7ae23fd..000 --- a/MAINTAINERS +++ /dev/null @@ -1,147 +0,0 @@ -See CONTRIBUTING.md for details of gem5's contribution process. - -This file contains the keywords used in commit messages. Each keyword has one -or more maintainers. At least one (not all) of these maintainers must review -the patch before it can be pushed. These people will automatically be emailed -when you upload the patch to Gerrit (https://gem5-review.googlesource.com). -These keywords mostly follow the directory structure. - -Maintainers have the following responsibilities: -1. That at least one maintainer of each subsystem reviews all changes to that - subsystem (they will be automatically tagged and emailed on each new - change). -2. They will complete your reviews in a timely manner (within a few business - days). -3. They pledge to uphold gem5's community standards and its code of conduct by - being polite and professional in their code reviews. See CODE-OF-CONDUCT.md. - -PMC Members (general maintainers): - Andreas Sandberg - Brad Beckmann - David Wood - Gabe Black - Giacomo Travaglini - Jason Lowe-Power (chair) - Matt Sinclair - Tony Gutierrez - Steve Reinhardt - -arch: General architecture-specific components - Gabe Black -arch-arm: - Andreas Sandberg - Giacomo Travaglini -arch-gcn3: - UNSUPPORTED -arch-mips: - UNSUPPORTED -arch-power: - Boris Shingarov -arch-riscv: - UNSUPPORTED -arch-sparc: - Gabe Black -arch-x86: - Gabe Black - -base: - Bobby Bruce -base-stats: - UNSUPPORTED - -configs: - Jason Lowe-Power - -cpu: General changes to all CPU models (e.g., BaseCPU) - Gabe Black - Jason Lowe-Power -cpu-kvm: - Andreas Sandberg -cpu-minor: - Zhengrong Wang -cpu-o3: - UNSUPPORTED -cpu-simple: - Jason Lowe-Power - Gabe Black - -dev: - Gabe Black -dev-hsa: - UNSUPPORTED -dev-virtio: - Andreas Sandberg -dev-arm: - Andreas Sandberg - Giacomo Travaglini - -doc: - Bobby Bruce - -ext: Components external to gem5 - Bobby Bruce - Jason Lowe-Power -ext-testlib: - Bobby Bruce - Hoa Nguyen - -fastmodel: Changes relating to ARM Fast Models - Gabe Black - -gpu-compute: - Matt Poremba - -learning-gem5: The code and configs for the Learning gem5 book - Jason Lowe-Power - -mem: General memory system (e.g., XBar, Packet) - Nikos Nikoleris -mem-cache: Classic caches and coherence - Nikos Nikoleris -mem-dram: - Nikos Nikoleris -mem-garnet: Garnet subcomponent of Ruby - Srikant Bharadwaj -mem-ruby: Ruby structures and protocols - Jason Lowe-Power - -misc: Anything outside of the other categories - Bobby Bruce - Jason Lowe-Power - -python: Python SimObject wrapping and infrastructure - Andreas Sandberg - Jason Lowe-Power - -resources: The gem5-resources repo with auxiliary resources for simulation - Bobby Bruce - Jason Lowe-Power - -scons: Build system - Gabe Black - -sim: General simulation components - Jason Lowe-Power -sim-se: Syscall emulation - UNSUPPORTED - -system-arm: - Andreas Sandberg - Giacomo Travaglini - -systemc: Code for the gem5 SystemC implementation and interface - Gabe Black - -tests: testing changes - Bobby Bruce - -util: - Gabe Black -util-docker: - Bobby Bruce -util-m5: - Gabe Black - -website: The gem5-website repo which contains the gem5.org site - Bobby Bruce - Hoa Nguyen diff --git a/MAINTAINERS.yaml b/MAINTAINERS.yaml new file mode 100644 index 000..8a2bf75 --- /dev/null +++ b/MAINTAINERS.yaml @@ -0,0 +1,303 @@ +# See CONTRIBUTING.md for details of gem5's contribution process. +# +# This file contains a list of gem5's subsystems and their +# maintainers. The key used to identifity a subsystem should be used +# as a tag in commit messages targetting that subsystem. At least one +# (not all) of these maintainers must review the patch before it can +# be pushed. These people will automatically be emailed when you +# upload the patch to Gerrit (https://gem5-review.googlesource.com). +# These subsystem keys mostly follow the directory structure. +# +# Maintainers have the following responsibilities: +# 1. That at least one maintainer of each su
[gem5-dev] Change in gem5/gem5[develop]: arch-x86, cpu-kvm: add x86 kvm test to long regression
mike upton has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34855 )
Change subject: arch-x86, cpu-kvm: add x86 kvm test to long regression
..
arch-x86, cpu-kvm: add x86 kvm test to long regression
revised patch based on reviews
Change-Id: I18d219080ff8ab1c42c9e1a12aadd89606802b25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34855
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: mike upton
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 13 insertions(+), 4 deletions(-)
Approvals:
mike upton: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index d73f3a1..94b6e7e 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -25,7 +25,9 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
+import subprocess
from testlib import *
+import platform
if config.bin_path:
@@ -43,8 +45,10 @@
image = DownloadedProgram(image_url, base_path, image_name, True)
kernel = DownloadedProgram(kernel_url, base_path, kernel_name)
+def support_kvm():
+return os.access("/dev/kvm", os.R_OK | os.W_OK)
-def test_boot(cpu_type, num_cpus, boot_type):
+def test_boot(cpu_type, num_cpus, boot_type, host):
gem5_verify_config(
name = 'test-ubuntu_boot-' + cpu_type + '_cpu-' + num_cpus
+ '_cpus-'
+ boot_type + '_boot',
@@ -59,14 +63,19 @@
'--boot-type', boot_type,
],
valid_isas = ('X86',),
-valid_hosts = constants.supported_hosts,
+valid_hosts = host,
length = constants.long_tag,
)
# Test every CPU type
cpu_types = ('atomic', 'simple',)
for cpu_type in cpu_types:
-test_boot(cpu_type, '1', 'init')
+test_boot(cpu_type, '1', 'init', constants.supported_hosts)
# Test a multicore system
-test_boot('atomic', '4', 'systemd')
+test_boot('atomic', '4', 'systemd', constants.supported_hosts)
+
+#KVM
+if(support_kvm() and (platform.machine() == constants.host_x86_64_tag)):
+test_boot('kvm', '1', 'init', (constants.host_x86_64_tag,))
+test_boot('kvm', '4', 'systemd', (constants.host_x86_64_tag,))
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34855
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18d219080ff8ab1c42c9e1a12aadd89606802b25
Gerrit-Change-Number: 34855
Gerrit-PatchSet: 4
Gerrit-Owner: mike upton
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-Reviewer: mike upton
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Specify version of rocm-cmake in gcn3 Dockerfile
Kyle Roarty has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37155 ) Change subject: util: Specify version of rocm-cmake in gcn3 Dockerfile .. util: Specify version of rocm-cmake in gcn3 Dockerfile This patch updates the gcn3 Dockerfile to use the version of rocm-cmake that MIOpen specifies in its dev-requirements.txt. This fixes a build conflict with newer versions of rocm-cmake that require a higher version of SCons than we have in the Dockerfile. Change-Id: I70887fd91807b77e5015037830cfe96560ac8a31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37155 Maintainer: Gabe Black Maintainer: Matt Sinclair Reviewed-by: Bobby R. Bruce Reviewed-by: Matt Sinclair Tested-by: kokoro --- M util/dockerfiles/gcn-gpu/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Matt Sinclair: Looks good to me, approved; Looks good to me, approved Bobby R. Bruce: Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/util/dockerfiles/gcn-gpu/Dockerfile b/util/dockerfiles/gcn-gpu/Dockerfile index 7a9ec8f..19f3ad7 100644 --- a/util/dockerfiles/gcn-gpu/Dockerfile +++ b/util/dockerfiles/gcn-gpu/Dockerfile @@ -73,6 +73,7 @@ RUN git -C /HIP/ checkout 0e3d824e && git -C /HIP/ apply /patch/hip.patch_v2 && \ git -C /hipBLAS/ checkout ee57787e && git -C /hipBLAS/ apply /patch/hipBLAS.patch && \ git -C /rocBLAS/ checkout cbff4b4e && git -C /rocBLAS/ apply /patch/rocBLAS.patch && \ +git -C /rocm-cmake/ checkout 12670acb && \ git -C /MIOpenGEMM/ checkout 9547fb9e && \ git -C /MIOpen/ checkout 01d6ca55c && git -C /MIOpen/ apply /patch/miopen-conv.patch -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37155 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I70887fd91807b77e5015037830cfe96560ac8a31 Gerrit-Change-Number: 37155 Gerrit-PatchSet: 2 Gerrit-Owner: Kyle Roarty Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Kyle Roarty Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: Revert "arch-x86, cpu-kvm: add x86 kvm test to long regression"
Attention is currently required from: Bobby R. Bruce, Giacomo Travaglini,
Gabe Black.
Hello kokoro, Bobby R. Bruce, Giacomo Travaglini, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/37119
to review the following change.
Change subject: Revert "arch-x86, cpu-kvm: add x86 kvm test to long
regression"
..
Revert "arch-x86, cpu-kvm: add x86 kvm test to long regression"
This reverts commit 04b87cc29ae5195e0c2fcc1ad895b350de4aa066.
Reason for revert: should not have pushed, missed comments.
Change-Id: I91e32a0a4fbe1ea0c1e0b4aae88ffa1667bdec26
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index 94b6e7e..d73f3a1 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -25,9 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
-import subprocess
from testlib import *
-import platform
if config.bin_path:
@@ -45,10 +43,8 @@
image = DownloadedProgram(image_url, base_path, image_name, True)
kernel = DownloadedProgram(kernel_url, base_path, kernel_name)
-def support_kvm():
-return os.access("/dev/kvm", os.R_OK | os.W_OK)
-def test_boot(cpu_type, num_cpus, boot_type, host):
+def test_boot(cpu_type, num_cpus, boot_type):
gem5_verify_config(
name = 'test-ubuntu_boot-' + cpu_type + '_cpu-' + num_cpus
+ '_cpus-'
+ boot_type + '_boot',
@@ -63,19 +59,14 @@
'--boot-type', boot_type,
],
valid_isas = ('X86',),
-valid_hosts = host,
+valid_hosts = constants.supported_hosts,
length = constants.long_tag,
)
# Test every CPU type
cpu_types = ('atomic', 'simple',)
for cpu_type in cpu_types:
-test_boot(cpu_type, '1', 'init', constants.supported_hosts)
+test_boot(cpu_type, '1', 'init')
# Test a multicore system
-test_boot('atomic', '4', 'systemd', constants.supported_hosts)
-
-#KVM
-if(support_kvm() and (platform.machine() == constants.host_x86_64_tag)):
-test_boot('kvm', '1', 'init', (constants.host_x86_64_tag,))
-test_boot('kvm', '4', 'systemd', (constants.host_x86_64_tag,))
+test_boot('atomic', '4', 'systemd')
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37119
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I91e32a0a4fbe1ea0c1e0b4aae88ffa1667bdec26
Gerrit-Change-Number: 37119
Gerrit-PatchSet: 1
Gerrit-Owner: mike upton
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-Attention: Bobby R. Bruce
Gerrit-Attention: Giacomo Travaglini
Gerrit-Attention: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86, kvm: clean up x86 long regresion kvm code
mike upton has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37120 )
Change subject: arch-x86, kvm: clean up x86 long regresion kvm code
..
arch-x86, kvm: clean up x86 long regresion kvm code
This commit cleans up the code for x86 kvm long regressions.
Somehow the old version went is as the last patchset.
This is the intended code, which should match the last comments.
Change-Id: I9af02a51ce8ed5098887fb0a6b9240db95227bc3
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index 94b6e7e..3140595 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -25,9 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
-import subprocess
from testlib import *
-import platform
if config.bin_path:
@@ -76,6 +74,6 @@
test_boot('atomic', '4', 'systemd', constants.supported_hosts)
#KVM
-if(support_kvm() and (platform.machine() == constants.host_x86_64_tag)):
+if(support_kvm()):
test_boot('kvm', '1', 'init', (constants.host_x86_64_tag,))
test_boot('kvm', '4', 'systemd', (constants.host_x86_64_tag,))
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37120
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9af02a51ce8ed5098887fb0a6b9240db95227bc3
Gerrit-Change-Number: 37120
Gerrit-PatchSet: 1
Gerrit-Owner: mike upton
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[hotfix-garnet-network-interface]: misc: Updated the RELEASE-NOTES and version number
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37116 ) Change subject: misc: Updated the RELEASE-NOTES and version number .. misc: Updated the RELEASE-NOTES and version number Updated the RELEASE-NOTES.md and version number for the v20.1.0.1 hot-fix. Change-Id: I51f7ba6f1178a2d8e80488ed2184b8735c2234a2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37116 Maintainer: Bobby R. Bruce Reviewed-by: Daniel Carvalho Tested-by: kokoro --- M RELEASE-NOTES.md M src/Doxyfile M src/base/version.cc 3 files changed, 8 insertions(+), 2 deletions(-) Approvals: Daniel Carvalho: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 492bb96..46c8795 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -1,3 +1,9 @@ +# Version 20.1.0.1 + +**[HOTFIX]** A patch was applied to fix the Garnet network interface stats. +Previously, the flit source delay was computed using both tick and cycles. +This bug affected the overall behavior of the Garnet Network Model. + # Version 20.1.0.0 Thank you to everyone that made this release possible! diff --git a/src/Doxyfile b/src/Doxyfile index d029a66..83770d5 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = v20.1.0.0 +PROJECT_NUMBER = v20.1.0.1 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index 8edb8c6..3ad07fa 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -29,4 +29,4 @@ /** * @ingroup api_base_utils */ -const char *gem5Version = "20.1.0.0"; +const char *gem5Version = "20.1.0.1"; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37116 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: hotfix-garnet-network-interface Gerrit-Change-Id: I51f7ba6f1178a2d8e80488ed2184b8735c2234a2 Gerrit-Change-Number: 37116 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-garnet-network-interface]: mem-garnet: Fix garnet network interface stats
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37115 ) Change subject: mem-garnet: Fix garnet network interface stats .. mem-garnet: Fix garnet network interface stats Fixing a bug in garnet network interface where flit source delay is computed using both tick and cycle. Change-Id: If21a985f371a818611d13e9cd5ce344dbcf5fb2b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36416 Reviewed-by: Srikant Bharadwaj Maintainer: Matthew Poremba Tested-by: kokoro Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37115 Maintainer: Bobby R. Bruce Reviewed-by: Daniel Carvalho Reviewed-by: Jieming Yin --- M src/mem/ruby/network/garnet/NetworkInterface.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Jieming Yin: Looks good to me, approved Srikant Bharadwaj: Looks good to me, approved Daniel Carvalho: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/network/garnet/NetworkInterface.cc b/src/mem/ruby/network/garnet/NetworkInterface.cc index 6dbe0d9..bd5390f 100644 --- a/src/mem/ruby/network/garnet/NetworkInterface.cc +++ b/src/mem/ruby/network/garnet/NetworkInterface.cc @@ -435,7 +435,7 @@ net_msg_ptr->getMessageSize()), oPort->bitWidth(), curTick()); -fl->set_src_delay(curTick() - ticksToCycles(msg_ptr->getTime())); +fl->set_src_delay(curTick() - msg_ptr->getTime()); niOutVcs[vc].insert(fl); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37115 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: hotfix-garnet-network-interface Gerrit-Change-Id: If21a985f371a818611d13e9cd5ce344dbcf5fb2b Gerrit-Change-Number: 37115 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jieming Yin Gerrit-Reviewer: Srikant Bharadwaj Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: include system syscall header in syscall table files
Kyle Roarty has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/37195 ) Change subject: arch-x86: include system syscall header in syscall table files .. arch-x86: include system syscall header in syscall table files The getdents syscall is only implemented on hosts that define SYS_getdents, which is located in . That header was missed when splitting the syscall tables into their own files; this patch adds the header to the syscall table files. Change-Id: I28d54f6ea2874aa533c89ed7520561e19fe5e5f9 --- M src/arch/x86/linux/syscall_tbl32.cc M src/arch/x86/linux/syscall_tbl64.cc 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/linux/syscall_tbl32.cc b/src/arch/x86/linux/syscall_tbl32.cc index 855de88..50d0969 100644 --- a/src/arch/x86/linux/syscall_tbl32.cc +++ b/src/arch/x86/linux/syscall_tbl32.cc @@ -25,6 +25,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include + #include "arch/x86/linux/linux.hh" #include "arch/x86/linux/se_workload.hh" #include "arch/x86/linux/syscalls.hh" diff --git a/src/arch/x86/linux/syscall_tbl64.cc b/src/arch/x86/linux/syscall_tbl64.cc index 3516ea2..8630265 100644 --- a/src/arch/x86/linux/syscall_tbl64.cc +++ b/src/arch/x86/linux/syscall_tbl64.cc @@ -25,6 +25,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include + #include "arch/x86/linux/linux.hh" #include "arch/x86/linux/se_workload.hh" #include "arch/x86/linux/syscalls.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37195 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I28d54f6ea2874aa533c89ed7520561e19fe5e5f9 Gerrit-Change-Number: 37195 Gerrit-PatchSet: 1 Gerrit-Owner: Kyle Roarty Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] gem5 v20.1.0.1 Hotfix Release [Garnet Network Model]
Dear all, In the gem5 v20.1.0.0 release there was a bug in the Garnet Network Stats, which adversely affected the overall behavior of the Garnet Network Model. The bug, and related fix, are discussed here: https://gem5-review.googlesource.com/c/public/gem5/+/36416. On November 6th, we applied this fix to the stable branch, marking the release of gem5 v20.1.0.1. Those using the Garnet Network Model are strongly encouraged to pull this largest release from the gem5 stable branch : https://gem5.googlesource.com/public/gem5 Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: include system syscall header in syscall table files
Kyle Roarty has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/37195 ) Change subject: arch-x86: include system syscall header in syscall table files .. arch-x86: include system syscall header in syscall table files The getdents syscall is only implemented on hosts that define SYS_getdents, which is located in . That header was missed when splitting the syscall tables into their own files; this patch adds the header to the syscall table files. Change-Id: I28d54f6ea2874aa533c89ed7520561e19fe5e5f9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37195 Reviewed-by: Matt Sinclair Reviewed-by: Matthew Poremba Maintainer: Matt Sinclair Maintainer: Gabe Black Tested-by: kokoro --- M src/arch/x86/linux/syscall_tbl32.cc M src/arch/x86/linux/syscall_tbl64.cc 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Matthew Poremba: Looks good to me, approved Matt Sinclair: Looks good to me, approved; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/x86/linux/syscall_tbl32.cc b/src/arch/x86/linux/syscall_tbl32.cc index 855de88..50d0969 100644 --- a/src/arch/x86/linux/syscall_tbl32.cc +++ b/src/arch/x86/linux/syscall_tbl32.cc @@ -25,6 +25,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include + #include "arch/x86/linux/linux.hh" #include "arch/x86/linux/se_workload.hh" #include "arch/x86/linux/syscalls.hh" diff --git a/src/arch/x86/linux/syscall_tbl64.cc b/src/arch/x86/linux/syscall_tbl64.cc index 3516ea2..8630265 100644 --- a/src/arch/x86/linux/syscall_tbl64.cc +++ b/src/arch/x86/linux/syscall_tbl64.cc @@ -25,6 +25,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include + #include "arch/x86/linux/linux.hh" #include "arch/x86/linux/se_workload.hh" #include "arch/x86/linux/syscalls.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37195 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I28d54f6ea2874aa533c89ed7520561e19fe5e5f9 Gerrit-Change-Number: 37195 Gerrit-PatchSet: 2 Gerrit-Owner: Kyle Roarty Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Kyle Roarty Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: kokoro Gerrit-CC: Daniel Gerzhoy Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
