[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Bare metal workload.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45045 )
Change subject: arch-x86: Bare metal workload.
..
arch-x86: Bare metal workload.
Change-Id: I9ff6f5a9970cc7af2ba639be18f1881748074777
---
M src/arch/x86/X86FsWorkload.py
A src/arch/x86/bare_metal/SConscript
A src/arch/x86/bare_metal/workload.cc
A src/arch/x86/bare_metal/workload.hh
4 files changed, 180 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/X86FsWorkload.py b/src/arch/x86/X86FsWorkload.py
index 1a4248f..95dc8fa 100644
--- a/src/arch/x86/X86FsWorkload.py
+++ b/src/arch/x86/X86FsWorkload.py
@@ -39,7 +39,12 @@
from m5.objects.SMBios import X86SMBiosSMBiosTable
from m5.objects.IntelMP import X86IntelMPFloatingPointer,
X86IntelMPConfigTable
from m5.objects.ACPI import X86ACPIRSDP
-from m5.objects.Workload import KernelWorkload
+from m5.objects.Workload import KernelWorkload, Workload
+
+class X86BareMetalWorkload(Workload):
+type = 'X86BareMetalWorkload'
+cxx_header = 'arch/x86/bare_metal/workload.hh'
+cxx_class = 'X86ISA::BareMetalWorkload'
class X86FsWorkload(KernelWorkload):
type = 'X86FsWorkload'
diff --git a/src/arch/x86/bare_metal/SConscript
b/src/arch/x86/bare_metal/SConscript
new file mode 100644
index 000..817a60d
--- /dev/null
+++ b/src/arch/x86/bare_metal/SConscript
@@ -0,0 +1,46 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2005-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+if env['TARGET_ISA'] != 'x86':
+Return()
+
+Source('workload.cc')
diff --git a/src/arch/x86/bare_metal/workload.cc
b/src/arch/x86/bare_metal/workload.cc
new file mode 100644
index 000..5e03bdc
--- /dev/null
+++ b/src/arch/x86/bare_metal/workload.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED.
[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Use GuestABI to call pseudo insts.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42388 )
Change subject: arch-sparc: Use GuestABI to call pseudo insts.
..
arch-sparc: Use GuestABI to call pseudo insts.
Rather than decode and call each PsuedoInst function one by one, we can
use a GuestABI which knows how to marshal arguments and return values
and call the pseudoInst dispatch function which will do the work for us,
and make SPARC able to call any pseudo inst, not just the ones it was
hard coded to recognize.
Change-Id: I28192c4feeaf86a77c0f23c5b131929e45ec6d74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42388
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Gabe Black
---
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/includes.isa
A src/arch/sparc/pseudo_inst_abi.hh
3 files changed, 77 insertions(+), 26 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 8535242..1917207 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1001,30 +1001,12 @@
0x81: FailUnimpl::siam();
}
// M5 special opcodes use the reserved IMPDEP2A opcode space
-0x37: decode M5FUNC {
-format BasicOperate {
-// we have 7 bits of space here to play with...
-0x21: m5exit({{
-PseudoInst::m5exit(xc->tcBase(), O0);
-}}, No_OpClass, IsNonSpeculative);
-0x23: m5sum({{
-O0 = PseudoInst::m5sum(xc->tcBase(),
-O0, O1, O2, O3, O4, O5);
-}}, IsNonSpeculative);
-0x50: m5readfile({{
-O0 = PseudoInst::readfile(xc->tcBase(), O0, O1,
O2);
-}}, IsNonSpeculative);
-0x51: m5break({{
-PseudoInst::debugbreak(xc->tcBase());
-}}, IsNonSpeculative);
-0x54: m5panic({{
-panic("M5 panic instruction called at pc = %#x.",
PC);
-}}, No_OpClass, IsNonSpeculative);
-}
-default: Trap::impdep2({{
+0x37: BasicOperate::pseudo_inst({{
+if (!PseudoInst::pseudoInst(
+xc->tcBase(), M5FUNC)) {
fault = std::make_shared();
-}});
-}
+}
+}}, No_OpClass, IsNonSpeculative);
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if (target & 0x3) {
diff --git a/src/arch/sparc/isa/includes.isa
b/src/arch/sparc/isa/includes.isa
index dba7f18..1dade27 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -53,15 +53,16 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh" // some constructors use MemReq flags
+
}};
output decoder {{
#include
#include "arch/sparc/decoder.hh"
-#include "base/loader/symtab.hh"
#include "base/cprintf.hh"
#include "base/fenv.hh"
+#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
@@ -69,13 +70,13 @@
}};
output exec {{
-#include "base/fenv.hh"
-
#include
#include
#include "arch/generic/memhelpers.hh"
#include "arch/sparc/asi.hh"
+#include "arch/sparc/pseudo_inst_abi.hh"
+#include "base/fenv.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/Sparc.hh"
diff --git a/src/arch/sparc/pseudo_inst_abi.hh
b/src/arch/sparc/pseudo_inst_abi.hh
new file mode 100644
index 000..446043a
--- /dev/null
+++ b/src/arch/sparc/pseudo_inst_abi.hh
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE
[gem5-dev] Change in gem5/gem5[develop]: base: Make the BaseRemoteGDB class able to handle multiple TCs.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44611 )
Change subject: base: Make the BaseRemoteGDB class able to handle multiple
TCs.
..
base: Make the BaseRemoteGDB class able to handle multiple TCs.
Only one is set up corrent, the one passed in from the constructor.
Others can be added with addThreadContext.
The inconsistency of adding one ThreadContext through the constructor
and others through addThreadContext isn't great, but this way we can
ensure that there is always at least one ThreadContext. I'm not sure
what the GDB stub should do if there aren't any threads. I don't think
that the protocol can actually handle that, judging from the
documentation I can find.
Change-Id: I9160c3701ce78dcbbe99de1a6fe2a13e7e69404e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44611
Reviewed-by: Gabe Black
Reviewed-by: Daniel Carvalho
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/null/remote_gdb.hh
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/sim/system.cc
4 files changed, 74 insertions(+), 21 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/null/remote_gdb.hh b/src/arch/null/remote_gdb.hh
index c47ca9b..cef2338 100644
--- a/src/arch/null/remote_gdb.hh
+++ b/src/arch/null/remote_gdb.hh
@@ -38,6 +38,8 @@
#ifndef __ARCH_NULL_REMOTE_GDB_HH__
#define __ARCH_NULL_REMOTE_GDB_HH__
+#include "base/types.hh"
+
class ThreadContext;
class BaseRemoteGDB
@@ -47,7 +49,7 @@
bool breakpoint() { return false; }
void replaceThreadContext(ThreadContext *tc) {}
-bool trap(int type) { return true; }
+bool trap(ContextID id, int type) { return true; }
virtual ~BaseRemoteGDB() {}
};
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 98686cf..8839f81 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -132,9 +132,11 @@
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -182,7 +184,7 @@
DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc());
if (tc == gdb->tc)
-gdb->trap(SIGTRAP);
+gdb->trap(tc->contextId(), SIGTRAP);
}
};
@@ -351,9 +353,10 @@
BaseRemoteGDB::BaseRemoteGDB(System *_system, ThreadContext *c, int
_port) :
connectEvent(nullptr), dataEvent(nullptr), _port(_port), fd(-1),
-active(false), attached(false), sys(_system), tc(c),
+active(false), attached(false), sys(_system),
trapEvent(this), singleStepEvent(*this)
{
+addThreadContext(c);
}
BaseRemoteGDB::~BaseRemoteGDB()
@@ -438,11 +441,36 @@
}
void
+BaseRemoteGDB::addThreadContext(ThreadContext *_tc)
+{
+M5_VAR_USED auto it_success = threads.insert({_tc->contextId(), _tc});
+assert(it_success.second);
+// If no ThreadContext is current selected, select this one.
+if (!tc)
+assert(selectThreadContext(_tc->contextId()));
+}
+
+void
BaseRemoteGDB::replaceThreadContext(ThreadContext *_tc)
{
-ContextID id = _tc->contextId();
-panic_if(id != tc->contextId(), "No context with ID %d found.", id);
-tc = _tc;
+auto it = threads.find(_tc->contextId());
+panic_if(it == threads.end(), "No context with ID %d found.",
+_tc->contextId());
+it->second = _tc;
+}
+
+bool
+BaseRemoteGDB::selectThreadContext(ContextID id)
+{
+auto it = threads.find(id);
+if (it == threads.end())
+return false;
+
+tc = it->second;
+// Update the register cache for the new thread context, if there is
one.
+if (regCachePtr)
+regCachePtr->getRegs(tc);
+return true;
}
// This function does all command processing for interfacing to a
@@ -451,12 +479,16 @@
// makes sense to use POSIX errno values, because that is what the
// gdb/remote.c functions want to return.
bool
-BaseRemoteGDB::trap(int type)
+BaseRemoteGDB::trap(ContextID id, int type)
{
-
if (!attached)
return false;
+if (tc->contextId() != id) {
+if (!selectThreadContext(id))
+return false;
+}
+
DPRINTF(GDBMisc, "trap: PC=%s\n", tc->pcState());
clearSingleStep();
@@ -534,6 +566,7 @@
if (revent & POLLIN) {
trapEvent.type(SIGILL);
+trapEvent.id(tc->contextId());
scheduleInstCommitEvent(, 0);
} else if (revent & POLLNVAL) {
descheduleInstCommitEvent();
@@ -688,7 +721,7 @@
{
if (!singleStepEvent.scheduled())
scheduleInstCommitEvent(, 1);
-trap(SIGTRAP);
+trap(tc->contextId(), SIGTRAP);
}
void
@@ -927,11 +960,13 @@
// should complain.
if (all)
throw CmdError("E03");
-// If GDB cares which thread we're using and wants a different
one, we
-// don't
[gem5-dev] Change in gem5/gem5[develop]: base: Fill out the 'H' thread setting command in remote GDB.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44609 )
Change subject: base: Fill out the 'H' thread setting command in remote GDB.
..
base: Fill out the 'H' thread setting command in remote GDB.
Distinguish between the 'g' and 'c' subcommands. 'c' sets what thread(s)
should be continued or single stepped when those commands are used, and
'g' sets what thread(s) should be used for anything else. Also, insist
that all threads are used for continuing or single stepping.
Still complain if we're asked to switch threads, since we only have one
and we can't change to anything else.
Change-Id: Ia15c055baba48f75fc29ef369567535b0aa2c76b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44609
Tested-by: kokoro
Reviewed-by: Bobby R. Bruce
Reviewed-by: Daniel Carvalho
Maintainer: Bobby R. Bruce
---
M src/base/remote_gdb.cc
1 file changed, 24 insertions(+), 4 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index efda8e8..98686cf 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -909,13 +909,33 @@
bool
BaseRemoteGDB::cmdSetThread(GdbCommand::Context )
{
-const char *p = ctx.data + 1; // Ignore the subcommand byte.
-ContextID tid = 0;
+const char *p = ctx.data;
+char subcommand = *p++;
+int tid = 0;
bool all, any;
if (!parseThreadId(, all, any, tid))
throw CmdError("E01");
-if (any || all || tid != tc->contextId())
-throw CmdError("E02");
+
+if (subcommand == 'c') {
+// We can only single step or continue all threads at once, since
we
+// stop time itself and not individual threads.
+if (!all)
+throw CmdError("E02");
+} else if (subcommand == 'g') {
+// We don't currently support reading registers, memory, etc, from
all
+// threads at once. GDB may never ask for this, but if it does we
+// should complain.
+if (all)
+throw CmdError("E03");
+// If GDB cares which thread we're using and wants a different
one, we
+// don't support that right now.
+if (!any && tid != tc->contextId())
+throw CmdError("E04");
+// Since we weren't asked to do anything, we succeeded.
+} else {
+throw CmdError("E05");
+}
+
send("OK");
return true;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia15c055baba48f75fc29ef369567535b0aa2c76b
Gerrit-Change-Number: 44609
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Stop using DPRINTF_UNCONDITIONAL in the event class.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44986 )
Change subject: sim: Stop using DPRINTF_UNCONDITIONAL in the event class.
..
sim: Stop using DPRINTF_UNCONDITIONAL in the event class.
Just because the current methods of the base class only call
Event::trace from within DTRACE(Event), that's no guarantee that future
methods will, that the call sites won't be changed so that they don't,
or any number of subclasses that may not even exist today will.
Instead, we should incur the very slight overhead of checking the
Debug::Event variable again to ensure expected behavior, and to avoid
unnecessary complexity for a very small optimization when we're already
enabled a high overhead behavior like tracing for all events in a
virtual function.
Change-Id: I1c360b2ba73ad73c0658e85e9122f1fef07f93ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44986
Reviewed-by: Daniel Carvalho
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/sim/eventq.cc
1 file changed, 1 insertion(+), 5 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 3e99683..92863b1 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -376,16 +376,12 @@
void
Event::trace(const char *action)
{
-// This DPRINTF is unconditional because calls to this function
-// are protected by an 'if (DTRACE(Event))' in the inlined Event
-// methods.
-//
// This is just a default implementation for derived classes where
// it's not worth doing anything special. If you want to put a
// more informative message in the trace, override this method on
// the particular subclass where you have the information that
// needs to be printed.
-DPRINTF_UNCONDITIONAL(Event, "%s %s %s @ %d\n",
+DPRINTF(Event, "%s %s %s @ %d\n",
description(), instanceString(), action, when());
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1c360b2ba73ad73c0658e85e9122f1fef07f93ce
Gerrit-Change-Number: 44986
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Stop "using namespace Debug" in DPRINTF style macros.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44985 )
Change subject: base: Stop "using namespace Debug" in DPRINTF style macros.
..
base: Stop "using namespace Debug" in DPRINTF style macros.
This is apparently not relied on by anything, and could lead to
surprising name lookups since it's not obvious that name lookup is
different in DPRINTF.
Change-Id: Ic2084ac14b85babe49c9d759575b3b03cb432061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44985
Reviewed-by: Giacomo Travaglini
Reviewed-by: Daniel Carvalho
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/base/trace.hh
1 file changed, 0 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/trace.hh b/src/base/trace.hh
index 86dec09..36fcee4 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -169,14 +169,12 @@
#if TRACING_ON
#define DDUMP(x, data, count) do { \
-using namespace Debug; \
if (M5_UNLIKELY(DTRACE(x))) \
Trace::getDebugLogger()->dump( \
curTick(), name(), data, count, #x); \
} while (0)
#define DPRINTF(x, ...) do { \
-using namespace Debug; \
if (M5_UNLIKELY(DTRACE(x))) {\
Trace::getDebugLogger()->dprintf_flag( \
curTick(), name(), #x, __VA_ARGS__); \
@@ -184,7 +182,6 @@
} while (0)
#define DPRINTFS(x, s, ...) do {\
-using namespace Debug; \
if (M5_UNLIKELY(DTRACE(x))) { \
Trace::getDebugLogger()->dprintf_flag( \
curTick(), s->name(), #x, __VA_ARGS__); \
@@ -192,7 +189,6 @@
} while (0)
#define DPRINTFR(x, ...) do { \
-using namespace Debug; \
if (M5_UNLIKELY(DTRACE(x))) { \
Trace::getDebugLogger()->dprintf_flag( \
(Tick)-1, std::string(), #x, __VA_ARGS__); \
--
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Gerrit-Change-Id: Ic2084ac14b85babe49c9d759575b3b03cb432061
Gerrit-Change-Number: 44985
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Add `--with-lto` to enabled LTO; remove `--no-lto`
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44887 )
Change subject: scons: Add `--with-lto` to enabled LTO; remove `--no-lto`
..
scons: Add `--with-lto` to enabled LTO; remove `--no-lto`
LTO is no longer enabled by default and can instead be enabled by
`--with-lto`.
Change-Id: I2eea7d447703491675c02730707cf9026cface5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44887
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M SConstruct
M src/SConscript
2 files changed, 9 insertions(+), 12 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index f3d65f0..53fa124 100755
--- a/SConstruct
+++ b/SConstruct
@@ -105,8 +105,8 @@
AddOption('--gold-linker', action='store_true', help='Use the gold linker')
AddOption('--no-compress-debug', action='store_true',
help="Don't compress debug info in build files")
-AddOption('--no-lto', action='store_true',
- help='Disable Link-Time Optimization for fast')
+AddOption('--with-lto', action='store_true',
+ help='Enable Link-Time Optimization')
AddOption('--verbose', action='store_true',
help='Print full tool command lines')
AddOption('--without-python', action='store_true',
@@ -328,10 +328,9 @@
error('gcc version 5 or newer required.\n'
'Installed version:', main['CXXVERSION'])
-# Add the appropriate Link-Time Optimization (LTO) flags
-# unless LTO is explicitly turned off. Note that these flags
-# are only used by the fast target.
-if not GetOption('no_lto'):
+# Add the appropriate Link-Time Optimization (LTO) flags if
`--with-lto` is
+# set.
+if GetOption('with_lto'):
# g++ uses "make" to parallelize LTO. The program can be overriden
with
# the environment variable "MAKE", but we currently make no
attempt to
# plumb that variable through.
@@ -354,8 +353,8 @@
error('clang version 3.9 or newer required.\n'
'Installed version:', main['CXXVERSION'])
-# If not disabled, set the Link-Time Optimization (LTO) flags.
-if not GetOption('no_lto'):
+# Set the Link-Time Optimization (LTO) flags if enabled.
+if GetOption('with_lto'):
for var in 'LTO_CCFLAGS', 'LTO_LDFLAGS':
main[var] = ['-flto']
diff --git a/src/SConscript b/src/SConscript
index 47aa2ea..bf2d22e 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1435,11 +1435,9 @@
# the optimization to the ldflags as LTO defers the optimization
# to link time
for target in ['opt', 'fast', 'prof', 'perf']:
-ccflags[target] += ['-O3']
-ldflags[target] += ['-O3']
+ccflags[target] += ['-O3'] + env['LTO_CCFLAGS']
+ldflags[target] += ['-O3'] + env['LTO_LDFLAGS']
-ccflags['fast'] += env['LTO_CCFLAGS']
-ldflags['fast'] += env['LTO_LDFLAGS']
elif env['CLANG']:
ccflags['debug'] += ['-g', '-O0']
# opt, fast, prof and perf all share the same cc flags
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2eea7d447703491675c02730707cf9026cface5f
Gerrit-Change-Number: 44887
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Revert "Enable LTO for opt, perf and prof builds."
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44886 )
Change subject: scons: Revert "Enable LTO for opt, perf and prof builds."
..
scons: Revert "Enable LTO for opt, perf and prof builds."
This reverts
https://gem5-review.googlesource.com/c/public/gem5/+/40815
Change-Id: I7dbd2b70c90c98f38c7c02eb052571f7b6bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44886
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M SConstruct
M src/SConscript
2 files changed, 8 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 3e2df39..f3d65f0 100755
--- a/SConstruct
+++ b/SConstruct
@@ -328,7 +328,9 @@
error('gcc version 5 or newer required.\n'
'Installed version:', main['CXXVERSION'])
-# If not disabled, set the Link-Time Optimization (LTO) flags.
+# Add the appropriate Link-Time Optimization (LTO) flags
+# unless LTO is explicitly turned off. Note that these flags
+# are only used by the fast target.
if not GetOption('no_lto'):
# g++ uses "make" to parallelize LTO. The program can be overriden
with
# the environment variable "MAKE", but we currently make no
attempt to
diff --git a/src/SConscript b/src/SConscript
index 831f5c6..47aa2ea 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1435,8 +1435,11 @@
# the optimization to the ldflags as LTO defers the optimization
# to link time
for target in ['opt', 'fast', 'prof', 'perf']:
-ccflags[target] += ['-O3'] + env['LTO_CCFLAGS']
-ldflags[target] += ['-O3'] + env['LTO_LDFLAGS']
+ccflags[target] += ['-O3']
+ldflags[target] += ['-O3']
+
+ccflags['fast'] += env['LTO_CCFLAGS']
+ldflags['fast'] += env['LTO_LDFLAGS']
elif env['CLANG']:
ccflags['debug'] += ['-g', '-O0']
# opt, fast, prof and perf all share the same cc flags
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44886
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7dbd2b70c90c98f38c7c02eb052571f7b6bd
Gerrit-Change-Number: 44886
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Replace assert with gem5_assert
Gabriel Busnot has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/45028 ) Change subject: misc: Replace assert with gem5_assert .. misc: Replace assert with gem5_assert Replacement performed with a basic sed plus some filtering not affect the use of the verb assert in comments. cassert is no longer included when gem5_assert only is used. Change-Id: Ide2718de8c987f6ab2bed084efc68f8aa75f17de --- M src/arch/amdgpu/gcn3/gpu_mem_helpers.hh M src/arch/amdgpu/gcn3/insts/inst_util.hh M src/arch/amdgpu/gcn3/insts/instructions.cc M src/arch/amdgpu/gcn3/insts/instructions.hh M src/arch/amdgpu/gcn3/insts/op_encodings.cc M src/arch/amdgpu/gcn3/operand.hh M src/arch/amdgpu/vega/gpu_mem_helpers.hh M src/arch/amdgpu/vega/insts/inst_util.hh M src/arch/amdgpu/vega/insts/instructions.cc M src/arch/amdgpu/vega/insts/instructions.hh M src/arch/amdgpu/vega/insts/op_encodings.cc M src/arch/amdgpu/vega/operand.hh M src/arch/arm/decoder.cc M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc M src/arch/arm/fastmodel/iris/thread_context.cc M src/arch/arm/fastmodel/iris/tlb.cc M src/arch/arm/faults.cc M src/arch/arm/htm.cc M src/arch/arm/insts/fplib.cc M src/arch/arm/insts/macromem.cc M src/arch/arm/insts/mem.hh M src/arch/arm/insts/mem64.hh M src/arch/arm/insts/misc64.hh M src/arch/arm/insts/neon64_mem.hh M src/arch/arm/insts/pred_inst.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/sve.cc M src/arch/arm/insts/sve_macromem.hh M src/arch/arm/insts/tme64ruby.cc M src/arch/arm/insts/vfp.cc M src/arch/arm/interrupts.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa_device.cc M src/arch/arm/kvm/arm_cpu.cc M src/arch/arm/kvm/gic.cc M src/arch/arm/linux/fs_workload.cc M src/arch/arm/linux/se_workload.cc M src/arch/arm/locked_mem.hh M src/arch/arm/mmu.hh M src/arch/arm/nativetrace.cc M src/arch/arm/pauth_helpers.cc M src/arch/arm/pmu.cc M src/arch/arm/pmu.hh M src/arch/arm/regs/int.hh M src/arch/arm/regs/misc.cc M src/arch/arm/semihosting.cc M src/arch/arm/stage2_lookup.cc M src/arch/arm/stage2_mmu.cc M src/arch/arm/system.hh M src/arch/arm/table_walker.cc M src/arch/arm/table_walker.hh M src/arch/arm/tlb.cc M src/arch/arm/tracers/tarmac_parser.cc M src/arch/arm/tracers/tarmac_parser.hh M src/arch/arm/utility.cc M src/arch/generic/memhelpers.hh M src/arch/generic/vec_pred_reg.hh M src/arch/mips/interrupts.cc M src/arch/mips/tlb.cc M src/arch/power/interrupts.hh M src/arch/power/tlb.cc M src/arch/riscv/decoder.cc M src/arch/riscv/interrupts.hh M src/arch/riscv/isa.cc M src/arch/riscv/pagetable_walker.cc M src/arch/riscv/tlb.cc M src/arch/sparc/faults.cc M src/arch/sparc/insts/micro.hh M src/arch/sparc/interrupts.hh M src/arch/sparc/isa.cc M src/arch/sparc/isa.hh M src/arch/sparc/nativetrace.cc M src/arch/sparc/pagetable.hh M src/arch/sparc/process.cc M src/arch/sparc/tlb.cc M src/arch/sparc/ua2005.cc M src/arch/x86/bios/acpi.cc M src/arch/x86/bios/e820.cc M src/arch/x86/bios/smbios.cc M src/arch/x86/cpuid.cc M src/arch/x86/decoder.cc M src/arch/x86/decoder.hh M src/arch/x86/emulenv.cc M src/arch/x86/faults.cc M src/arch/x86/fs_workload.cc M src/arch/x86/insts/macroop.hh M src/arch/x86/insts/microldstop.hh M src/arch/x86/insts/static_inst.cc M src/arch/x86/interrupts.cc M src/arch/x86/isa.cc M src/arch/x86/linux/syscalls.cc M src/arch/x86/pagetable_walker.cc M src/arch/x86/process.cc M src/arch/x86/regs/misc.hh M src/arch/x86/tlb.cc M src/arch/x86/x86_traits.hh M src/base/SConscript M src/base/bitfield.hh M src/base/cast.hh M src/base/chunk_generator.hh M src/base/circular_queue.hh M src/base/debug.test.cc M src/base/filters/base.hh M src/base/filters/block_bloom_filter.cc M src/base/filters/bulk_bloom_filter.cc M src/base/filters/multi_bloom_filter.cc M src/base/framebuffer.hh M src/base/gtest/logging_mock.cc M src/base/inet.cc M src/base/intmath.hh M src/base/loader/elf_object.cc M src/base/loader/image_file_data.cc M src/base/pixel.cc M src/base/sat_counter.hh M src/base/sat_counter.test.cc M src/base/socket.test.cc M src/base/statistics.cc M src/base/statistics.hh M src/base/stats/hdf5.cc M src/base/stats/storage.cc M src/base/stats/storage.hh M src/base/stats/storage.test.cc M src/base/stats/text.cc M src/base/trie.hh M src/base/types.hh M src/base/vnc/vncinput.cc M src/base/vnc/vncserver.cc M src/cpu/activity.cc M src/cpu/base.cc M src/cpu/base.hh M src/cpu/checker/cpu.cc M src/cpu/checker/cpu.hh M src/cpu/inst_res.hh M src/cpu/kvm/base.cc M src/cpu/kvm/device.cc M src/cpu/kvm/perfevent.cc M src/cpu/kvm/timer.cc M src/cpu/kvm/vm.cc M src/cpu/kvm/x86_cpu.cc M src/cpu/minor/buffers.hh M src/cpu/minor/cpu.cc M src/cpu/minor/decode.cc M src/cpu/minor/dyn_inst.cc M src/cpu/minor/dyn_inst.hh M src/cpu/minor/exec_context.hh M src/cpu/minor/execute.cc M src/cpu/minor/fetch1.cc M src/cpu/minor/fetch2.cc M src/cpu/minor/lsq.cc M src/cpu/minor/pipe_data.cc M src/cpu/o3/commit_impl.hh M
[gem5-dev] Change in gem5/gem5[develop]: base: Define the gem5_assert macro
Gabriel Busnot has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45027 )
Change subject: base: Define the gem5_assert macro
..
base: Define the gem5_assert macro
gem5_assert is a drop-in replacement for regular assert.
Change-Id: Icad1719c0e6fbb066471d1fecfb12eedd65aa690
---
M src/base/logging.hh
M src/base/logging.test.cc
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/src/base/logging.hh b/src/base/logging.hh
index 650aecd..20d7ecb 100644
--- a/src/base/logging.hh
+++ b/src/base/logging.hh
@@ -299,4 +299,27 @@
} while (0)
#endif // NDEBUG
/** @} */ // end of api_logger
+
+/**
+ * The assert macro will function like a normal assert, but will use panic
+ * instead of straight abort(). This allows to perform some cleaning up in
+ * ExitLogger::exit() before calling abort(). This macro is not active in
fast
+ * builds.
+ *
+ * @param cond Condition that is checked; if false -> panic
+ *
+ * \def gem5_assert(cond)
+ *
+ * @ingroup api_logger
+ */
+#ifdef NDEBUG
+// Fallback to regular gem5_assert behavior (normally, do nothing)
+#define gem5_assert(cond) assert(cond)
+#else //!NDEBUG
+#define gem5_assert(cond) \
+(static_cast(cond) ? \
+void (0) : \
+[]{panic(std::string("(") + #cond + ") failed");}())
+#endif // NDEBUG
+/** @} */ // end of api_logger
#endif // __BASE_LOGGING_HH__
diff --git a/src/base/logging.test.cc b/src/base/logging.test.cc
index 3f16070..13b1ee6 100644
--- a/src/base/logging.test.cc
+++ b/src/base/logging.test.cc
@@ -552,3 +552,16 @@
ASSERT_DEATH(chatty_assert(false, "message\n"), ::testing::HasSubstr(
"panic: assert(false) failed: message\nMemory Usage:"));
}
+
+/** Test macro gem5_assert. */
+TEST(LoggingDeathTest, GEM5Assert)
+{
+#ifdef NDEBUG
+GTEST_SKIP() << "Skipping as assertions are "
+"stripped out of fast builds";
+#endif
+gem5_assert(true);
+ASSERT_DEATH(gem5_assert(true), ::testing::HasSubstr(
+"panic: (false) failed: message\nMemory Usage:"));
+}
+
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45027
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icad1719c0e6fbb066471d1fecfb12eedd65aa690
Gerrit-Change-Number: 45027
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel Busnot
Gerrit-MessageType: newchange
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[gem5-dev] Re: ISA object and ISA specific CPU components
At a high level, I think this is a good direction. Specifically, I like the idea of making the ISA object a singleton for the simulation, or at least a member of the system, instead of one per CPU is great. We should probably make it per-system in case we want to support a simulation with multiple ISAs at some point in the future. The TLBs should not be part of the ISA. These are just "caches" and should be ISA-agnostic just like the caches and memories are. While they may need to store ISA-specific data (e.g., PTEs, ASIDs, etc. are ISA-specific), the mechanism for a TLB is not ISA-specific. There was recently some push to go this direction, we need to finish this at some point. Cheers, Jason On Tue, Apr 27, 2021 at 6:12 PM Gabe Black via gem5-dev wrote: > Hi folks. I can write up a more detailed document once there has been some > discussion about this, but I've been thinking about how the ISA object > works, and how the various ISA specific components of a CPU (decoder, TLBs, > interrupt object, ISA object itself) are hooked into each other. > > As of today, each context of execution has its own copy of the decoder, > the TLBs, the interrupt object (the local APIC in x86, basically ISA > specific interrupt handling logic), and the ISA object (home of MiscRegs, > some other stuff). > > My initial idea behind creating the ISA object was that it could be a home > for settings which affect the ISA itself, like what optional features were > enabled, what specific version of the ISA was in effect, etc. It made sense > to build that into the thing handling MiscRegs, since the value of and > behavior of those registers. > > All of these objects could, at least in theory, have configuration > parameters associated with them (size of the TLB, ISA parameters for > supported features, etc), and are generally represented by SimObjects which > are separately configured, and then plugged into the CPU in python. > > One problem with having the ISA object hold ISA specific configuration > comes from the fact that it's set up per thread, and there isn't a > centralized collection point for settings that should be common across > several threads. ARM currently solves this problem by creating a custom > System class, I believe the only one still in use in gem5 now, which holds > those settings and then distributes them to the ISA objects (I believe?). > This also creates a problem where there needs to be a custom System object, > and it needs to communicate with the ISA objects and keep each other in > sync. > > > What I think might make more sense is to adjust the role of the ISA object > a bit and expand it to be a single object which is assigned to a System. It > could then absorb all the ISA specific properties which are now part of the > ARM custom System class. Then, every time a ThreadContext is registered > with the System, the ISA object would have a chance to register its own > objects with it, including adding thread specific information like an > interrupts object, a decoder, a local object to handle MiscReg accesses, > etc., which could, as necessary, have ties back to the common ISA object. > > There would need to be a balance here between things which come from the > ISA object and things which do need to come from each CPU in the system, > like a way to set different TLB sizes for differently spec-ed cores for > instance. Maybe the ISA has some settings for those objects, and it sets > them post-facto when setting up a thread? > > Additionally, the new ISA regClassInfo array which describes what register > types there are and their properties could then be common to all threads > instead of duplicated in each ISA instance, and could be installed in the > ThreadContext by the ISA object, instead of having to be fetched from the > ISA object by everybody else as needed. > > You can probably tell that I haven't thought this out completely, but I > wanted to throw this out there for people to see and respond to, so please > see it and respond to it :-). > > Gabe > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add and rename some opcode fields
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40884 )
Change subject: arch-power: Add and rename some opcode fields
..
arch-power: Add and rename some opcode fields
This introduces separate extended opcode (XO) fields for DS,
X, XFL, XFX, XL and XO form instructions and renames the
primary opcode field to PO based on the convention used in
the Power ISA manual.
Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40884
Tested-by: kokoro
Reviewed-by: Boris Shingarov
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/unimp.isa
M src/arch/power/isa/formats/unknown.isa
4 files changed, 11 insertions(+), 7 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 6cc67dd..3ea6d8c 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -34,10 +34,14 @@
// are reversed sometimes. Not sure of a fix to this though...
// Opcode fields
-def bitfield OPCODE<31:26>;
-def bitfield X_XO <10:0>;
-def bitfield XO_XO <10:1>;
+def bitfield PO<31:26>;
def bitfield A_XO <5:1>;
+def bitfield DS_XO <1:0>;
+def bitfield X_XO <10:1>;
+def bitfield XFL_XO<10:1>;
+def bitfield XFX_XO<10:1>;
+def bitfield XL_XO <10:1>;
+def bitfield XO_XO <9:1>;
// Register fields
def bitfield RA<20:16>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index a42861b..1a8b375 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -34,7 +34,7 @@
// Power ISA v3.0B has been used for instruction formats, opcode numbers,
// opcode field names, register names, etc.
//
-decode OPCODE default Unknown::unknown() {
+decode PO default Unknown::unknown() {
format IntImmArithOp {
7: mulli({{
diff --git a/src/arch/power/isa/formats/unimp.isa
b/src/arch/power/isa/formats/unimp.isa
index fef28ce..a3f4692 100644
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -112,7 +112,7 @@
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
- "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
OPCODE,
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
PO,
inst2string(machInst));
return std::make_shared();
}
diff --git a/src/arch/power/isa/formats/unknown.isa
b/src/arch/power/isa/formats/unknown.isa
index d0f81f1..d83f79c 100644
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -63,7 +63,7 @@
Addr pc, const Loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
-"unknown", machInst, OPCODE,
inst2string(machInst));
+"unknown", machInst, PO, inst2string(machInst));
}
}};
@@ -73,7 +73,7 @@
{
panic("attempt to execute unknown instruction at %#x"
"(inst 0x%08x, opcode 0x%x, binary: %s)",
- xc->pcState().pc(), machInst, OPCODE, inst2string(machInst));
+ xc->pcState().pc(), machInst, PO, inst2string(machInst));
return std::make_shared();
}
}};
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Gerrit-Change-Number: 40884
Gerrit-PatchSet: 5
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: lkcl
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor instruction decoding
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40883 )
Change subject: arch-power: Refactor instruction decoding
..
arch-power: Refactor instruction decoding
This reorders the decoding logic based on the values of
the opcode fields. The first level ordering is based on
the primary opcode (PO) and the second level ordering is
based on the extended opcode (XO).
Change-Id: Ia2d457967bfebb7b20163b56db1cbbe03ac17ceb
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40883
Tested-by: kokoro
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
---
M src/arch/power/isa/decoder.isa
1 file changed, 460 insertions(+), 446 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 71f8b3e..a42861b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -31,22 +31,154 @@
// The actual Power ISA decoder
// --
//
-// I've used the Power ISA Book I v2.06 for instruction formats,
-// opcode numbers, register names, etc.
+// Power ISA v3.0B has been used for instruction formats, opcode numbers,
+// opcode field names, register names, etc.
//
decode OPCODE default Unknown::unknown() {
+format IntImmArithOp {
+7: mulli({{
+int32_t src = Ra_sw;
+int64_t prod = src * imm;
+Rt = (uint32_t)prod;
+}});
+
+8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
+ [computeCA]);
+}
+
format IntImmOp {
10: cmpli({{
Xer xer = XER;
uint32_t cr = makeCRFieldUnsigned(Ra_uw, uimm, xer.so);
CR = insertCRField(CR, BF, cr);
-}});
+}});
+
11: cmpi({{
Xer xer = XER;
uint32_t cr = makeCRFieldSigned(Ra_sw, imm, xer.so);
CR = insertCRField(CR, BF, cr);
+}});
+}
+
+format IntImmArithOp {
+12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
+ [computeCA]);
+
+13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
+ [computeCA, computeCR0]);
+}
+
+format IntImmArithCheckRaOp {
+14: addi({{ Rt = Ra + imm; }},
+ {{ Rt = imm }});
+
+15: addis({{ Rt = Ra + (imm << 16); }},
+ {{ Rt = imm << 16; }});
+}
+
+16: decode AA {
+
+// Conditionally branch relative to PC based on CR and CTR.
+0: BranchPCRelCondCtr::bc({{ NIA = (uint32_t)(CIA + disp); }});
+
+// Conditionally branch to fixed address based on CR and CTR.
+1: BranchNonPCRelCondCtr::bca({{ NIA = targetAddr; }});
+}
+
+17: IntOp::sc({{ return std::make_shared(); }});
+
+18: decode AA {
+
+// Unconditionally branch relative to PC.
+0: BranchPCRel::b({{ NIA = (uint32_t)(CIA + disp); }});
+
+// Unconditionally branch to fixed address.
+1: BranchNonPCRel::ba({{ NIA = targetAddr; }});
+}
+
+19: decode XO_XO {
+
+0: CondMoveOp::mcrf({{
+uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
+CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
+}});
+
+// Conditionally branch to address in LR based on CR and CTR.
+16: BranchLrCondCtr::bclr({{ NIA = LR & 0xfffc; }});
+
+format CondLogicOp {
+33: crnor({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, !(crBa | crBb));
}});
+
+129: crandc({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa & !crBb);
+}});
+}
+
+150: MiscOp::isync({{ }}, [ IsSerializeAfter ]);
+
+format CondLogicOp {
+193: crxor({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa ^ crBb);
+}});
+
+255: crnand({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, !(crBa & crBb));
+}});
+
+257: crand({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa & crBb);
+}});
+
+289: creqv({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa == crBb);
+}});
+
+
[gem5-dev] Change in gem5/gem5[develop]: base: Fix truncated compressed output upon panic()
Gabriel Busnot has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45025 )
Change subject: base: Fix truncated compressed output upon panic()
..
base: Fix truncated compressed output upon panic()
When panic was called, the non-flushed debug log was truncated if a
compressed
output file was used. This is fixed by manually destructing the `simout`
global
variable before calling abort().
Debug output has also been speedup by removing all explicit stream flushes
involved in the debug printing (some might ). Using stdout as the debug
output
is now as fast as file redirection and prevents log truncation in all cases
thanks to cout being tied to cerr.
Change-Id: Id01397eca608b5dc9e4bfe3fbdd864b6f07e4ad9
---
M src/base/cprintf.cc
M src/base/logging.cc
M src/base/stats/text.cc
M src/base/trace.cc
4 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index 7a3e958..9b2b576 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -78,13 +78,13 @@
break;
case '\n':
-stream << std::endl;
+stream << '\n';
++ptr;
break;
case '\r':
++ptr;
if (*ptr != '\n')
-stream << std::endl;
+stream << '\n';
break;
default:
@@ -289,13 +289,13 @@
break;
case '\n':
-stream << std::endl;
+stream << '\n';
++ptr;
break;
case '\r':
++ptr;
if (*ptr != '\n')
-stream << std::endl;
+stream << '\n';
break;
default:
diff --git a/src/base/logging.cc b/src/base/logging.cc
index 1290455..7021a65 100644
--- a/src/base/logging.cc
+++ b/src/base/logging.cc
@@ -43,6 +43,7 @@
#include
#include "base/hostinfo.hh"
+#include "base/output.hh"
namespace {
@@ -59,6 +60,9 @@
ccprintf(ss, "Memory Usage: %ld KBytes\n", memUsage());
Logger::log(loc, s + ss.str());
}
+
+void
+exit() override {simout.~OutputDirectory();}
};
class FatalLogger : public ExitLogger
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 26f1622..0d08889 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -297,7 +297,7 @@
if (units && !unitStr.empty()) {
ccprintf(stream, " (%s)", unitStr);
}
-stream << std::endl;
+stream << '\n';
}
}
@@ -394,7 +394,7 @@
if (units && !unitStr.empty()) {
ccprintf(stream, " (%s)", unitStr);
}
-stream << std::endl;
+stream << '\n';
}
}
@@ -572,7 +572,7 @@
if (units && !unitStr.empty()) {
ccprintf(stream, " (%s)", unitStr);
}
-stream << std::endl;
+stream << '\n';
}
if (data.type == Dist && data.overflow != NAN) {
diff --git a/src/base/trace.cc b/src/base/trace.cc
index eee6a4d..a80b39a 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -158,7 +158,6 @@
stream << name << ": ";
stream << message;
-stream.flush();
if (DTRACE(FmtStackTrace)) {
print_backtrace();
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id01397eca608b5dc9e4bfe3fbdd864b6f07e4ad9
Gerrit-Change-Number: 45025
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel Busnot
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Define m5_assert macro and replace assert with it
Gabriel Busnot has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/45026 ) Change subject: base: Define m5_assert macro and replace assert with it .. base: Define m5_assert macro and replace assert with it The m5_assert macro relies on panic to trigger abort(). It allows to perform some clean-up using ExitLogger::exit() before ending the program. It solves the incomplete log issue in case of assert failure for instance. Change-Id: I3e2e8d636ac880fc12b8557ccbe3325ab1896345 --- M src/arch/amdgpu/gcn3/gpu_mem_helpers.hh M src/arch/amdgpu/gcn3/insts/inst_util.hh M src/arch/amdgpu/gcn3/insts/instructions.cc M src/arch/amdgpu/gcn3/insts/instructions.hh M src/arch/amdgpu/gcn3/insts/op_encodings.cc M src/arch/amdgpu/gcn3/operand.hh M src/arch/amdgpu/vega/gpu_mem_helpers.hh M src/arch/amdgpu/vega/insts/inst_util.hh M src/arch/amdgpu/vega/insts/instructions.cc M src/arch/amdgpu/vega/insts/instructions.hh M src/arch/amdgpu/vega/insts/op_encodings.cc M src/arch/amdgpu/vega/operand.hh M src/arch/arm/decoder.cc M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc M src/arch/arm/fastmodel/iris/thread_context.cc M src/arch/arm/fastmodel/iris/tlb.cc M src/arch/arm/faults.cc M src/arch/arm/htm.cc M src/arch/arm/insts/fplib.cc M src/arch/arm/insts/macromem.cc M src/arch/arm/insts/mem.hh M src/arch/arm/insts/mem64.hh M src/arch/arm/insts/misc64.hh M src/arch/arm/insts/neon64_mem.hh M src/arch/arm/insts/pred_inst.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/sve.cc M src/arch/arm/insts/sve_macromem.hh M src/arch/arm/insts/tme64ruby.cc M src/arch/arm/insts/vfp.cc M src/arch/arm/interrupts.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa_device.cc M src/arch/arm/kvm/arm_cpu.cc M src/arch/arm/kvm/gic.cc M src/arch/arm/linux/fs_workload.cc M src/arch/arm/linux/se_workload.cc M src/arch/arm/locked_mem.hh M src/arch/arm/mmu.hh M src/arch/arm/nativetrace.cc M src/arch/arm/pauth_helpers.cc M src/arch/arm/pmu.cc M src/arch/arm/pmu.hh M src/arch/arm/regs/int.hh M src/arch/arm/regs/misc.cc M src/arch/arm/semihosting.cc M src/arch/arm/stage2_lookup.cc M src/arch/arm/stage2_mmu.cc M src/arch/arm/system.hh M src/arch/arm/table_walker.cc M src/arch/arm/table_walker.hh M src/arch/arm/tlb.cc M src/arch/arm/tracers/tarmac_parser.cc M src/arch/arm/tracers/tarmac_parser.hh M src/arch/arm/utility.cc M src/arch/generic/memhelpers.hh M src/arch/generic/vec_pred_reg.hh M src/arch/mips/interrupts.cc M src/arch/mips/tlb.cc M src/arch/power/interrupts.hh M src/arch/power/tlb.cc M src/arch/riscv/decoder.cc M src/arch/riscv/interrupts.hh M src/arch/riscv/isa.cc M src/arch/riscv/pagetable_walker.cc M src/arch/riscv/tlb.cc M src/arch/sparc/faults.cc M src/arch/sparc/insts/micro.hh M src/arch/sparc/interrupts.hh M src/arch/sparc/isa.cc M src/arch/sparc/isa.hh M src/arch/sparc/nativetrace.cc M src/arch/sparc/pagetable.hh M src/arch/sparc/process.cc M src/arch/sparc/tlb.cc M src/arch/sparc/ua2005.cc M src/arch/x86/bios/acpi.cc M src/arch/x86/bios/e820.cc M src/arch/x86/bios/smbios.cc M src/arch/x86/cpuid.cc M src/arch/x86/decoder.cc M src/arch/x86/decoder.hh M src/arch/x86/emulenv.cc M src/arch/x86/faults.cc M src/arch/x86/fs_workload.cc M src/arch/x86/insts/macroop.hh M src/arch/x86/insts/microldstop.hh M src/arch/x86/insts/static_inst.cc M src/arch/x86/interrupts.cc M src/arch/x86/isa.cc M src/arch/x86/linux/syscalls.cc M src/arch/x86/pagetable_walker.cc M src/arch/x86/process.cc M src/arch/x86/regs/misc.hh M src/arch/x86/tlb.cc M src/arch/x86/x86_traits.hh M src/base/bitfield.hh M src/base/cast.hh M src/base/chunk_generator.hh M src/base/circular_queue.hh M src/base/filters/base.hh M src/base/filters/block_bloom_filter.cc M src/base/filters/bulk_bloom_filter.cc M src/base/filters/multi_bloom_filter.cc M src/base/framebuffer.hh M src/base/inet.cc M src/base/intmath.hh M src/base/intmath.test.cc M src/base/loader/elf_object.cc M src/base/loader/image_file_data.cc M src/base/logging.hh M src/base/logging.test.cc M src/base/pixel.cc M src/base/sat_counter.hh M src/base/statistics.cc M src/base/statistics.hh M src/base/stats/hdf5.cc M src/base/stats/storage.cc M src/base/stats/storage.hh M src/base/stats/text.cc M src/base/trie.hh M src/base/types.hh M src/base/vnc/vncinput.cc M src/base/vnc/vncserver.cc M src/base/vnc/vncserver.hh M src/cpu/activity.cc M src/cpu/base.cc M src/cpu/base.hh M src/cpu/checker/cpu.cc M src/cpu/checker/cpu.hh M src/cpu/inst_res.hh M src/cpu/kvm/base.cc M src/cpu/kvm/device.cc M src/cpu/kvm/perfevent.cc M src/cpu/kvm/timer.cc M src/cpu/kvm/vm.cc M src/cpu/kvm/x86_cpu.cc M src/cpu/minor/buffers.hh M src/cpu/minor/cpu.cc M src/cpu/minor/decode.cc M src/cpu/minor/dyn_inst.cc M src/cpu/minor/dyn_inst.hh M src/cpu/minor/exec_context.hh M src/cpu/minor/execute.cc M src/cpu/minor/fetch1.cc M src/cpu/minor/fetch2.cc M src/cpu/minor/lsq.cc M src/cpu/minor/pipe_data.cc M src/cpu/o3/commit_impl.hh M
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use PageTableWalker flag
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44966 )
Change subject: arch-arm: Use PageTableWalker flag
..
arch-arm: Use PageTableWalker flag
This is aligning with RISCV and X86. Prior to this patch the Arm
TableWalker was using the TLBVerbose flag. We now use the generic
PageTableWalker flag, in most of the table walker code.
We still rely on the TLBVerbose for some methods.
Those are not conceptually related to the table walker:
For example the memAttrs methods are populating the TLB entry fields
before inserting it in the TLB. Describing the entry fields is
not strictly related to the walking mechanism
Change-Id: Ia75fef052cd44905cc41247f8e590e3ce3912252
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44966
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/table_walker.cc
1 file changed, 23 insertions(+), 15 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 8587443..82a9570 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -46,6 +46,7 @@
#include "cpu/thread_context.hh"
#include "debug/Checkpoint.hh"
#include "debug/Drain.hh"
+#include "debug/PageTableWalker.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "dev/dma_device.hh"
@@ -201,7 +202,7 @@
// For atomic mode, a new WalkerState instance should be only
created
// once per TLB. For timing mode, a new instance is generated for
every
// TLB miss.
-DPRINTF(TLBVerbose, "creating new instance of WalkerState\n");
+DPRINTF(PageTableWalker, "creating new instance of WalkerState\n");
currState = new WalkerState();
currState->tableWalker = this;
@@ -209,7 +210,8 @@
// If we are mixing functional mode with timing (or even
// atomic), we need to to be careful and clean up after
// ourselves to not risk getting into an inconsistent state.
-DPRINTF(TLBVerbose, "creating functional instance of
WalkerState\n");
+DPRINTF(PageTableWalker,
+"creating functional instance of WalkerState\n");
savedCurrState = currState;
currState = new WalkerState();
currState->tableWalker = this;
@@ -1720,7 +1722,7 @@
if ((currState->longDesc.type() == LongDescriptor::Block) ||
(currState->longDesc.type() == LongDescriptor::Page)) {
-DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, pxn: %d, "
+DPRINTF(PageTableWalker, "Analyzing L%d descriptor: %#llx,
pxn: %d, "
"xn: %d, ap: %d, af: %d, type: %d\n",
currState->longDesc.lookupLevel,
currState->longDesc.data,
@@ -1730,7 +1732,7 @@
currState->longDesc.af(),
currState->longDesc.type());
} else {
-DPRINTF(TLBVerbose, "Analyzing L%d descriptor: %#llx, type: %d\n",
+DPRINTF(PageTableWalker, "Analyzing L%d descriptor: %#llx,
type: %d\n",
currState->longDesc.lookupLevel,
currState->longDesc.data,
currState->longDesc.type());
@@ -1931,10 +1933,13 @@
}
-DPRINTF(TLBVerbose, "L1 Desc object host
addr: %p\n",>l1Desc.data);
-DPRINTF(TLBVerbose, "L1 Desc object
data: %08x\n",currState->l1Desc.data);
+DPRINTF(PageTableWalker, "L1 Desc object host addr: %p\n",
+>l1Desc.data);
+DPRINTF(PageTableWalker, "L1 Desc object data: %08x\n",
+currState->l1Desc.data);
-DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n",
currState->vaddr_tainted);
+DPRINTF(PageTableWalker, "calling doL1Descriptor for vaddr:%#x\n",
+currState->vaddr_tainted);
doL1Descriptor();
stateQueues[L1].pop_front();
@@ -1956,7 +1961,7 @@
// delay is not set so there is no L2 to do
// Don't finish the translation if a stage 2 look up is underway
stats.walkServiceTime.sample(curTick() - currState->startTime);
-DPRINTF(TLBVerbose, "calling translateTiming again\n");
+DPRINTF(PageTableWalker, "calling translateTiming again\n");
tlb->translateTiming(currState->req, currState->tc,
currState->transState, currState->mode);
stats.walksShortTerminatedAtLevel[0]++;
@@ -1986,7 +1991,7 @@
currState->stage2Tran = NULL;
}
-DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n",
+DPRINTF(PageTableWalker, "calling doL2Descriptor for vaddr:%#x\n",
currState->vaddr_tainted);
doL2Descriptor();
@@ -1997,7 +2002,7 @@
stats.walksShortTerminatedAtLevel[1]++;
} else {
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, arch-x86: Define unique PageTableWalker flag
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44965 )
Change subject: arch-riscv, arch-x86: Define unique PageTableWalker flag
..
arch-riscv, arch-x86: Define unique PageTableWalker flag
Rather than defining multiple flags (one per ISA), we should define
a single PageTableWalker flag shared by all ISAs
Change-Id: Iad460bcd9a69d5c6f90443e43feec318429165aa
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44965
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/generic/SConscript
M src/arch/riscv/SConscript
M src/arch/x86/SConscript
3 files changed, 2 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index 3ad4878..fb144f9 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -47,6 +47,8 @@
SimObject('BaseTLB.py')
SimObject('ISACommon.py')
+DebugFlag('PageTableWalker',
+ "Page table walker state machine debugging")
DebugFlag('TLB')
if env['TARGET_ISA'] == 'null':
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 03e382c..291499c 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -75,8 +75,6 @@
DebugFlag('RiscvMisc')
DebugFlag('TLBVerbose')
DebugFlag('PMP')
-DebugFlag('PageTableWalker', \
- "Page table walker state machine debugging")
# Add in files generated by the ISA description.
ISADesc('isa/main.isa')
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index f790ec1..d7da290 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -77,8 +77,6 @@
DebugFlag('Faults', "Trace all faults/exceptions/traps")
DebugFlag('LocalApic', "Local APIC debugging")
-DebugFlag('PageTableWalker', \
- "Page table walker state machine debugging")
DebugFlag('Decoder', "Decoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iad460bcd9a69d5c6f90443e43feec318429165aa
Gerrit-Change-Number: 44965
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base,python: Simplify how we check if a debug flag is enabled.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45007 )
Change subject: base,python: Simplify how we check if a debug flag is
enabled.
..
base,python: Simplify how we check if a debug flag is enabled.
Compound debug flags are intended to be a way to enable or disable a
group of simple debug flags at once, so that you don't need to enumerate
every more specialized flag in an area to get a broad amount of
debugging, nor do you give up the ability to select a general area
easily by making more specific flags.
It doesn't, however, make a lot of sense to check the value of a
compound debug flag, since it could be enabled but then have individual
subflags disabled. Exactly whether that means the compound flag should
be enabled or not is not clear, and figuring it out takes a fair amount
of work since each member simple flag needs to be visited.
Also, by having different behavior depending on the flag type, the
"enabled" method needed to be virtual.
This change eliminates the virtual method and moves the _tracing bool
member into the base class. If a subclass (only SimpleFlag currently)
wants to start or stop tracing based on itself, it should set or clear
this flag. Also, the "enabled" method has been renamed to "tracing",
since that's actually what it tracked. Being enabled by itself is not
sufficient to be tracing since there is also a global enable.
In addition to simplifying the code, this should speed up checks of
debug flags significantly since the call to tracing (formerly enabled)
can be inlined and will involve only a simple dereference. Also, since
_tracing is the first member of the class, we avoid having to even
calculate an offset into the object.
Finally, rather than duplicate the logic to convert a flag to bool in
the python wrapper, we can just use a cast to bool and take advantage of
the version in C++.
Change-Id: I3dc64c2364f0239294093686ddac6fcc8441f306
---
M src/base/debug.cc
M src/base/debug.hh
M src/python/pybind11/debug.cc
3 files changed, 9 insertions(+), 24 deletions(-)
diff --git a/src/base/debug.cc b/src/base/debug.cc
index 38eb25f..34bc4f4 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -137,20 +137,6 @@
}
bool
-CompoundFlag::enabled() const
-{
-if (_kids.empty())
-return false;
-
-for (auto& k : _kids) {
-if (!k->enabled())
-return false;
-}
-
-return true;
-}
-
-bool
changeFlag(const char *s, bool value)
{
Flag *f = findFlag(s);
@@ -188,7 +174,7 @@
FlagsMap::iterator end = allFlags().end();
for (; i != end; ++i) {
SimpleFlag *f = dynamic_cast(i->second);
-if (f && f->enabled())
+if (f && f->tracing())
ccprintf(os, "%s\n", f->name());
}
}
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 4b77e16..c5d3f53 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -62,6 +62,8 @@
virtual void sync() { }
+bool _tracing = false; // tracing is enabled and flag is on
+
public:
Flag(const char *name, const char *desc);
virtual ~Flag();
@@ -69,11 +71,12 @@
std::string name() const { return _name; }
std::string desc() const { return _desc; }
+bool tracing() const { return _tracing; }
+
virtual void enable() = 0;
virtual void disable() = 0;
-virtual bool enabled() const = 0;
-operator bool() const { return enabled(); }
+operator bool() const { return tracing(); }
static void globalEnable();
static void globalDisable();
@@ -85,7 +88,6 @@
/** Whether this flag changes debug formatting. */
const bool _isFormat = false;
-bool _tracing = false; // tracing is enabled and flag is on
bool _enabled = false; // flag enablement status
void sync() override { _tracing = _globalEnable && _enabled; }
@@ -95,8 +97,6 @@
: Flag(name, desc), _isFormat(is_format)
{}
-bool enabled() const override { return _tracing; }
-
void enable() override { _enabled = true; sync(); }
void disable() override { _enabled = false; sync(); }
@@ -127,7 +127,6 @@
void enable() override;
void disable() override;
-bool enabled() const override;
};
typedef std::map FlagsMap;
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index a2b5406..cca0f9c 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -94,9 +94,9 @@
.def_property_readonly("desc", ::Flag::desc)
.def("enable", ::Flag::enable)
.def("disable", ::Flag::disable)
-.def_property("enabled",
+.def_property("tracing",
[](const Debug::Flag *flag) {
- return flag->enabled();
+ return flag->tracing();
},
[](Debug::Flag *flag, bool state) {
if
[gem5-dev] Change in gem5/gem5[develop]: misc: Collapse all uses of DTRACE(x) to Debug::x.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45009 )
Change subject: misc: Collapse all uses of DTRACE(x) to Debug::x.
..
misc: Collapse all uses of DTRACE(x) to Debug::x.
Change-Id: I99d9a9544b539117b375186e3e425d73d3c5cab7
---
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/riscv/process.cc
M src/base/remote_gdb.cc
M src/base/stats/group.cc
M src/base/trace.cc
M src/cpu/base.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/execute.cc
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch2.cc
M src/cpu/minor/func_unit.cc
M src/cpu/minor/pipeline.cc
M src/cpu/minor/scoreboard.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/profile.hh
M src/cpu/simple/base.cc
M src/cpu/trace/trace_cpu.cc
M src/dev/net/i8254xGBe.cc
M src/dev/net/ns_gige.cc
M src/dev/net/sinic.cc
M src/dev/serial/terminal.cc
M src/dev/virtio/base.cc
M src/dev/virtio/fs9p.cc
M src/kern/linux/events.hh
M src/mem/external_slave.cc
M src/mem/qos/mem_sink.cc
M src/sim/drain.cc
M src/sim/eventq.cc
M src/sim/eventq.hh
37 files changed, 61 insertions(+), 61 deletions(-)
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index e827c22..9846996 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -586,7 +586,7 @@
setOneReg(ri->id, value);
}
-if (DTRACE(KvmContext))
+if (Debug::KvmContext)
dumpKvmStateCore();
}
@@ -624,7 +624,7 @@
}
warned = true;
-if (DTRACE(KvmContext))
+if (Debug::KvmContext)
dumpKvmStateMisc();
}
@@ -730,7 +730,7 @@
pc.set(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
tc->pcState(pc);
-if (DTRACE(KvmContext))
+if (Debug::KvmContext)
dumpKvmStateCore();
}
@@ -763,7 +763,7 @@
warned = true;
-if (DTRACE(KvmContext))
+if (Debug::KvmContext)
dumpKvmStateMisc();
}
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index be4e3a9..30aebd6 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -167,7 +167,7 @@
memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
initVirtMem->writeString(memState->getStackMin(), arg.c_str());
argPointers.push_back(memState->getStackMin());
-if (DTRACE(Stack)) {
+if (Debug::Stack) {
std::string wrote;
initVirtMem->readString(wrote, argPointers.back());
DPRINTFN("Wrote arg \"%s\" to address %p\n",
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index fc6813c..7b9788a 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -649,8 +649,8 @@
proxy.readBlob(vaddr, data, size);
#if TRACING_ON
-if (DTRACE(GDBRead)) {
-if (DTRACE(GDBExtra)) {
+if (Debug::GDBRead) {
+if (Debug::GDBExtra) {
char buf[1024];
mem2hex(buf, data, size);
DPRINTFNR(": %s\n", buf);
@@ -666,9 +666,9 @@
bool
BaseRemoteGDB::write(Addr vaddr, size_t size, const char *data)
{
-if (DTRACE(GDBWrite)) {
+if (Debug::GDBWrite) {
DPRINTFN("write: addr=%#x, size=%d", vaddr, size);
-if (DTRACE(GDBExtra)) {
+if (Debug::GDBExtra) {
char buf[1024];
mem2hex(buf, data, size);
DPRINTFNR(": %s\n", buf);
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index de546cd..459adae 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -66,7 +66,7 @@
g->regStats();
for (auto : statGroups) {
-if (DTRACE(Stats)) {
+if (Debug::Stats) {
M5_VAR_USED const SimObject *so =
dynamic_cast(this);
DPRINTF(Stats, "%s: regStats in group %s\n",
diff --git a/src/base/trace.cc b/src/base/trace.cc
index eee6a4d..0137ad7 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -148,10 +148,10 @@
if (!name.empty() && ignore.match(name))
return;
-if (!DTRACE(FmtTicksOff) && (when != MaxTick))
+if (!Debug::FmtTicksOff && (when != MaxTick))
ccprintf(stream, "%7d: ", when);
-if (DTRACE(FmtFlag) && !flag.empty())
+if (Debug::FmtFlag && !flag.empty())
stream << flag << ": ";
if (!name.empty())
@@ -160,7 +160,7 @@
stream << message;
stream.flush();
-if (DTRACE(FmtStackTrace)) {
+if (Debug::FmtStackTrace) {
print_backtrace();
STATIC_ERR("\n");
}
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index c40c001..1badf0f 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -579,7 +579,7 @@
/* This code no longer works since the zero register (e.g.,
* r31 on Alpha) doesn't necessarily contain zero at this
[gem5-dev] Change in gem5/gem5[develop]: base: Simplify the definition of DTRACE.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45006 )
Change subject: base: Simplify the definition of DTRACE.
..
base: Simplify the definition of DTRACE.
Instead of gating the behavior of DTRACE based on TRACING_ON in the
preprocessor, move it to C++. Beyond being a little simpler, this
ensures that the value of Debug::x is always valid (the proper header is
included, x is spelled correctly, etc) even if TRACING_ON is false.
Change-Id: Ie0085c0f8753ad5283ef1850d493706b977c21a8
---
M src/base/debug.hh
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 38d92f9..4b77e16 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -151,11 +151,7 @@
* @ingroup api_trace
* @{
*/
-#if TRACING_ON
-# define DTRACE(x) (Debug::x)
-#else // !TRACING_ON
-# define DTRACE(x) (false)
-#endif // TRACING_ON
+#define DTRACE(x) (TRACING_ON && Debug::x)
/** @} */ // end of api_trace
#endif // __BASE_DEBUG_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie0085c0f8753ad5283ef1850d493706b977c21a8
Gerrit-Change-Number: 45006
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Move TRACING_ON check into Flag::tracing().
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45008 )
Change subject: base: Move TRACING_ON check into Flag::tracing().
..
base: Move TRACING_ON check into Flag::tracing().
Now DTRACE is simply an alias for Debug::x. We should keep it now for
compatibility, but it can be removed over time.
Change-Id: Icda18ff57126328e98e440e3a81bf13caa0c27df
---
M src/base/debug.hh
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index c5d3f53..4575fff 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -57,13 +57,13 @@
protected:
static bool _globalEnable; // whether debug tracings are enabled
+bool _tracing = false; // tracing is enabled and flag is on
+
const char *_name;
const char *_desc;
virtual void sync() { }
-bool _tracing = false; // tracing is enabled and flag is on
-
public:
Flag(const char *name, const char *desc);
virtual ~Flag();
@@ -71,7 +71,7 @@
std::string name() const { return _name; }
std::string desc() const { return _desc; }
-bool tracing() const { return _tracing; }
+bool tracing() const { return TRACING_ON && _tracing; }
virtual void enable() = 0;
virtual void disable() = 0;
@@ -150,7 +150,7 @@
* @ingroup api_trace
* @{
*/
-#define DTRACE(x) (TRACING_ON && Debug::x)
+#define DTRACE(x) (Debug::x)
/** @} */ // end of api_trace
#endif // __BASE_DEBUG_HH__
--
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Gerrit-Change-Id: Icda18ff57126328e98e440e3a81bf13caa0c27df
Gerrit-Change-Number: 45008
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
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[gem5-dev] Change in gem5/gem5[develop]: base: Collapse the DTRACE macro in DPRINTF.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45005 )
Change subject: base: Collapse the DTRACE macro in DPRINTF.
..
base: Collapse the DTRACE macro in DPRINTF.
We've already checked if TRACING_ON is set, so we can just check the
value of Debug::x directly.
Change-Id: Ifcc183b9e56fd45a2c6278ab5739ae2fbe2b32c0
---
M src/base/trace.hh
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/base/trace.hh b/src/base/trace.hh
index 21a5ead..2e560b9 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -167,27 +167,27 @@
*/
#define DDUMP(x, data, count) do { \
-if (M5_UNLIKELY(TRACING_ON && DTRACE(x)))\
+if (M5_UNLIKELY(TRACING_ON && Debug::x)) \
Trace::getDebugLogger()->dump( \
curTick(), name(), data, count, #x); \
} while (0)
#define DPRINTF(x, ...) do { \
-if (M5_UNLIKELY(TRACING_ON && DTRACE(x))) { \
+if (M5_UNLIKELY(TRACING_ON && Debug::x)) { \
Trace::getDebugLogger()->dprintf_flag( \
curTick(), name(), #x, __VA_ARGS__); \
}\
} while (0)
#define DPRINTFS(x, s, ...) do {\
-if (M5_UNLIKELY(TRACING_ON && DTRACE(x))) { \
+if (M5_UNLIKELY(TRACING_ON && Debug::x)) { \
Trace::getDebugLogger()->dprintf_flag( \
curTick(), s->name(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFR(x, ...) do { \
-if (M5_UNLIKELY(TRACING_ON && DTRACE(x))) {\
+if (M5_UNLIKELY(TRACING_ON && Debug::x)) { \
Trace::getDebugLogger()->dprintf_flag( \
(Tick)-1, std::string(), #x, __VA_ARGS__); \
} \
--
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Gerrit-Change-Id: Ifcc183b9e56fd45a2c6278ab5739ae2fbe2b32c0
Gerrit-Change-Number: 45005
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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