[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use regIdx() instead of creating an InstRegIndex directly.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42353 )
Change subject: arch-x86: Use regIdx() instead of creating an InstRegIndex
directly.
..
arch-x86: Use regIdx() instead of creating an InstRegIndex directly.
The microcode assembler provides a regIdx() wrapper which will wrap
constants with an appropriate InstRegIndex constructor without having to
do so manually.
Change-Id: I782289bdfcbe4e3552ff44123dfce2ccc86f9266
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42353
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
M
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
M src/arch/x86/isa/insts/system/msrs.py
M src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
4 files changed, 38 insertions(+), 38 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 554d93f..b59d85f 100644
---
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -35,24 +35,24 @@
microcode = '''
def macroop STMXCSR_M {
-rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+rdval t1, regIdx("MISCREG_MXCSR")
st t1, seg, sib, disp
};
def macroop STMXCSR_P {
-rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+rdval t1, regIdx("MISCREG_MXCSR")
rdip t7
st t1, seg, riprel, disp
};
def macroop LDMXCSR_M {
ld t1, seg, sib, disp
-wrval "InstRegIndex(MISCREG_MXCSR)", t1
+wrval regIdx("MISCREG_MXCSR"), t1
};
def macroop LDMXCSR_P {
rdip t7
ld t1, seg, riprel, disp
-wrval "InstRegIndex(MISCREG_MXCSR)", t1
+wrval regIdx("MISCREG_MXCSR"), t1
};
'''
diff --git
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
index c46f849..c519b56 100644
---
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
+++
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
@@ -43,16 +43,16 @@
'''
loadXMMRegTemplate = '''
-ldfp "InstRegIndex(FLOATREG_XMM_LOW(%(idx)i))", seg, %(mode)s, \
+ldfp regIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i", dataSize=8
-ldfp "InstRegIndex(FLOATREG_XMM_HIGH(%(idx)i))", seg, %(mode)s, \
+ldfp regIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i + 8", dataSize=8
'''
storeXMMRegTemplate = '''
-stfp "InstRegIndex(FLOATREG_XMM_LOW(%(idx)i))", seg, %(mode)s, \
+stfp regIdx("FLOATREG_XMM_LOW(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i", dataSize=8
-stfp "InstRegIndex(FLOATREG_XMM_HIGH(%(idx)i))", seg, %(mode)s, \
+stfp regIdx("FLOATREG_XMM_HIGH(%(idx)i)"), seg, %(mode)s, \
"DISPLACEMENT + 160 + 16 * %(idx)i + 8", dataSize=8
'''
@@ -80,10 +80,10 @@
rdxftw t1
st t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=1
-rdval t1, "InstRegIndex(MISCREG_FOP)"
+rdval t1, regIdx("MISCREG_FOP")
st t1, seg, %(mode)s, "DISPLACEMENT + 6", dataSize=2
-rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+rdval t1, regIdx("MISCREG_MXCSR")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 8", dataSize=4
# MXCSR_MASK, software assumes the default (0xFFBF) if 0.
@@ -92,24 +92,24 @@
""" + storeAllDataRegs
fxsave32Template = """
-rdval t1, "InstRegIndex(MISCREG_FIOFF)"
+rdval t1, regIdx("MISCREG_FIOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=4
-rdval t1, "InstRegIndex(MISCREG_FISEG)"
+rdval t1, regIdx("MISCREG_FISEG")
st t1, seg, %(mode)s, "DISPLACEMENT + 12", dataSize=2
-rdval t1, "InstRegIndex(MISCREG_FOOFF)"
+rdval t1, regIdx("MISCREG_FOOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=4
-rdval t1, "InstRegIndex(MISCREG_FOSEG)"
+rdval t1, regIdx("MISCREG_FOSEG")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
""" + fxsaveCommonTemplate
fxsave64Template = """
-rdval t1, "InstRegIndex(MISCREG_FIOFF)"
+rdval t1, regIdx("MISCREG_FIOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=8
-rdval t1, "InstRegIndex(MISCREG_FOOFF)"
+rdval t1, regIdx("MISCREG_FOOFF")
st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0",
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix style and use uop args in seqop.isa.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42351 )
Change subject: arch-x86: Fix style and use uop args in seqop.isa.
..
arch-x86: Fix style and use uop args in seqop.isa.
Change-Id: I41ed7f0aa8dd00ed0f6f8361837945810d12bf9e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42351
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/isa/microops/seqop.isa
2 files changed, 100 insertions(+), 137 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
index ac4d81e..6fa09f5 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -264,6 +264,22 @@
}
};
+struct UpcOp
+{
+using ArgType = MicroPC;
+
+MicroPC target;
+
+template
+UpcOp(InstType *inst, ArgType _target) : target(_target) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "%#x", target);
+}
+};
+
struct FaultOp
{
using ArgType = Fault;
diff --git a/src/arch/x86/isa/microops/seqop.isa
b/src/arch/x86/isa/microops/seqop.isa
index 64f749b..7b52101 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -33,114 +33,81 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-output header {{
-class SeqOpBase : public X86ISA::X86MicroopBase
-{
- protected:
-uint16_t target;
-uint8_t cc;
-
- public:
-SeqOpBase(ExtMachInst _machInst, const char * instMnem,
-const char * mnemonic, uint64_t setFlags,
-uint16_t _target, uint8_t _cc);
-
-SeqOpBase(ExtMachInst _machInst, const char * instMnem,
-const char * mnemonic,
-uint16_t _target, uint8_t _cc);
-
-std::string generateDisassembly(Addr pc,
-const Loader::SymbolTable *symtab) const override;
-};
-}};
-
-def template SeqOpDeclare {{
+def template BrDeclare {{
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
-%(class_name)s(ExtMachInst _machInst, const char * instMnem,
-uint64_t setFlags, uint16_t _target, uint8_t _cc);
+%(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
+uint64_t set_flags, uint16_t _target, uint8_t _cc) :
+%(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
+%(op_class)s, _target, _cc)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
-X86ISA::PCState branchTarget(const X86ISA::PCState ) const
-override;
+X86ISA::PCState
+branchTarget(const X86ISA::PCState ) const override
+{
+X86ISA::PCState pcs = branchPC;
+DPRINTF(X86, "Br branchTarget PC info: %s, Target: %d\n",
+pcs, (int16_t)target);
+pcs.nupc(target);
+pcs.uAdvance();
+return pcs;
+}
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
};
}};
-def template SeqOpExecute {{
-Fault %(class_name)s::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
+def template EretDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ private:
+%(reg_idx_arr_decl)s;
+
+ public:
+%(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
+uint64_t set_flags, uint8_t _cc) :
+%(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
+%(op_class)s, _cc)
{
-%(op_decl)s;
-%(op_rd)s;
-if (%(cond_test)s) {
-%(code)s;
-} else {
-%(else_code)s;
-}
-%(op_wb)s;
-return NoFault;
+%(set_reg_idx_arr)s;
+%(constructor)s;
}
+
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
}};
-output decoder {{
-SeqOpBase::SeqOpBase(
-ExtMachInst machInst, const char * mnemonic, const char *
instMnem,
-uint64_t setFlags, uint16_t _target, uint8_t _cc) :
-X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass),
-target(_target), cc(_cc)
+def template SeqOpExecute {{
+Fault
+%(class_name)s::execute(ExecContext *xc,
+Trace::InstRecord *traceData) const
{
-}
-}};
-
-def template
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Correct style and use uop args in specop.isa.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42350 )
Change subject: arch-x86: Correct style and use uop args in specop.isa.
..
arch-x86: Correct style and use uop args in specop.isa.
Also spin fixed code out into header files.
Change-Id: I1b326c8cb999d797102ba36b5c13850023a50615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42350
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/insts/microop.hh
M src/arch/x86/insts/microop_args.hh
A src/arch/x86/insts/microspecop.hh
M src/arch/x86/isa/includes.isa
M src/arch/x86/isa/microops/specop.isa
5 files changed, 120 insertions(+), 105 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index ac12cec..13c4bee 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -141,6 +141,20 @@
using StaticInst::branchTarget;
};
+class MicroCondBase : public X86MicroopBase
+{
+ protected:
+uint8_t cc;
+
+ public:
+MicroCondBase(ExtMachInst mach_inst, const char *mnem,
+const char *inst_mnem, uint64_t set_flags, OpClass op_class,
+uint8_t _cc) :
+X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, op_class),
+cc(_cc)
+{}
+};
+
}
#endif //__ARCH_X86_INSTS_MICROOP_HH__
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
index a3ebe29..ac4d81e 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -37,6 +37,7 @@
#include "arch/x86/types.hh"
#include "base/cprintf.hh"
#include "cpu/reg_class.hh"
+#include "sim/faults.hh"
namespace X86ISA
{
@@ -263,6 +264,22 @@
}
};
+struct FaultOp
+{
+using ArgType = Fault;
+
+Fault fault;
+
+template
+FaultOp(InstType *inst, ArgType _fault) : fault(_fault) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, fault ? fault->name() : "NoFault");
+}
+};
+
struct AddrOp
{
struct ArgType
diff --git a/src/arch/x86/insts/microspecop.hh
b/src/arch/x86/insts/microspecop.hh
new file mode 100644
index 000..3d2c631
--- /dev/null
+++ b/src/arch/x86/insts/microspecop.hh
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_MICROSPECOP_HH__
+#define __ARCH_X86_INSTS_MICROSPECOP_HH__
+
+#include "arch/x86/insts/microop.hh"
+#include "cpu/exec_context.hh"
+
+namespace X86ISA
+{
+
+class MicroHalt : public InstOperands
+{
+ public:
+MicroHalt(ExtMachInst mach_inst, const char *inst_mnem,
+uint64_t set_flags) :
+InstOperands(mach_inst, "halt", inst_mnem,
+set_flags | (1ULL << StaticInst::IsNonSpeculative) |
+(1ULL << StaticInst::IsQuiesce),
+No_OpClass)
+{}
+
+Fault
+execute(ExecContext *xc, Trace::InstRecord *) const override
+{
+xc->tcBase()->suspend();
+return NoFault;
+}
+};
+
+} // namespace X86ISA
+
+#endif //__ARCH_X86_INSTS_MICROSPECOP_HH__
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 5016718..addc561 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -60,6 +60,7 @@
#include "arch/x86/insts/microldstop.hh"
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use the newly flexible RegOpT to implement the limm uop.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42349 )
Change subject: arch-x86: Use the newly flexible RegOpT to implement the
limm uop.
..
arch-x86: Use the newly flexible RegOpT to implement the limm uop.
Change-Id: I7ac632d891b0f6b42794eb894bde3c18ce82718a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42349
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/isa/microops/limmop.isa
2 files changed, 45 insertions(+), 62 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
index d57ae12..a3ebe29 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -247,6 +247,22 @@
}
};
+struct Imm64Op
+{
+using ArgType = uint64_t;
+
+uint64_t imm64;
+
+template
+Imm64Op(InstType *inst, ArgType _imm64) : imm64(_imm64) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "%#x", imm64);
+}
+};
+
struct AddrOp
{
struct ArgType
diff --git a/src/arch/x86/isa/microops/limmop.isa
b/src/arch/x86/isa/microops/limmop.isa
index 0dbce82..3a7f026 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -40,71 +40,40 @@
//
def template MicroLimmOpExecute {{
-Fault %(class_name)s::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
-{
-%(op_decl)s;
-%(op_rd)s;
-%(code)s;
-%(op_wb)s;
-return NoFault;
-}
+Fault
+%(class_name)s::execute(ExecContext *xc,
+Trace::InstRecord *traceData) const
+{
+%(op_decl)s;
+%(op_rd)s;
+%(code)s;
+%(op_wb)s;
+return NoFault;
+}
}};
def template MicroLimmOpDeclare {{
-class %(class_name)s : public X86ISA::X86MicroopBase
+class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
- protected:
-const RegIndex dest;
-const uint64_t imm;
-const uint8_t dataSize;
-RegIndex foldOBit;
-
-std::string generateDisassembly(Addr pc,
-const Loader::SymbolTable *symtab) const override;
-
public:
-%(class_name)s(ExtMachInst _machInst,
-const char * instMnem,
-uint64_t setFlags, InstRegIndex _dest,
-uint64_t _imm, uint8_t _dataSize);
+template
+%(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
+uint64_t set_flags, Dest _dest,
+uint64_t _imm, uint8_t data_size) :
+%(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
+%(op_class)s, _dest, _imm, data_size, 0)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
-def template MicroLimmOpDisassembly {{
-std::string
-%(class_name)s::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream response;
-
-printMnemonic(response, instMnem, mnemonic);
-printDestReg(response, 0, dataSize);
-response << ", ";
-ccprintf(response, "%#x", imm);
-return response.str();
-}
-}};
-
-def template MicroLimmOpConstructor {{
-%(class_name)s::%(class_name)s(
-ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
-InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
-%(base_class)s(machInst, "%(mnemonic)s", instMnem,
-setFlags, %(op_class)s),
-dest(_dest.index()), imm(_imm), dataSize(_dataSize)
-{
-%(set_reg_idx_arr)s;
-foldOBit = (dataSize == 1 && !machInst.rex.present) ? 1 << 6 : 0;
-%(constructor)s;
-}
-}};
-
let {{
class LimmOp(X86Microop):
def __init__(self, dest, imm, dataSize="env.dataSize"):
@@ -162,21 +131,19 @@
}};
let {{
+base = 'X86ISA::RegOpT'
# Build up the all register version of this micro op
-iops = [InstObjParams("limm", "Limm", 'X86MicroopBase',
-{"code" : "DestReg = merge(DestReg, imm, dataSize);"}),
-InstObjParams("limm", "LimmBig", 'X86MicroopBase',
-{"code" : "DestReg = imm & mask(dataSize * 8);"})]
+iops = [InstObjParams("limm", "Limm", base,
+{"code" : "DestReg = merge(DestReg, imm64, dataSize);"}),
+InstObjParams("limm", "LimmBig", base,
+{"code" : "DestReg = imm64 & mask(dataSize * 8);"})]
for iop in iops:
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use the *Op classes with FP microops.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42348 )
Change subject: arch-x86: Use the *Op classes with FP microops.
..
arch-x86: Use the *Op classes with FP microops.
Change-Id: I79e68ad5a0233047d44079d8453bf232cb64d27e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42348
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/SConscript
D src/arch/x86/insts/microfpop.cc
M src/arch/x86/insts/microfpop.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/isa/microops/fpop.isa
5 files changed, 138 insertions(+), 205 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index b0f908b..4eb98f1 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -50,7 +50,6 @@
Source('faults.cc')
Source('fs_workload.cc')
Source('insts/badmicroop.cc')
-Source('insts/microfpop.cc')
Source('insts/micromediaop.cc')
Source('insts/microop.cc')
Source('insts/microregop.cc')
diff --git a/src/arch/x86/insts/microfpop.cc
b/src/arch/x86/insts/microfpop.cc
deleted file mode 100644
index 1a32b6a..000
--- a/src/arch/x86/insts/microfpop.cc
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/x86/insts/microfpop.hh"
-
-#include
-
-#include "arch/x86/regs/misc.hh"
-
-namespace X86ISA
-{
-
-std::string
-FpOp::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream response;
-
-printMnemonic(response, instMnem, mnemonic);
-printDestReg(response, 0, dataSize);
-response << ", ";
-printSrcReg(response, 0, dataSize);
-response << ", ";
-printSrcReg(response, 1, dataSize);
-return response.str();
-}
-
-}
diff --git a/src/arch/x86/insts/microfpop.hh
b/src/arch/x86/insts/microfpop.hh
index 245a899..3cd92cf 100644
--- a/src/arch/x86/insts/microfpop.hh
+++ b/src/arch/x86/insts/microfpop.hh
@@ -43,36 +43,23 @@
namespace X86ISA
{
-/**
- * Base classes for FpOps which provides a generateDisassembly method.
- */
class FpOp : public X86MicroopBase
{
protected:
-const RegIndex src1;
-const RegIndex src2;
-const RegIndex dest;
-const uint8_t dataSize;
const int8_t spm;
-RegIndex foldOBit;
// Constructor
-FpOp(ExtMachInst _machInst,
-const char *mnem, const char *_instMnem,
-uint64_t setFlags,
-InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
-uint8_t _dataSize, int8_t _spm,
-OpClass __opClass) :
-X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
-__opClass),
-
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Remove static code from debug.isa and fix style.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42347 )
Change subject: arch-x86: Remove static code from debug.isa and fix style.
..
arch-x86: Remove static code from debug.isa and fix style.
Fix style problems in debug.isa, and move static code out of the ISA
description into a plain header file.
Change-Id: I8369bd8d46ad11b66cac8249cc981a8d279a1492
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42347
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/insts/badmicroop.cc
A src/arch/x86/insts/microdebug.hh
M src/arch/x86/isa/includes.isa
M src/arch/x86/isa/microops/debug.isa
4 files changed, 90 insertions(+), 62 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/badmicroop.cc
b/src/arch/x86/insts/badmicroop.cc
index 21707c6..4e8633b 100644
--- a/src/arch/x86/insts/badmicroop.cc
+++ b/src/arch/x86/insts/badmicroop.cc
@@ -54,7 +54,7 @@
// try to delete the static memory when it was destructed.
const StaticInstPtr badMicroop =
-new X86ISAInst::MicroDebug(dummyMachInst, "panic", "BAD",
+new MicroDebug(dummyMachInst, "panic", "BAD",
StaticInst::IsMicroop | StaticInst::IsLastMicroop,
new GenericISA::M5PanicFault("Invalid microop!"));
diff --git a/src/arch/x86/insts/microdebug.hh
b/src/arch/x86/insts/microdebug.hh
new file mode 100644
index 000..b3af1e7
--- /dev/null
+++ b/src/arch/x86/insts/microdebug.hh
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_MICRODEBUG_HH__
+#define __ARCH_X86_INSTS_MICRODEBUG_HH__
+
+#include "arch/x86/insts/microop.hh"
+
+namespace X86ISA
+{
+
+class MicroDebug : public X86ISA::X86MicroopBase
+{
+ protected:
+std::shared_ptr fault;
+
+ public:
+MicroDebug(ExtMachInst mach_inst, const char *mnem, const char
*inst_mnem,
+uint64_t set_flags, GenericISA::M5DebugFault *_fault) :
+X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, No_OpClass),
+fault(_fault)
+{}
+
+Fault
+execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+{
+return fault;
+}
+
+std::string
+generateDisassembly(Addr pc,
+const Loader::SymbolTable *symtab) const override
+{
+std::stringstream response;
+
+printMnemonic(response, instMnem, mnemonic);
+response << "\"" << fault->message() << "\"";
+
+return response.str();
+}
+};
+
+} // namespace X86ISA
+
+#endif //__ARCH_X86_INSTS_MICRODEBUG_HH__
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 1e1d865..5016718 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -55,6 +55,7 @@
#include "arch/generic/debugfaults.hh"
#include "arch/x86/emulenv.hh"
#include "arch/x86/insts/macroop.hh"
+#include "arch/x86/insts/microdebug.hh"
#include "arch/x86/insts/microfpop.hh"
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/insts/micromediaop.hh"
diff --git a/src/arch/x86/isa/microops/debug.isa
b/src/arch/x86/isa/microops/debug.isa
index 326f245..5023682 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -39,47 +39,6 @@
//
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use the new op bases for memory microops.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42346 )
Change subject: arch-x86: Use the new op bases for memory microops.
..
arch-x86: Use the new op bases for memory microops.
Change-Id: I73538b547093e6f872e085686ea164ef89527321
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42346
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/SConscript
D src/arch/x86/insts/microldstop.cc
M src/arch/x86/insts/microldstop.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
M src/arch/x86/isa/microops/ldstop.isa
M src/arch/x86/isa/operands.isa
7 files changed, 327 insertions(+), 298 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 9b16fad..b0f908b 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -51,7 +51,6 @@
Source('fs_workload.cc')
Source('insts/badmicroop.cc')
Source('insts/microfpop.cc')
-Source('insts/microldstop.cc')
Source('insts/micromediaop.cc')
Source('insts/microop.cc')
Source('insts/microregop.cc')
diff --git a/src/arch/x86/insts/microldstop.cc
b/src/arch/x86/insts/microldstop.cc
deleted file mode 100644
index 1debacc..000
--- a/src/arch/x86/insts/microldstop.cc
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * Copyright (c) 2015 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/x86/insts/microldstop.hh"
-
-#include
-
-namespace X86ISA
-{
-
-std::string
-LdStOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)
const
-{
-std::stringstream response;
-
-printMnemonic(response, instMnem, mnemonic);
-if (flags[IsLoad])
-printDestReg(response, 0, dataSize);
-else
-printSrcReg(response, 2, dataSize);
-response << ", ";
-printMem(response, segment, scale, index, base, disp, addressSize,
false);
-return response.str();
-}
-
-std::string
-LdStSplitOp::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream response;
-
-printMnemonic(response, instMnem, mnemonic);
-int baseRegIdx = flags[IsLoad] ? 0 : 2;
-response << "[";
-printDestReg(response, baseRegIdx, dataSize);
-response << ", ";
-printDestReg(response, baseRegIdx+1, dataSize);
-response << "], ";
-printMem(response, segment, scale, index, base, disp, addressSize,
false);
-return response.str();
-}
-
-}
diff --git a/src/arch/x86/insts/microldstop.hh
b/src/arch/x86/insts/microldstop.hh
index 2611095..1272cb0 100644
--- a/src/arch/x86/insts/microldstop.hh
+++
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Generalize the RegOp operands.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42345 )
Change subject: arch-x86: Generalize the RegOp operands.
..
arch-x86: Generalize the RegOp operands.
This mechanism can now be used in other types of microops.
Change-Id: I82cb15b9d7b3c1e684aaa7482ea98b313f1d85d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42345
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
A src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/microregop.hh
M src/arch/x86/isa/microops/regop.isa
3 files changed, 223 insertions(+), 172 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
new file mode 100644
index 000..27af296
--- /dev/null
+++ b/src/arch/x86/insts/microop_args.hh
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
+#define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
+
+#include
+#include
+#include
+
+#include "arch/x86/insts/static_inst.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/types.hh"
+#include "base/cprintf.hh"
+#include "cpu/reg_class.hh"
+
+namespace X86ISA
+{
+
+struct DestOp
+{
+using ArgType = InstRegIndex;
+const RegIndex dest;
+const size_t size;
+RegIndex index() const { return dest; }
+
+DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
+};
+
+struct Src1Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src1;
+const size_t size;
+RegIndex index() const { return src1; }
+
+Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
+};
+
+struct Src2Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src2;
+const size_t size;
+RegIndex index() const { return src2; }
+
+Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
+};
+
+template
+struct FoldedOp : public Base
+{
+template
+FoldedOp(InstType *inst, typename Base::ArgType idx) :
+Base(INTREG_FOLDED(idx.index(), inst->foldOBit), inst->dataSize)
+{}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printReg(os, RegId(IntRegClass, this->index()),
+this->size);
+}
+};
+
+template
+struct CrOp : public Base
+{
+template
+CrOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "cr%d", this->index());
+}
+};
+
+template
+struct DbgOp : public Base
+{
+template
+DbgOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "dr%d", this->index());
+}
+
+};
+
+template
+struct SegOp : public Base
+{
+template
+SegOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printSegment(os, this->index());
+}
+};
+
+template
+struct MiscOp : public Base
+{
+template
+MiscOp(InstType *inst, typename Base::ArgType idx) :
+Base(idx.index(), inst->dataSize)
+{}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printReg(os, RegId(MiscRegClass, this->index()),
+
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Factor out duplication in the new RegOp base classes.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42344 )
Change subject: arch-x86: Factor out duplication in the new RegOp base
classes.
..
arch-x86: Factor out duplication in the new RegOp base classes.
Instead of having the cross product of dest/src1/src2 and folded int,
debug, control, misc, and segment operands, break them up so they can be
mixed together in different combinations using "using" declarations.
Change-Id: I04357b08bd8a6cd91c2e4df64a2c6cb760bfe90e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42344
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/insts/microregop.hh
1 file changed, 90 insertions(+), 186 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/microregop.hh
b/src/arch/x86/insts/microregop.hh
index e7bd053..37e9d6f 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -43,217 +43,121 @@
namespace X86ISA
{
-struct RegOpDest
+struct DestOp
{
using ArgType = InstRegIndex;
+const RegIndex dest;
+const size_t size;
+RegIndex index() const { return dest; }
-RegIndex dest;
-size_t size;
+DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
+};
+struct Src1Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src1;
+const size_t size;
+RegIndex index() const { return src1; }
+
+Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
+};
+
+struct Src2Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src2;
+const size_t size;
+RegIndex index() const { return src2; }
+
+Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
+};
+
+template
+struct FoldedOp : public Base
+{
template
-RegOpDest(InstType *inst, ArgType idx) :
-dest(INTREG_FOLDED(idx.index(), inst->foldOBit)),
-size(inst->dataSize)
+FoldedOp(InstType *inst, typename Base::ArgType idx) :
+Base(INTREG_FOLDED(idx.index(), inst->foldOBit), inst->dataSize)
{}
void
print(std::ostream ) const
{
-X86StaticInst::printReg(os, RegId(IntRegClass, dest), size);
+X86StaticInst::printReg(os, RegId(IntRegClass, this->index()),
+this->size);
}
};
-struct RegOpDbgDest
+template
+struct CrOp : public Base
{
-using ArgType = InstRegIndex;
-
-RegIndex dest;
-size_t size;
-
template
-RegOpDbgDest(InstType *inst, ArgType idx) : dest(idx.index()),
-size(inst->dataSize)
+CrOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "cr%d", this->index());
+}
+};
+
+template
+struct DbgOp : public Base
+{
+template
+DbgOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "dr%d", this->index());
+}
+
+};
+
+template
+struct SegOp : public Base
+{
+template
+SegOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printSegment(os, this->index());
+}
+};
+
+template
+struct MiscOp : public Base
+{
+template
+MiscOp(InstType *inst, typename Base::ArgType idx) :
+Base(idx.index(), inst->dataSize)
{}
void
print(std::ostream ) const
{
-ccprintf(os, "dr%d", dest);
+X86StaticInst::printReg(os, RegId(MiscRegClass, this->index()),
+this->size);
}
};
-struct RegOpCrDest
-{
-using ArgType = InstRegIndex;
+using RegOpDest = FoldedOp;
+using RegOpDbgDest = DbgOp;
+using RegOpCrDest = CrOp;
+using RegOpSegDest = SegOp;
+using RegOpMiscDest = MiscOp;
-RegIndex dest;
-size_t size;
+using RegOpSrc1 = FoldedOp;
+using RegOpDbgSrc1 = DbgOp;
+using RegOpCrSrc1 = CrOp;
+using RegOpSegSrc1 = SegOp;
+using RegOpMiscSrc1 = MiscOp;
-template
-RegOpCrDest(InstType *inst, ArgType idx) : dest(idx.index()),
-size(inst->dataSize)
-{}
-
-void
-print(std::ostream ) const
-{
-ccprintf(os, "cr%d", dest);
-}
-};
-
-struct RegOpSegDest
-{
-using ArgType = InstRegIndex;
-
-RegIndex dest;
-size_t size;
-
-template
-RegOpSegDest(InstType *inst, ArgType idx) : dest(idx.index()),
-size(inst->dataSize)
-{}
-
-void
-print(std::ostream ) const
-{
-X86StaticInst::printSegment(os, dest);
-}
-};
-
-struct RegOpMiscDest
-{
-using ArgType = InstRegIndex;
-
-RegIndex dest;
-size_t size;
-
-template
-RegOpMiscDest(InstType *inst, ArgType idx) : dest(idx.index()),
-size(inst->dataSize)
-{}
-
-void
-
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix x86 build.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45205 )
Change subject: arch-x86: Fix x86 build.
..
arch-x86: Fix x86 build.
Variation of fix by Maximilian Stein:
https://gem5-review.googlesource.com/c/public/gem5/+/45185
Placate gcc, which thinks we're doing something wrong when using
strncpy. Also ensure that fixed size buffers for strings are filled
completely, rather than just filling in the part which holds the string
we want.
Change-Id: I59f51f6a56a3a3e2632eb89ecb6db709fbbd165d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45205
Maintainer: Gabe Black
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/bios/acpi.cc
1 file changed, 25 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc
index 53b6e4d..9a5d32e 100644
--- a/src/arch/x86/bios/acpi.cc
+++ b/src/arch/x86/bios/acpi.cc
@@ -37,6 +37,7 @@
#include "arch/x86/bios/acpi.hh"
+#include
#include
#include
@@ -52,6 +53,26 @@
namespace ACPI
{
+static void
+fillCopy(void *dest, size_t dest_size, const void *src, size_t src_size)
+{
+src_size = std::min(src_size, dest_size);
+const size_t zero_size = dest_size - src_size;
+
+uint8_t *pos = (uint8_t *)dest;
+
+std::memcpy(pos, src, src_size);
+pos += src_size;
+
+std::memset(pos, 0, zero_size);
+}
+
+static void
+fillCopy(void *dest, size_t dest_size, const std::string )
+{
+fillCopy(dest, dest_size, src.c_str(), src.length());
+}
+
const char RSDP::signature[] = "RSD PTR ";
static uint8_t
@@ -93,7 +114,7 @@
static_assert(sizeof(signature) - 1 == sizeof(data->signature),
"signature length mismatch");
std::memcpy(data->signature, signature, sizeof(data->signature));
-std::strncpy(data->oemID, params().oem_id.c_str(),
sizeof(data->oemID));
+fillCopy(data->oemID, sizeof(data->oemID), params().oem_id);
data->revision = params().revision;
data->length = mem.size();
@@ -133,12 +154,11 @@
// Fill in the header.
auto& p = params();
Mem* header = (Mem*)mem.data();
-std::strncpy(header->signature, signature, sizeof(header->signature));
+fillCopy(header->signature, sizeof(header->signature), signature);
header->length = mem.size();
header->revision = revision;
-std::strncpy(header->oemID, p.oem_id.c_str(), sizeof(header->oemID));
-std::strncpy(header->oemTableID, p.oem_table_id.c_str(),
-sizeof(header->oemTableID));
+fillCopy(header->oemID, sizeof(header->oemID), p.oem_id);
+fillCopy(header->oemTableID, sizeof(header->oemTableID),
p.oem_table_id);
header->oemRevision = p.oem_revision;
header->creatorID = p.creator_id;
header->creatorRevision = p.creator_revision;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I59f51f6a56a3a3e2632eb89ecb6db709fbbd165d
Gerrit-Change-Number: 45205
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Maximilian Stein
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Get rid of is*Reg() methods in RegId.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45226 )
Change subject: arch,cpu: Get rid of is*Reg() methods in RegId.
..
arch,cpu: Get rid of is*Reg() methods in RegId.
These bake in the existing set of RegClass values and are not flexible
or scalable.
Change-Id: I107460cd82960d96916d1644403b7635820045a0
---
M src/arch/arm/insts/misc.cc
M src/arch/mips/isa/base.isa
M src/arch/power/insts/static_inst.cc
M src/arch/riscv/utility.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/x86/insts/static_inst.cc
M src/cpu/checker/cpu.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_map.hh
M src/cpu/o3/scoreboard.hh
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
16 files changed, 167 insertions(+), 194 deletions(-)
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index f70b7a7..9c79f60 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -52,7 +52,7 @@
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
const RegId& reg = srcRegIdx(i);
-if (!reg.isMiscReg()) {
+if (!reg.is(MiscRegClass)) {
continue;
}
if (reg.index() == MISCREG_CPSR) {
@@ -80,7 +80,7 @@
bool foundPsr = false;
for (unsigned i = 0; i < numDestRegs(); i++) {
const RegId& reg = destRegIdx(i);
-if (!reg.isMiscReg()) {
+if (!reg.is(MiscRegClass)) {
continue;
}
if (reg.index() == MISCREG_CPSR) {
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 45f873f..fa038a2 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -88,7 +88,7 @@
void
MipsStaticInst::printReg(std::ostream , RegId reg) const
{
-if (reg.isIntReg()) {
+if (reg.is(IntRegClass)) {
ccprintf(os, "r%d", reg.index());
} else {
ccprintf(os, "f%d", reg.index());
diff --git a/src/arch/power/insts/static_inst.cc
b/src/arch/power/insts/static_inst.cc
index 97730b3..35cf286 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -36,11 +36,14 @@
void
PowerStaticInst::printReg(std::ostream , RegId reg) const
{
-if (reg.isIntReg())
+switch (reg.classValue()) {
+ case IntRegClass:
ccprintf(os, "r%d", reg.index());
-else if (reg.isFloatReg())
+break;
+ case FloatRegClass:
ccprintf(os, "f%d", reg.index());
-else if (reg.isMiscReg())
+break;
+ case MiscRegClass:
switch (reg.index()) {
case 0: ccprintf(os, "cr"); break;
case 1: ccprintf(os, "xer"); break;
@@ -49,8 +52,10 @@
default: ccprintf(os, "unknown_reg");
break;
}
-else if (reg.isCCReg())
-panic("printReg: POWER does not implement CCRegClass\n");
+break;
+ default:
+panic("printReg: Unrecognized register class.");
+}
}
std::string
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 68a7421..bae341e 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -102,7 +102,7 @@
inline std::string
registerName(RegId reg)
{
-if (reg.isIntReg()) {
+if (reg.is(IntRegClass)) {
if (reg.index() >= NumIntArchRegs) {
/*
* This should only happen if a instruction is being
speculatively
diff --git a/src/arch/sparc/insts/static_inst.cc
b/src/arch/sparc/insts/static_inst.cc
index 72e4c6b..6369152 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -104,7 +104,7 @@
const int MaxInput = 32;
const int MaxMicroReg = 40;
RegIndex reg_idx = reg.index();
-if (reg.isIntReg()) {
+if (reg.is(IntRegClass)) {
// If we used a register from the next or previous window,
// take out the offset.
while (reg_idx >= MaxMicroReg)
@@ -149,7 +149,7 @@
break;
}
}
-} else if (reg.isFloatReg()) {
+} else if (reg.is(FloatRegClass)) {
ccprintf(os, "%%f%d", reg_idx);
} else {
switch (reg_idx) {
diff --git a/src/arch/x86/insts/static_inst.cc
b/src/arch/x86/insts/static_inst.cc
index 6a9286e..9ec9b89 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -134,71 +134,74 @@
RegIndex reg_idx = reg.index();
-if (reg.isIntReg()) {
-const char * suffix = "";
-bool fold = reg_idx & IntFoldBit;
-reg_idx &= ~IntFoldBit;
+switch (reg.classValue()) {
+ case IntRegClass:
+{
+const char * suffix = "";
+bool fold = reg_idx & IntFoldBit;
+reg_idx &= ~IntFoldBit;
-if (fold)
-
[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Rename RegClass to RegClassIndex.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45229 )
Change subject: arch,cpu: Rename RegClass to RegClassIndex.
..
arch,cpu: Rename RegClass to RegClassIndex.
This type is really an index which selects a RegClass, not a RegClass
itself.
A follow on change will rename RegClassInfo to RegClass.
Change-Id: I2c1b1d4105bd11b58680053b484d4c1aa1055a9f
---
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/x86/insts/static_inst.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/reg_class.hh
5 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/src/arch/arm/tracers/tarmac_record.hh
b/src/arch/arm/tracers/tarmac_record.hh
index b02f780..f47b703 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -160,7 +160,7 @@
/** True if register entry is valid */
bool regValid;
/** Register class */
-RegClass regClass;
+RegClassIndex regClass;
/** Register arch number */
RegIndex regRel;
/** Register name to be printed */
diff --git a/src/arch/x86/insts/static_inst.hh
b/src/arch/x86/insts/static_inst.hh
index 52f8048..57dba5f 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -60,7 +60,7 @@
// unified space concept, it is easier for the moment to rely on
// an helper function to compute the RegClass. It would be nice
// to fix those definition and get rid of this.
-RegClass
+RegClassIndex
computeRegClass(RegIndex _idx)
{
if (_idx < FP_Reg_Base) {
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index bdbea30..18dab11 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -191,7 +191,7 @@
}
PhysRegFile::IdRange
-PhysRegFile::getRegIds(RegClass cls)
+PhysRegFile::getRegIds(RegClassIndex cls)
{
switch (cls)
{
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index fca0959..880e849 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -351,7 +351,7 @@
* Auxiliary function to transition from Full vector mode to Elem mode
* and to initialise the rename map.
*/
-IdRange getRegIds(RegClass cls);
+IdRange getRegIds(RegClassIndex cls);
/**
* Get the true physical register id.
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 36c4206..0f303ec 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -49,7 +49,7 @@
#include "config/the_isa.hh"
/** Enumerate the classes of registers. */
-enum RegClass
+enum RegClassIndex
{
IntRegClass,///< Integer register
FloatRegClass, ///< Floating-point register
@@ -86,7 +86,7 @@
{
protected:
static const char* regClassStrings[];
-RegClass regClass;
+RegClassIndex regClass;
RegIndex regIdx;
ElemIndex elemIdx;
static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
@@ -97,10 +97,11 @@
public:
RegId() : RegId(IntRegClass, 0) {}
-RegId(RegClass reg_class, RegIndex reg_idx)
+RegId(RegClassIndex reg_class, RegIndex reg_idx)
: RegId(reg_class, reg_idx, IllegalElemIndex) {}
-explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex
elem_idx)
+explicit RegId(RegClassIndex reg_class, RegIndex reg_idx,
+ElemIndex elem_idx)
: regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
numPinnedWrites(0)
{
@@ -144,7 +145,7 @@
}
/** @return true if it is of the specified class. */
-bool is(RegClass reg_class) const { return regClass == reg_class; }
+bool is(RegClassIndex reg_class) const { return regClass == reg_class;
}
/** Index accessors */
/** @{ */
@@ -174,7 +175,7 @@
/** Elem accessor */
RegIndex elemIndex() const { return elemIdx; }
/** Class accessor */
-RegClass classValue() const { return regClass; }
+RegClassIndex classValue() const { return regClass; }
/** Return a const char* with the register class name. */
const char* className() const { return regClassStrings[regClass]; }
@@ -205,14 +206,14 @@
{}
/** Scalar PhysRegId constructor. */
-explicit PhysRegId(RegClass _regClass, RegIndex _regIdx,
+explicit PhysRegId(RegClassIndex _regClass, RegIndex _regIdx,
RegIndex _flatIdx)
: RegId(_regClass, _regIdx), flatIdx(_flatIdx),
numPinnedWritesToComplete(0), pinned(false)
{}
/** Vector PhysRegId constructor (w/ elemIndex). */
-explicit PhysRegId(RegClass _regClass, RegIndex _regIdx,
+explicit PhysRegId(RegClassIndex _regClass, RegIndex _regIdx,
ElemIndex elem_idx, RegIndex flat_idx)
: RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx),
numPinnedWritesToComplete(0), pinned(false)
--
To view, visit
[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete an unnecessary return in RegId::flatIndex.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45225 )
Change subject: cpu: Delete an unnecessary return in RegId::flatIndex.
..
cpu: Delete an unnecessary return in RegId::flatIndex.
panic() is marked [[noreturn]], so there's no need to put a dummy return
after it.
Change-Id: Icebba480ef583a149188d4d6f9481fe0bbd95082
---
M src/cpu/reg_class.hh
1 file changed, 0 insertions(+), 1 deletion(-)
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 9c4af45..fa8e2a1 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -192,7 +192,6 @@
return Scale * regIdx + elemIdx;
}
panic("Trying to flatten a register without class!");
-return -1;
}
/** @} */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icebba480ef583a149188d4d6f9481fe0bbd95082
Gerrit-Change-Number: 45225
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Get rid of the unused NumRegClasses constant.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45227 )
Change subject: cpu: Get rid of the unused NumRegClasses constant.
..
cpu: Get rid of the unused NumRegClasses constant.
Change-Id: Icb2918a97f58a79159307a5d7cba877899268caa
---
M src/cpu/reg_class.hh
1 file changed, 0 insertions(+), 6 deletions(-)
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 2f63865..7081409 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -77,12 +77,6 @@
RegIndex zeroReg() const { return _zeroReg; }
};
-/** Number of register classes.
- * This value is not part of the enum, because putting it there makes the
- * compiler complain about unhandled cases in some switch statements.
- */
-const int NumRegClasses = MiscRegClass + 1;
-
/** Register ID: describe an architectural register with its class and
index.
* This structure is used instead of just the register index to
disambiguate
* between different classes of registers. For example, a integer register
with
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Icb2918a97f58a79159307a5d7cba877899268caa
Gerrit-Change-Number: 45227
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Get rid of the redundant PhysRegIndex type.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45228 )
Change subject: cpu: Get rid of the redundant PhysRegIndex type.
..
cpu: Get rid of the redundant PhysRegIndex type.
It was defined to be effectively the same type as RegIndex, which is a
uint16_t. Having two types for essentially the same thing (which the
compiler would treat as equivalent) adds unnecessary complexity.
Change-Id: Ibf6badc19e3b0a27c3bc3e68def1e686dbef3ea8
---
M src/cpu/o3/dep_graph.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/rob.hh
M src/cpu/reg_class.hh
5 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/src/cpu/o3/dep_graph.hh b/src/cpu/o3/dep_graph.hh
index 1100742..c34e8d9 100644
--- a/src/cpu/o3/dep_graph.hh
+++ b/src/cpu/o3/dep_graph.hh
@@ -87,27 +87,27 @@
void reset();
/** Inserts an instruction to be dependent on the given index. */
-void insert(PhysRegIndex idx, const DynInstPtr _inst);
+void insert(RegIndex idx, const DynInstPtr _inst);
/** Sets the producing instruction of a given register. */
-void setInst(PhysRegIndex idx, const DynInstPtr _inst)
+void setInst(RegIndex idx, const DynInstPtr _inst)
{ dependGraph[idx].inst = new_inst; }
/** Clears the producing instruction. */
-void clearInst(PhysRegIndex idx)
+void clearInst(RegIndex idx)
{ dependGraph[idx].inst = NULL; }
/** Removes an instruction from a single linked list. */
-void remove(PhysRegIndex idx, const DynInstPtr _to_remove);
+void remove(RegIndex idx, const DynInstPtr _to_remove);
/** Removes and returns the newest dependent of a specific register. */
-DynInstPtr pop(PhysRegIndex idx);
+DynInstPtr pop(RegIndex idx);
/** Checks if the entire dependency graph is empty. */
bool empty() const;
/** Checks if there are any dependents on a specific register. */
-bool empty(PhysRegIndex idx) const { return !dependGraph[idx].next; }
+bool empty(RegIndex idx) const { return !dependGraph[idx].next; }
/** Debugging function to dump out the dependency graph.
*/
@@ -179,8 +179,7 @@
template
void
-DependencyGraph::insert(PhysRegIndex idx,
-const DynInstPtr _inst)
+DependencyGraph::insert(RegIndex idx, const DynInstPtr
_inst)
{
//Add this new, dependent instruction at the head of the dependency
//chain.
@@ -200,7 +199,7 @@
template
void
-DependencyGraph::remove(PhysRegIndex idx,
+DependencyGraph::remove(RegIndex idx,
const DynInstPtr _to_remove)
{
DepEntry *prev = [idx];
@@ -238,7 +237,7 @@
template
DynInstPtr
-DependencyGraph::pop(PhysRegIndex idx)
+DependencyGraph::pop(RegIndex idx)
{
DepEntry *node;
node = dependGraph[idx].next;
diff --git a/src/cpu/o3/probe/elastic_trace.hh
b/src/cpu/o3/probe/elastic_trace.hh
index 24148b7..fb802d5 100644
--- a/src/cpu/o3/probe/elastic_trace.hh
+++ b/src/cpu/o3/probe/elastic_trace.hh
@@ -87,7 +87,7 @@
public:
typedef typename O3CPUImpl::DynInstPtr DynInstPtr;
typedef typename O3CPUImpl::DynInstConstPtr DynInstConstPtr;
-typedef typename std::pair SeqNumRegPair;
+typedef typename std::pair SeqNumRegPair;
/** Trace record types corresponding to instruction node types */
typedef ProtoMessage::InstDepRecord::RecordType RecordType;
@@ -239,7 +239,7 @@
* After Write dependencies. The key is the renamed physical register
and
* the value is the instruction sequence number of its last producer.
*/
-std::unordered_map physRegDepMap;
+std::unordered_map physRegDepMap;
/**
* @defgroup TraceInfo Struct for a record in the instruction
dependency
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 8871b48..bdbea30 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -72,8 +72,8 @@
+ _numPhysicalCCRegs),
vecMode(vmode)
{
-PhysRegIndex phys_reg;
-PhysRegIndex flat_reg_idx = 0;
+RegIndex phys_reg;
+RegIndex flat_reg_idx = 0;
// The initial batch of registers are the integer ones
for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index 6d972eb..ba5e027 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -62,7 +62,7 @@
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
-typedef std::pair UnmapInfo;
+typedef std::pair UnmapInfo;
typedef typename std::list::iterator InstIt;
/** Possible ROB statuses. */
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 7081409..36c4206 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -188,12 +188,6 @@
}
};
-/** Physical register index type.
- * Although the Impl might be a better for this, but there are a few
classes
- *
[gem5-dev] Change in gem5/gem5[develop]: scons,tests: Delete support for the UnitTest scons class/function.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45168 )
Change subject: scons,tests: Delete support for the UnitTest scons
class/function.
..
scons,tests: Delete support for the UnitTest scons class/function.
There are no more UnitTest()s, and we shouldn't write any new ones.
Delete the function-like class used to set them up.
Change-Id: Ia353cf698c907b5c7f7c383495f611089fa8b019
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45168
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/SConscript
1 file changed, 0 insertions(+), 17 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index bf2d22e..41ae1ad 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -589,22 +589,6 @@
else:
return env.Program(self.path(env), objs)
-class UnitTest(Executable):
-'''Create a UnitTest'''
-def __init__(self, target, *srcs_and_filts, **kwargs):
-super(UnitTest, self).__init__(target, *srcs_and_filts)
-
-self.main = kwargs.get('main', False)
-
-def declare(self, env):
-sources = list(self.sources)
-for f in self.filters:
-sources += Source.all.apply_filter(env, f)
-objs = self.srcs_to_objs(env, sources) + env['STATIC_OBJS']
-if self.main:
-objs += env['MAIN_OBJS']
-return super(UnitTest, self).declare(env, objs)
-
class GTest(Executable):
'''Create a unit test based on the google test framework.'''
all = []
@@ -660,7 +644,6 @@
Export('ProtoBuf')
Export('GrpcProtoBuf')
Export('Executable')
-Export('UnitTest')
Export('GTest')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia353cf698c907b5c7f7c383495f611089fa8b019
Gerrit-Change-Number: 45168
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Delete the unittest/genini.py script.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45167 )
Change subject: misc: Delete the unittest/genini.py script.
..
misc: Delete the unittest/genini.py script.
It looks like this script was intended to be used to generate config.ini
files from a given gem5 configuration, although some of the functions
and paths it uses are quite obsolete and won't work any more, for
instance m5execfile and the util/pbs directory.
The currently recommended way to generate a config.ini file is to run a
configurtion up to the point it would be generated and then stop it,
that *will* work today, and while it's not necessarily elegant to have
to run a simulation to an arbitrary point and then kill it, relying on
the config.ini itself, an intermediate artifact, is also not
particularly elegant.
Rather than move this script to util or config, either of which would be
a more appropriate home for it, and then also attempting to fix it up to
work with modern gem5, where it may then still sit unused and forgotten,
it's better to just delete it and rely on the other existing method.
Change-Id: I1ae2842730bbe5e76549eb1d962d7d30fb5edfc0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45167
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
D src/unittest/genini.py
1 file changed, 0 insertions(+), 72 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/unittest/genini.py b/src/unittest/genini.py
deleted file mode 100755
index 854ce02..000
--- a/src/unittest/genini.py
+++ /dev/null
@@ -1,72 +0,0 @@
-#!/usr/bin/env python2.7
-# Copyright (c) 2005 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import getopt, os, os.path, sys
-from os.path import join as joinpath, realpath
-
-mypath = sys.path[0]
-sys.path.append(joinpath(mypath, '..'))
-sys.path.append(joinpath(mypath, '../python'))
-sys.path.append(joinpath(mypath, '../util/pbs'))
-
-pathlist = [ '.' ]
-
-m5_build_env = {}
-
-try:
-opts, args = getopt.getopt(sys.argv[1:], '-E:I:')
-for opt,arg in opts:
-if opt == '-E':
-offset = arg.find('=')
-if offset == -1:
-name = arg
-value = 'True'
-else:
-name = arg[:offset]
-value = arg[offset+1:]
-os.environ[name] = value
-m5_build_env[name] = value
-if opt == '-I':
-pathlist.append(arg)
-except getopt.GetoptError:
-sys.exit('Improper Usage')
-
-import __main__
-__main__.m5_build_env = m5_build_env
-
-from m5 import *
-
-for path in pathlist:
-AddToPath(path)
-
-for arg in args:
-m5execfile(arg, globals())
-
-if 'root' in globals() and isinstance(root, Root):
-instantiate(root)
-else:
-print("Instantiation skipped: no root object found.")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1ae2842730bbe5e76549eb1d962d7d30fb5edfc0
Gerrit-Change-Number: 45167
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas
[gem5-dev] Change in gem5/gem5[develop]: tests: Remove the stattest "UnitTest".
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45166 )
Change subject: tests: Remove the stattest "UnitTest".
..
tests: Remove the stattest "UnitTest".
This "UnitTest" would compile against and exercise the various stats
types in gem5, but did not verify that anything that happened was
correct. It was also not really a unit test in the sense that while it
did try to do something fairly specific, it did that using an
arbitrarily large portion of gem5.
Actual unit tests using the googletest framework are a more appropriate
way to test these mechanisms.
Change-Id: I3b424e9f5ffcf41f7de1cb42e6a222bf1c40054a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45166
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
D src/unittest/SConscript
D src/unittest/stattest.cc
D src/unittest/stattestmain.py
3 files changed, 0 insertions(+), 743 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/unittest/SConscript b/src/unittest/SConscript
deleted file mode 100644
index 43eb16a..000
--- a/src/unittest/SConscript
+++ /dev/null
@@ -1,32 +0,0 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-Import('*')
-
-stattest_py = PySource('m5', 'stattestmain.py', tags='stattest')
-UnitTest('stattest', 'stattest.cc', with_tag('stattest'), main=True)
diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
deleted file mode 100644
index 7e80669..000
--- a/src/unittest/stattest.cc
+++ /dev/null
@@ -1,692 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "pybind11/pybind11.h"
-
-#include
[gem5-dev] Change in gem5/gem5[develop]: tests: Delete the nmtest "UnitTest".
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45165 )
Change subject: tests: Delete the nmtest "UnitTest".
..
tests: Delete the nmtest "UnitTest".
This "UnitTest" actually links against all of gem5, and can be used to
look at a binary and find either what symbol goes with an address, or
what address goes with a symbol.
While that could be a useful thing to want to do, there are other ways
to do that with external tools. Also, other than by seeing if this tool
compiles and manually seeing if it returns reasonable results, this
doesn't really actually test anything.
Finally, this is one of the old style "UnitTest"s, quotes intentional,
since while it may try to do a fairly specific thing, it actually
exercises an arbitrarily large portion of gem5 as a whole to do it, does
not self report success or failure, contain any test cases or input data
or expected output, and is not run automatically as part of our testing
suite.
Tests for the underlying classes in the Loader namespace would be/are
more appropriate, and make this test unnecessary.
Change-Id: I48db315d3da440fd26be0a81cc8e07affcacda46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45165
Reviewed-by: Giacomo Travaglini
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/unittest/SConscript
D src/unittest/nmtest.cc
2 files changed, 0 insertions(+), 74 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/unittest/SConscript b/src/unittest/SConscript
index 5008066..43eb16a 100644
--- a/src/unittest/SConscript
+++ b/src/unittest/SConscript
@@ -28,7 +28,5 @@
Import('*')
-UnitTest('nmtest', 'nmtest.cc')
-
stattest_py = PySource('m5', 'stattestmain.py', tags='stattest')
UnitTest('stattest', 'stattest.cc', with_tag('stattest'), main=True)
diff --git a/src/unittest/nmtest.cc b/src/unittest/nmtest.cc
deleted file mode 100644
index fd24524..000
--- a/src/unittest/nmtest.cc
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include
-#include
-#include
-
-#include "base/loader/object_file.hh"
-#include "base/logging.hh"
-#include "base/str.hh"
-
-int
-main(int argc, char *argv[])
-{
-if (argc != 2 && argc != 3)
-panic("usage: %s \n", argv[0]);
-
-auto *obj = Loader::createObjectFile(argv[1]);
-if (!obj)
-panic("file not found\n");
-
-if (argc == 2) {
-for (const Loader::Symbol : obj->symtab())
-cprintf("%#x %s\n", symbol.address, symbol.name);
-} else {
-std::string symbol = argv[2];
-Addr address;
-
-if (symbol[0] == '0' && symbol[1] == 'x') {
-Loader::SymbolTable::const_iterator it;
-if (to_number(symbol, address) &&
-(it = obj->symtab().find(address)) != obj->symtab().end())
{
-cprintf("address = %#x, symbol = %s\n", address, it->name);
-} else {
-cprintf("address = %#x was not found\n", address);
-}
-} else {
-auto it = obj->symtab().find(symbol);
-if (it != obj->symtab().end())
-
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix x86 build.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45205 )
Change subject: arch-x86: Fix x86 build.
..
arch-x86: Fix x86 build.
Variation of fix by Maximilian Stein:
https://gem5-review.googlesource.com/c/public/gem5/+/45185
Placate gcc, which thinks we're doing something wrong when using
strncpy. Also ensure that fixed size buffers for strings are filled
completely, rather than just filling in the part which holds the string
we want.
Change-Id: I59f51f6a56a3a3e2632eb89ecb6db709fbbd165d
---
M src/arch/x86/bios/acpi.cc
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc
index 53b6e4d..9a5d32e 100644
--- a/src/arch/x86/bios/acpi.cc
+++ b/src/arch/x86/bios/acpi.cc
@@ -37,6 +37,7 @@
#include "arch/x86/bios/acpi.hh"
+#include
#include
#include
@@ -52,6 +53,26 @@
namespace ACPI
{
+static void
+fillCopy(void *dest, size_t dest_size, const void *src, size_t src_size)
+{
+src_size = std::min(src_size, dest_size);
+const size_t zero_size = dest_size - src_size;
+
+uint8_t *pos = (uint8_t *)dest;
+
+std::memcpy(pos, src, src_size);
+pos += src_size;
+
+std::memset(pos, 0, zero_size);
+}
+
+static void
+fillCopy(void *dest, size_t dest_size, const std::string )
+{
+fillCopy(dest, dest_size, src.c_str(), src.length());
+}
+
const char RSDP::signature[] = "RSD PTR ";
static uint8_t
@@ -93,7 +114,7 @@
static_assert(sizeof(signature) - 1 == sizeof(data->signature),
"signature length mismatch");
std::memcpy(data->signature, signature, sizeof(data->signature));
-std::strncpy(data->oemID, params().oem_id.c_str(),
sizeof(data->oemID));
+fillCopy(data->oemID, sizeof(data->oemID), params().oem_id);
data->revision = params().revision;
data->length = mem.size();
@@ -133,12 +154,11 @@
// Fill in the header.
auto& p = params();
Mem* header = (Mem*)mem.data();
-std::strncpy(header->signature, signature, sizeof(header->signature));
+fillCopy(header->signature, sizeof(header->signature), signature);
header->length = mem.size();
header->revision = revision;
-std::strncpy(header->oemID, p.oem_id.c_str(), sizeof(header->oemID));
-std::strncpy(header->oemTableID, p.oem_table_id.c_str(),
-sizeof(header->oemTableID));
+fillCopy(header->oemID, sizeof(header->oemID), p.oem_id);
+fillCopy(header->oemTableID, sizeof(header->oemTableID),
p.oem_table_id);
header->oemRevision = p.oem_revision;
header->creatorID = p.creator_id;
header->creatorRevision = p.creator_revision;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45205
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I59f51f6a56a3a3e2632eb89ecb6db709fbbd165d
Gerrit-Change-Number: 45205
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42686 )
Change subject: arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
..
arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
The only thing still in arch/registers.hh were related to vector
registers. To make it obvious that nothing else should be added, this
change renames the file so that it has the much less generic name
arch/vecregs.hh.
Change-Id: I729697dc576e1978047688d9700dc07ff9b17044
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42686
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/SConscript
M src/arch/arm/htm.hh
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.hh
M src/arch/arm/isa_device.hh
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/linux/se_workload.hh
M src/arch/arm/pmu.hh
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
M src/arch/arm/tracers/tarmac_base.hh
M src/arch/arm/tracers/tarmac_parser.hh
R src/arch/arm/vecregs.hh
R src/arch/mips/vecregs.hh
R src/arch/null/vecregs.hh
R src/arch/power/vecregs.hh
R src/arch/riscv/vecregs.hh
R src/arch/sparc/vecregs.hh
M src/arch/x86/emulenv.hh
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/arch/x86/isa/includes.isa
M src/arch/x86/linux/se_workload.cc
M src/arch/x86/linux/syscalls.cc
M src/arch/x86/pseudo_inst_abi.hh
R src/arch/x86/vecregs.hh
M src/cpu/exec_context.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/execute.cc
M src/cpu/minor/scoreboard.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rob.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M src/cpu/trace/trace_cpu.hh
M src/dev/riscv/clint.hh
M src/dev/riscv/plic.cc
M src/sim/process.hh
44 files changed, 36 insertions(+), 57 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 73c6afb..f362f1c 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -61,9 +61,9 @@
isa.hh
locked_mem.hh
page_size.hh
-registers.hh
remote_gdb.hh
types.hh
+vecregs.hh
'''),
env.subst('${TARGET_ISA}'))
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
index 6757622..3f1f60e 100644
--- a/src/arch/arm/htm.hh
+++ b/src/arch/arm/htm.hh
@@ -44,8 +44,8 @@
* ISA-specific types for hardware transactional memory.
*/
-#include "arch/arm/registers.hh"
#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/vec.hh"
#include "arch/generic/htm.hh"
#include "base/types.hh"
diff --git a/src/arch/arm/insts/tme64ruby.cc
b/src/arch/arm/insts/tme64ruby.cc
index 5e22deb..defc622 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -39,7 +39,6 @@
#include "arch/arm/htm.hh"
#include "arch/arm/insts/tme64.hh"
#include "arch/arm/locked_mem.hh"
-#include "arch/arm/registers.hh"
#include "arch/generic/memhelpers.hh"
#include "debug/ArmTme.hh"
#include "mem/packet_access.hh"
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index e60878d..ead22d0 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -42,7 +42,6 @@
#define __ARCH_ARM_INTERRUPT_HH__
#include "arch/arm/faults.hh"
-#include "arch/arm/registers.hh"
#include "arch/arm/regs/misc.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/interrupts.hh"
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 197350a..bc773f5 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -42,7 +42,7 @@
#define __ARCH_ARM_ISA_HH__
#include "arch/arm/isa_device.hh"
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/int.hh"
#include "arch/arm/regs/misc.hh"
#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
diff --git a/src/arch/arm/isa_device.hh b/src/arch/arm/isa_device.hh
index 365b3e0..63e6b8e 100644
--- a/src/arch/arm/isa_device.hh
+++ b/src/arch/arm/isa_device.hh
@@ -38,8 +38,8 @@
#ifndef __ARCH_ARM_ISA_DEVICE_HH__
#define __ARCH_ARM_ISA_DEVICE_HH__
-#include "arch/arm/registers.hh"
#include "base/compiler.hh"
+#include "base/types.hh"
class ThreadContext;
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index e827c22..31b2ee0 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -44,7 +44,8 @@
#include
#include "arch/arm/interrupts.hh"
-#include "arch/arm/registers.hh"
+#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/misc.hh"
#include "cpu/kvm/base.hh"
#include "debug/Kvm.hh"
#include "debug/KvmContext.hh"
diff --git a/src/arch/arm/linux/se_workload.hh
b/src/arch/arm/linux/se_workload.hh
index 6156661..1c68e20 100644
---
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using 16 bit VMID
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45186 )
Change subject: arch-arm: Using 16 bit VMID
..
arch-arm: Using 16 bit VMID
Change-Id: Ia4f408b8e84b5f52f6b48fd5d4bbc2a5fac87154
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/pagetable.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index a8c3a14..2d37b93 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -109,7 +109,7 @@
// use (AArch32 w/ LPAE and AArch64)
uint16_t asid; // Address Space Identifier
-uint8_t vmid; // Virtual machine Identifier
+uint16_t vmid; // Virtual machine Identifier
uint8_t N; // Number of bits in pagesize
uint8_t innerAttrs;
uint8_t outerAttrs;
@@ -188,22 +188,22 @@
}
bool
-match(Addr va, uint8_t _vmid, bool hypLookUp, bool secure_lookup,
+match(Addr va, uint16_t _vmid, bool hyp_lookup, bool secure_lookup,
ExceptionLevel target_el, bool in_host) const
{
-return match(va, 0, _vmid, hypLookUp, secure_lookup, true,
+return match(va, 0, _vmid, hyp_lookup, secure_lookup, true,
target_el, in_host);
}
bool
-match(Addr va, uint16_t asn, uint8_t _vmid, bool hypLookUp,
+match(Addr va, uint16_t asn, uint16_t _vmid, bool hyp_lookup,
bool secure_lookup, bool ignore_asn, ExceptionLevel target_el,
bool in_host) const
{
bool match = false;
Addr v = vpn << N;
if (valid && va >= v && va <= v + size && (secure_lookup
== !nstid) &&
-(hypLookUp == isHyp))
+(hyp_lookup == isHyp))
{
match = checkELMatch(target_el, in_host);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 82a9570..9b81b08 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -188,7 +188,7 @@
Fault
TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t
_asid,
- uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
+ uint16_t _vmid, bool _isHyp, TLB::Mode _mode,
TLB::Translation *_trans, bool _timing, bool _functional,
bool secure, TLB::ArmTranslationType tranType,
bool _stage2Req)
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 4f0373a..bd666c9 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -744,7 +744,7 @@
/** ASID that we're servicing the request under */
uint16_t asid;
-uint8_t vmid;
+uint16_t vmid;
boolisHyp;
/** Translation state for delayed requests */
@@ -941,7 +941,7 @@
PortID idx=InvalidPortID) override;
Fault walk(const RequestPtr , ThreadContext *tc,
- uint16_t asid, uint8_t _vmid,
+ uint16_t asid, uint16_t _vmid,
bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
bool timing, bool functional, bool secure,
TLB::ArmTranslationType tranType, bool _stage2Req);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bea1e16..789b29a 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -163,7 +163,7 @@
}
TlbEntry*
-TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
+TLB::lookup(Addr va, uint16_t asn, uint16_t vmid, bool hyp, bool secure,
bool functional, bool ignore_asn, ExceptionLevel target_el,
bool in_host, BaseTLB::Mode mode)
{
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 5aa72b5..6f0f75f 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -222,7 +222,7 @@
* @param mode to differentiate between read/writes/fetches.
* @return pointer to TLB entry if it exists
*/
-TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
+TlbEntry *lookup(Addr vpn, uint16_t asn, uint16_t vmid, bool hyp,
bool secure, bool functional,
bool ignore_asn, ExceptionLevel target_el,
bool in_host, BaseTLB::Mode mode);
@@ -423,7 +423,7 @@
bool isHyp;
TTBCR ttbcr;
uint16_t asid;
-uint8_t vmid;
+uint16_t vmid;
PRRR prrr;
NMRR nmrr;
HCR hcr;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia4f408b8e84b5f52f6b48fd5d4bbc2a5fac87154
Gerrit-Change-Number: 45186
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45187 )
Change subject: arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID
..
arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID
In an Armv8.1 implementation, when EL2 is using AArch64, the VMID size
is an IMPLEMENTATION DEFINED choice of 8 bits or 16 bits.
When implemented, this feature is supported only when EL2 is using AArch64.
The ID_AA64MMFR1_EL1.VMIDBits field identifies the supported VMID size.
Change-Id: I7acde0a9ba285d4740771133debd60a7a7515954
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc_types.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
4 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 80035ae..69a350f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2177,6 +2177,7 @@
case MISCREG_TCR_EL1:
case MISCREG_TCR_EL2:
case MISCREG_TCR_EL3:
+ case MISCREG_VTCR_EL2:
case MISCREG_SCTLR_EL2:
case MISCREG_SCTLR_EL3:
case MISCREG_HSCTLR:
diff --git a/src/arch/arm/regs/misc_types.hh
b/src/arch/arm/regs/misc_types.hh
index c3fd06e..66b1809 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -563,6 +563,7 @@
Bitfield<13, 12> sh0;
Bitfield<15, 14> tg0;
Bitfield<18, 16> ps; // Only defined for VTCR_EL2
+Bitfield<19> vs; // Only defined for VTCR_EL2
Bitfield<21> ha; // Only defined for VTCR_EL2
Bitfield<22> hd; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 789b29a..a117ebd 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2016-2020 ARM Limited
+ * Copyright (c) 2010-2013, 2016-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1372,6 +1372,35 @@
return >getDMAPort();
}
+uint16_t
+TLB::getVMID(ThreadContext *tc) const
+{
+AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+VTCR_t vtcr = tc->readMiscReg(MISCREG_VTCR_EL2);
+uint16_t vmid = 0;
+
+switch (mmfr1.vmidbits) {
+ case 0b:
+// 8 bits
+vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
+break;
+ case 0b0010:
+if (vtcr.vs && ELIs64(tc, EL2)) {
+// 16 bits
+vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 63, 48);
+} else {
+// 8 bits
+vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
+}
+break;
+ default:
+panic("Reserved ID_AA64MMFR1_EL1.VMIDBits value: %#x",
+ mmfr1.vmidbits);
+}
+
+return vmid;
+}
+
void
TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
{
@@ -1456,7 +1485,7 @@
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
if (haveVirtualization) {
-vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
+vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tranType & HypMode;
isHyp &= (tranType & S1S2NsTran) == 0;
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 6f0f75f..12a8a20 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -443,6 +443,10 @@
void updateMiscReg(ThreadContext *tc,
ArmTranslationType tranType = NormalTran);
+/** Returns the current VMID
+ * (information stored in the VTTBR_EL2 register) */
+uint16_t getVMID(ThreadContext *tc) const;
+
public:
void invalidateMiscReg() { miscRegValid = false; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7acde0a9ba285d4740771133debd60a7a7515954
Gerrit-Change-Number: 45187
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Enable ARMv8.1-VMID16 by default
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/45188 ) Change subject: arch-arm: Enable ARMv8.1-VMID16 by default .. arch-arm: Enable ARMv8.1-VMID16 by default Change-Id: Ibeb724cf1e599b10b4ddcc030d3c8eda59afea47 Signed-off-by: Giacomo Travaglini --- M src/arch/arm/ArmISA.py 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 59d3919..f210f7e 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -113,8 +113,8 @@ # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA id_aa64mmfr0_el1 = Param.UInt64(0x00f2, "AArch64 Memory Model Feature Register 0") -# PAN | HPDS | !VHE -id_aa64mmfr1_el1 = Param.UInt64(0x00101000, +# PAN | HPDS | !VHE | VMIDBits +id_aa64mmfr1_el1 = Param.UInt64(0x00101020, "AArch64 Memory Model Feature Register 1") # |VARANGE id_aa64mmfr2_el1 = Param.UInt64(0x0001, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45188 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibeb724cf1e599b10b4ddcc030d3c8eda59afea47 Gerrit-Change-Number: 45188 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40892 )
Change subject: arch-power: Refactor load-store instructions
..
arch-power: Refactor load-store instructions
This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.
Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40892
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
4 files changed, 57 insertions(+), 16 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 596d78d..4c2688c 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -63,7 +63,7 @@
}
// Print the displacement
-ss << ", " << (int32_t)disp;
+ss << ", " << d;
// Print the address register
ss << "(";
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index de9b46c..e982515 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -63,11 +63,12 @@
{
protected:
-int16_t disp;
+int64_t d;
/// Constructor
MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : MemOp(mnem, _machInst, __opClass), disp(machInst.d)
+ : MemOp(mnem, _machInst, __opClass),
+d(sext<16>(machInst.d))
{
}
@@ -75,6 +76,38 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
+/**
+ * Class for memory operations with shifted displacement.
+ */
+class MemDispShiftOp : public MemOp
+{
+ protected:
+
+int64_t ds;
+
+/// Constructor
+MemDispShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : MemOp(mnem, _machInst, __opClass),
+ds(sext<14>(machInst.ds))
+{
+}
+};
+
+
+/**
+ * Class for memory operations with register indexed addressing.
+ */
+class MemIndexOp : public MemOp
+{
+ protected:
+
+/// Constructor
+MemIndexOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : MemOp(mnem, _machInst, __opClass)
+{
+}
+};
+
} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index ac52ab3..e00ce3b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -527,9 +527,7 @@
55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});
58: decode DS_XO {
-2: LoadDispOp::lwa({{ Rt = Mem_sw; }},
- {{ EA = Ra + (disp & 0xfffc); }},
- {{ EA = disp & 0xfffc; }});
+2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
}
format FloatArithOp {
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index c7be2b1..1b2500c 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -240,7 +240,7 @@
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Load', mem_flags, inst_flags)
+ 'MemIndexOp', 'Load', mem_flags, inst_flags)
}};
@@ -249,7 +249,7 @@
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Store', mem_flags, inst_flags)
+ 'MemIndexOp', 'Store', mem_flags, inst_flags)
}};
@@ -262,7 +262,7 @@
# Generate the class
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
- base_class = 'MemOp',
+ base_class = 'MemIndexOp',
exec_template_base = 'Load')
}};
@@ -276,13 +276,13 @@
# Generate the class
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
- base_class = 'MemOp',
+ base_class = 'MemIndexOp',
exec_template_base = 'Store')
}};
-def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp;
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix build after merging #42824
Maximilian Stein has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/45185 ) Change subject: arch-x86: Fix build after merging #42824 .. arch-x86: Fix build after merging #42824 Caused by std::strncpy and -Werror=stringop-truncation. Change-Id: Ib05f267e0a385e186b44e9fad96541009e545fdc --- M src/arch/x86/bios/acpi.cc 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc index 53b6e4d..6ae94b0 100644 --- a/src/arch/x86/bios/acpi.cc +++ b/src/arch/x86/bios/acpi.cc @@ -37,6 +37,7 @@ #include "arch/x86/bios/acpi.hh" +#include #include #include @@ -93,7 +94,8 @@ static_assert(sizeof(signature) - 1 == sizeof(data->signature), "signature length mismatch"); std::memcpy(data->signature, signature, sizeof(data->signature)); -std::strncpy(data->oemID, params().oem_id.c_str(), sizeof(data->oemID)); +std::memcpy(data->oemID, params().oem_id.c_str(), +std::min(sizeof(data->oemID), params().oem_id.length())); data->revision = params().revision; data->length = mem.size(); @@ -133,12 +135,14 @@ // Fill in the header. auto& p = params(); Mem* header = (Mem*)mem.data(); -std::strncpy(header->signature, signature, sizeof(header->signature)); +std::memcpy(header->signature, signature, +std::min(sizeof(header->signature), std::strlen(signature))); header->length = mem.size(); header->revision = revision; -std::strncpy(header->oemID, p.oem_id.c_str(), sizeof(header->oemID)); -std::strncpy(header->oemTableID, p.oem_table_id.c_str(), -sizeof(header->oemTableID)); +std::memcpy(header->oemID, p.oem_id.c_str(), +std::min(sizeof(header->oemID), p.oem_id.length())); +std::memcpy(header->oemTableID, p.oem_table_id.c_str(), +std::min(sizeof(header->oemTableID), p.oem_table_id.length())); header->oemRevision = p.oem_revision; header->creatorID = p.creator_id; header->creatorRevision = p.creator_revision; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45185 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib05f267e0a385e186b44e9fad96541009e545fdc Gerrit-Change-Number: 45185 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Stein Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Implement ACPI root tables
Maximilian Stein has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42824 )
Change subject: arch-x86: Implement ACPI root tables
..
arch-x86: Implement ACPI root tables
The RSDP points to the RSDT (32 bit) and/or the XSDT (64 bit), which are
both instances of the abstract System Description Table.
This commit implements the mechanism to write the three data structures
to memory based on the full system's configuration. The SysDescTable
class acts as base class for the RSDT and XSDT as well as any future
implementation of other System Description Tables.
Change-Id: I710279a72376c04f2a636ff2e96fa80228d03eaf
Signed-off-by: Maximilian Stein
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42824
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/SConscript
M src/arch/x86/bios/ACPI.py
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/acpi.hh
M src/arch/x86/fs_workload.cc
M src/arch/x86/fs_workload.hh
6 files changed, 248 insertions(+), 52 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index d7da290..9b16fad 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -79,6 +79,7 @@
DebugFlag('LocalApic', "Local APIC debugging")
DebugFlag('Decoder', "Decoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
+DebugFlag('ACPI', "ACPI debugging")
python_files = (
'__init__.py',
diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py
index 77de42f..19edac4 100644
--- a/src/arch/x86/bios/ACPI.py
+++ b/src/arch/x86/bios/ACPI.py
@@ -48,8 +48,8 @@
oem_table_id = Param.String('', 'oem table ID')
oem_revision = Param.UInt32(0, 'oem revision number for the table')
-creator_id = Param.String('',
-'string identifying the generator of the table')
+creator_id = Param.UInt32(0,
+'ID identifying the generator of the table')
creator_revision = Param.UInt32(0,
'revision number for the creator of the table')
@@ -78,6 +78,7 @@
# here.
revision = Param.UInt8(2, 'revision of ACPI being used, zero indexed')
-rsdt = Param.X86ACPIRSDT(NULL, 'root system description table')
+rsdt = Param.X86ACPIRSDT(X86ACPIRSDT(),
+'root system description table')
xsdt = Param.X86ACPIXSDT(X86ACPIXSDT(),
'extended system description table')
diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc
index 8cdcdac..91c8e47 100644
--- a/src/arch/x86/bios/acpi.cc
+++ b/src/arch/x86/bios/acpi.cc
@@ -37,16 +37,34 @@
#include "arch/x86/bios/acpi.hh"
+#include
+#include
+
+#include "base/trace.hh"
#include "mem/port.hh"
-#include "params/X86ACPIRSDP.hh"
-#include "params/X86ACPIRSDT.hh"
-#include "params/X86ACPISysDescTable.hh"
-#include "params/X86ACPIXSDT.hh"
+#include "mem/port_proxy.hh"
#include "sim/byteswap.hh"
#include "sim/sim_object.hh"
+namespace X86ISA
+{
+
+namespace ACPI
+{
+
+const char RSDP::signature[] = "RSD PTR ";
+
+static uint8_t
+apic_checksum(uint8_t* ptr, std::size_t size)
+{
+uint8_t sum = 0;
+for (unsigned i = 0; i < size; ++i)
+sum += ptr[i];
+return 0x100 - sum;
+}
+
Addr
-X86ISA::ACPI::LinearAllocator::alloc(std::size_t size, unsigned align)
+LinearAllocator::alloc(std::size_t size, unsigned align)
{
if (align) {
unsigned offset = next % align;
@@ -59,24 +77,124 @@
return chunk;
}
-const char X86ISA::ACPI::RSDP::signature[] = "RSD PTR ";
-
-X86ISA::ACPI::RSDP::RSDP(const Params ) : SimObject(p), oemID(p.oem_id),
-revision(p.revision), rsdt(p.rsdt), xsdt(p.xsdt)
+RSDP::RSDP(const Params ) :
+SimObject(p),
+rsdt(p.rsdt),
+xsdt(p.xsdt)
{}
-X86ISA::ACPI::SysDescTable::SysDescTable(const Params ,
-const char * _signature, uint8_t _revision) : SimObject(p),
-signature(_signature), revision(_revision),
-oemID(p.oem_id), oemTableID(p.oem_table_id),
-oemRevision(p.oem_revision),
-creatorID(p.creator_id), creatorRevision(p.creator_revision)
+Addr
+RSDP::write(PortProxy& phys_proxy, Allocator& alloc) const
+{
+std::vector mem(sizeof(Mem));
+Addr addr = alloc.alloc(mem.size(), 16);
+
+Mem* data = (Mem*)mem.data();
+static_assert(sizeof(signature) - 1 == sizeof(data->signature),
+"signature length mismatch");
+std::memcpy(data->signature, signature, sizeof(data->signature));
+std::strncpy(data->oemID, params().oem_id.c_str(),
sizeof(data->oemID));
+data->revision = params().revision;
+data->length = mem.size();
+
+if (rsdt) {
+data->rsdtAddress = rsdt->write(phys_proxy, alloc);
+DPRINTF(ACPI, "Allocated RSDT @ %llx\n", data->rsdtAddress);
+}
+if (xsdt) {
+data->xsdtAddress = xsdt->write(phys_proxy, alloc);
+
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Add ACPI support for MADT
Maximilian Stein has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41953 )
Change subject: arch-x86: Add ACPI support for MADT
..
arch-x86: Add ACPI support for MADT
This extends the ACPI implementation to support the MADT. This table
contains information about the interrupt system (Local APIC, IO-APIC)
and partially replaces the Intel MP tables.
The change is particularly needed to support other OSes than Linux that
do not support Intel MP.
Change-Id: I132226f46f4d54e2e0b964e2986004e3e5f5f347
Signed-off-by: Maximilian Stein
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41953
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/bios/ACPI.py
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/acpi.hh
3 files changed, 336 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py
index 19edac4..5dfcb4d 100644
--- a/src/arch/x86/bios/ACPI.py
+++ b/src/arch/x86/bios/ACPI.py
@@ -67,6 +67,66 @@
entries = VectorParam.X86ACPISysDescTable([], 'system description
tables')
+
+class X86ACPIMadtRecord(SimObject):
+type = 'X86ACPIMadtRecord'
+cxx_class = 'X86ISA::ACPI::MADT::Record'
+cxx_header = 'arch/x86/bios/acpi.hh'
+abstract = True
+
+class X86ACPIMadt(X86ACPISysDescTable):
+type = 'X86ACPIMadt'
+cxx_class = 'X86ISA::ACPI::MADT::MADT'
+cxx_header = 'arch/x86/bios/acpi.hh'
+
+local_apic_address = Param.UInt32(0, 'Address of the local apic')
+flags = Param.UInt32(0, 'Flags')
+records = VectorParam.X86ACPIMadtRecord([], 'Records in this MADT')
+
+class X86ACPIMadtLAPIC(X86ACPIMadtRecord):
+type = 'X86ACPIMadtLAPIC'
+cxx_header = 'arch/x86/bios/acpi.hh'
+cxx_class = 'X86ISA::ACPI::MADT::LAPIC'
+
+acpi_processor_id = Param.UInt8(0, 'ACPI Processor ID')
+apic_id = Param.UInt8(0, 'APIC ID')
+flags = Param.UInt32(0, 'Flags')
+
+class X86ACPIMadtIOAPIC(X86ACPIMadtRecord):
+type = 'X86ACPIMadtIOAPIC'
+cxx_header = 'arch/x86/bios/acpi.hh'
+cxx_class = 'X86ISA::ACPI::MADT::IOAPIC'
+
+id = Param.UInt8(0, 'I/O APIC ID')
+address = Param.Addr(0, 'I/O APIC Address')
+int_base = Param.UInt32(0, 'Global Interrupt Base')
+
+class X86ACPIMadtIntSourceOverride(X86ACPIMadtRecord):
+type = 'X86ACPIMadtIntSourceOverride'
+cxx_header = 'arch/x86/bios/acpi.hh'
+cxx_class = 'X86ISA::ACPI::MADT::IntSourceOverride'
+
+bus_source = Param.UInt8(0, 'Bus Source')
+irq_source = Param.UInt8(0, 'IRQ Source')
+sys_int = Param.UInt32(0, 'Global System Interrupt')
+flags = Param.UInt16(0, 'Flags')
+
+class X86ACPIMadtNMI(X86ACPIMadtRecord):
+type = 'X86ACPIMadtNMI'
+cxx_header = 'arch/x86/bios/acpi.hh'
+cxx_class = 'X86ISA::ACPI::MADT::NMI'
+
+acpi_processor_id = Param.UInt8(0, 'ACPI Processor ID')
+flags = Param.UInt16(0, 'Flags')
+lint_no = Param.UInt8(0, 'LINT# (0 or 1)')
+
+class X86ACPIMadtLAPICOverride(X86ACPIMadtRecord):
+type = 'X86ACPIMadtLAPICOverride'
+cxx_header = 'arch/x86/bios/acpi.hh'
+cxx_class = 'X86ISA::ACPI::MADT::LAPICOverride'
+
+address = Param.Addr(0, '64-bit Physical Address of Local APIC')
+
# Root System Description Pointer Structure
class X86ACPIRSDP(SimObject):
type = 'X86ACPIRSDP'
diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc
index 91c8e47..53b6e4d 100644
--- a/src/arch/x86/bios/acpi.cc
+++ b/src/arch/x86/bios/acpi.cc
@@ -195,6 +195,119 @@
entries = p.entries;
}
+
+ MADT
+MADT::MADT::MADT(const Params& p) :
+SysDescTable(p, "APIC", 4),
+records(p.records)
+{}
+
+Addr
+MADT::MADT::writeBuf(PortProxy& phys_proxy, Allocator& alloc,
+std::vector& mem) const
+{
+// Since this table ends with a variably sized array, it can't be
extended
+// by another table type.
+assert(mem.empty());
+mem.resize(sizeof(Mem));
+
+Mem* header = reinterpret_cast(mem.data());
+header->localAPICAddress = params().local_apic_address;
+header->flags = params().flags;
+
+for (const auto& record : records) {
+auto entry = record->prepare();
+mem.insert(mem.end(), entry.begin(), entry.end());
+}
+
+DPRINTF(ACPI, "MADT: writing %d records (size: %d)\n",
+records.size(), mem.size());
+
+return SysDescTable::writeBuf(phys_proxy, alloc, mem);
+}
+
+void
+MADT::Record::prepareBuf(std::vector& mem) const
+{
+assert(mem.size() >= sizeof(Mem));
+DPRINTF(ACPI, "MADT: writing record type %d (size: %d)\n",
+type, mem.size());
+
+Mem* header = reinterpret_cast(mem.data());
+header->type = type;
+header->length = mem.size();
+}
+
+void
+MADT::LAPIC::prepareBuf(std::vector& mem) const
+{
+assert(mem.empty());
+mem.resize(sizeof(Mem));
+
+
[gem5-dev] Change in gem5/gem5[develop]: configs: Use MADT in x86 full system simulation
Maximilian Stein has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/42825 ) Change subject: configs: Use MADT in x86 full system simulation .. configs: Use MADT in x86 full system simulation ACPI's MADT describes the interrupt system of a processor/system and partially replaces the Intel MP tables. The config now simply adds the ACPI variant, so an OS can use either Intel MP or ACPI for interrupt configuration. Change-Id: Ie3d293aac0925666f7661a03eab10218f04c8d0c Signed-off-by: Maximilian Stein Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42825 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- M configs/common/FSConfig.py 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 92f6798..e85d225 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -494,6 +494,7 @@ # Set up the Intel MP table base_entries = [] ext_entries = [] +madt_records = [] for i in range(numCPUs): bp = X86IntelMPProcessor( local_apic_id = i, @@ -501,6 +502,11 @@ enable = True, bootstrap = (i == 0)) base_entries.append(bp) +lapic = X86ACPIMadtLAPIC( +acpi_processor_id=i, +apic_id=i, +flags=1) +madt_records.append(lapic) io_apic = X86IntelMPIOAPIC( id = numCPUs, version = 0x11, @@ -508,6 +514,8 @@ address = 0xfec0) self.pc.south_bridge.io_apic.apic_id = io_apic.id base_entries.append(io_apic) +madt_records.append(X86ACPIMadtIOAPIC(id=io_apic.id, +address=io_apic.address, int_base=0)) # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", # but linux kernel cannot config PCI device if it was not connected to # PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1. @@ -527,6 +535,13 @@ dest_io_apic_id = io_apic.id, dest_io_apic_intin = 16) base_entries.append(pci_dev4_inta) +pci_dev4_inta_madt = X86ACPIMadtIntSourceOverride( +bus_source = pci_dev4_inta.source_bus_id, +irq_source = pci_dev4_inta.source_bus_irq, +sys_int = pci_dev4_inta.dest_io_apic_intin, +flags = 0 +) +madt_records.append(pci_dev4_inta_madt) def assignISAInt(irq, apicPin): assign_8259_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'ExtInt', @@ -546,6 +561,14 @@ dest_io_apic_id = io_apic.id, dest_io_apic_intin = apicPin) base_entries.append(assign_to_apic) +# acpi +assign_to_apic_acpi = X86ACPIMadtIntSourceOverride( +bus_source = 1, +irq_source = irq, +sys_int = apicPin, +flags = 0 +) +madt_records.append(assign_to_apic_acpi) assignISAInt(0, 2) assignISAInt(1, 1) for i in range(3, 15): @@ -553,6 +576,13 @@ workload.intel_mp_table.base_entries = base_entries workload.intel_mp_table.ext_entries = ext_entries +madt = X86ACPIMadt(local_apic_address=0, +records=madt_records, oem_id='madt') +workload.acpi_description_table_pointer.rsdt.entries.append(madt) +workload.acpi_description_table_pointer.xsdt.entries.append(madt) +workload.acpi_description_table_pointer.oem_id = 'gem5' +workload.acpi_description_table_pointer.rsdt.oem_id='gem5' +workload.acpi_description_table_pointer.xsdt.oem_id='gem5' return self def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42825 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie3d293aac0925666f7661a03eab10218f04c8d0c Gerrit-Change-Number: 42825 Gerrit-PatchSet: 11 Gerrit-Owner: Maximilian Stein Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Maximilian Stein Gerrit-Reviewer: kokoro Gerrit-CC: Bobby R. Bruce Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for DS form instructions
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40891 ) Change subject: arch-power: Add fields for DS form instructions .. arch-power: Add fields for DS form instructions This introduces the DS field used by DS form instructions which specifies a signed integer immediate operand. Change-Id: I0e7a77e7a63fce4e50b7941850c277f556e65724 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40891 Reviewed-by: Boris Shingarov Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/arch/power/types.hh 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index 72dcd1e..1e896e4 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -52,6 +52,7 @@ // Immediate fields Bitfield<15, 0> si; Bitfield<15, 0> d; +Bitfield<15, 2> ds; // Special purpose register identifier Bitfield<20, 11> spr; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40891 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0e7a77e7a63fce4e50b7941850c277f556e65724 Gerrit-Change-Number: 40891 Gerrit-PatchSet: 6 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix precedence of register operands
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40890 )
Change subject: arch-power: Fix precedence of register operands
..
arch-power: Fix precedence of register operands
When RS and RA are both used as operands by an instruction,
RS takes precedence over RA. In such cases, either both the
register operands are used as sources or RS is a source and
RA is a destination.
This changes the order by giving RS the highest precedence
and will be useful for proper disassembly generation.
Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40890
Reviewed-by: Boris Shingarov
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/isa/operands.isa
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index 23cf50b..8cb39eb 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -41,9 +41,9 @@
def operands {{
# General Purpose Integer Reg Operands
-'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
-'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
-'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
+'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
+'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
+'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
# General Purpose Floating Point Reg Operands
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40890
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Gerrit-Change-Number: 40890
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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