[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Fix building with Fast Model.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46120 )
Change subject: fastmodel: Fix building with Fast Model.
..
fastmodel: Fix building with Fast Model.
Some build errors had crept in over time. This change fixes them.
Change-Id: I457d32190aa65b0ecd2d6de3f4f5d42d922ae5d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46120
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
7 files changed, 36 insertions(+), 22 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 43510e6..98c2922 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -28,6 +28,7 @@
#include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
+#include "arch/arm/regs/misc.hh"
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
#include "sim/core.hh"
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc
b/src/arch/arm/fastmodel/GIC/gic.cc
index 3133757..2830c83 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -70,7 +70,7 @@
SCGIC::SCGIC(const SCFastModelGICParams ,
sc_core::sc_module_name _name)
-: scx_evs_GIC(_name)
+: scx_evs_GIC(_name), _params(params)
{
signalInterrupt.bind(signal_interrupt);
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh
b/src/arch/arm/fastmodel/GIC/gic.hh
index 33997fd..b283108 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -81,6 +81,7 @@
};
std::unique_ptr terminator;
+const SCFastModelGICParams &_params;
public:
SCGIC(const SCFastModelGICParams ) : SCGIC(p, p.name.c_str()) {}
diff --git a/src/arch/arm/fastmodel/iris/isa.cc
b/src/arch/arm/fastmodel/iris/isa.cc
index 4aac71f..9312d4e 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -28,8 +28,8 @@
#include "arch/arm/fastmodel/iris/isa.hh"
#include "arch/arm/regs/misc.hh"
+#include "base/logging.hh"
#include "cpu/thread_context.hh"
-#include "params/IrisISA.hh"
#include "sim/serialize.hh"
void
@@ -40,3 +40,9 @@
miscRegs[i] = tc->readMiscRegNoEffect(i);
SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS);
}
+
+void
+Iris::ISA::copyRegsFrom(ThreadContext *src)
+{
+panic("copyRegsFrom not implemented");
+}
diff --git a/src/arch/arm/fastmodel/iris/isa.hh
b/src/arch/arm/fastmodel/iris/isa.hh
index a7ae7b5..9b2828c 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -39,13 +39,15 @@
public:
ISA(const Params ) : BaseISA(p) {}
-void serialize(CheckpointOut ) const;
+void serialize(CheckpointOut ) const override;
+
+void copyRegsFrom(ThreadContext *src) override;
bool
inUserMode() const override
{
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-return ::inUserMode(cpsr);
+ArmISA::CPSR cpsr = tc->readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
+return ArmISA::inUserMode(cpsr);
}
};
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 2392592..0219ab5 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -670,7 +670,7 @@
call().resource_read(_instId, result, vecRegIds.at(idx));
size_t data_size = result.data.size() * (sizeof(*result.data.data()));
size_t size = std::min(data_size, reg.size());
-memcpy(reg.raw_ptr(), (void *)result.data.data(), size);
+memcpy(reg.as(), (void *)result.data.data(), size);
return reg;
}
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 5c8d82f..22ea42b 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -32,6 +32,7 @@
#include
#include
+#include "arch/arm/regs/vec.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "iris/IrisInstance.h"
@@ -276,21 +277,22 @@
panic("%s not implemented.", __FUNCTION__);
}
-const VecRegContainer (const RegId ) const override;
-VecRegContainer &
+const ArmISA::VecRegContainer (const RegId ) const
override;
+ArmISA::VecRegContainer &
getWritableVecReg(const RegId ) override
{
panic("%s not
[gem5-dev] Change in gem5/gem5[develop]: sim: Make SEWorkload an abstract SimObject
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46379 ) Change subject: sim: Make SEWorkload an abstract SimObject .. sim: Make SEWorkload an abstract SimObject As far as I can tell, each ISA must subclass the SEWorkload anyway. By not being abstract, the params system automatically adds a create() function that should never be used and can conflict with TheISA::SEWorkload. Change-Id: I971a52fb63c3e0bf287f3761706cda34dc9cf931 Signed-off-by: Jason Lowe-Power --- M src/sim/Workload.py 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/src/sim/Workload.py b/src/sim/Workload.py index 91c1c55..e957de6 100644 --- a/src/sim/Workload.py +++ b/src/sim/Workload.py @@ -65,6 +65,7 @@ type = 'SEWorkload' cxx_header = "sim/se_workload.hh" cxx_class = 'SEWorkload' +abstract = True @classmethod def _is_compatible_with(cls, obj): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46379 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I971a52fb63c3e0bf287f3761706cda34dc9cf931 Gerrit-Change-Number: 46379 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Put all Params::create funcs in one file
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46380 )
Change subject: scons: Put all Params::create funcs in one file
..
scons: Put all Params::create funcs in one file
The automatic generation of the params' create functions is causing GCC
linking errors on debug builds. The problem is that many of the .o files
are much larger than 1MB, and when there are 100s of 10-20MB files to
link, GCC cannot include debug symbols within a 32 bit offset.
The underlying issue seems to be that there are many header files which
include inline functions and they are replicated in the .o files.
Instead of moving code around in many files hoping to accidentally fix
the issue (this seemed to have happened recently on develop), this
change instead makes sure that all of the headers are only included in a
single .o file by grouping all of the create() functions in a single
file.
In the future, we should probably revisit how we are automatically
creating the create functions. See the linked issue below for more
details.
Change-Id: I45cd47e0027c72922cd65466f58e962d8bc46797
Issue-on: https://gem5.atlassian.net/browse/GEM5-1003
Signed-off-by: Jason Lowe-Power
---
M src/SConscript
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index cc51b9f..c671f27 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -986,6 +986,7 @@
obj.cxx_param_decl(code)
code.write(target[0].abspath)
+# Note: This function is unused because of the hack below.
def createSimObjectParamDef(target, source, env):
assert len(target) == 1 and len(source) == 1
@@ -996,6 +997,16 @@
obj.cxx_param_def(code)
code.write(target[0].abspath)
+# This function puts all of the create() parameter implementations in a
single
+# file to get around GCC's limit on the size of the debug symbols in the
+# linking stage.
+def createAllSimObjectParamDef(target, source, env):
+code = code_formatter()
+for name,simobj in sorted(sim_objects.items()):
+if not getattr(simobj, 'abstract', False) and
hasattr(simobj, 'type'):
+simobj.cxx_param_def(code)
+code.write(target[0].abspath)
+
def createSimObjectCxxConfig(is_header):
def body(target, source, env):
assert len(target) == 1 and len(source) == 1
@@ -1041,6 +1052,7 @@
# Generate all of the SimObject param C++ struct header files
params_hh_files = []
+all_deps = []
for name,simobj in sorted(sim_objects.items()):
# If this simobject's source changes, we need to regenerate the header.
py_source = PySource.modules[simobj.__module__]
@@ -1060,11 +1072,26 @@
env.Depends(hh_file, depends + extra_deps)
if not getattr(simobj, 'abstract', False) and hasattr(simobj, 'type'):
-cc_file = File('params/%s.cc' % name)
-env.Command(cc_file, Value(name),
-MakeAction(createSimObjectParamDef,
Transform("SOPARMCC")))
-env.Depends(cc_file, depends + extra_deps)
-Source(cc_file)
+# NOTE: The code below will create one cc file for each param.
However,
+# this results in many MB+ object files that when linked
causes
+# GCC to die in many cases. TODO: Find a better solution to
this
+# bug. See GEM5-1003.
+# cc_file = File('params/%s.cc' % name)
+# env.Command(cc_file, Value(name),
+# MakeAction(createSimObjectParamDef,
+#Transform("SOPARMCC")))
+# env.Depends(cc_file, depends + extra_deps)
+# Source(cc_file)
+all_deps += extra_deps
+
+# Create a single large cc file for all of the create() functions. This is
+# needed so that there is only one large object file instead of 100s when
each
+# param has it's own cc file. See GEM5-1003.
+params_cc_file = File('params/create_functions.cc')
+env.Command(params_cc_file, Value('create_functions'),
+MakeAction(createAllSimObjectParamDef, Transform('SOPARMCC')))
+env.Depends(params_cc_file, depends + all_deps)
+Source(params_cc_file)
# C++ parameter description files
if GetOption('with_cxx_config'):
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46380
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I45cd47e0027c72922cd65466f58e962d8bc46797
Gerrit-Change-Number: 46380
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: mem-ruby: replace desks, add desc where required
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46179 )
Change subject: mem-ruby: replace desks, add desc where required
..
mem-ruby: replace desks, add desc where required
Events in *.sm are required to have "desc" defined.
JIRA: https://gem5.atlassian.net/browse/GEM5-999
Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46119
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
(cherry picked from commit 5c34457a3839466367e6ccfd1abde2fa01062fe0)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46179
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
DMA_WRITE_PARTIAL, desc="DMA Write partial line";
DMA_ACK, desc="DMA Ack";
Data, desc="Data to directory";
-All_Acks, desk="All pending acks, unblocks, etc have been
received";
+All_Acks, desc="All pending acks, unblocks, etc have been
received";
}
// TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm
b/src/mem/ruby/protocol/chi/CHI-cache.sm
index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
state_declaration(State, default="Cache_State_null") {
// Stable states
-I, AccessPermission:Invalid,desk="Invalid / not present locally or
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or
upstream";
// States when block is present in local cache only
SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
UD_T, AccessPermission:Read_Write, desc="UD with use timeout";
// Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid, desk="Upstream requester has line in
UD/UC";
-RSC, AccessPermission:Invalid, desk="Upstream requester has line in
SC";
-RSD, AccessPermission:Invalid, desk="Upstream requester has line in
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has
exclusive access";
+RU, AccessPermission:Invalid, desc="Upstream requester has line in
UD/UC";
+RSC, AccessPermission:Invalid, desc="Upstream requester has line in
SC";
+RSD, AccessPermission:Invalid, desc="Upstream requester has line in
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has
exclusive access";
// Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write, desk="UC + RSC";
-UC_RU, AccessPermission:Invalid, desk="UC + RU";
-UD_RU, AccessPermission:Invalid, desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write, desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write, desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write, desc="UC + RSC";
+UC_RU, AccessPermission:Invalid, desc="UC + RU";
+UD_RU, AccessPermission:Invalid, desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write, desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write, desc="UD + RSC";
// Generic transient state
// There is only a transient "BUSY" state. The actions taken at this
state
@@ -261,90 +261,90 @@
// Events triggered by sequencer requests or snoops in the rdy queue
// See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-
[gem5-dev] Change in gem5/gem5[develop]: configs: fix se.py error when using "--redirects"
Hoa Nguyen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46099 ) Change subject: configs: fix se.py error when using "--redirects" .. configs: fix se.py error when using "--redirects" Currently, the workload is initialized before host filesystem redirections take place (i.e. before --redirects is taken into account). This change moves the initialization of the workload to the place where the redirections have taken place. JIRA: https://gem5.atlassian.net/browse/GEM5-1001 Change-Id: Id8f4c8486b4e0adb19ccc25d02d0c28cbf671063 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46099 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M configs/example/se.py 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/example/se.py b/configs/example/se.py index 891dd72..65acf6a 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -166,8 +166,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)], mem_mode = test_mem_mode, mem_ranges = [AddrRange(args.mem_size)], -cache_line_size = args.cacheline_size, -workload = SEWorkload.init_compatible(mp0_path)) +cache_line_size = args.cacheline_size) if numThreads > 1: system.multi_thread = True @@ -262,6 +261,8 @@ MemConfig.config_mem(args, system) config_filesystem(system, args) +system.workload = SEWorkload.init_compatible(mp0_path) + if args.wait_gdb: for cpu in system.cpu: cpu.wait_for_remote_gdb = True -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46099 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id8f4c8486b4e0adb19ccc25d02d0c28cbf671063 Gerrit-Change-Number: 46099 Gerrit-PatchSet: 5 Gerrit-Owner: Hoa Nguyen Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-CC: Bobby R. Bruce Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-dram: Kick refresh on rank after each response
Patrick Sheridan has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46339 )
Change subject: mem-dram: Kick refresh on rank after each response
..
mem-dram: Kick refresh on rank after each response
Currently the MemCtrl::processRespondEvent calls dram->checkRefreshState
only if respQueue is empty.
This causes an issue in a multi-rank DRAM device if a rank is waiting for a
refresh but the mem_pkt for that rank
is not the last one in the respQueue. This change will call
checkRefreshState for every mem_pkt, and adds an
additional check in checkRefreshState so that if oustandingEvents > 1, it
does not start the refresh.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1005
Change-Id: Id6160ec4e9429b4317b26d81283ec5d0688583a7
---
M src/mem/mem_ctrl.cc
M src/mem/mem_interface.cc
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index f663fa7..1e139de 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -535,12 +535,14 @@
DPRINTF(Drain, "Controller done draining\n");
signalDrainDone();
-} else if (mem_pkt->isDram()) {
+}
+}
+
+if (mem_pkt->isDram() && drainState() != DrainState::Draining) {
// check the refresh state and kick the refresh event loop
// into action again if banks already closed and just waiting
// for read to complete
dram->checkRefreshState(mem_pkt->rank);
-}
}
// We have made a location in the queue available at this point,
diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index 2a2ae18..7073069 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -989,7 +989,8 @@
Rank& rank_ref = *ranks[rank];
if ((rank_ref.refreshState == REF_PRE) &&
-!rank_ref.prechargeEvent.scheduled()) {
+!rank_ref.prechargeEvent.scheduled() &&
+rank_ref.outstandingEvents == 1) {
// kick the refresh event loop into action again if banks already
// closed and just waiting for read to complete
schedule(rank_ref.refreshEvent, curTick());
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id6160ec4e9429b4317b26d81283ec5d0688583a7
Gerrit-Change-Number: 46339
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Sheridan
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Adopt the gem5 namespace
Daniel Carvalho has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46323 ) Change subject: misc: Adopt the gem5 namespace .. misc: Adopt the gem5 namespace Apply the gem5 namespace to the codebase. Some anonymous namespaces could theoretically be removed, but since this change's main goal was to keep conflicts at a minimum, it was decided not to modify much the general shape of the files. A few missing comments of the form "// namespace X" that occurred before the newly added "} // namespace gem5" have been added for consistency. Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d Signed-off-by: Daniel R. Carvalho --- M src/SConscript M src/arch/amdgpu/gcn3/decoder.cc M src/arch/amdgpu/gcn3/gpu_decoder.hh M src/arch/amdgpu/gcn3/gpu_isa.hh M src/arch/amdgpu/gcn3/gpu_mem_helpers.hh M src/arch/amdgpu/gcn3/gpu_registers.hh M src/arch/amdgpu/gcn3/gpu_types.hh M src/arch/amdgpu/gcn3/insts/gpu_static_inst.cc M src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh M src/arch/amdgpu/gcn3/insts/inst_util.hh M src/arch/amdgpu/gcn3/insts/instructions.cc M src/arch/amdgpu/gcn3/insts/instructions.hh M src/arch/amdgpu/gcn3/insts/op_encodings.cc M src/arch/amdgpu/gcn3/insts/op_encodings.hh M src/arch/amdgpu/gcn3/isa.cc M src/arch/amdgpu/gcn3/operand.hh M src/arch/amdgpu/gcn3/registers.cc M src/arch/amdgpu/vega/decoder.cc M src/arch/amdgpu/vega/gpu_decoder.hh M src/arch/amdgpu/vega/gpu_isa.hh M src/arch/amdgpu/vega/gpu_mem_helpers.hh M src/arch/amdgpu/vega/gpu_registers.hh M src/arch/amdgpu/vega/gpu_types.hh M src/arch/amdgpu/vega/insts/gpu_static_inst.cc M src/arch/amdgpu/vega/insts/gpu_static_inst.hh M src/arch/amdgpu/vega/insts/inst_util.hh M src/arch/amdgpu/vega/insts/instructions.cc M src/arch/amdgpu/vega/insts/instructions.hh M src/arch/amdgpu/vega/insts/op_encodings.cc M src/arch/amdgpu/vega/insts/op_encodings.hh M src/arch/amdgpu/vega/isa.cc M src/arch/amdgpu/vega/operand.hh M src/arch/amdgpu/vega/registers.cc M src/arch/arm/ArmFsWorkload.py M src/arch/arm/ArmISA.py M src/arch/arm/ArmInterrupts.py M src/arch/arm/ArmMMU.py M src/arch/arm/ArmNativeTrace.py M src/arch/arm/ArmPMU.py M src/arch/arm/ArmSeWorkload.py M src/arch/arm/ArmSemihosting.py M src/arch/arm/ArmSystem.py M src/arch/arm/ArmTLB.py M src/arch/arm/aapcs32.hh M src/arch/arm/aapcs64.hh M src/arch/arm/aapcs64.test.cc M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh M src/arch/arm/fastmodel/CortexA76/evs.cc M src/arch/arm/fastmodel/CortexA76/evs.hh M src/arch/arm/fastmodel/CortexA76/thread_context.cc M src/arch/arm/fastmodel/CortexA76/thread_context.hh M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh M src/arch/arm/fastmodel/CortexR52/evs.cc M src/arch/arm/fastmodel/CortexR52/evs.hh M src/arch/arm/fastmodel/CortexR52/thread_context.cc M src/arch/arm/fastmodel/CortexR52/thread_context.hh M src/arch/arm/fastmodel/FastModel.py M src/arch/arm/fastmodel/GIC/FastModelGIC.py M src/arch/arm/fastmodel/GIC/gic.cc M src/arch/arm/fastmodel/GIC/gic.hh M src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc M src/arch/arm/fastmodel/PL330_DMAC/pl330.hh M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc M src/arch/arm/fastmodel/amba_from_tlm_bridge.hh M src/arch/arm/fastmodel/amba_ports.hh M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh M src/arch/arm/fastmodel/common/signal_receiver.hh M src/arch/arm/fastmodel/fastmodel.cc M src/arch/arm/fastmodel/iris/Iris.py M src/arch/arm/fastmodel/iris/cpu.cc M src/arch/arm/fastmodel/iris/cpu.hh M src/arch/arm/fastmodel/iris/interrupts.cc M src/arch/arm/fastmodel/iris/interrupts.hh M src/arch/arm/fastmodel/iris/isa.cc M src/arch/arm/fastmodel/iris/isa.hh M src/arch/arm/fastmodel/iris/memory_spaces.hh M src/arch/arm/fastmodel/iris/mmu.hh M src/arch/arm/fastmodel/iris/thread_context.cc M src/arch/arm/fastmodel/iris/thread_context.hh M src/arch/arm/fastmodel/iris/tlb.cc M src/arch/arm/fastmodel/iris/tlb.hh M src/arch/arm/fastmodel/protocol/exported_clock_rate_control.hh M src/arch/arm/fastmodel/protocol/signal_interrupt.hh M src/arch/arm/faults.cc M src/arch/arm/faults.hh M src/arch/arm/freebsd/freebsd.cc M src/arch/arm/freebsd/freebsd.hh M src/arch/arm/freebsd/fs_workload.cc M src/arch/arm/freebsd/fs_workload.hh M src/arch/arm/freebsd/se_workload.cc M src/arch/arm/freebsd/se_workload.hh M src/arch/arm/fs_workload.cc M src/arch/arm/fs_workload.hh M src/arch/arm/htm.cc M src/arch/arm/htm.hh M src/arch/arm/insts/branch.cc M src/arch/arm/insts/branch.hh M src/arch/arm/insts/branch64.cc M src/arch/arm/insts/branch64.hh M src/arch/arm/insts/crypto.cc M src/arch/arm/insts/crypto.hh M
[gem5-dev] Change in gem5/gem5[develop]: python: Fix include of pybind
Daniel Carvalho has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46319 ) Change subject: python: Fix include of pybind .. python: Fix include of pybind The included file was not the correct one to get the macro from, but the macro will use the original file included. Change-Id: I612f0d0b291cc2da8668c60471b7b78c7967ea5b Signed-off-by: Daniel R. Carvalho --- M src/python/pybind11/core.hh 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/src/python/pybind11/core.hh b/src/python/pybind11/core.hh index 4fc9cc0..33562e8 100644 --- a/src/python/pybind11/core.hh +++ b/src/python/pybind11/core.hh @@ -38,6 +38,7 @@ #ifndef __PYTHON_PYBIND11_CORE_HH__ #define __PYTHON_PYBIND11_CORE_HH__ +#include "pybind11/cast.h" #include "pybind11/stl_bind.h" #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46319 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I612f0d0b291cc2da8668c60471b7b78c7967ea5b Gerrit-Change-Number: 46319 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Carvalho Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Adopt the gem5 namespace in the ISA files
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46327 )
Change subject: arch: Adopt the gem5 namespace in the ISA files
..
arch: Adopt the gem5 namespace in the ISA files
Make the necessary modifications to support the gem5
namespace in the ISA files.
The .isa files currently limited to a single namespace.
This limitation should be later removed to make it
easier to accomodate a better API.
Change-Id: Ibd2c5ba936b7fcc4b97e7db7b161c0755b6b9872
Signed-off-by: Daniel R. Carvalho
---
M src/arch/amdgpu/gcn3/ast_interpreter.py
M src/arch/arm/isa/includes.isa
M src/arch/isa_parser/isa_parser.py
M src/arch/mips/isa/includes.isa
M src/arch/power/isa/includes.isa
M src/arch/riscv/isa/includes.isa
M src/arch/sparc/isa/includes.isa
M src/arch/x86/isa/includes.isa
8 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/src/arch/amdgpu/gcn3/ast_interpreter.py
b/src/arch/amdgpu/gcn3/ast_interpreter.py
index 6bd035c..8a7bfc7 100644
--- a/src/arch/amdgpu/gcn3/ast_interpreter.py
+++ b/src/arch/amdgpu/gcn3/ast_interpreter.py
@@ -1479,6 +1479,9 @@
cg.cg_include('gpu-internal/arch/vi/gpu_types.hh')
cg.cg_newline()
+cg.cg_namespace('gem5')
+cg.cg_newline()
+
cg.cg_code('class GPUStaticInst;')
cg.cg_newline()
@@ -1559,6 +1562,7 @@
cg.cg_end('union InstFormat') # cg_union
cg.cg_end('namespace ViISA') # cg_namespace
+cg.cg_end('namespace gem5') # cg_namespace
cg.cg_newline()
cg.cg_code('#endif // __GPU_INTERNAL_ARCH_VI_DECODER_HH__')
@@ -1577,6 +1581,7 @@
cg.cg_include('gpu-internal/arch/vi/instructions.hh')
cg.cg_newline()
+cg.cg_namespace('gem5')
cg.cg_namespace('ViISA')
cg.cg_method(None, 'Decoder', 'Decoder', [], [])
@@ -1652,6 +1657,7 @@
cg.cg_newline()
cg.cg_end('namespace ViISA') # cg_namespace
+cg.cg_end('namespace gem5') # cg_namespace
cg.generate()
@@ -1669,6 +1675,7 @@
cg.cg_include('gpu-internal/arch/vi/op_encodings.hh')
cg.cg_newline()
+cg.cg_namespace('gem5')
cg.cg_namespace('ViISA')
for info in self.refined_op_info:
@@ -1902,6 +1909,7 @@
cg.cg_end(op_inst) # cg_class
cg.cg_end('namespace ViISA') # cg_namespace
+cg.cg_end('namespace gem5') # cg_namespace
cg.cg_code('#endif // __GPU_INTERNAL_ARCH_VI_INSTRUCTIONS_HH__')
cg.generate()
@@ -2746,6 +2754,7 @@
cg.cg_include('gpu-internal/arch/vi/inst_util.hh')
cg.cg_newline()
+cg.cg_namespace('gem5')
cg.cg_namespace('ViISA')
instruction_index = 0
@@ -2884,6 +2893,7 @@
cg.cg_end('isValid') # cg_method
cg.cg_end('namespace ViISA') # cg_namespace
+cg.cg_end('namespace gem5') # cg_namespace
cg.generate()
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index a09655b..3ec3e65 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -70,10 +70,13 @@
#include "mem/packet.hh"
#include "sim/faults.hh"
+namespace gem5
+{
namespace ArmISAInst
{
using namespace ArmISA;
-}
+} // namespace ArmISAInst
+} // namespace gem5
}};
@@ -91,6 +94,7 @@
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
+using namespace gem5;
using namespace ArmISA;
}};
@@ -116,6 +120,7 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
+using namespace gem5;
using namespace ArmISA;
}};
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index bfe9c91..9cfd5ba 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -606,8 +606,10 @@
fn = 'decoder-ns.hh.inc'
assert(fn in self.files)
-f.write('namespace %s {\n#include "%s"\n}\n'
-% (self.namespace, fn))
+f.write('namespace gem5\n{\n')
+f.write('namespace %s {\n#include "%s"\n} // namespace %s\n'
+% (self.namespace, fn, self.namespace))
+f.write('} // namespace gem5')
f.write('\n#endif // __ARCH_%s_GENERATED_DECODER_HH__\n' %
self.isa_name.upper())
@@ -648,11 +650,13 @@
fn = 'decoder-ns.cc.inc'
assert(fn in self.files)
+print('namespace gem5\n{\n', file=f)
print('namespace %s {' % self.namespace, file=f)
if splits > 1:
print('#define __SPLIT %u' % i, file=f)
print('#include "%s"' % fn, file=f)
-print('}', file=f)
+print('} // namespace %s' % self.namespace, file=f)
+print('} // namespace gem5', file=f)
# instruction execution
splits = self.splits[self.get_file('exec')]
[gem5-dev] Change in gem5/gem5[develop]: RFC,dev,sim: Fix compiler not finding specialized byte_swap
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46322 )
Change subject: RFC,dev,sim: Fix compiler not finding specialized byte_swap
..
RFC,dev,sim: Fix compiler not finding specialized byte_swap
The specialized version of byte_swap cannot be found by
the compiler. As a temporary workaround to get the major
patch going, move the specialization to the base header
file.
Change-Id: I7d2bfc1c29b70042860ae06cdc043c0490cd8916
Signed-off-by: Daniel R. Carvalho
---
M src/dev/virtio/base.hh
M src/sim/byteswap.hh
2 files changed, 40 insertions(+), 37 deletions(-)
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index 350e510..074f085 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -55,40 +55,6 @@
class VirtQueue;
-/** @{
- * @name VirtIO endian conversion helpers
- *
- * VirtIO prior to version 1.0 (legacy versions) normally send values
- * to the host in the guest systems native byte order. This is going
- * to change in version 1.0 which mandates little endian. We currently
- * only support the legacy version of VirtIO (the new and shiny
- * standard is still in a draft state and not implemented by the
- * kernel). Once we support the new standard, we should negotiate the
- * VirtIO version with the guest and automatically use the right type
- * of byte swapping.
- */
-
-
-static inline vring_used_elem
-swap_byte(vring_used_elem v)
-{
-v.id = swap_byte(v.id);
-v.len = swap_byte(v.len);
-return v;
-}
-
-static inline vring_desc
-swap_byte(vring_desc v)
-{
-v.addr = swap_byte(v.addr);
-v.len = swap_byte(v.len);
-v.flags = swap_byte(v.flags);
-v.next = swap_byte(v.next);
-return v;
-}
-
-/** @} */
-
/**
* VirtIO descriptor (chain) wrapper
*
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 30e63d1..fd07e0c 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -33,9 +33,6 @@
#ifndef __SIM_BYTE_SWAP_HH__
#define __SIM_BYTE_SWAP_HH__
-#include "base/types.hh"
-#include "enums/ByteOrder.hh"
-
// This lets us figure out what the byte order of the host system is
#if defined(__linux__)
#include
@@ -55,6 +52,10 @@
#include
+#include "base/types.hh"
+#include "dev/virtio/virtio_ring.h"
+#include "enums/ByteOrder.hh"
+
// These functions actually perform the swapping for parameters of various
bit
// lengths.
inline uint64_t
@@ -144,6 +145,42 @@
return a;
}
+/** @{
+ * @name VirtIO endian conversion helpers
+ *
+ * VirtIO prior to version 1.0 (legacy versions) normally send values
+ * to the host in the guest systems native byte order. This is going
+ * to change in version 1.0 which mandates little endian. We currently
+ * only support the legacy version of VirtIO (the new and shiny
+ * standard is still in a draft state and not implemented by the
+ * kernel). Once we support the new standard, we should negotiate the
+ * VirtIO version with the guest and automatically use the right type
+ * of byte swapping.
+ */
+
+
+template
+inline std::enable_if_t::value, T>
+swap_byte(T v)
+{
+v.id = swap_byte(v.id);
+v.len = swap_byte(v.len);
+return v;
+}
+
+template
+inline std::enable_if_t::value, T>
+swap_byte(T v)
+{
+v.addr = swap_byte(v.addr);
+v.len = swap_byte(v.len);
+v.flags = swap_byte(v.flags);
+v.next = swap_byte(v.next);
+return v;
+}
+
+/** @} */
+
//The conversion functions with fixed endianness on both ends don't need to
//be in a namespace
template inline T betole(T value) {return swap_byte(value);}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46322
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7d2bfc1c29b70042860ae06cdc043c0490cd8916
Gerrit-Change-Number: 46322
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Adopt the gem5 namespace in generated files
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46328 )
Change subject: misc: Adopt the gem5 namespace in generated files
..
misc: Adopt the gem5 namespace in generated files
Adopt the gem5 namespace in the files that are
automatically generated.
Change-Id: Ie7b1204f3518ff3cd2c14798b10e983965176d4b
Signed-off-by: Daniel R. Carvalho
---
M src/SConscript
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
M src/python/m5/SimObject.py
M src/python/m5/params.py
M util/cpt_upgrader.py
6 files changed, 136 insertions(+), 29 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index b1aa8bf..10f9a25 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1312,7 +1312,10 @@
code('''\
#include "sim/init.hh"
-namespace {
+namespace gem5
+{
+namespace
+{
''')
blobToCpp(data, 'data_' + sym, code)
@@ -1328,6 +1331,7 @@
${{len(marshalled)}});
} // anonymous namespace
+} // namespace gem5
''')
code.write(str(target[0]))
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 77c999d..827835d 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -244,6 +244,7 @@
class $py_ident(RubyController):
type = '$py_ident'
cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
+cxx_class = 'gem5::$py_ident'
''')
code.indent()
for param in self.config_parameters:
@@ -301,6 +302,9 @@
# for adding information to the protocol debug trace
code('''
+namespace gem5
+{
+
extern std::stringstream ${ident}_transitionComment;
class $c_ident : public AbstractController
@@ -455,8 +459,14 @@
code('${{var.type.c_ident}}$th* m_${{var.ident}}_ptr;')
code.dedent()
-code('};')
-code('#endif // __${ident}_CONTROLLER_H__')
+code('''
+};
+
+} // namespace gem5
+
+#endif // __${ident}_CONTROLLER_H__
+''')
+
code.write(path, '%s.hh' % c_ident)
def printControllerCC(self, path, includes):
@@ -535,6 +545,9 @@
num_in_ports = len(self.in_ports)
code('''
+namespace gem5
+{
+
int $c_ident::m_num_controllers = 0;
std::vector $c_ident::eventVec;
std::vector > $c_ident::transVec;
@@ -1205,6 +1218,8 @@
code('''
return read;
}
+
+} // namespace gem5
''')
code.write(path, "%s.cc" % c_ident)
@@ -1257,6 +1272,8 @@
port_to_buf_map, in_msg_bufs, msg_bufs = self.getBufferMaps(ident)
code('''
+namespace gem5
+{
void
${ident}_Controller::wakeup()
@@ -1332,6 +1349,8 @@
break;
}
}
+
+} // namespace gem5
''')
code.write(path, "%s_Wakeup.cc" % self.ident)
@@ -1363,6 +1382,9 @@
#define GET_TRANSITION_COMMENT() (${ident}_transitionComment.str())
#define CLEAR_TRANSITION_COMMENT() (${ident}_transitionComment.str(""))
+namespace gem5
+{
+
TransitionResult
${ident}_Controller::doTransition(${ident}_Event event,
''')
@@ -1590,6 +1612,8 @@
return TransitionResult_Valid;
}
+
+} // namespace gem5
''')
code.write(path, "%s_Transitions.cc" % self.ident)
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index da6460b..b10e583 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -228,6 +228,11 @@
code('#include "mem/ruby/protocol/$0.hh"', self["interface"])
parent = " : public %s" % self["interface"]
+code('')
+code('namespace gem5')
+code('{')
+code('')
+
code('''
$klass ${{self.c_ident}}$parent
{
@@ -387,14 +392,16 @@
code('};')
code('''
-inline std::ostream&
-operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
+inline ::std::ostream&
+operator<<(::std::ostream& out, const ${{self.c_ident}}& obj)
{
obj.print(out);
-out << std::flush;
+out << ::std::flush;
return out;
}
+} // namespace gem5
+
#endif // __${{self.c_ident}}_HH__
''')
@@ -416,6 +423,11 @@
#include "mem/ruby/system/RubySystem.hh"
''')
+code('')
+code('namespace gem5')
+code('{')
+code('')
+
code('''
/** \\brief Print the state of this object */
void
@@ -444,6 +456,10 @@
for item in self.methods:
code(self.methods[item].generateCode())
+code('')
+code('} // namespace gem5')
+code('')
+
code.write(path, "%s.cc" % self.c_ident)
def printEnumHH(self, path):
@@ -469,6 +485,13 @@
code('#include "base/logging.hh"')
code('#include "mem/ruby/common/Address.hh"')
code('#include "mem/ruby/common/TypeDefines.hh"')
+
+code('')
+code('namespace gem5')
+code('{')
+code('')
+
+if self.isMachineType:
code('struct MachineID;')
code('''
@@ -496,30 +519,15 @@
};
[gem5-dev] Change in gem5/gem5[develop]: misc: Move namespace std out of namespace gem5
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46324 )
Change subject: misc: Move namespace std out of namespace gem5
..
misc: Move namespace std out of namespace gem5
These included in the gem5 namespace, but they shouldn't
be.
Change-Id: Ic52886395420871a5b965f426d6c5871d8fef141
Signed-off-by: Daniel R. Carvalho
---
M src/arch/power/types.hh
M src/arch/x86/types.hh
M src/base/bitunion.hh
M src/base/channel_addr.hh
M src/cpu/reg_class.hh
M src/cpu/simple/probes/simpoint.hh
M src/mem/ruby/common/MachineID.hh
M src/sim/futex_map.cc
M src/sim/futex_map.hh
9 files changed, 96 insertions(+), 84 deletions(-)
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index a4437c8..2073f4f 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -91,19 +91,19 @@
// typedef int RegContextParam;
// typedef int RegContextVal;
-} // PowerISA namespace
+} // namespace PowerISA
+} // namespace gem5
namespace std {
template<>
-struct hash : public hash
+struct hash : public hash
{
-size_t operator()(const PowerISA::ExtMachInst ) const {
+size_t operator()(const gem5::PowerISA::ExtMachInst ) const {
return hash::operator()((uint32_t)emi);
};
};
} // namespace std
-} // namespace gem5
#endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 94dfd3e..a2c2771 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -290,16 +290,27 @@
return true;
}
-}
+} // namespace X86ISA
+
+// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
+// and UNSERIALIZE_SCALAR.
+template <>
+void paramOut(CheckpointOut , const std::string ,
+const X86ISA::ExtMachInst );
+template <>
+void paramIn(CheckpointIn , const std::string ,
+X86ISA::ExtMachInst );
+
+} // namespace gem5
namespace std
{
template<>
-struct hash
+struct hash
{
size_t
-operator()(const X86ISA::ExtMachInst ) const
+operator()(const gem5::X86ISA::ExtMachInst ) const
{
return (((uint64_t)emi.legacy << 48) |
((uint64_t)emi.rex << 40) |
@@ -315,17 +326,6 @@
};
};
-}
-
-// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
-// and UNSERIALIZE_SCALAR.
-template <>
-void paramOut(CheckpointOut , const std::string ,
-const X86ISA::ExtMachInst );
-template <>
-void paramIn(CheckpointIn , const std::string ,
-X86ISA::ExtMachInst );
-
-} // namespace gem5
+} // namespace std
#endif // __ARCH_X86_TYPES_HH__
diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index 7e6892a..0ef2695 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -540,21 +540,6 @@
template
using BitUnionBaseType = typename
bitfield_backend::BitUnionBaseType::Type;
-
-//An STL style hash structure for hashing BitUnions based on their base
type.
-namespace std
-{
-template
-struct hash > : public hash >
-{
-size_t
-operator() (const BitUnionType ) const
-{
-return hash >::operator()(val);
-}
-};
-} // namespace std
-
namespace bitfield_backend
{
template
@@ -627,4 +612,18 @@
} // namespace gem5
+//An STL style hash structure for hashing BitUnions based on their base
type.
+namespace std
+{
+template
+struct hash> : public
hash>
+{
+size_t
+operator() (const gem5::BitUnionType ) const
+{
+return hash >::operator()(val);
+}
+};
+} // namespace std
+
#endif // __BASE_BITUNION_HH__
diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 168c8b2..ad60bae 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -195,17 +195,20 @@
ChannelAddr _end;
};
+} // namespace gem5
+
namespace std
{
template<>
-struct hash
+struct hash
{
-typedef ChannelAddr argument_type;
+typedef gem5::ChannelAddr argument_type;
typedef std::size_t result_type;
result_type
-operator()(argument_type const ) const noexcept {
-return std::hash{}(
+operator()(argument_type const ) const noexcept
+{
+return std::hash{}(
static_cast(a));
}
};
@@ -214,8 +217,6 @@
/**
* @ingroup api_channel_addr
*/
-std::ostream <<(std::ostream , const ChannelAddr );
-
-} // namespace gem5
+std::ostream <<(std::ostream , const gem5::ChannelAddr );
#endif // __BASE_CHANNEL_ADDR_HH__
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 2edcc28..eaa2c0e 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -307,19 +307,22 @@
using PhysRegIdPtr = PhysRegId*;
+} // namespace gem5
+
namespace std
{
template<>
-struct hash
+struct hash
{
size_t
-operator()(const RegId& reg_id) const
+operator()(const gem5::RegId& reg_id) const
[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm: Fix missing includes
Daniel Carvalho has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46321 ) Change subject: cpu-kvm: Fix missing includes .. cpu-kvm: Fix missing includes "struct kvm_*" are declared in linux/kvm.h, and were not being included despite being used. Change-Id: I511bad19882450f8ecdd6b5efb687026d0fd94ca Signed-off-by: Daniel R. Carvalho --- M src/cpu/kvm/base.hh M src/cpu/kvm/vm.hh 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh index a19152b..892ec7f 100644 --- a/src/cpu/kvm/base.hh +++ b/src/cpu/kvm/base.hh @@ -38,6 +38,7 @@ #ifndef __CPU_KVM_BASE_HH__ #define __CPU_KVM_BASE_HH__ +#include #include #include diff --git a/src/cpu/kvm/vm.hh b/src/cpu/kvm/vm.hh index 340e6f5..be2d5ba 100644 --- a/src/cpu/kvm/vm.hh +++ b/src/cpu/kvm/vm.hh @@ -39,6 +39,8 @@ #ifndef __CPU_KVM_KVMVM_HH__ #define __CPU_KVM_KVMVM_HH__ +#include + #include #include "base/addr_range.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46321 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I511bad19882450f8ecdd6b5efb687026d0fd94ca Gerrit-Change-Number: 46321 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Carvalho Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Appease compiler with return values
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46320 )
Change subject: mem-ruby: Appease compiler with return values
..
mem-ruby: Appease compiler with return values
Add default values for the cases where gem5 panics to
appease the compiler.
Change-Id: Ib15a63abfb6f1ffed6ce628f52a57388d2173c44
Signed-off-by: Daniel R. Carvalho
---
M src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
M src/mem/slicc/symbols/Type.py
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index aa37cc5..48e3b9d 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -50,10 +50,9 @@
#include "base/logging.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
#include "mem/ruby/common/Address.hh"
+#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
-class DataBlock;
-
class AbstractCacheEntry : public ReplaceableEntry
{
private:
@@ -73,8 +72,15 @@
// The methods below are those called by ruby runtime, add when it
// is absolutely necessary and should all be virtual function.
-virtual DataBlock& getDataBlk()
-{ panic("getDataBlk() not implemented!"); }
+virtual DataBlock&
+getDataBlk()
+{
+panic("getDataBlk() not implemented!");
+
+// Dummy return to appease the compiler
+static DataBlock b;
+return b;
+}
int validBlocks;
virtual int& getNumValidBlocks()
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 7ac77ac..da6460b 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -586,6 +586,7 @@
default:
panic("Unknown state access permission converstion for
${{self.c_ident}}");
}
+return AccessPermission_Invalid;
}
''')
@@ -626,6 +627,7 @@
default:
panic("Invalid range for type ${{self.c_ident}}");
}
+return "-1";
}
// Code to convert from a string to the enumeration
@@ -689,6 +691,7 @@
default:
panic("Invalid range for type ${{self.c_ident}}");
}
+return -1;
}
/** \\brief returns the machine type for each base vector index used by
NetDest
@@ -772,6 +775,7 @@
default:
panic("Invalid range for type ${{self.c_ident}}");
}
+return -1;
}
''')
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46320
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib15a63abfb6f1ffed6ce628f52a57388d2173c44
Gerrit-Change-Number: 46320
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Annotate zero-idiom instructions in ISA parser
Arthur Perais has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46299 )
Change subject: arch-arm: Annotate zero-idiom instructions in ISA parser
..
arch-arm: Annotate zero-idiom instructions in ISA parser
Several Aarch64 instructions are zero-idioms (e.g., eor x0, x1, x1).
This patch annotates the most obvious ones and introduces the
isZeroIdiom() API on StaticInst and DynInst.
Detected idioms are :
and dst, src, 0x0
and dst, xzr, src
and dst, src, xzr
eor dst, src1, src2 with src1 == src2 and src2 not a shifted/extended
register
movz dst, 0x0
CPU may then use this information to perform zero-idiom elimination
at Rename, for instance.
Change-Id: Ib9399f064b9f29f4653c3684b75d19973fcccfd6
---
M src/arch/arm/isa/insts/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/isa_parser/isa_parser.py
M src/cpu/StaticInstFlags.py
M src/cpu/o3/dyn_inst.hh
M src/cpu/static_inst.hh
6 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/isa/insts/aarch64.isa
b/src/arch/arm/isa/insts/aarch64.isa
index fbedf89..1eb328e 100644
--- a/src/arch/arm/isa/insts/aarch64.isa
+++ b/src/arch/arm/isa/insts/aarch64.isa
@@ -36,8 +36,12 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
let {{
-movzCode = 'Dest64 = ((uint64_t)imm1) << imm2;'
-movzIop = ArmInstObjParams("movz", "Movz", "RegImmImmOp", movzCode, [])
+snippet_movz = {}
+snippet_movz['code'] = 'Dest64 = ((uint64_t)imm1) << imm2;'
+snippet_movz['constructor_opt'] = '''
+flags[IsZeroIdiom] = (_imm1 == 0x0);
+'''
+movzIop = ArmInstObjParams("movz", "Movz", "RegImmImmOp",
snippet_movz, [])
header_output += RegImmImmOpDeclare.subst(movzIop)
decoder_output += RegImmImmOpConstructor.subst(movzIop)
exec_output += BasicExecute.subst(movzIop)
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 11df936..8dc05ed 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -96,7 +96,30 @@
''' + code
ccCode = createCcCode64(carryCode64[flagType],
overflowCode64[flagType])
Name = mnem.capitalize() + suffix
-iop = ArmInstObjParams(mnem, Name, base, code)
+
+snippet_mnem = {}
+snippet_mnem['code'] = code
+
+if mnem == 'and':
+ if base == 'DataXImmOp':
+# and rd, rs1, 0x0
+snippet_mnem['constructor_opt'] = '''
+flags[IsZeroIdiom] = _imm == 0x0;
+'''
+ else:
+# and rd, rs1, xzr
+# and rd, xzr, rs2
+snippet_mnem['constructor_opt'] = '''
+flags[IsZeroIdiom] = (_op1 == 31) || (_op2 == 31);
+'''
+elif mnem == 'eor':
+ # eor rd, rs1, rs2 with rs1 == rs2
+ if base == 'DataXSRegOp':
+snippet_mnem['constructor_opt'] = '''
+flags[IsZeroIdiom] = (_op1 == _op2) && (_shiftAmt == 0);
+'''
+
+iop = ArmInstObjParams(mnem, Name, base, snippet_mnem)
iopCc = ArmInstObjParams(mnem + "s", Name + "Cc", base, code +
ccCode)
def subst(iop):
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index bfe9c91..6764af1 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -410,6 +410,9 @@
self.constructor = header + \
self.operands.concatAttrStrings('constructor')
+if 'constructor_opt' in snippets.keys():
+self.constructor = self.constructor +
snippets['constructor_opt']
+
self.flags = self.operands.concatAttrLists('flags')
self.op_class = None
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 4775289..a74198e 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -68,6 +68,10 @@
'IsCall', # Subroutine call.
'IsReturn', # Subroutine return.
+## Rename-optimizations
+
+'IsZeroIdiom', # Is the instruction always producing 0x0
+
'IsSerializing',# Serializes pipeline: won't execute until all
# older instructions have committed.
'IsSerializeBefore',
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 24665a5..f1531d8 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -597,6 +597,7 @@
bool isControl() const { return staticInst->isControl(); }
bool isCall() const { return staticInst->isCall(); }
bool isReturn() const { return staticInst->isReturn(); }
+bool isZeroIdiom()const { return staticInst->isZeroIdiom(); }
bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
bool isCondCtrl()
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Prevent a mistarget from sending execution on an incorrect path
Arthur Perais has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46260 )
Change subject: cpu-o3: Prevent a mistarget from sending execution on an
incorrect path
..
cpu-o3: Prevent a mistarget from sending execution on an incorrect path
This fixes the unlikely but possible following case :
- Assume cond/uncond direct branch A jumping to next branch (PC + 4 in
ARM). From
the point of view of the PCState object, the instruction is not branching
(PCState::branching() will return false since it tests whether nextPC != PC
+ 4 for ARM).
This gets cached in the BTB.
- Assume another cond branch B that is predicted taken but uses the PCState
object of the
first branch A from the BTB due to a partial tag match (BTB is not fully
tagged).
- At decode, the mistarget will be detected because the target given by the
BTB does
not match the target encoded in the instruction B. However, to determine
what PC to send to
fetch, decode looks at inst->pcState().branching(), which returns false
because the PCState
object has PC X, and nextPC X + 4 (ARM case). Therefore, Decode sends the
fallthrough address of branch B, despite it being predicted taken. If the
prediction is
correct, Exec will not realize that the target is wrong since it is the
Decode stage's job.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-947
Change-Id: Ia3b960bb660bdfd3c348988d6532735fa3268990
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46260
Reviewed-by: Nathanael Premillieu
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/o3/decode.cc
1 file changed, 11 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Nathanael Premillieu: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 993ab73..c568f5d 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -290,11 +290,18 @@
toFetch->decodeInfo[tid].squash = true;
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
-toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
+
+// Looking at inst->pcState().branching()
+// may yield unexpected results if the branch
+// was predicted taken but aliased in the BTB
+// with a branch jumping to the next instruction (mistarget)
+// Using PCState::branching() will send execution on the
+// fallthrough and this will not be caught at execution (since
+// branch was correctly predicted taken)
+toFetch->decodeInfo[tid].branchTaken = inst->readPredTaken() |
+ inst->isUncondCtrl();
+
toFetch->decodeInfo[tid].squashInst = inst;
-if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
-toFetch->decodeInfo[tid].branchTaken = true;
-}
InstSeqNum squash_seq_num = inst->seqNum;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46260
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia3b960bb660bdfd3c348988d6532735fa3268990
Gerrit-Change-Number: 46260
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Perais
Gerrit-Reviewer: Arthur Perais
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nathanael Premillieu
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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