[gem5-dev] Change in gem5/gem5[develop]: scons: Switch to c++17.

2021-07-06 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45902 )


Change subject: scons: Switch to c++17.
..

scons: Switch to c++17.

Change-Id: I90d121ab4dbf53f3bd30bcdb5f5101d9c7cdc437
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45902
Reviewed-by: Daniel Carvalho 
Reviewed-by: Bobby R. Bruce 
Maintainer: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 041701f..ca1bc7b 100755
--- a/SConstruct
+++ b/SConstruct
@@ -316,8 +316,8 @@
 main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
  '-Wno-sign-compare', '-Wno-unused-parameter'])

-# We always compile using C++14
-main.Append(CXXFLAGS=['-std=c++14'])
+# We always compile using C++17
+main.Append(CXXFLAGS=['-std=c++17'])

 if sys.platform.startswith('freebsd'):
 main.Append(CCFLAGS=['-I/usr/local/include'])



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I90d121ab4dbf53f3bd30bcdb5f5101d9c7cdc437
Gerrit-Change-Number: 45902
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [JOBS] Postdoctoral researcher in GEM5 simulator

2021-07-06 Thread José Luis Abellán Miguel via gem5-dev 
Dear community,

Please, consider applying to the following link:

https://www.hipeac.net/jobs/12407/postdoctoral-researcher-to-build-next-gen-heterogeneous-computer-architecture-simulator/

For any informal inquiries, please send me an email to this address (
jlabel...@ucam.edu).

Thank you so much!

Best regards,

-- 
José L. Abellán, PhD
*Associate Professor* - Titular Acreditado


*Secretary of the TCIA Doctoral Program
*

*UCAM Universidad Católica de Murcia*
Phone:  +34 968 278 821
Email:jlabel...@ucam.edu
Web:  https://sites.google.com/ucam.edu/jlabellan
Skype:   jlabellan





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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Forward declare kvm_vcpu_init

2021-07-06 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47679 )



Change subject: arch-arm: Forward declare kvm_vcpu_init
..

arch-arm: Forward declare kvm_vcpu_init

Signed-off-by: Giacomo Travaglini 
Change-Id: I6fa5be48498d1a8f9c070e9ded11e8cadd4b89a1
---
M src/arch/arm/kvm/base_cpu.hh
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index ec9e5ad..3b2beb3 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -44,6 +44,7 @@
 #include "dev/arm/base_gic.hh"

 struct kvm_reg_list;
+struct kvm_vcpu_init;

 namespace gem5
 {
@@ -111,7 +112,7 @@
  *
  * @param target CPU type to emulate
  */
-void kvmArmVCpuInit(const struct kvm_vcpu_init );
+void kvmArmVCpuInit(const kvm_vcpu_init );

   private:
 std::unique_ptr tryGetRegList(uint64_t nelem) const;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6fa5be48498d1a8f9c070e9ded11e8cadd4b89a1
Gerrit-Change-Number: 47679
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: No need to copy haveLPAE when switching TLBs

2021-07-06 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46899 )


Change subject: arch-arm: No need to copy haveLPAE when switching TLBs
..

arch-arm: No need to copy haveLPAE when switching TLBs

When calling the TLB::takeOverFrom, there is no need to
copy the fixed haveLPAE variable as it is a system level
parameter (from ArmSystem) and it is assumed to be the same
for all TLBs (even the switched out)

Signed-off-by: Giacomo Travaglini 
Change-Id: I0b010d18ae71e43290f7f76f229c1a231ff42ac0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46899
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/arch/arm/tlb.cc
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bc49aae..a1929a4 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -469,7 +469,6 @@
 /* Make sure we actually have a valid type */
 if (otlb) {
 _attr = otlb->_attr;
-haveLPAE = otlb->haveLPAE;
 directToStage2 = otlb->directToStage2;
 stage2Req = otlb->stage2Req;
 stage2DescReq = otlb->stage2DescReq;

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0b010d18ae71e43290f7f76f229c1a231ff42ac0
Gerrit-Change-Number: 46899
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Forward declare kvm_reg_list

2021-07-06 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47619 )


Change subject: arch-arm: Forward declare kvm_reg_list
..

arch-arm: Forward declare kvm_reg_list

The adoption of the gem5 namespace [1] broke aarch64 builds with
the following error:

build/ARM/arch/arm/kvm/base_cpu.cc:198:22: error: aggregate
'gem5::kvm_reg_list regs_probe' has incomplete type and cannot be
defined

In file included from build/ARM/arch/arm/kvm/base_cpu.cc:38:0:
build/ARM/arch/arm/kvm/base_cpu.hh:115:28: note: forward declaration of
'struct gem5::kvm_reg_list'
 std::unique_ptr tryGetRegList(uint64_t nelem)
const;

Forward declaring the struct defined in linux/kvm.hh (included in source
file) in the global namespace, rather than the gem5 one fixes the
problem

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/46323

Signed-off-by: Giacomo Travaglini 
Change-Id: I96c7d31aa4810edcf98e23cefeaf4895620b6444
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47619
Reviewed-by: Daniel Carvalho 
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/arch/arm/kvm/base_cpu.cc
M src/arch/arm/kvm/base_cpu.hh
2 files changed, 8 insertions(+), 6 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index d7df280..524b410 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -201,10 +201,10 @@

 // Request the actual register list now that we know how many
 // register we need to allocate space for.
-std::unique_ptr regs;
-const size_t size(sizeof(struct kvm_reg_list) +
+std::unique_ptr regs;
+const size_t size(sizeof(kvm_reg_list) +
   regs_probe.n * sizeof(uint64_t));
-regs.reset((struct kvm_reg_list *)operator new(size));
+regs.reset((kvm_reg_list *)operator new(size));
 regs->n = regs_probe.n;
 if (!getRegList(*regs))
 panic("Failed to determine register list size.\n");
@@ -223,7 +223,7 @@
 }

 bool
-BaseArmKvmCPU::getRegList(struct kvm_reg_list ) const
+BaseArmKvmCPU::getRegList(kvm_reg_list ) const
 {
 if (ioctl(KVM_GET_REG_LIST, (void *)) == -1) {
 if (errno == E2BIG) {
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index 81e8596..ec9e5ad 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -43,6 +43,8 @@
 #include "cpu/kvm/base.hh"
 #include "dev/arm/base_gic.hh"

+struct kvm_reg_list;
+
 namespace gem5
 {

@@ -112,7 +114,7 @@
 void kvmArmVCpuInit(const struct kvm_vcpu_init );

   private:
-std::unique_ptr tryGetRegList(uint64_t nelem)  
const;

+std::unique_ptr tryGetRegList(uint64_t nelem) const;

 /**
  * Get a list of registers supported by getOneReg() and setOneReg().
@@ -121,7 +123,7 @@
  * is too small to hold the complete register list (the required
  * size is written to regs.n in this case). True on success.
  */
-bool getRegList(struct kvm_reg_list ) const;
+bool getRegList(kvm_reg_list ) const;

 /**
  * Cached copy of the list of registers supported by KVM

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I96c7d31aa4810edcf98e23cefeaf4895620b6444
Gerrit-Change-Number: 47619
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Add error messages to BloomFilter::Perfect

2021-07-06 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44112 )


Change subject: base: Add error messages to BloomFilter::Perfect
..

base: Add error messages to BloomFilter::Perfect

Warn the user when they use BloomFilter::Perfect's
parameters incorrectly.

Change-Id: Ib493c5f508e47a5f18e43c023755ef960954f5cc
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44112
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/base/filters/BloomFilters.py
M src/base/filters/perfect_bloom_filter.cc
2 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/filters/BloomFilters.py  
b/src/base/filters/BloomFilters.py

index 02d2052..7832f47 100644
--- a/src/base/filters/BloomFilters.py
+++ b/src/base/filters/BloomFilters.py
@@ -98,3 +98,8 @@

 # The base filter is not needed. Use a dummy value.
 size = 1
+
+# This filter does not use saturating counters - as long as the entry  
is

+# set, it is present; thus, it only needs one bit.
+num_bits = 1
+threshold = 1
diff --git a/src/base/filters/perfect_bloom_filter.cc  
b/src/base/filters/perfect_bloom_filter.cc

index 0424ddc..7583a1a 100644
--- a/src/base/filters/perfect_bloom_filter.cc
+++ b/src/base/filters/perfect_bloom_filter.cc
@@ -28,6 +28,7 @@

 #include "base/filters/perfect_bloom_filter.hh"

+#include "base/logging.hh"
 #include "params/BloomFilterPerfect.hh"

 namespace gem5
@@ -40,6 +41,12 @@
 Perfect::Perfect(const BloomFilterPerfectParams )
 : Base(p)
 {
+fatal_if(p.size != 1, "The perfect Bloom filter cannot be limited to  
a "

+"specific size.");
+fatal_if(p.num_bits != 1, "The perfect Bloom filter tracks entries "
+"perfectly using an unlimited amount of 1-bit entries.");
+fatal_if(p.threshold != 1, "The perfect Bloom filter uses 1-bit  
entries; "

+"thus, their thresholds must be 1.");
 }

 Perfect::~Perfect()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib493c5f508e47a5f18e43c023755ef960954f5cc
Gerrit-Change-Number: 44112
Gerrit-PatchSet: 9
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove sim/cur_tick dependency from sim/core.hh

2021-07-06 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/43592 )


Change subject: misc: Remove sim/cur_tick dependency from sim/core.hh
..

misc: Remove sim/cur_tick dependency from sim/core.hh

Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.

Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M ext/sst/gem5.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/linux/fs_workload.hh
M src/arch/arm/semihosting.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/riscv/isa.cc
M src/arch/x86/regs/int.hh
M src/base/pollevent.cc
M src/base/pollevent.hh
M src/base/stats/storage.hh
M src/base/trace.hh
M src/base/vnc/vncserver.cc
M src/cpu/inst_pb_trace.cc
M src/cpu/o3/cpu.cc
M src/cpu/pc_event.cc
M src/cpu/testers/traffic_gen/trace_gen.cc
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/dev/intel_8254_timer.cc
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_iface.cc
M src/dev/net/dist_iface.hh
M src/dev/net/etherbus.cc
M src/dev/net/etherdump.cc
M src/dev/net/etherlink.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/tcp_iface.cc
M src/dev/pci/device.cc
M src/dev/storage/ide_disk.cc
M src/dev/virtio/fs9p.cc
M src/kern/freebsd/events.cc
M src/mem/cache/base.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/queue.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/write_queue_entry.hh
M src/mem/comm_monitor.cc
M src/mem/mem_checker.cc
M src/mem/mem_checker.hh
M src/mem/packet.hh
M src/mem/probes/mem_trace.cc
M src/mem/request.hh
M src/mem/ruby/profiler/StoreTrace.cc
M src/mem/ruby/structures/BankedArray.cc
M src/mem/ruby/structures/BankedArray.hh
M src/python/pybind11/core.cc
M src/sim/core.hh
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/sim/global_event.cc
M src/sim/init.cc
M src/sim/init_signals.cc
M src/sim/power_state.cc
M src/sim/power_state.hh
M src/sim/root.cc
M src/sim/stat_control.hh
M src/systemc/channel/sc_clock.cc
M src/systemc/core/event.cc
M src/systemc/core/sc_main.cc
M src/systemc/core/scheduler.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/utils/tracefile.cc
M src/systemc/utils/vcd.cc
M util/systemc/gem5_within_systemc/sc_module.cc
72 files changed, 52 insertions(+), 54 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index efe73eb..3049567 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -52,7 +52,7 @@
 #include 

 // gem5 Headers
-#include 
+#include 
 #include 
 #include 
 #include 
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index 5f7562e..e9b468d 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -31,7 +31,6 @@
 #include "arch/arm/regs/misc.hh"
 #include "base/logging.hh"
 #include "dev/arm/base_gic.hh"
-#include "sim/core.hh"
 #include "systemc/tlm_bridge/gem5_to_tlm.hh"

 namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index 1ab1b29..4f14e7e 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -30,7 +30,6 @@
 #include "arch/arm/fastmodel/iris/cpu.hh"
 #include "base/logging.hh"
 #include "dev/arm/base_gic.hh"
-#include "sim/core.hh"
 #include "systemc/tlm_bridge/gem5_to_tlm.hh"

 namespace gem5
diff --git a/src/arch/arm/linux/fs_workload.hh  
b/src/arch/arm/linux/fs_workload.hh

index 3531ea9..659de9d 100644
--- a/src/arch/arm/linux/fs_workload.hh
+++ b/src/arch/arm/linux/fs_workload.hh
@@ -52,7 +52,6 @@
 #include "base/output.hh"
 #include "kern/linux/events.hh"
 #include "params/ArmFsLinux.hh"
-#include "sim/core.hh"

 namespace gem5
 {
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 2c237ca..a21852d 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -49,6 +49,7 @@
 #include "arch/arm/utility.hh"
 #include "cpu/thread_context.hh"
 #include "mem/port_proxy.hh"
+#include "sim/core.hh"
 #include "sim/guest_abi.hh"
 #include "sim/sim_object.hh"

diff --git a/src/arch/arm/tracers/tarmac_parser.cc  
b/src/arch/arm/tracers/tarmac_parser.cc

index 52b9558..f262c6c 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++

[gem5-dev] Change in gem5/gem5[develop]: base: Avoid dereferencing end() in findNearest

2021-07-06 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/43591 )


Change subject: base: Avoid dereferencing end() in findNearest
..

base: Avoid dereferencing end() in findNearest

When used with next_addr, findNearest will return the
next (even larger) address than the nearest larger
address. The problem is that when there is no valid
next, the function was dereferencing addrMap.end().

Fix this by marking next address as 0, since 0 is
not larger than any other address.

Places that use this function should be revisited
to make sure they account for this behavior, as
reported in the following Jira issue:
https://gem5.atlassian.net/browse/GEM5-936

Change-Id: I29ed80ff921b205209aeb5db05ffd3019d8595ce
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43591
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Bobby R. Bruce 
---
M src/base/loader/symtab.hh
1 file changed, 10 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/loader/symtab.hh b/src/base/loader/symtab.hh
index 200accc..e48e400 100644
--- a/src/base/loader/symtab.hh
+++ b/src/base/loader/symtab.hh
@@ -348,8 +348,9 @@
 }

 /**
- * Find the nearest symbol equal to or less than the supplied
- * address (e.g., the label for the enclosing function).
+ * Find the nearest symbol equal to or less than the supplied address
+ * (e.g., the label for the enclosing function). If there is no valid
+ * next address, next_addr is assigned 0.
  *
  * @param addr  The address to look up.
  * @param next_addr Address of following symbol (to determine the valid
@@ -363,7 +364,13 @@
 if (!upperBound(addr, i))
 return end();

-next_addr = i->first;
+// If there is no next address, make it 0 since 0 is not larger  
than

+// any other address, so it is clear that next is not valid
+if (i == addrMap.end()) {
+next_addr = 0;
+} else {
+next_addr = i->first;
+}
 --i;
 return symbols.begin() + i->second;
 }



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I29ed80ff921b205209aeb5db05ffd3019d8595ce
Gerrit-Change-Number: 43591
Gerrit-PatchSet: 11
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Not compiling with systemc when host is RISCV

2021-07-06 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47660 )



Change subject: scons: Not compiling with systemc when host is RISCV
..

scons: Not compiling with systemc when host is RISCV

Compiling gem5 with systemc enabled results in the errors
described in https://gem5.atlassian.net/browse/GEM5-1027.

This change tells scons not to compile gem5 with systemc
when the host ISA is RISC-V.

JIRA: https://gem5.atlassian.net/browse/GEM5-1027

Change-Id: I04e1bc722c9d702472152c9116d89938e8408047
Signed-off-by: Hoa Nguyen 
---
M src/systemc/SConsopts
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 4f2ae5c..65451cf 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -28,6 +28,12 @@
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
+import platform
+host_isa = platform.machine()
+if host_isa.startswith("riscv"):
+if warn:
+warning('Warning: Systemc may not work on RISC-V.')
+return False
 if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04e1bc722c9d702472152c9116d89938e8408047
Gerrit-Change-Number: 47660
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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