date:20210707

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,arch-vega,gpu-compute: Move request counters

2021-07-07 Thread Matt Sinclair (Gerrit) via gem5-dev

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45347 )


Change subject: arch-gcn3,arch-vega,gpu-compute: Move request counters
..

arch-gcn3,arch-vega,gpu-compute: Move request counters

When the Vega ISA got committed, it lacked the request counter
tracking for memory requests that existed in the GCN3 code.

Instead of copying over the same lines from the GCN3 code to the Vega
code, this commit makes the various memory pipelines handle updating the
request counter information instead, as every memory instruction calls a
memory pipeline.

This commit also adds an issueRequest in scalar_memory_pipeline, as
previously, the gpuDynInsts were explicitly placed in the queue of
issuedRequests.

Change-Id: I5140d3b2f12be582f2ae9ff7c433167aeec5b68e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45347
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.cc
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/scalar_memory_pipeline.cc
M src/gpu-compute/scalar_memory_pipeline.hh
6 files changed, 82 insertions(+), 408 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc  
b/src/arch/amdgpu/gcn3/insts/instructions.cc

index bc66ebe..a421454 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -4497,12 +4497,7 @@
 calcAddr(gpuDynInst, addr, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe
-.getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+.issueRequest(gpuDynInst);
 }

 void
@@ -4556,12 +4551,7 @@
 calcAddr(gpuDynInst, addr, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe.
-getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+issueRequest(gpuDynInst);
 }

 void
@@ -4613,12 +4603,7 @@
 calcAddr(gpuDynInst, addr, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe.
-getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+issueRequest(gpuDynInst);
 }

 void
@@ -4670,12 +4655,7 @@
 calcAddr(gpuDynInst, addr, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe.
-getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+issueRequest(gpuDynInst);
 }

 void
@@ -4727,12 +4707,7 @@
 calcAddr(gpuDynInst, addr, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe.
-getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+issueRequest(gpuDynInst);
 }

 void
@@ -4785,12 +4760,7 @@
 calcAddr(gpuDynInst, rsrcDesc, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe
-.getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+.issueRequest(gpuDynInst);
 } // execute

 void
@@ -4844,12 +4814,7 @@
 calcAddr(gpuDynInst, rsrcDesc, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe
-.getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-gpuDynInst->wavefront()->validateRequestCounters();
+.issueRequest(gpuDynInst);
 } // execute

 void
@@ -4903,12 +4868,7 @@
 calcAddr(gpuDynInst, rsrcDesc, offset);

 gpuDynInst->computeUnit()->scalarMemoryPipe
-.getGMReqFIFO().push(gpuDynInst);
-
-wf->scalarRdGmReqsInPipe--;
-wf->scalarOutstandingReqsRdGm++;
-gpuDynInst->wavefront()->outstandingReqs++;
-

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,gpu-compute: Set gpuDynInst exec_mask before use

2021-07-07 Thread Matt Sinclair (Gerrit) via gem5-dev

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45346 )


Change subject: arch-gcn3,gpu-compute: Set gpuDynInst exec_mask before use
..

arch-gcn3,gpu-compute: Set gpuDynInst exec_mask before use

vector_register_file uses the exec_mask of a memory instruction in
order to determine if it should mark a register as in-use or not.
Previously, the exec_mask of memory instructions was only set on
execution of that instruction, which occurs after the code in
vector_register_file. This led to the code reading potentially garbage
data, leading to a scenario where a register would be marked used when
it shouldn't be.

This fix sets the exec_mask of memory instructions in schedule_stage,
which works because the only time the wavefront execMask() is updated is
on a instruction executing, and we know the previous instruction will
have executed by the time schedule_stage executes, due to the order the
pipeline is executed in.

This also undoes part of a patch from last year (62ec973) which treated
the symptom of accidental register allocation, without preventing the
registers from being allocated in the first place.

This patch also removes now redundant code that sets the exec_mask in
instructions.cc for memory instructions

Change-Id: Idabd3502764fb06133ac2458606c1aaf6f04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45346
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Maintainer: Matthew Poremba 
Tested-by: kokoro 
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/vector_register_file.cc
3 files changed, 30 insertions(+), 156 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc  
b/src/arch/amdgpu/gcn3/insts/instructions.cc

index 8c77b8c..bc66ebe 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -31243,7 +31243,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -31304,7 +31303,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -31368,7 +31366,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -31548,7 +31545,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -31608,7 +31604,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -32073,7 +32068,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -32135,7 +32129,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -32200,7 +32193,6 @@
 {
 Wavefront *wf = gpuDynInst->wavefront();
 gpuDynInst->execUnitId = wf->execUnitId;
-gpuDynInst->exec_mask = wf->execMask();
 gpuDynInst->latency.init(gpuDynInst->computeUnit());
 gpuDynInst->latency.set(
 gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
@@ -32284,7 +32276,6 @@
 {

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Read registers in execute instead of initiateAcc

2021-07-07 Thread Matt Sinclair (Gerrit) via gem5-dev

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45345 )


Change subject: arch-gcn3: Read registers in execute instead of initiateAcc
..

arch-gcn3: Read registers in execute instead of initiateAcc

Certain memory writes were reading their registers in
initiateAcc, which lead to scenarios where a subsequent instruction
would execute, clobbering the value in that register before the memory
writes' initiateAcc method was called, causing the memory write to read
wrong data.

This patch moves all register reads to execute, preventing the above
scenario from happening.

Change-Id: Iee107c19e4b82c2e172bf2d6cc95b79983a43d83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45345
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Reviewed-by: Alex Dutu 
Maintainer: Matt Sinclair 
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
1 file changed, 116 insertions(+), 125 deletions(-)

Approvals:
  Alex Dutu: Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass



diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc  
b/src/arch/amdgpu/gcn3/insts/instructions.cc

index b5a4300..8c77b8c 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -5068,8 +5068,13 @@
 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
 ScalarRegU32 offset(0);
 ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+ConstScalarOperandU32 sdata(gpuDynInst, instData.SDATA);

 addr.read();
+sdata.read();
+
+std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
+sizeof(ScalarRegU32));

 if (instData.IMM) {
 offset = extData.OFFSET;
@@ -5093,10 +5098,6 @@
 void
 Inst_SMEM__S_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
 {
-ConstScalarOperandU32 sdata(gpuDynInst, instData.SDATA);
-sdata.read();
-std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
-sizeof(ScalarRegU32));
 initMemWrite<1>(gpuDynInst);
 } // initiateAcc

@@ -5127,8 +5128,13 @@
 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
 ScalarRegU32 offset(0);
 ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+ConstScalarOperandU64 sdata(gpuDynInst, instData.SDATA);

 addr.read();
+sdata.read();
+
+std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
+sizeof(ScalarRegU64));

 if (instData.IMM) {
 offset = extData.OFFSET;
@@ -5152,10 +5158,6 @@
 void
 Inst_SMEM__S_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
 {
-ConstScalarOperandU64 sdata(gpuDynInst, instData.SDATA);
-sdata.read();
-std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
-sizeof(ScalarRegU64));
 initMemWrite<2>(gpuDynInst);
 } // initiateAcc

@@ -5186,8 +5188,13 @@
 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
 ScalarRegU32 offset(0);
 ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+ConstScalarOperandU128 sdata(gpuDynInst, instData.SDATA);

 addr.read();
+sdata.read();
+
+std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
+4 * sizeof(ScalarRegU32));

 if (instData.IMM) {
 offset = extData.OFFSET;
@@ -5211,10 +5218,6 @@
 void
 Inst_SMEM__S_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
 {
-ConstScalarOperandU128 sdata(gpuDynInst, instData.SDATA);
-sdata.read();
-std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
-4 * sizeof(ScalarRegU32));
 initMemWrite<4>(gpuDynInst);
 } // initiateAcc

@@ -35746,9 +35749,18 @@
 ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
 ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
 ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+ConstVecOperandI8 data(gpuDynInst, extData.VDATA);

 rsrcDesc.read();
 offset.read();
+data.read();
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->d_data))[lane]
+= data[lane];
+}
+}

 int inst_offset = instData.OFFSET;

@@ -35793,16 +35805,6 @@
 void
 Inst_MUBUF__BUFFER_STORE_BYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
 {
-ConstVecOperandI8 data(gpuDynInst, extData.VDATA);
-data.read();
-
-for (int lane = 0; lane <

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Check for WAX dependences

2021-07-07 Thread Matt Sinclair (Gerrit) via gem5-dev

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47539 )


Change subject: gpu-compute: Check for WAX dependences
..

gpu-compute: Check for WAX dependences

This adds checking if the destination registers are free or busy
in the operandsReady() function for both scalar and vector
registers. This allows us to catch WAX dependences between instructions.

Change-Id: I0fb0b29e9608fca0d90c059422d4d9500d5b2a7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47539
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/scalar_register_file.cc
M src/gpu-compute/vector_register_file.cc
2 files changed, 22 insertions(+), 0 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/scalar_register_file.cc  
b/src/gpu-compute/scalar_register_file.cc

index 52e0a2f..3a00093 100644
--- a/src/gpu-compute/scalar_register_file.cc
+++ b/src/gpu-compute/scalar_register_file.cc
@@ -64,6 +64,17 @@
 }
 }

+for (const auto& dstScalarOp : ii->dstScalarRegOperands()) {
+for (const auto& physIdx : dstScalarOp.physIndices()) {
+if (regBusy(physIdx)) {
+DPRINTF(GPUSRF, "WAX stall: WV[%d]: %s: physReg[%d]\n",
+w->wfDynId, ii->disassemble(), physIdx);
+w->stats.numTimesBlockedDueWAXDependencies++;
+return false;
+}
+}
+}
+
 return true;
 }

diff --git a/src/gpu-compute/vector_register_file.cc  
b/src/gpu-compute/vector_register_file.cc

index dc5434d..2355643 100644
--- a/src/gpu-compute/vector_register_file.cc
+++ b/src/gpu-compute/vector_register_file.cc
@@ -71,6 +71,17 @@
 }
 }

+for (const auto& dstVecOp : ii->dstVecRegOperands()) {
+for (const auto& physIdx : dstVecOp.physIndices()) {
+if (regBusy(physIdx)) {
+DPRINTF(GPUVRF, "WAX stall: WV[%d]: %s: physReg[%d]\n",
+w->wfDynId, ii->disassemble(), physIdx);
+w->stats.numTimesBlockedDueWAXDependencies++;
+return false;
+}
+}
+}
+
 return true;
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47539
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0fb0b29e9608fca0d90c059422d4d9500d5b2a7d
Gerrit-Change-Number: 47539
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Add a branch_prediction namespace

2021-07-07 Thread Daniel Carvalho (Gerrit) via gem5-dev

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47303 )


Change subject: cpu: Add a branch_prediction namespace
..

cpu: Add a branch_prediction namespace

Encapsulate all branch-prediction-related files
in a branch_prediction namespace. This will allow
these files to be renamed to drop the BP suffix.

Issued-on: https://gem5.atlassian.net/browse/GEM5-982
Change-Id: I640c0caa846a3aade6fae95e9a93e4318ae9fca0
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47303
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/cpu/minor/fetch2.hh
M src/cpu/o3/fetch.hh
M src/cpu/pred/2bit_local.cc
M src/cpu/pred/2bit_local.hh
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/bi_mode.cc
M src/cpu/pred/bi_mode.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/btb.cc
M src/cpu/pred/btb.hh
M src/cpu/pred/indirect.hh
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/ltage.cc
M src/cpu/pred/ltage.hh
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_64KB.cc
M src/cpu/pred/multiperspective_perceptron_64KB.hh
M src/cpu/pred/multiperspective_perceptron_8KB.cc
M src/cpu/pred/multiperspective_perceptron_8KB.hh
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
M src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/ras.cc
M src/cpu/pred/ras.hh
M src/cpu/pred/simple_indirect.cc
M src/cpu/pred/simple_indirect.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage.cc
M src/cpu/pred/tage.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
M src/cpu/pred/tournament.cc
M src/cpu/pred/tournament.hh
M src/cpu/simple/base.hh
47 files changed, 216 insertions(+), 37 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh
index 09b7867..41a7a7f 100644
--- a/src/cpu/minor/fetch2.hh
+++ b/src/cpu/minor/fetch2.hh
@@ -93,7 +93,7 @@
 bool processMoreThanOneInput;

 /** Branch predictor passed from Python configuration */
-BPredUnit 
+branch_prediction::BPredUnit 

   public:
 /* Public so that Pipeline can pass it to Fetch1 */
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index f138718..5bfb01a 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -411,7 +411,7 @@
 TimeBuffer::wire toDecode;

 /** BPredUnit. */
-BPredUnit *branchPred;
+branch_prediction::BPredUnit *branchPred;

 TheISA::PCState pc[MaxThreads];

diff --git a/src/cpu/pred/2bit_local.cc b/src/cpu/pred/2bit_local.cc
index 61ce776..c9aa714 100644
--- a/src/cpu/pred/2bit_local.cc
+++ b/src/cpu/pred/2bit_local.cc
@@ -36,6 +36,9 @@
 namespace gem5
 {

+namespace branch_prediction
+{
+
 LocalBP::LocalBP(const LocalBPParams )
 : BPredUnit(params),
   localPredictorSize(params.localPredictorSize),
@@ -137,4 +140,5 @@
 {
 }

+} // namespace branch_prediction
 } // namespace gem5
diff --git a/src/cpu/pred/2bit_local.hh b/src/cpu/pred/2bit_local.hh
index 8d2a09b..55f45ca 100644
--- a/src/cpu/pred/2bit_local.hh
+++ b/src/cpu/pred/2bit_local.hh
@@ -51,6 +51,9 @@
 namespace gem5
 {

+namespace branch_prediction
+{
+
 /**
  * Implements a local predictor that uses the PC to index into a table of
  * counters.  Note that any time a pointer to the bp_history is given, it
@@ -125,6 +128,7 @@
 const unsigned indexMask;
 };

+} // namespace branch_prediction
 } // namespace gem5

 #endif // __CPU_PRED_2BIT_LOCAL_PRED_HH__
diff --git a/src/cpu/pred/BranchPredictor.py  
b/src/cpu/pred/BranchPredictor.py

index aa8e5cf..c6abebb 100644
--- a/src/cpu/pred/BranchPredictor.py
+++ b/src/cpu/pred/BranchPredictor.py
@@ -31,7 +31,7 @@

 class IndirectPredictor(SimObject):
 type = 'IndirectPredictor'
-cxx_class = 'gem5::IndirectPredictor'
+cxx_class = 'gem5::branch_prediction::IndirectPredictor'
 cxx_header = "cpu/pred/indirect.hh"
 abstract = True

@@ -39,7 +39,7 @@

 class SimpleIndirectPredictor(IndirectPredictor):
 type = 'SimpleIndirectPredictor'
-cxx_class = 'gem5::SimpleIndirectPredictor'
+cxx_class = 'gem5::branch_prediction::SimpleIndirectPredictor'
 cxx_header = "cpu/pred/simple_indirect.hh"

 indirectHashGHR = Param.Bool(True, "Hash branch predictor GHR")
@@

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Rename debug variables

2021-07-07 Thread Daniel Carvalho (Gerrit) via gem5-dev

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47304 )


Change subject: arch-arm: Rename debug variables
..

arch-arm: Rename debug variables

Pave the way for a "debug" namespace.

Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47304
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/self_debug.cc
3 files changed, 15 insertions(+), 20 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index adb1207..d81651b 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1103,16 +1103,16 @@
 } else if (stage2) {
 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
 tc->setMiscReg(T::HFarIndex,  OVAddr);
-} else if (debug > ArmFault::NODEBUG) {
+} else if (debugType > ArmFault::NODEBUG) {
 DBGDS32 Rext =  tc->readMiscReg(MISCREG_DBGDSCRext);
 tc->setMiscReg(T::FarIndex, faultAddr);
-if (debug == ArmFault::BRKPOINT){
+if (debugType == ArmFault::BRKPOINT){
 Rext.moe = 0x1;
-} else if (debug == ArmFault::VECTORCATCH){
+} else if (debugType == ArmFault::VECTORCATCH){
 Rext.moe = 0x5;
-} else if (debug > ArmFault::VECTORCATCH) {
+} else if (debugType > ArmFault::VECTORCATCH) {
 Rext.moe = 0xa;
-fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
+fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
 }

 tc->setMiscReg(T::FsrIndex, fsr);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index da05eb9..6d5411f 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -456,7 +456,7 @@
 bool stage2;
 bool s1ptw;
 ArmFault::TranMethod tranMethod;
-ArmFault::DebugType debug;
+ArmFault::DebugType debugType;

   public:
 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
@@ -465,7 +465,8 @@
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
 faultAddr(_faultAddr), OVAddr(0), write(_write),
 domain(_domain), source(_source), srcEncoded(0),
-stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),  
debug(_debug)

+stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
+debugType(_debug)
 {}

 bool getFaultVAddr(Addr ) const override;
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index e8d00ed..551abbb 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -96,8 +96,7 @@
 if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
 const DBGBCR ctr = p.getControlReg(tc);
 if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
-bool debug = p.test(tc, pc, el, ctr, false);
-if (debug){
+if (p.test(tc, pc, el, ctr, false)) {
 if (to32)
 p.onUse = true;
 return triggerException(tc, pc);
@@ -138,8 +137,7 @@
 for (auto : arWatchPoints){
 idxtmp ++;
 if (p.enable) {
-bool debug = p.test(tc, vaddr, el, write, atomic, size);
-if (debug){
+if (p.test(tc, vaddr, el, write, atomic, size)) {
 return triggerWatchpointException(tc, vaddr, write, cm);
 }
 }
@@ -212,12 +210,8 @@
 bool
 BrkPoint::testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
 {
-bool debug = false;
 const DBGBCR ctr = getControlReg(tc);
-if ((ctr.bt & 0x1) && enable) {
-debug = test(tc, vaddr, el, ctr, true);
-}
-return debug;
+return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
 }

 bool
@@ -730,12 +724,12 @@
 return NoFault;

 ExceptionLevel el = (ExceptionLevel) currEL(tc);
-bool debug;
+bool do_debug;
 if (fault == nullptr)
-debug = vcExcpt->addressMatching(tc, addr, el);
+do_debug = vcExcpt->addressMatching(tc, addr, el);
 else
-debug = vcExcpt->exceptionTrapping(tc, el, fault);
-if (debug) {
+do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
+if (do_debug) {
 if (enableTdeTge) {
 return std::make_shared(0, 0x22,
 EC_PREFETCH_ABORT_TO_HYP);

--
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[gem5-dev] Change in gem5/gem5[develop]: base: Dump page table over RSP

2021-07-07 Thread Boris Shingarov (Gerrit) via gem5-dev

Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47719 )


Change subject: base: Dump page table over RSP
..

base: Dump page table over RSP

Add a non-standard extension to the RSP protocol: the "." command
requests a dump of the simulated page table.
The dump consists of concatenated records, one record per page table
entry.  Each record contains the entry's "virtual" value written as
hex, followed by a colon (:), followed by the entry's "physical" value
written as hex, followed by a semicolon (;).

At the time of writing, one practical use of this feature (in
combination with the "shared_backstore" parameter) is extremely fast
Miranda-Ingalls simulation of JIT compilers.

Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47719
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
4 files changed, 27 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index f2ecfcc..c3353b7 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -153,6 +153,7 @@
 #include "mem/port.hh"
 #include "mem/port_proxy.hh"
 #include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -872,6 +873,8 @@
 { 'z', { "KGDB_CLR_HW_BKPT", ::cmdClrHwBkpt } },
 // insert breakpoint or watchpoint
 { 'Z', { "KGDB_SET_HW_BKPT", ::cmdSetHwBkpt } },
+// non-standard RSP extension: dump page table
+{ '.', { "GET_PAGE_TABLE", ::cmdDumpPageTable } },
 };

 bool
@@ -1219,6 +1222,13 @@
 }

 bool
+BaseRemoteGDB::cmdDumpPageTable(GdbCommand::Context )
+{
+send(tc->getProcessPtr()->pTable->externalize().c_str());
+return true;
+}
+
+bool
 BaseRemoteGDB::cmdAsyncStep(GdbCommand::Context )
 {
 const char *p = ctx.data;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index eb0661d..1089607 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -336,6 +336,7 @@
 bool cmdAsyncStep(GdbCommand::Context );
 bool cmdClrHwBkpt(GdbCommand::Context );
 bool cmdSetHwBkpt(GdbCommand::Context );
+bool cmdDumpPageTable(GdbCommand::Context );

 struct QuerySetCommand
 {
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index a311a0a..6e27c30 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -206,4 +206,14 @@
 }
 }

+const std::string
+EmulationPageTable::externalize() const
+{
+std::stringstream ss;
+for (PTable::const_iterator it=pTable.begin(); it != pTable.end();  
++it) {

+ss << std::hex << it->first << ":" << it->second.paddr << ";";
+}
+return ss.str();
+}
+
 } // namespace gem5
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 900d446..c115a41 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -162,6 +162,12 @@
  */
 Fault translate(const RequestPtr );

+/**
+ * Dump all items in the pTable, to a concatenation of strings of the  
form

+ *Addr:Entry;
+ */
+const std::string externalize() const;
+
 void getMappings(std::vector> *addr_mappings);

 void serialize(CheckpointOut ) const override;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Gerrit-Change-Number: 47719
Gerrit-PatchSet: 2
Gerrit-Owner: Boris Shingarov 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Check for instruction-count events before fetch

2021-07-07 Thread Boris Shingarov (Gerrit) via gem5-dev

Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27587 )


Change subject: cpu: Check for instruction-count events before fetch
..

cpu: Check for instruction-count events before fetch

Instruction fetch should not commence if there already is an
instruction-count event in the queue.

The most conspicuous scenario where this leads to obvious breakage,
is guest debugging.  Imagine the first bytes in the program pointed to
by _start are invalid instruction encoding, and we pass the --wait-gdb
flag.  Then in GDB we set $pc to point to valid instructions, and we
"continue".  gem5 will abort with "invalid instruction".

This is not how real targets behave: neither software- (e.g. ptrace)
based debuggers, nor low-level (e.g. OpenOCD or XMD connected over
JTAG to debug early initialization code eg when the MMU has not been
switched on yet, etc.)  Fetching should start from where $pc was set
to.  This patch tries to model this behavior.

Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27587
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
4 files changed, 11 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4b9b773..12accc3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -646,6 +646,8 @@
 return;
 }

+serviceInstCountEvents();
+
 Fault fault = NoFault;

 TheISA::PCState pcState = thread->pcState();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0a4595c..135094f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -302,6 +302,12 @@
  instRequestorId(), instAddr);
 }

+void
+BaseSimpleCPU::serviceInstCountEvents()
+{
+SimpleExecContext _info = *threadInfo[curThread];
+t_info.thread->comInstEventQueue.serviceEvents(t_info.numInst);
+}

 void
 BaseSimpleCPU::preExecute()
@@ -316,9 +322,6 @@
 t_info.setPredicate(true);
 t_info.setMemAccPredicate(true);

-// check for instruction-count-based events
-thread->comInstEventQueue.serviceEvents(t_info.numInst);
-
 // decode the instruction
 TheISA::PCState pcState = thread->pcState();

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 8117138..cee786d 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -130,6 +130,7 @@
   public:
 void checkForInterrupts();
 void setupFetchRequest(const RequestPtr );
+void serviceInstCountEvents();
 void preExecute();
 void postExecute();
 void advancePC(const Fault );
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ad0e039..76bc1af 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -805,6 +805,8 @@
 if (tryCompleteDrain())
 return;

+serviceInstCountEvents();
+
 if (_status == BaseSimpleCPU::Running) {
 // kick off fetch of next instruction... callback from icache
 // response will cause that instruction to be executed,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Gerrit-Change-Number: 27587
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Explicitly add librt to scons

2021-07-07 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47659 )


Change subject: scons: Explicitly add librt to scons
..

scons: Explicitly add librt to scons

gem5 uses the `shm_open()` funciton from .
This function requires linking to librt.

JIRA: https://gem5.atlassian.net/browse/GEM5-1015

Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47659
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A src/mem/SConsopts
1 file changed, 38 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/SConsopts b/src/mem/SConsopts
new file mode 100644
index 000..7d6ef35
--- /dev/null
+++ b/src/mem/SConsopts
@@ -0,0 +1,38 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+from gem5_scons import warning
+
+import gem5_scons
+
+with gem5_scons.Configure(main) as conf:
+have_shm_open = \
+conf.CheckLibWithHeader([None, 'rt'], 'sys/mman.h', 'C',
+'shm_open("/test", 0, 0);')
+if not have_shm_open:
+warning("Can't find library for sys/mman.")

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Gerrit-Change-Number: 47659
Gerrit-PatchSet: 9
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base-stats: Fix stat descriptions

2021-07-07 Thread Davide Basilio Bartolini (Gerrit) via gem5-dev

Davide Basilio Bartolini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47741 )



Change subject: base-stats: Fix stat descriptions
..

base-stats: Fix stat descriptions

Change-Id: Ib43dc9261287f10c615786a0d533304ab55ac232
---
M src/mem/mem_interface.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index e9c35d2..84bd808 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -2546,9 +2546,9 @@
  "Average memory access latency per NVM burst"),

 ADD_STAT(bytesRead, statistics::units::Byte::get(),
- "Total number of bytes read from DRAM"),
+ "Total number of bytes read from NVM"),
 ADD_STAT(bytesWritten, statistics::units::Byte::get(),
- "Total number of bytes written to DRAM"),
+ "Total number of bytes written to NVM"),
 ADD_STAT(avgRdBW, statistics::units::Rate<
 statistics::units::Byte, statistics::units::Second>::get(),
  "Average DRAM read bandwidth in MiBytes/s"),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib43dc9261287f10c615786a0d533304ab55ac232
Gerrit-Change-Number: 47741
Gerrit-PatchSet: 1
Gerrit-Owner: Davide Basilio Bartolini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Update ARMv8.1-PAN to allow unprivileged instructions.

2021-07-07 Thread Richard Cooper (Gerrit) via gem5-dev

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47779 )



Change subject: arch-arm: Update ARMv8.1-PAN to allow unprivileged  
instructions.

..

arch-arm: Update ARMv8.1-PAN to allow unprivileged instructions.

Update the ARMv8.1-PAN implementation to allow specified unprivileged
instructions to execute even when the cpsr.pan bit is set. The
specified instructions generate memory requests with the
TLB::ArmFlags::UserMode flags bit set.

See sections D5.4.2 (About PSTATE.PAN) and G5.6.2 (About the PAN bit)
of the Arm Architecture Reference Manual for details.
https://developer.arm.com/documentation/ddi0487/latest/

Change-Id: I9e904e0154de72c2e4cc70cbc49b3c8407a3cb1d
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
2 files changed, 18 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index e9c487e..8941f9e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -898,7 +898,7 @@
 break;
   case EL1:
 {
-if (checkPAN(tc, ap, req, mode)) {
+if (checkPAN(tc, ap, req, mode, is_priv)) {
 grant = false;
 grant_read = false;
 break;
@@ -938,7 +938,7 @@
 }
 break;
   case EL2:
-if (hcr.e2h && checkPAN(tc, ap, req, mode)) {
+if (hcr.e2h && checkPAN(tc, ap, req, mode, is_priv)) {
 grant = false;
 grant_read = false;
 break;
@@ -998,7 +998,7 @@

 bool
 TLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr ,
-  BaseMMU::Mode mode)
+  BaseMMU::Mode mode, const bool is_priv)
 {
 // The PAN bit has no effect on:
 // 1) Instruction accesses.
@@ -1006,15 +1006,22 @@
 // 3) Address translation instructions, other than ATS1E1RP and
 // ATS1E1WP when ARMv8.2-ATS1E1 is implemented. (Unimplemented in
 // gem5)
-// 4) Unprivileged instructions (Unimplemented in gem5)
-AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
-if (mmfr1.pan && cpsr.pan && (ap & 0x1) && mode != BaseMMU::Execute &&
-(!req->isCacheMaintenance() ||
-(req->getFlags() & Request::CACHE_BLOCK_ZERO))) {
+// 4) Instructions to be treated as unprivileged, unless
+// HCR_EL2.{E2H, TGE} == {1, 0}
+const AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+if (mmfr1.pan && cpsr.pan && (ap & 0x1) && mode != BaseMMU::Execute) {
+if (req->isCacheMaintenance() &&
+!(req->getFlags() & Request::CACHE_BLOCK_ZERO)) {
+// Cache maintenance other than DC ZVA
+return false;
+} else if (!is_priv && !(hcr.e2h && !hcr.tge)) {
+// Treated as unprivileged unless HCR_EL2.{E2H, TGE} == {1, 0}
+return false;
+}
 return true;
-} else {
-return false;
 }
+
+return false;
 }

 Fault
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 3d399c6..72e8803 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -259,7 +259,7 @@
 Fault checkPermissions64(TlbEntry *te, const RequestPtr ,
  BaseMMU::Mode mode, ThreadContext *tc);
 bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr ,
-  BaseMMU::Mode mode);
+  BaseMMU::Mode mode, const bool is_priv);

 /** Reset the entire TLB. Used for CPU switching to prevent stale
  * translations after multiple switches

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[gem5-dev] Change in gem5/gem5[develop]: misc: Fix nesting of namespace{} and if-endif.

2021-07-07 Thread Richard Cooper (Gerrit) via gem5-dev

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47761 )



Change subject: misc: Fix nesting of namespace{} and if-endif.
..

misc: Fix nesting of namespace{} and if-endif.

Fix a build error caused by the misaligned nesting of namespace{} and
if-endif. Previously, if HAVE_TUNTAP is not defined then the gem5
namespace is not closed.

Change-Id: I5e45d2271f97bb9e38c91565adb6aff0a7b43744
---
M src/dev/net/ethertap.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc
index 979b03e..5b1e957 100644
--- a/src/dev/net/ethertap.cc
+++ b/src/dev/net/ethertap.cc
@@ -472,6 +472,6 @@
 return true;
 }

-} // namespace gem5
+#endif // HAVE_TUNTAP

-#endif
+} // namespace gem5

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix for build error in recent MacOS 11.

2021-07-07 Thread Richard Cooper (Gerrit) via gem5-dev

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47760 )



Change subject: arch-arm: Fix for build error in recent MacOS 11.
..

arch-arm: Fix for build error in recent MacOS 11.

On a recent version of MacOS 11, the build fails due to the missing
sysctl.h include. Updated the preprocessor macros to include this file
for __APPLE__ builds.

Change-Id: I985d6c2ea97b82b32750bb562b2051f87d6c2e65
---
M src/arch/arm/freebsd/se_workload.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/freebsd/se_workload.cc  
b/src/arch/arm/freebsd/se_workload.cc

index d478b59..6a4a62d 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -34,7 +34,7 @@
 #include "arch/arm/freebsd/se_workload.hh"

 #include 
-#if !defined ( __GNU_LIBRARY__ ) && defined(__FreeBSD__)
+#if !defined( __GNU_LIBRARY__ ) && (defined(__FreeBSD__) ||  
defined(__APPLE__))

 #include 
 #endif


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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Fix for build error in MacOS.

2021-07-07 Thread Richard Cooper (Gerrit) via gem5-dev

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47759 )



Change subject: sim-se: Fix for build error in MacOS.
..

sim-se: Fix for build error in MacOS.

On MacOS the build fails because the types of readfds, writefds, and
errorfds cannot be automatically converted to fd_set*. Added casts
similar to the ones used for the FD_ZERO calls to help the compiler.

Change-Id: I40a2268f7f2ca1bece1ecafda52dfddf2212364d
---
M src/sim/syscall_emul.hh
1 file changed, 9 insertions(+), 3 deletions(-)



diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 802f547..aa02fd6 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -2377,13 +2377,19 @@
  */
 for (int i = 0; i < nfds_h; i++) {
 if (readfds && FD_ISSET(i, _h))
-FD_SET(trans_map[i], readfds);
+FD_SET(trans_map[i],
+   reinterpret_cast(
+   (typename OS::fd_set *)readfds));

 if (writefds && FD_ISSET(i, _h))
-FD_SET(trans_map[i], writefds);
+FD_SET(trans_map[i],
+   reinterpret_cast(
+   (typename OS::fd_set *)writefds));

 if (errorfds && FD_ISSET(i, _h))
-FD_SET(trans_map[i], errorfds);
+FD_SET(trans_map[i],
+   reinterpret_cast(
+   (typename OS::fd_set *)errorfds));
 }

 return retval;

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[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Update .gitignore to ingore run results

2021-07-07 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47222 )


Change subject: util-gem5art: Update .gitignore to ingore run results
..

util-gem5art: Update .gitignore to ingore run results

Change-Id: Iedb944c2be7889dbf3d9eaabb78c4a1bc967af3e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47222
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M util/gem5art/.gitignore
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/gem5art/.gitignore b/util/gem5art/.gitignore
index ec44db5..22ffc35 100644
--- a/util/gem5art/.gitignore
+++ b/util/gem5art/.gitignore
@@ -6,3 +6,4 @@
 *.egg-info/
 .vscode/
 .mypy_cache/
+/run/results/**



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Id: Iedb944c2be7889dbf3d9eaabb78c4a1bc967af3e
Gerrit-Change-Number: 47222
Gerrit-PatchSet: 6
Gerrit-Owner: Bobby R. Bruce 
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Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Fix the artifact test with incorrect git repo

2021-07-07 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47220 )


Change subject: util-gem5art: Fix the artifact test with incorrect git repo
..

util-gem5art: Fix the artifact test with incorrect git repo

The gem5art tests add the current repository as an artifact. Previously
this repository was called "gem5art". Since moving to the gem5 repo, it
is now called "gem5". Therefore the test checking the repository name
needed fixed.

Note: We need a better solution for testing gem5art's git functionality.
Using the current repository is not stable, as this fix shows. Noted
in Jira: https://gem5.atlassian.net/browse/GEM5-1013.

Change-Id: I017ff039ccb1c0a290f9aa1a09bd738c1820f88f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47220
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M util/gem5art/artifact/tests/test_artifact.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/gem5art/artifact/tests/test_artifact.py  
b/util/gem5art/artifact/tests/test_artifact.py

index 6a54650..897113d 100644
--- a/util/gem5art/artifact/tests/test_artifact.py
+++ b/util/gem5art/artifact/tests/test_artifact.py
@@ -92,7 +92,7 @@
 def test_origin(self):
 git = artifact.artifact.getGit(Path("."))
 self.assertTrue(
-git["origin"].endswith("gem5art"), "Origin should end with  
gem5art"
+git["origin"].endswith("gem5"), "Origin should end with  
gem5art"

 )





2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Change-Id: I017ff039ccb1c0a290f9aa1a09bd738c1820f88f
Gerrit-Change-Number: 47220
Gerrit-PatchSet: 6
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add Python test dependencies to Docker

2021-07-07 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47219 )


Change subject: util-docker: Add Python test dependencies to Docker
..

util-docker: Add Python test dependencies to Docker

These are needed to run our Python tests

Change-Id: Ifd6904a59ad3b6217a337bd5e912c3e7e2e10c17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47219
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
M util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
2 files changed, 8 insertions(+), 2 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile

index 775e549..5a9fd8d 100644
--- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
@@ -31,7 +31,10 @@
 RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3 python3-six doxygen libboost-all-dev \
-libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config \
+python3-pip python3-venv
+
+RUN pip3 install mypy

 RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

 RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1
diff --git a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile

index 3facf7e..76d3011 100644
--- a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile
@@ -32,4 +32,7 @@
 RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3-six python-is-python3 doxygen libboost-all-dev \
-libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config pip \
+python3-venv
+
+RUN pip install mypy
\ No newline at end of file

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Gerrit-Change-Id: Ifd6904a59ad3b6217a337bd5e912c3e7e2e10c17
Gerrit-Change-Number: 47219
Gerrit-PatchSet: 5
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base-stats: Fix stat name clash

2021-07-07 Thread Davide Basilio Bartolini (Gerrit) via gem5-dev

Davide Basilio Bartolini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47739 )



Change subject: base-stats: Fix stat name clash
..

base-stats: Fix stat name clash

Fixes JIRA issue https://gem5.atlassian.net/browse/GEM5-1028

Change-Id: Id7b294fb3c66e495bebfbe105a8d888ecc0c7198
---
M src/base/stats/hdf5.cc
M src/mem/mem_interface.cc
2 files changed, 12 insertions(+), 5 deletions(-)



diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
index 0dca54f..90bd8cd 100644
--- a/src/base/stats/hdf5.cc
+++ b/src/base/stats/hdf5.cc
@@ -253,8 +253,15 @@
 props.setDeflate(1);

 fspace = H5::DataSpace(rank, dims, max_dims.data());
-data_set = group.createDataSet(info.name,  
H5::PredType::NATIVE_DOUBLE,

-   fspace, props);
+try {
+data_set = group.createDataSet(info.name,
+H5::PredType::NATIVE_DOUBLE, fspace, props);
+} catch (const H5::Exception ) {
+  std::string err = "Failed creating H5::DataSet " +  info.name  
+ "; ";

+  err += e.getDetailMsg() + " in " + e.getFuncName();
+  // Rethrow std exception so that it's passed on to the Python  
world

+  throw std::runtime_error(err);
+}

 if (enableDescriptions && !info.desc.empty()) {
 addMetaData(data_set, "description", info.desc);
diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index e9c35d2..835d857 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -1849,7 +1849,7 @@
 }

 DRAMInterface::DRAMStats::DRAMStats(DRAMInterface &_dram)
-: statistics::Group(&_dram),
+: statistics::Group(&_dram, "interface"),
 dram(_dram),

 ADD_STAT(readBursts, statistics::units::Count::get(),
@@ -2546,9 +2546,9 @@
  "Average memory access latency per NVM burst"),

 ADD_STAT(bytesRead, statistics::units::Byte::get(),
- "Total number of bytes read from DRAM"),
+ "Total number of bytes read from NVM"),
 ADD_STAT(bytesWritten, statistics::units::Byte::get(),
- "Total number of bytes written to DRAM"),
+ "Total number of bytes written to NVM"),
 ADD_STAT(avgRdBW, statistics::units::Rate<
 statistics::units::Byte, statistics::units::Second>::get(),
  "Average DRAM read bandwidth in MiBytes/s"),

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[gem5-dev] Change in gem5/gem5[develop]: base-stats: Add basic test for hdf5 stats

2021-07-07 Thread Davide Basilio Bartolini (Gerrit) via gem5-dev

Davide Basilio Bartolini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47740 )



Change subject: base-stats: Add basic test for hdf5 stats
..

base-stats: Add basic test for hdf5 stats

Related JIRA issue: https://gem5.atlassian.net/browse/GEM5-1028

Change-Id: I67badcf261f04cd446d016a4ad3d7393bad9a6ba
---
A tests/gem5/stats/test_hdf5.py
M tests/gem5/verifier.py
2 files changed, 78 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py
new file mode 100644
index 000..85167c1
--- /dev/null
+++ b/tests/gem5/stats/test_hdf5.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+'''
+Test file for the hdf5 stats.
+It just runs an SE simulation with the hdf5 stats and checks that the
+simulation succeeds and the stats file exists.
+No specific checks on the stats are performed.
+'''
+import re
+import os
+from testlib import *
+
+ok_exit_regex = re.compile(
+r'Exiting @ tick \d+ because exiting with last active thread context'
+)
+
+path =  
joinpath(config.bin_path, 'test-progs', 'hello', 'bin', 'arm', 'linux')

+filename = 'hello'
+url = (config.resource_url + '/test-progs/hello/bin/arm/linux/hello')
+test_program = DownloadedProgram(url, path, filename)
+
+stdout_verifier = verifier.MatchRegex(ok_exit_regex)
+h5_verifier = verifier.CheckH5StatsExist()
+gem5_verify_config(
+name='hdf5_test',
+verifiers=[stdout_verifier, h5_verifier],
+fixtures=(test_program,),
+config=os.path.join(config.base_dir, 'configs', 'example','se.py'),
+config_args=['--cmd', joinpath(test_program.path, filename)],
+gem5_args=['--stats-file=h5://stats.h5'],
+valid_isas=(constants.arm_tag,)
+)
diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py
index b539a67..91912f1 100644
--- a/tests/gem5/verifier.py
+++ b/tests/gem5/verifier.py
@@ -11,6 +11,7 @@
 # modified or unmodified, in source code or in binary form.
 #
 # Copyright (c) 2017 Mark D. Hill and David A. Wood
+# Copyright (c) 2021 Huawei International
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -40,6 +41,7 @@
 Built in test cases that verify particular details about a gem5 run.
 '''
 import re
+import os

 from testlib import test_util
 from testlib.configuration import constants
@@ -59,6 +61,17 @@
 return test_util.TestFunction(self._test,
 name=name, fixtures=self.fixtures)

+class CheckH5StatsExist(Verifier):
+def __init__(self, stats_file='stats.h5'):
+super(CheckH5StatsExist, self).__init__()
+self.stats_file = stats_file
+
+def test(self, params):
+tempdir = params.fixtures[constants.tempdir_fixture_name].path
+h5_file = joinpath(tempdir, self.stats_file)
+if not os.path.isfile(h5_file):
+

[gem5-dev] Change in gem5/gem5[develop]: docker-util: Remove building of GCC 5 and 6 Docker images

2021-07-07 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47462 )


Change subject: docker-util: Remove building of GCC 5 and 6 Docker images
..

docker-util: Remove building of GCC 5 and 6 Docker images

Building of these images is no longer required as GCC 5 and 6 have been
dropped.

Change-Id: Ife0331843214fe545c5620a2f77ede3adb436700
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47462
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M util/cloudbuild/cloudbuild_create_images.yaml
1 file changed, 0 insertions(+), 16 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/cloudbuild/cloudbuild_create_images.yaml  
b/util/cloudbuild/cloudbuild_create_images.yaml

index 31876fb..7549012 100644
--- a/util/cloudbuild/cloudbuild_create_images.yaml
+++ b/util/cloudbuild/cloudbuild_create_images.yaml
@@ -20,20 +20,6 @@
 - name: 'gcr.io/cloud-builders/docker'
   args: ['build',
 '-t',
-'gcr.io/$PROJECT_ID/gcc-version-5:latest',
-'--build-arg', 'version=5',
-'util/dockerfiles/ubuntu-18.04_gcc-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/gcc-version-6:latest',
-'--build-arg', 'version=6',
-'util/dockerfiles/ubuntu-18.04_gcc-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
 'gcr.io/$PROJECT_ID/gcc-version-7:latest',
 '--build-arg', 'version=7',
 'util/dockerfiles/ubuntu-18.04_gcc-version']
@@ -110,8 +96,6 @@
 images: ['gcr.io/$PROJECT_ID/ubuntu-20.04_all-dependencies:latest',
  'gcr.io/$PROJECT_ID/ubuntu-20.04_min-dependencies:latest',
  'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest',
- 'gcr.io/$PROJECT_ID/gcc-version-5:latest',
- 'gcr.io/$PROJECT_ID/gcc-version-6:latest',
  'gcr.io/$PROJECT_ID/gcc-version-7:latest',
  'gcr.io/$PROJECT_ID/gcc-version-8:latest',
  'gcr.io/$PROJECT_ID/gcc-version-9:latest',



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ife0331843214fe545c5620a2f77ede3adb436700
Gerrit-Change-Number: 47462
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc,tests: Remove support for GCC 6

2021-07-07 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47460 )


Change subject: misc,tests: Remove support for GCC 6
..

misc,tests: Remove support for GCC 6

Supporting GCC 7 onwards will allow us to move to the C++17 standard.

Change-Id: I805945230d77dacdc6b0a863153b28276025ecdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47460
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index 11b84a0..bf1d281 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -14,7 +14,6 @@
 "gcc-version-9"
 "gcc-version-8"
 "gcc-version-7"
-"gcc-version-6"
 "clang-version-11"
 "clang-version-10"
 "clang-version-9"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I805945230d77dacdc6b0a863153b28276025ecdc
Gerrit-Change-Number: 47460
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Dump page table over RSP

2021-07-07 Thread Boris Shingarov (Gerrit) via gem5-dev

Boris Shingarov has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47719 )



Change subject: base: Dump page table over RSP
..

base: Dump page table over RSP

Add a non-standard extension to the RSP protocol: the "." command
requests a dump of the simulated page table.
The dump consists of concatenated records, one record per page table
entry.  Each record contains the entry's "virtual" value written as
hex, followed by a colon (:), followed by the entry's "physical" value
written as hex, followed by a semicolon (;).

At the time of writing, one practical use of this feature (in
combination with the "shared_backstore" parameter) is extremely fast
Miranda-Ingalls simulation of JIT compilers.

Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
4 files changed, 27 insertions(+), 0 deletions(-)



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index f2ecfcc..c3353b7 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -153,6 +153,7 @@
 #include "mem/port.hh"
 #include "mem/port_proxy.hh"
 #include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -872,6 +873,8 @@
 { 'z', { "KGDB_CLR_HW_BKPT", ::cmdClrHwBkpt } },
 // insert breakpoint or watchpoint
 { 'Z', { "KGDB_SET_HW_BKPT", ::cmdSetHwBkpt } },
+// non-standard RSP extension: dump page table
+{ '.', { "GET_PAGE_TABLE", ::cmdDumpPageTable } },
 };

 bool
@@ -1219,6 +1222,13 @@
 }

 bool
+BaseRemoteGDB::cmdDumpPageTable(GdbCommand::Context )
+{
+send(tc->getProcessPtr()->pTable->externalize().c_str());
+return true;
+}
+
+bool
 BaseRemoteGDB::cmdAsyncStep(GdbCommand::Context )
 {
 const char *p = ctx.data;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index eb0661d..1089607 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -336,6 +336,7 @@
 bool cmdAsyncStep(GdbCommand::Context );
 bool cmdClrHwBkpt(GdbCommand::Context );
 bool cmdSetHwBkpt(GdbCommand::Context );
+bool cmdDumpPageTable(GdbCommand::Context );

 struct QuerySetCommand
 {
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index a311a0a..6e27c30 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -206,4 +206,14 @@
 }
 }

+const std::string
+EmulationPageTable::externalize() const
+{
+std::stringstream ss;
+for (PTable::const_iterator it=pTable.begin(); it != pTable.end();  
++it) {

+ss << std::hex << it->first << ":" << it->second.paddr << ";";
+}
+return ss.str();
+}
+
 } // namespace gem5
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 900d446..c115a41 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -162,6 +162,12 @@
  */
 Fault translate(const RequestPtr );

+/**
+ * Dump all items in the pTable, to a concatenation of strings of the  
form

+ *Addr:Entry;
+ */
+const std::string externalize() const;
+
 void getMappings(std::vector> *addr_mappings);

 void serialize(CheckpointOut ) const override;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47719
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Gerrit-Change-Number: 47719
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Forward declare kvm_vcpu_init

2021-07-07 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47679 )


Change subject: arch-arm: Forward declare kvm_vcpu_init
..

arch-arm: Forward declare kvm_vcpu_init

Signed-off-by: Giacomo Travaglini 
Change-Id: I6fa5be48498d1a8f9c070e9ded11e8cadd4b89a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47679
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/kvm/base_cpu.hh
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index ec9e5ad..3b2beb3 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -44,6 +44,7 @@
 #include "dev/arm/base_gic.hh"

 struct kvm_reg_list;
+struct kvm_vcpu_init;

 namespace gem5
 {
@@ -111,7 +112,7 @@
  *
  * @param target CPU type to emulate
  */
-void kvmArmVCpuInit(const struct kvm_vcpu_init );
+void kvmArmVCpuInit(const kvm_vcpu_init );

   private:
 std::unique_ptr tryGetRegList(uint64_t nelem) const;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6fa5be48498d1a8f9c070e9ded11e8cadd4b89a1
Gerrit-Change-Number: 47679
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove typedef (struct|enum) Foo in cpp files.

2021-07-07 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46199 )


Change subject: misc: Remove typedef (struct|enum) Foo in cpp files.
..

misc: Remove typedef (struct|enum) Foo in cpp files.

In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:

typedef struct
{
} Foo;

Foo foo;

In C++, this is unnecessary:

struct Foo
{
};

Foo foo;

Remove all of the first form in C++ files and replace them with the
second form.

Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/freebsd/freebsd.hh
M src/arch/arm/linux/linux.hh
M src/arch/mips/linux/linux.hh
M src/arch/power/linux/linux.hh
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/pmp.hh
M src/arch/sparc/linux/linux.hh
M src/arch/x86/linux/linux.hh
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_cpu_interface.hh
M src/dev/hsa/hsa_packet.hh
M src/dev/hsa/hsa_packet_processor.hh
M src/dev/hsa/hsa_queue.hh
M src/dev/storage/ide_disk.hh
M src/kern/linux/linux.hh
M src/kern/operatingsystem.hh
M src/kern/solaris/solaris.hh
M src/mem/cache/compressors/base_delta.hh
M src/mem/cache/compressors/cpack.hh
M src/mem/cache/compressors/fpc.hh
M src/mem/cache/compressors/fpcd.hh
M src/mem/cache/compressors/repeated_qwords.hh
M src/mem/cache/compressors/zero.hh
23 files changed, 142 insertions(+), 142 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/freebsd/freebsd.hh  
b/src/arch/arm/freebsd/freebsd.hh

index f47fb4e..cc2ffb8 100644
--- a/src/arch/arm/freebsd/freebsd.hh
+++ b/src/arch/arm/freebsd/freebsd.hh
@@ -126,7 +126,7 @@
  * sizeof st_lspare 4
  */

-typedef struct
+struct tgt_stat
 {
 uint32_t   st_dev;
 uint32_t   st_ino;
@@ -149,9 +149,9 @@
 uint32_t   st_lspare;
 uint64_t   st_birthtimX;
 uint64_t   st_birthtim;
-} tgt_stat;
+};

-typedef struct
+struct tgt_stat64
 {
 uint32_t   st_dev;
 uint32_t   st_ino;
@@ -174,7 +174,7 @@
 uint32_t   st_lspare;
 uint64_t   st_birthtimX;
 uint64_t   st_birthtim;
-} tgt_stat64;
+};

 /// For getrusage().
 struct rusage
@@ -296,7 +296,7 @@
 uint64_t iov_len;
 };

-typedef struct
+struct tgt_stat
 {
 uint32_t   st_dev;
 uint32_t   st_ino;
@@ -319,9 +319,9 @@
 uint32_t   st_lspare;
 uint64_t   st_birthtimX;
 uint64_t   st_birthtim;
-} tgt_stat;
+};

-typedef struct
+struct tgt_stat64
 {
 uint32_t   st_dev;
 uint32_t   st_ino;
@@ -344,7 +344,7 @@
 uint32_t   st_lspare;
 uint64_t   st_birthtimX;
 uint64_t   st_birthtim;
-} tgt_stat64;
+};

 /// For getrusage().
 struct rusage
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index 15faede..e795165 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -193,7 +193,7 @@
 };


-typedef struct
+struct tgt_stat
 {
 uint32_t st_dev;
 uint32_t st_ino;
@@ -213,9 +213,9 @@
 uint32_t st_mtime_nsec;
 uint32_t st_ctimeX;
 uint32_t st_ctime_nsec;
-} tgt_stat;
+};

-typedef struct
+struct tgt_stat64
 {
 uint64_t  st_dev;
 uint8_t   __pad0[4];
@@ -236,9 +236,9 @@
 uint32_t  st_ctimeX;
 uint32_t  st_ctime_nsec;
 uint64_t  st_ino;
-} tgt_stat64;
+};

-typedef struct
+struct tgt_sysinfo
 {
 int32_t  uptime;/* Seconds since boot */
 uint32_t loads[3];  /* 1, 5, and 15 minute load averages */
@@ -252,7 +252,7 @@
 uint32_t totalhigh; /* Total high memory size */
 uint32_t freehigh;  /* Available high memory size */
 uint32_t mem_unit;  /* Memory unit size in bytes */
-} tgt_sysinfo;
+};

 /// For getrusage().
 struct rusage
@@ -457,7 +457,7 @@
 uint64_t iov_len;
 };

-typedef struct
+struct tgt_stat
 {
 uint64_t st_dev;
 uint64_t st_ino;
@@ -476,9 +476,9 @@
 uint64_t st_mtime_nsec;
 uint64_t st_ctimeX;
 uint64_t st_ctime_nsec;
-} tgt_stat;
+};

-typedef struct
+struct tgt_stat64
 {
 uint64_t st_dev;
 uint64_t st_ino;
@@ -497,9 +497,9 @@
 uint64_t st_mtime_nsec;
 uint64_t st_ctimeX;
 uint64_t st_ctime_nsec;
-} tgt_stat64;
+};

-typedef struct
+struct tgt_sysinfo
 {
 int64_t  uptime;/* Seconds since boot */
 uint64_t loads[3];  /* 1, 5, and 15 minute load averages */
@@ -514,7 +514,7 @@
 uint64_t totalhigh; /* Total high memory

[gem5-dev] Change in gem5/gem5[develop]: scons: Not compiling with systemc when host is RISCV

2021-07-07 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47660 )


Change subject: scons: Not compiling with systemc when host is RISCV
..

scons: Not compiling with systemc when host is RISCV

Compiling gem5 with systemc enabled results in the errors
described in https://gem5.atlassian.net/browse/GEM5-1027.

This change tells scons not to compile gem5 with systemc
when the host ISA is RISC-V.

JIRA: https://gem5.atlassian.net/browse/GEM5-1027

Change-Id: I04e1bc722c9d702472152c9116d89938e8408047
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47660
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/systemc/SConsopts
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 4f2ae5c..891431c 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -28,6 +28,14 @@
 from gem5_scons import warning

 def use_systemc_check(env, warn=False):
+import platform
+host_isa = platform.machine()
+# Disallow compiling systemc if the host ISA is RISC-V.
+# The error is described here:  
https://gem5.atlassian.net/browse/GEM5-1027

+if host_isa.startswith("riscv"):
+if warn:
+warning('Warning: Systemc may not work on RISC-V.')
+return False
 if env['PLATFORM'] == 'darwin':
 if warn:
 warning('Warning: Systemc may not work on Mac OS.')

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04e1bc722c9d702472152c9116d89938e8408047
Gerrit-Change-Number: 47660
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,arch-vega,gpu-compute: Move request counters

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,gpu-compute: Set gpuDynInst exec_mask before use

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Read registers in execute instead of initiateAcc

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Check for WAX dependences

[gem5-dev] Change in gem5/gem5[develop]: cpu: Add a branch_prediction namespace

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Rename debug variables

[gem5-dev] Change in gem5/gem5[develop]: base: Dump page table over RSP

[gem5-dev] Change in gem5/gem5[develop]: cpu: Check for instruction-count events before fetch

[gem5-dev] Change in gem5/gem5[develop]: scons: Explicitly add librt to scons

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Fix stat descriptions

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Update ARMv8.1-PAN to allow unprivileged instructions.

[gem5-dev] Change in gem5/gem5[develop]: misc: Fix nesting of namespace{} and if-endif.

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix for build error in recent MacOS 11.

[gem5-dev] Change in gem5/gem5[develop]: sim-se: Fix for build error in MacOS.

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Update .gitignore to ingore run results

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Fix the artifact test with incorrect git repo

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add Python test dependencies to Docker

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Fix stat name clash

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Add basic test for hdf5 stats

[gem5-dev] Change in gem5/gem5[develop]: docker-util: Remove building of GCC 5 and 6 Docker images

[gem5-dev] Change in gem5/gem5[develop]: misc,tests: Remove support for GCC 6

[gem5-dev] Change in gem5/gem5[develop]: base: Dump page table over RSP

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Forward declare kvm_vcpu_init

[gem5-dev] Change in gem5/gem5[develop]: misc: Remove typedef (struct|enum) Foo in cpp files.

[gem5-dev] Change in gem5/gem5[develop]: scons: Not compiling with systemc when host is RISCV

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