[gem5-dev] Change in gem5/gem5[develop]: arch: Fix illegal instruction error message
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48923 )
Change subject: arch: Fix illegal instruction error message
..
arch: Fix illegal instruction error message
Previously, the reason for the fault was not printed to the output.
Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Signed-off-by: Hoa Nguyen
---
M src/arch/riscv/faults.hh
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 38c5638..a8df3f5 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -166,7 +166,8 @@
public:
IllegalInstFault(std::string r, const ExtMachInst inst)
-: InstFault("Illegal instruction", inst)
+: InstFault("Illegal instruction", inst),
+ reason(r)
{}
void invokeSE(ThreadContext *tc, const StaticInstPtr ) override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48923
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Gerrit-Change-Number: 48923
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: fix hook for 'deprecated' attribute
Tom Rollet has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48843 )
Change subject: scons: fix hook for 'deprecated' attribute
..
scons: fix hook for 'deprecated' attribute
On the new release, the compilation is polluted by the same warning:
> ''deprecated' attribute directive ignored
It seems that the hook added in this patch does not work:
https://gem5-review.googlesource.com/c/public/gem5/+/45246/1..7
The snippet of code compile with TryCompile on g++{8,9}.
It probably comes from the fact that the compilation
only creates a warning and not an error.
By adding temporarily '-Werror' for this compilation test,
it filters the faulty gcc versions.
Change-Id: I2b8b7a1a7e06df437b76e98d212947f4f9452311
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48843
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/SConsopts
1 file changed, 11 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/SConsopts b/src/base/SConsopts
index ea11bd4..9fafd64 100644
--- a/src/base/SConsopts
+++ b/src/base/SConsopts
@@ -56,12 +56,21 @@
# alternative stacks.
conf.env['HAVE_VALGRIND'] = conf.CheckCHeader('valgrind/valgrind.h')
-conf.env['HAVE_DEPRECATED_NAMESPACE'] = conf.TryCompile('''
+
+# Check if the compiler supports the [[gnu::deprecated]] attribute
+# Create a temporary environment with -Werror in CCFLAGS
+werror_env = main.Clone()
+werror_env.Append(CCFLAGS=['-Werror'])
+with gem5_scons.Configure(werror_env) as conf:
+
+# Store result in the main environment
+main['HAVE_DEPRECATED_NAMESPACE'] = conf.TryCompile('''
int main() {return 0;}
namespace [[gnu::deprecated("Test namespace deprecation")]]
test_deprecated_namespace {}
''', '.cc')
-if not conf.env['HAVE_DEPRECATED_NAMESPACE']:
+
+if not main['HAVE_DEPRECATED_NAMESPACE']:
warning("Deprecated namespaces are not supported by this
compiler.\n"
"Please make sure to check the mailing list for
deprecation "
"announcements.")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48843
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2b8b7a1a7e06df437b76e98d212947f4f9452311
Gerrit-Change-Number: 48843
Gerrit-PatchSet: 5
Gerrit-Owner: Tom Rollet
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Tom Rollet
Gerrit-Reviewer: kokoro
Gerrit-CC: Daniel Carvalho
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu: MiscReg read/writes polluting ExecContext integer stats
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48686 )
Change subject: cpu: MiscReg read/writes polluting ExecContext integer stats
..
cpu: MiscReg read/writes polluting ExecContext integer stats
Change-Id: Ic505c1157f9008f19bfc500b8f20334c63a64106
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48686
Reviewed-by: Gabe Black
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/cpu/simple/exec_context.hh
1 file changed, 13 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 23e6e47..7614491 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, 2020 ARM Limited
+ * Copyright (c) 2014-2018, 2020-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -128,6 +128,10 @@
"Number of times the CC registers were read"),
ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
"Number of times the CC registers were written"),
+ ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
+ "Number of times the Misc registers were read"),
+ ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
+ "Number of times the Misc registers were written"),
ADD_STAT(numMemRefs, statistics::units::Count::get(),
"Number of memory refs"),
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
@@ -237,6 +241,10 @@
statistics::Scalar numCCRegReads;
statistics::Scalar numCCRegWrites;
+// Number of misc register file accesses
+statistics::Scalar numMiscRegReads;
+statistics::Scalar numMiscRegWrites;
+
// Number of simulated memory references
statistics::Scalar numMemRefs;
statistics::Scalar numLoadInsts;
@@ -423,7 +431,7 @@
RegVal
readMiscRegOperand(const StaticInst *si, int idx) override
{
-execContextStats.numIntRegReads++;
+execContextStats.numMiscRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.is(MiscRegClass));
return thread->readMiscReg(reg.index());
@@ -432,7 +440,7 @@
void
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
-execContextStats.numIntRegWrites++;
+execContextStats.numMiscRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(MiscRegClass));
thread->setMiscReg(reg.index(), val);
@@ -445,7 +453,7 @@
RegVal
readMiscReg(int misc_reg) override
{
-execContextStats.numIntRegReads++;
+execContextStats.numMiscRegReads++;
return thread->readMiscReg(misc_reg);
}
@@ -456,7 +464,7 @@
void
setMiscReg(int misc_reg, RegVal val) override
{
-execContextStats.numIntRegWrites++;
+execContextStats.numMiscRegWrites++;
thread->setMiscReg(misc_reg, val);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48686
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic505c1157f9008f19bfc500b8f20334c63a64106
Gerrit-Change-Number: 48686
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: reuse local variable in QueuedPrefetcher
Nathanael Premillieu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48684 )
Change subject: mem-cache: reuse local variable in QueuedPrefetcher
..
mem-cache: reuse local variable in QueuedPrefetcher
Reuse local variable for PA in Queued::translationComplete.
Change-Id: Id3c0333ac1bf019ac21162aedf69f6019c818e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48684
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
Maintainer: Daniel Carvalho
---
M src/mem/cache/prefetch/queued.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index c54f442..597c88a 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -317,8 +317,8 @@
"cache/MSHR prefetch addr:%#x\n", target_paddr);
} else {
Tick pf_time = curTick() + clockPeriod() * latency;
-it->createPkt(it->translationRequest->getPaddr(), blkSize,
-requestorId, tagPrefetch, pf_time);
+it->createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
+ pf_time);
addToQueue(pfq, *it);
}
} else {
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48684
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id3c0333ac1bf019ac21162aedf69f6019c818e30
Gerrit-Change-Number: 48684
Gerrit-PatchSet: 5
Gerrit-Owner: Nathanael Premillieu
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nathanael Premillieu
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Simplifying the "advancePC" mechanism
Hi folks. Currently, when you need to advance a PC in gem5, you need to take an instruction object of the appropriate type and pass the PC object to its advancePC method. The idea here was that some PCs are unidimensional, or in other words have only one component (a simple address for instance), and some are multidimensional (an address plus micropc) and which dimension(s) you need to advance the PC in depend on factors like whether an instruction is microcoded, and also whether that instruction is the final microop in its macroop. If an ISA which doesn't use microcode (only POWER and MIPS, I think?) you save a little bit of effort by not bothering to check all that microcode business since you know for sure that it won't matter. In the other ISAs like x86, you can check whether the instruction you grabbed was either non-microcoded (advance the regular PC), microcoded and in the middle (advance the microPC only) or microcoded and at the end (advance the regular PC, reset the microPC). Also instructions which are not possibly microcoded could skip the check as well. This is ok but a little bit clunky since the PCState object is not self sufficient, and the instructions themselves have to have logic for advancing the PC. Instead, I'm thinking about making the arch decoder (or the logic around it in the CPU) set the microPC of final microops to be a sentry value like 0. When the PCState for an ISA which has microcode sees that sentry value, it will know to advance the regular PC and reset the microPC. "Normal" instructions will need to set the next microPC to 0 so that they immediately advance the regular PC. With the specific choice of 0, we could blindly set the microPC to the next microPC and get the right result, but that would mean a macroop could never *purposefully* loop back to its first microop, since that would look like it was ending the instruction. Another option could be 0x (microPCs are always 16 bits), but then the logic that detects that scenario would also have to override that value. The difference may be trivial, and it may be worth avoiding the limitation of using 0. Since the CPUs already have a lot of logic in them which figures out what they should do in these various scenarios, and since we're currently calling a virtual function on the StaticInst class, I think (hope) that while this new arrangement will be simpler, it will also be more efficient as well. Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: Add an exclude method to the AddrRange class
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48903 )
Change subject: base: Add an exclude method to the AddrRange class
..
base: Add an exclude method to the AddrRange class
This will allow us to define a list of ranges provided an exclude
pattern, which is handy when a fragmented memory map is present
Change-Id: Ib3d76ef178355585d80e9e600b7c60e66efa01c1
Signed-off-by: Giacomo Travaglini
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 391 insertions(+), 2 deletions(-)
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 6531a0b..a1a8761 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2014, 2017-2019 ARM Limited
+ * Copyright (c) 2012, 2014, 2017-2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -586,6 +586,60 @@
}
/**
+ * Subtract a list of intervals from the range and return
+ * the resulting collection of ranges, so that the union
+ * of the two lists cover the original range
+ *
+ * The exclusion list can contain overlapping ranges
+ * Interleaving ranges are not supported and will fail the
+ * assertion.
+ *
+ * @param the input exclusion list
+ * @return the resulting collection of ranges
+ *
+ *
+ * @ingroup api_addr_range
+ */
+std::vector
+exclude(const std::vector _ranges)
+{
+assert(!interleaved());
+
+auto sorted_ranges = exclude_ranges;
+std::sort(sorted_ranges.begin(), sorted_ranges.end());
+
+std::vector ranges;
+
+Addr next_start = start();
+for (const auto : sorted_ranges) {
+assert(!e.interleaved());
+if (!intersects(e))
+continue;
+
+if (e.start() <= next_start) {
+if (e.end() < end()) {
+if (next_start < e.end())
+next_start = e.end();
+} else {
+return ranges;
+}
+} else {
+ranges.push_back(AddrRange(next_start, e.start()));
+if (e.end() < end()) {
+next_start = e.end();
+} else {
+return ranges;
+}
+}
+}
+
+if (next_start < end())
+ranges.push_back(AddrRange(next_start, end()));
+
+return ranges;
+}
+
+/**
* Less-than operator used to turn an STL map into a binary search
* tree of non-overlapping address ranges.
*
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 00cf251..c063296 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019 The Regents of the University of California
- * Copyright (c) 2018-2019 ARM Limited
+ * Copyright (c) 2018-2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1090,3 +1090,338 @@
EXPECT_EQ(0x5, r.start());
EXPECT_EQ(0xA, r.end());
}
+
+/*
+ * The exclude list is excluding the entire range: return an empty
+ * list of ranges
+ *
+ * |-|
+ * | range |
+ * |-|
+ *
+ * |--|
+ * | exclude_range |
+ * |--|
+ */
+TEST(AddrRangeTest, ExcludeAll)
+{
+const std::vector exclude_ranges{
+AddrRange(0x0, 0x200)
+};
+
+AddrRange r(0x00, 0x100);
+auto ranges = r.exclude(exclude_ranges);
+
+EXPECT_TRUE(ranges.empty());
+}
+
+/*
+ * The exclude list is excluding the entire range: return an empty
+ * list of ranges. The exclude_range = range
+ *
+ * |-|
+ * | range |
+ * |-|
+ *
+ * |-|
+ * |exclude_range|
+ * |-|
+ */
+TEST(AddrRangeTest, ExcludeAllEqual)
+{
+const std::vector exclude_ranges{
+AddrRange(0x0, 0x100)
+};
+
+AddrRange r(0x00, 0x100);
+auto ranges = r.exclude(exclude_ranges);
+
+EXPECT_TRUE(ranges.empty());
+}
+
+/*
+ * The exclude list is made of multiple adjacent ranges covering the entire
+ * interval: return an empty list of ranges.
+ *
+ * |---|
+ * |range |
+ * |---|
+ *
+ * |--|---|--|
+ * | exclude_range | exclude_range | exclude_range |
+ * |--|---|--|
+ */
+TEST(AddrRangeTest,
[gem5-dev] Change in gem5/gem5[develop]: python: Expose the AddrRange exclude to the python world
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48904 )
Change subject: python: Expose the AddrRange exclude to the python world
..
python: Expose the AddrRange exclude to the python world
Change-Id: I9cb1bf66d4e9390c8d3c4403afec9f896d19c162
Signed-off-by: Giacomo Travaglini
---
M src/python/m5/params.py
M src/python/pybind11/core.cc
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 67bba65..79c1bcb 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -864,6 +864,17 @@
return AddrRange(int(self.start), int(self.end),
self.masks, int(self.intlvMatch))
+def exclude(self, ranges):
+from _m5.range import AddrRangeVector
+
+# The wrapped C++ class is assuming an AddrRangeVector
+# We are therefore converting to it before excluding ranges
+# and reconverting it into a list of AddrRange before returning
+pybind_exclude = AddrRangeVector([ r.getValue() for r in ranges ])
+pybind_include = self.getValue().exclude(pybind_ranges)
+
+return [ AddrRange(r.start(), r.end()) for r in pybind_include ]
+
# Boolean parameter type. Python doesn't let you subclass bool, since
# it doesn't want to let you create multiple instances of True and
# False. Thus this is a little more complicated than String.
diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc
index 0e9c311..257ae23 100644
--- a/src/python/pybind11/core.cc
+++ b/src/python/pybind11/core.cc
@@ -167,6 +167,7 @@
.def("mergesWith", ::mergesWith)
.def("intersects", ::intersects)
.def("isSubset", ::isSubset)
+.def("exclude", ::exclude)
;
// We need to make vectors of AddrRange opaque to avoid weird
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48904
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9cb1bf66d4e9390c8d3c4403afec9f896d19c162
Gerrit-Change-Number: 48904
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util: Add a fallback when checking for root.isa in checkpoints.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48883 )
Change subject: util: Add a fallback when checking for root.isa in
checkpoints.
..
util: Add a fallback when checking for root.isa in checkpoints.
The upgraders in util/cpt_upgraders have been able to check the
root.isa element of checkpoints to determine what "the" ISA is for a
simulation, as a quick way to bail out of that particular updater
applies only to specific ISAs. We are moving away from the idea that
there is a single ISA, and so this mechanism will no longer work.
Fortunately, these cpt_upgraders are only relevant for old checkpoints.
If a checkpoint doesn't have a root.isa element inside it at all, we
know (as of this writing) that it is newer than all of these upgraders
and hence they do not apply. Any new upgraders will have to be written
to not rely on the root.isa field which will be removed. If that sort
of field is still needed, it can be added somewhere else in the
hierarchy, perhaps at the system level, or as part of the actual ISA
object.
The simplest way to implement this new behavior is to add a fallback
option when an upgrader looks for root.isa, specifically ''. If the
root.isa element does not exist, the script will get '' back, and this
will not match whatever ISA it's trying to check against. The one even
remotely more complicated script is isa-is-simobject.py which has
several behaviors for different ISAs. In that case, we just explicitly
check for '' and return early if that's what we found.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056
Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7
---
M util/cpt_upgraders/arm-ccregs.py
M util/cpt_upgraders/arm-contextidr-el2.py
M util/cpt_upgraders/arm-gem5-gic-ext.py
M util/cpt_upgraders/arm-gicv2-banked-regs.py
M util/cpt_upgraders/arm-hdlcd-upgrade.py
M util/cpt_upgraders/arm-miscreg-teehbr.py
M util/cpt_upgraders/arm-sve.py
M util/cpt_upgraders/arm-sysreg-mapping-ns.py
M util/cpt_upgraders/armv8.py
M util/cpt_upgraders/isa-is-simobject.py
M util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py
M util/cpt_upgraders/x86-add-tlb.py
12 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/util/cpt_upgraders/arm-ccregs.py
b/util/cpt_upgraders/arm-ccregs.py
index 2e3cf1a..3bce036 100644
--- a/util/cpt_upgraders/arm-ccregs.py
+++ b/util/cpt_upgraders/arm-ccregs.py
@@ -1,7 +1,7 @@
# Use condition code registers for the ARM architecture.
# Previously the integer register file was used for these registers.
def upgrader(cpt):
-if cpt.get('root','isa') == 'arm':
+if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
diff --git a/util/cpt_upgraders/arm-contextidr-el2.py
b/util/cpt_upgraders/arm-contextidr-el2.py
index 9910ded..87d7ab6 100644
--- a/util/cpt_upgraders/arm-contextidr-el2.py
+++ b/util/cpt_upgraders/arm-contextidr-el2.py
@@ -1,6 +1,6 @@
# Add the ARM CONTEXTIDR_EL2 miscreg.
def upgrader(cpt):
-if cpt.get('root','isa') == 'arm':
+if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections
diff --git a/util/cpt_upgraders/arm-gem5-gic-ext.py
b/util/cpt_upgraders/arm-gem5-gic-ext.py
index 50114b3..d4d5880 100644
--- a/util/cpt_upgraders/arm-gem5-gic-ext.py
+++ b/util/cpt_upgraders/arm-gem5-gic-ext.py
@@ -38,7 +38,7 @@
structures. Resize them to match the new GIC."""
import re
-if cpt.get('root','isa') != 'arm':
+if cpt.get('root', 'isa', fallback='') != 'arm':
return
old_cpu_max = 8
diff --git a/util/cpt_upgraders/arm-gicv2-banked-regs.py
b/util/cpt_upgraders/arm-gicv2-banked-regs.py
index 703598c..e6437e6 100644
--- a/util/cpt_upgraders/arm-gicv2-banked-regs.py
+++ b/util/cpt_upgraders/arm-gicv2-banked-regs.py
@@ -35,7 +35,7 @@
# duplicate banked registers into new per-cpu arrays.
def upgrader(cpt):
-if cpt.get('root','isa') == 'arm':
+if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
diff --git a/util/cpt_upgraders/arm-hdlcd-upgrade.py
b/util/cpt_upgraders/arm-hdlcd-upgrade.py
index 05a3bb5..a7885a2 100644
--- a/util/cpt_upgraders/arm-hdlcd-upgrade.py
+++ b/util/cpt_upgraders/arm-hdlcd-upgrade.py
@@ -39,7 +39,7 @@
after they are loaded. Expect some timing differences."""
import re
-if cpt.get('root','isa') != 'arm':
+if cpt.get('root', 'isa', fallback='') != 'arm':
return
option_names = {
diff --git a/util/cpt_upgraders/arm-miscreg-teehbr.py
b/util/cpt_upgraders/arm-miscreg-teehbr.py
index f0174d5..1717d40 100644
--- a/util/cpt_upgraders/arm-miscreg-teehbr.py
+++ b/util/cpt_upgraders/arm-miscreg-teehbr.py
@@ -1,6 +1,6 @@
# Add the ARM MISCREG TEEHBR
def upgrader(cpt):
-if cpt.get('root','isa') ==
[gem5-dev] Change in gem5/gem5[develop]: sim: Don't serialize a root.isa string in checkpoints.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48884 )
Change subject: sim: Don't serialize a root.isa string in checkpoints.
..
sim: Don't serialize a root.isa string in checkpoints.
We are moving away from having a single ISA in a simulation. That means
it will no longer make sense to have a single, particular ISA at the
root of the object hierarchy which applies to the entire simulation.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056
Change-Id: If4d354ac423e7ab4d3efbc6544d4feea93f56ab3
---
M src/sim/root.cc
1 file changed, 0 insertions(+), 3 deletions(-)
diff --git a/src/sim/root.cc b/src/sim/root.cc
index ef35ed9..e53f09d 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -42,7 +42,6 @@
#include "base/hostinfo.hh"
#include "base/logging.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "debug/TimeSync.hh"
#include "sim/core.hh"
#include "sim/cur_tick.hh"
@@ -206,8 +205,6 @@
Root::serialize(CheckpointOut ) const
{
SERIALIZE_SCALAR(FullSystem);
-std::string isa = THE_ISA_STR;
-SERIALIZE_SCALAR(isa);
globals.serializeSection(cp, "globals");
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48884
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4d354ac423e7ab4d3efbc6544d4feea93f56ab3
Gerrit-Change-Number: 48884
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Stop generating THE_ISA_STR in config/the_isa.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48885 )
Change subject: scons: Stop generating THE_ISA_STR in config/the_isa.hh.
..
scons: Stop generating THE_ISA_STR in config/the_isa.hh.
This macro is no longer used or needed.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056
Change-Id: Ib90f739c2d0df4c655239e55ecfe0da486ee3bf7
---
M src/SConscript
1 file changed, 0 insertions(+), 1 deletion(-)
diff --git a/src/SConscript b/src/SConscript
index 6a630da..fd3981b 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -769,7 +769,6 @@
#define THE_ISA ${{define(target_isa)}}
#define TheISA ${{namespace(target_isa)}}
-#define THE_ISA_STR "${{target_isa}}"
#endif // __CONFIG_THE_ISA_HH__''')
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48885
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib90f739c2d0df4c655239e55ecfe0da486ee3bf7
Gerrit-Change-Number: 48885
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Do not run test_hdf5 if HDF5 is not present
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48685 )
Change subject: tests: Do not run test_hdf5 if HDF5 is not present
..
tests: Do not run test_hdf5 if HDF5 is not present
This regression is failing on machines not supporting the
HDF5 library
Signed-off-by: Giacomo Travaglini
Change-Id: I5c6762596dc86a9a2b0612d77f9f76e772d9fa42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48685
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M tests/gem5/stats/test_hdf5.py
1 file changed, 34 insertions(+), 18 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py
index 85167c1..a9702c8 100644
--- a/tests/gem5/stats/test_hdf5.py
+++ b/tests/gem5/stats/test_hdf5.py
@@ -1,4 +1,5 @@
# Copyright (c) 2021 Huawei International
+# Copyright (c) 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -43,23 +44,38 @@
import os
from testlib import *
-ok_exit_regex = re.compile(
-r'Exiting @ tick \d+ because exiting with last active thread context'
-)
+def have_hdf5():
+have_hdf5_file = os.path.join(
+config.base_dir, 'build',
constants.arm_tag, 'config', 'have_hdf5.hh')
+with open(have_hdf5_file) as f:
+content = f.read()
-path =
joinpath(config.bin_path, 'test-progs', 'hello', 'bin', 'arm', 'linux')
-filename = 'hello'
-url = (config.resource_url + '/test-progs/hello/bin/arm/linux/hello')
-test_program = DownloadedProgram(url, path, filename)
+result = re.match("#define HAVE_HDF5 ([0-1])", content)
+if not result:
+raise Exception(
+f"Unable to find the HAVE_HDF5 in {have_hdf5_file}")
+else:
+return result.group(1) == "1"
-stdout_verifier = verifier.MatchRegex(ok_exit_regex)
-h5_verifier = verifier.CheckH5StatsExist()
-gem5_verify_config(
-name='hdf5_test',
-verifiers=[stdout_verifier, h5_verifier],
-fixtures=(test_program,),
-config=os.path.join(config.base_dir, 'configs', 'example','se.py'),
-config_args=['--cmd', joinpath(test_program.path, filename)],
-gem5_args=['--stats-file=h5://stats.h5'],
-valid_isas=(constants.arm_tag,)
-)
+if have_hdf5():
+ok_exit_regex = re.compile(
+r'Exiting @ tick \d+ because exiting with last active thread context'
+)
+
+path = joinpath(config.bin_path, 'test-progs', 'hello',
+'bin', 'arm', 'linux')
+filename = 'hello'
+url = (config.resource_url + '/test-progs/hello/bin/arm/linux/hello')
+test_program = DownloadedProgram(url, path, filename)
+
+stdout_verifier = verifier.MatchRegex(ok_exit_regex)
+h5_verifier = verifier.CheckH5StatsExist()
+gem5_verify_config(
+name='hdf5_test',
+verifiers=[stdout_verifier, h5_verifier],
+fixtures=(test_program,),
+config=os.path.join(config.base_dir, 'configs', 'example','se.py'),
+config_args=['--cmd', joinpath(test_program.path, filename)],
+gem5_args=['--stats-file=h5://stats.h5'],
+valid_isas=(constants.arm_tag,)
+)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48685
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5c6762596dc86a9a2b0612d77f9f76e772d9fa42
Gerrit-Change-Number: 48685
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Davide Basilio Bartolini
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: print VA and PA in the prefetch queues
Nathanael Premillieu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48683 )
Change subject: mem-cache: print VA and PA in the prefetch queues
..
mem-cache: print VA and PA in the prefetch queues
As prefetcher can use VA and need translation, it is
interesting to see both VA and PA when printing the queues.
PA is printed as 0 if translation has not happened yet.
Also fix a bug when the pkt is not yet created.
Change-Id: I7cd225379c2930a8d6a7882efdb3dc7bc49fb8a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48683
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
Maintainer: Daniel Carvalho
---
M src/mem/cache/prefetch/queued.cc
1 file changed, 5 insertions(+), 2 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index ae4913d..c54f442 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -131,8 +131,11 @@
for (const_iterator it = queue.cbegin(); it != queue.cend();
it++, pos++) {
-DPRINTF(HWPrefetchQueue, "%s[%d]: Prefetch Req Addr: %#x
prio: %3d\n",
-queue_name, pos, it->pkt->getAddr(), it->priority);
+Addr vaddr = it->pfInfo.getAddr();
+/* Set paddr to 0 if not yet translated */
+Addr paddr = it->pkt ? it->pkt->getAddr() : 0;
+DPRINTF(HWPrefetchQueue, "%s[%d]: Prefetch Req VA: %#x PA: %#x "
+"prio: %3d\n", queue_name, pos, vaddr, paddr,
it->priority);
}
}
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48683
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7cd225379c2930a8d6a7882efdb3dc7bc49fb8a3
Gerrit-Change-Number: 48683
Gerrit-PatchSet: 4
Gerrit-Owner: Nathanael Premillieu
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Nathanael Premillieu
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
