[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add unit test for sim/serialize_handlers
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38776 )
Change subject: sim,tests: Add unit test for sim/serialize_handlers
..
sim,tests: Add unit test for sim/serialize_handlers
Add a GTest for the functionality of sim/serialize_handlers.hh.
Change-Id: I1128c7adb12a3c7d091e26db13733ba45e1e61fe
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38776
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/sim/SConscript
A src/sim/serialize_handlers.test.cc
2 files changed, 420 insertions(+), 0 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 20f8d6b..91fe15f 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -91,6 +91,7 @@
GTest('guest_abi.test', 'guest_abi.test.cc')
GTest('port.test', 'port.test.cc', 'port.cc')
GTest('proxy_ptr.test', 'proxy_ptr.test.cc')
+GTest('serialize_handlers.test', 'serialize_handlers.test.cc')
if env['TARGET_ISA'] != 'null':
SimObject('InstTracer.py')
diff --git a/src/sim/serialize_handlers.test.cc
b/src/sim/serialize_handlers.test.cc
new file mode 100644
index 000..a844b7a
--- /dev/null
+++ b/src/sim/serialize_handlers.test.cc
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2021 Daniel R. Carvalho
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include
+#include
+
+#include "sim/serialize_handlers.hh"
+
+using namespace gem5;
+
+TEST(SerializeTest, ParseParamInt8)
+{
+ParseParam parser;
+int8_t value(0);
+
+// Zero
+EXPECT_TRUE(parser.parse("0", value));
+EXPECT_EQ(0, value);
+
+// Booleans
+EXPECT_FALSE(parser.parse("true", value));
+EXPECT_FALSE(parser.parse("false", value));
+
+// 8-bit values
+EXPECT_FALSE(parser.parse("255", value));
+EXPECT_TRUE(parser.parse("-128", value));
+EXPECT_EQ(-128, value);
+
+// 16-bit values
+EXPECT_FALSE(parser.parse("1000", value));
+EXPECT_FALSE(parser.parse("-1000", value));
+
+// 32-bit values
+EXPECT_FALSE(parser.parse("2147483648", value));
+EXPECT_FALSE(parser.parse("-1073741824", value));
+
+// Doubles (scientific numbers should not be converted to integers
+// correctly)
+EXPECT_FALSE(parser.parse("123456.789", value));
+EXPECT_FALSE(parser.parse("-123456.789", value));
+EXPECT_FALSE(parser.parse("9.87654e+06", value));
+
+// Characters
+EXPECT_TRUE(parser.parse("69", value));
+EXPECT_EQ(69, value);
+EXPECT_TRUE(parser.parse("97", value));
+EXPECT_EQ(97, value);
+
+// Strings
+EXPECT_FALSE(parser.parse("Test", value));
+}
+
+TEST(SerializeTest, ParseParamUint32)
+{
+ParseParam parser;
+uint32_t value(0);
+
+// Zero
+EXPECT_TRUE(parser.parse("0", value));
+EXPECT_EQ(0, value);
+
+// Booleans
+EXPECT_FALSE(parser.parse("true", value));
+EXPECT_FALSE(parser.parse("false", value));
+
+// 8-bit values
+EXPECT_TRUE(parser.parse("255", value));
+EXPECT_EQ(255, value);
+EXPECT_FALSE(parser.parse("-128", value));
+
+// 16-bit values
+EXPECT_TRUE(parser.parse("1000", value));
+EXPECT_EQ(1000, value);
+EXPECT_FALSE(parser.parse("-1000", value));
+
+// 32-bit values
+EXPECT_TRUE(parser.parse("2147483648", value));
+EXPECT_EQ(2147483648, value);
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix memory leak of PMU events
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38703 )
Change subject: arch-arm: Fix memory leak of PMU events
..
arch-arm: Fix memory leak of PMU events
Memory of PMU events was never being released.
Change-Id: I3cd958310008799f0873af3a490f847a21b5
Issued-on: https://gem5.atlassian.net/browse/GEM5-857
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38703
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
2 files changed, 13 insertions(+), 17 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index ad4ea24..57df5f6 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -118,7 +118,7 @@
fatal_if(old_event != eventMap.end(), "An event with id %d has "
"been previously defined\n", id);
-swIncrementEvent = new SWIncrementEvent();
+swIncrementEvent = std::make_shared();
eventMap[id] = swIncrementEvent;
registerEvent(id);
}
@@ -130,18 +130,14 @@
DPRINTF(PMUVerbose, "PMU: Adding Probe Driven event with id '0x%x'"
"as probe %s:%s\n",id, obj->name(), probe_name);
-RegularEvent *event = nullptr;
+std::shared_ptr event;
auto event_entry = eventMap.find(id);
if (event_entry == eventMap.end()) {
-
-event = new RegularEvent();
+event = std::make_shared();
eventMap[id] = event;
-
} else {
-event = dynamic_cast(event_entry->second);
-if (!event) {
-fatal("Event with id %d is not probe driven\n", id);
-}
+event =
std::dynamic_pointer_cast(event_entry->second);
+fatal_if(!event, "Event with id %d is not probe driven\n", id);
}
event->addMicroarchitectureProbe(obj, probe_name);
@@ -182,7 +178,7 @@
counters.emplace_back(*this, index);
}
-PMUEvent *event = getEvent(cycleCounterEventId);
+std::shared_ptr event = getEvent(cycleCounterEventId);
panic_if(!event, "core cycle event is not present\n");
cycleCounter.enabled = true;
cycleCounter.attach(event);
@@ -531,7 +527,7 @@
}
void
-PMU::CounterState::attach(PMUEvent* event)
+PMU::CounterState::attach(const std::shared_ptr )
{
if (!resetValue) {
value = 0;
@@ -734,7 +730,7 @@
cycleCounter.unserializeSection(cp, "cycleCounter");
}
-PMU::PMUEvent*
+std::shared_ptr
PMU::getEvent(uint64_t eventId)
{
auto entry = eventMap.find(eventId);
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index b9b2747..46b10d0 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -408,7 +408,7 @@
* @param the id of the event to obtain
* @return a pointer to the event with id eventId
*/
-PMUEvent* getEvent(uint64_t eventId);
+std::shared_ptr getEvent(uint64_t eventId);
/** State of a counter within the PMU. **/
struct CounterState : public Serializable
@@ -442,7 +442,7 @@
*
* @param the event to attach the counter to
*/
-void attach(PMUEvent* event);
+void attach(const std::shared_ptr );
/**
* Obtain the counter id
@@ -482,7 +482,7 @@
protected: /* Configuration */
/** PmuEvent currently in use (if any) **/
-PMUEvent *sourceEvent;
+std::shared_ptr sourceEvent;
/** id of the counter instance **/
uint64_t counterId;
@@ -612,7 +612,7 @@
const uint64_t cycleCounterEventId;
/** The event that implements the software increment **/
-SWIncrementEvent *swIncrementEvent;
+std::shared_ptr swIncrementEvent;
protected: /* Configuration and constants */
/** Constant (configuration-dependent) part of the PMCR */
@@ -627,7 +627,7 @@
/**
* List of event types supported by this PMU.
*/
-std::map eventMap;
+std::map> eventMap;
};
} // namespace ArmISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38703
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3cd958310008799f0873af3a490f847a21b5
Gerrit-Change-Number: 38703
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Fix gem5 resources import in parsec test
Austin Harris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50787 ) Change subject: tests: Fix gem5 resources import in parsec test .. tests: Fix gem5 resources import in parsec test Change-Id: I271cf89130f31777ef43b00e0c15cf44835977e3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50787 Reviewed-by: Jason Lowe-Power Reviewed-by: Bobby R. Bruce Maintainer: Jason Lowe-Power Maintainer: Bobby R. Bruce Tested-by: kokoro --- M tests/gem5/configs/parsec_disk_run.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/gem5/configs/parsec_disk_run.py b/tests/gem5/configs/parsec_disk_run.py index c354cdf..401e88a 100644 --- a/tests/gem5/configs/parsec_disk_run.py +++ b/tests/gem5/configs/parsec_disk_run.py @@ -40,7 +40,7 @@ from m5.objects import Root -from gem5.components.resources.resource import Resource +from gem5.resources.resource import Resource from gem5.components.boards.x86_board import X86Board from gem5.components.memory.single_channel import SingleChannelDDR3_1600 from gem5.components.processors.simple_switchable_processor import ( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50787 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I271cf89130f31777ef43b00e0c15cf44835977e3 Gerrit-Change-Number: 50787 Gerrit-PatchSet: 2 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Remove the page_size.hh switching header file.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50766 ) Change subject: arch: Remove the page_size.hh switching header file. .. arch: Remove the page_size.hh switching header file. Change-Id: I23ac089a5f7152db6443e2b016d3c85a33bdc20d --- M src/arch/SConscript 1 file changed, 0 insertions(+), 1 deletion(-) diff --git a/src/arch/SConscript b/src/arch/SConscript index fb9f463..14f54e7 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -60,7 +60,6 @@ decoder.hh isa.hh locked_mem.hh -page_size.hh pcstate.hh vecregs.hh '''), -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50766 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I23ac089a5f7152db6443e2b016d3c85a33bdc20d Gerrit-Change-Number: 50766 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Get rid of the now unused System::getPageBytes method.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50764 )
Change subject: sim: Get rid of the now unused System::getPageBytes method.
..
sim: Get rid of the now unused System::getPageBytes method.
Change-Id: I90bd3f3468e0835b882de1b31df8481da04f5af1
---
M src/sim/system.hh
1 file changed, 0 insertions(+), 5 deletions(-)
diff --git a/src/sim/system.hh b/src/sim/system.hh
index f5a63c0..f25d279 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -392,11 +392,6 @@
return params().byte_order;
}
- /**
- * Get the page bytes for the ISA.
- */
-Addr getPageBytes() const { return TheISA::PageBytes; }
-
/**
* The thermal model used for this system (if any).
*/
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50764
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I90bd3f3468e0835b882de1b31df8481da04f5af1
Gerrit-Change-Number: 50764
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch: Make the MMU ranged translateFunction pure virtual.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50761 )
Change subject: arch: Make the MMU ranged translateFunction pure virtual.
..
arch: Make the MMU ranged translateFunction pure virtual.
The (simple) implementation in each ISAs MMU can then specify the page
size it wants, which is the page size appropriate for that ISA.
Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243
---
M src/arch/arm/mmu.hh
M src/arch/generic/mmu.cc
M src/arch/generic/mmu.hh
M src/arch/mips/mmu.hh
M src/arch/power/mmu.hh
M src/arch/riscv/mmu.hh
M src/arch/sparc/mmu.hh
M src/arch/x86/mmu.hh
8 files changed, 55 insertions(+), 12 deletions(-)
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index b80968b..27bd345 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -41,6 +41,7 @@
#ifndef __ARCH_ARM_MMU_HH__
#define __ARCH_ARM_MMU_HH__
+#include "arch/arm/page_size.hh"
#include "arch/arm/tlb.hh"
#include "arch/generic/mmu.hh"
@@ -81,6 +82,14 @@
TableWalker *dtbStage2Walker;
public:
+TranslationGenPtr
+translateFunctional(Addr start, Addr size, ThreadContext *tc,
+Mode mode, Request::Flags flags) override
+{
+return TranslationGenPtr(new MMUTranslationGen(
+PageBytes, start, size, tc, this, mode, flags));
+}
+
enum ArmFlags
{
AlignmentMask = 0x7,
diff --git a/src/arch/generic/mmu.cc b/src/arch/generic/mmu.cc
index 3d1de81..a765228 100644
--- a/src/arch/generic/mmu.cc
+++ b/src/arch/generic/mmu.cc
@@ -153,15 +153,6 @@
range.paddr = req->getPaddr();
}
-TranslationGenPtr
-BaseMMU::translateFunctional(Addr start, Addr size, ThreadContext *tc,
-BaseMMU::Mode mode, Request::Flags flags)
-{
-return TranslationGenPtr(new MMUTranslationGen(
-tc->getSystemPtr()->getPageBytes(), start, size, tc, this,
-mode, flags));
-}
-
void
BaseMMU::takeOverFrom(BaseMMU *old_mmu)
{
diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index 92752ec..57af5f5 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -142,7 +142,7 @@
};
virtual TranslationGenPtr translateFunctional(Addr start, Addr size,
-ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags);
+ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags) =
0;
virtual Fault
finalizePhysical(const RequestPtr , ThreadContext *tc,
diff --git a/src/arch/mips/mmu.hh b/src/arch/mips/mmu.hh
index 13ea937..f20c99c 100644
--- a/src/arch/mips/mmu.hh
+++ b/src/arch/mips/mmu.hh
@@ -39,7 +39,7 @@
#define __ARCH_MIPS_MMU_HH__
#include "arch/generic/mmu.hh"
-
+#include "arch/mips/page_size.hh"
#include "params/MipsMMU.hh"
namespace gem5
@@ -53,6 +53,14 @@
MMU(const MipsMMUParams )
: BaseMMU(p)
{}
+
+TranslationGenPtr
+translateFunctional(Addr start, Addr size, ThreadContext *tc,
+Mode mode, Request::Flags flags) override
+{
+return TranslationGenPtr(new MMUTranslationGen(
+PageBytes, start, size, tc, this, mode, flags));
+}
};
} // namespace MipsISA
diff --git a/src/arch/power/mmu.hh b/src/arch/power/mmu.hh
index 8507e4e..c82ced9 100644
--- a/src/arch/power/mmu.hh
+++ b/src/arch/power/mmu.hh
@@ -39,7 +39,7 @@
#define __ARCH_POWER_MMU_HH__
#include "arch/generic/mmu.hh"
-
+#include "arch/power/page_size.hh"
#include "params/PowerMMU.hh"
namespace gem5
@@ -53,6 +53,14 @@
MMU(const PowerMMUParams )
: BaseMMU(p)
{}
+
+TranslationGenPtr
+translateFunctional(Addr start, Addr size, ThreadContext *tc,
+Mode mode, Request::Flags flags) override
+{
+return TranslationGenPtr(new MMUTranslationGen(
+PageBytes, start, size, tc, this, mode, flags));
+}
};
} // namespace PowerISA
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index b0e645c..f8afaa7 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -40,6 +40,7 @@
#include "arch/generic/mmu.hh"
#include "arch/riscv/isa.hh"
+#include "arch/riscv/page_size.hh"
#include "arch/riscv/pma_checker.hh"
#include "arch/riscv/tlb.hh"
@@ -59,6 +60,14 @@
: BaseMMU(p), pma(p.pma_checker)
{}
+TranslationGenPtr
+translateFunctional(Addr start, Addr size, ThreadContext *tc,
+Mode mode, Request::Flags flags) override
+{
+return TranslationGenPtr(new MMUTranslationGen(
+PageBytes, start, size, tc, this, mode, flags));
+}
+
PrivilegeMode
getMemPriv(ThreadContext *tc, BaseMMU::Mode mode)
{
diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh
index c9bb539..e80f08d 100644
--- a/src/arch/sparc/mmu.hh
+++ b/src/arch/sparc/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_SPARC_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/sparc/page_size.hh"
#include
[gem5-dev] Change in gem5/gem5[develop]: mem: Add a translation gen helper class.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50758 )
Change subject: mem: Add a translation gen helper class.
..
mem: Add a translation gen helper class.
This class helps translate a region of memory one chunk at a time. The
generator returns an iterator through its begin and end methods which
can be used as part of a regular for loop, or as part of a range based
for loop. The iterator points to a Range object which holds the virtual
and physical address of the translation, the size of the region included
in the translation, and a Fault if the translation of that chunk
faulted.
When incrementing the iterator, if there was no fault it simply moves
ahead to the next region and attempts to translate it using a virtual
method implemented by subclasses. It's up to the subclass to determine
if there is now a fault, how many bytes have been translated if, for
instance, the page size is variable, and what the translated physical
address is.
If there was a fault, the iterator does not increment, it just clears
the fault and tries the previous translation again. This gives consumers
of the translation generator a chance to fix up faulting addresses
without having to abort the whole process and try again. This might be
useful if, for instance, you've reached the end of the stack and a new
page needs to be demand-paged in.
Change-Id: I8c4023845d989fe3781b1b73ab12f7c8855c9171
---
A src/mem/translation_gen.hh
1 file changed, 192 insertions(+), 0 deletions(-)
diff --git a/src/mem/translation_gen.hh b/src/mem/translation_gen.hh
new file mode 100644
index 000..36aea2c
--- /dev/null
+++ b/src/mem/translation_gen.hh
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_TRANSLATION_GEN_HH__
+#define __MEM_TRANSLATION_GEN_HH__
+
+#include
+#include
+
+#include "base/types.hh"
+#include "sim/faults.hh"
+
+namespace gem5
+{
+
+class TranslationGenConstIterator;
+
+class TranslationGen
+{
+ public:
+struct Range
+{
+Addr vaddr;
+Addr size = 0;
+
+Addr paddr = 0;
+Fault fault = NoFault;
+
+bool
+operator == (const Range ) const
+{
+return other.vaddr == vaddr && other.size == size &&
+other.paddr == paddr && other.fault == fault;
+}
+};
+
+ protected:
+virtual void translate(Range ) const = 0;
+
+Addr _start;
+Addr _size;
+
+ public:
+TranslationGen(Addr new_start, Addr new_size) :
+_start(new_start), _size(new_size)
+{}
+virtual ~TranslationGen() {}
+
+Addr start() const { return _start; }
+Addr size() const { return _size; }
+
+friend class TranslationGenConstIterator;
+using const_iterator = TranslationGenConstIterator;
+
+inline const_iterator begin() const;
+inline const_iterator end() const;
+};
+
+using TranslationGenPtr = std::unique_ptr;
+
+class TranslationGenConstIterator
+{
+ private:
+TranslationGen::Range current = {0};
+const TranslationGen *gen = nullptr;
+bool end = true;
+
+friend class TranslationGen;
+
+TranslationGenConstIterator() {}
+TranslationGenConstIterator(const TranslationGen *parent, Addr start) :
+current{start}, gen(parent), end(false)
+{}
+
+bool
+done()
+{
+assert(gen);
+return current.vaddr >= gen->start() + gen->size();
+}
+
+
[gem5-dev] Change in gem5/gem5[develop]: misc: Remove include of arch/page_size.hh, and fix up includes.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50765 ) Change subject: misc: Remove include of arch/page_size.hh, and fix up includes. .. misc: Remove include of arch/page_size.hh, and fix up includes. Remove the only remaining use of arch/page_size.hh, and fix up a couple files which were using one of the constants defined in a specific arch version of it without including the file they needed directly. Change-Id: I6da5638ca10c788bd42197f4f5180e6b66f7b87f --- M src/arch/arm/system.hh M src/arch/riscv/pagetable_walker.cc M src/dev/arm/generic_timer.cc M src/gpu-compute/gpu_compute_driver.cc M src/sim/system.hh 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh index f2ec5c3..a163ee4 100644 --- a/src/arch/arm/system.hh +++ b/src/arch/arm/system.hh @@ -45,6 +45,7 @@ #include #include +#include "arch/arm/page_size.hh" #include "kern/linux/events.hh" #include "params/ArmSystem.hh" #include "sim/full_system.hh" diff --git a/src/arch/riscv/pagetable_walker.cc b/src/arch/riscv/pagetable_walker.cc index bc15524..08767c2 100644 --- a/src/arch/riscv/pagetable_walker.cc +++ b/src/arch/riscv/pagetable_walker.cc @@ -53,6 +53,7 @@ #include #include "arch/riscv/faults.hh" +#include "arch/riscv/page_size.hh" #include "arch/riscv/pagetable.hh" #include "arch/riscv/tlb.hh" #include "base/bitfield.hh" diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc index 52f41fe..ba46fcd 100644 --- a/src/dev/arm/generic_timer.cc +++ b/src/dev/arm/generic_timer.cc @@ -39,6 +39,7 @@ #include +#include "arch/arm/page_size.hh" #include "arch/arm/system.hh" #include "arch/arm/utility.hh" #include "base/logging.hh" diff --git a/src/gpu-compute/gpu_compute_driver.cc b/src/gpu-compute/gpu_compute_driver.cc index 3adfadd..1069220 100644 --- a/src/gpu-compute/gpu_compute_driver.cc +++ b/src/gpu-compute/gpu_compute_driver.cc @@ -35,6 +35,7 @@ #include +#include "arch/x86/page_size.hh" #include "base/compiler.hh" #include "base/logging.hh" #include "base/trace.hh" diff --git a/src/sim/system.hh b/src/sim/system.hh index f25d279..7aeeea7 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -48,7 +48,6 @@ #include #include -#include "arch/page_size.hh" #include "base/loader/memory_image.hh" #include "base/loader/symtab.hh" #include "base/statistics.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50765 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6da5638ca10c788bd42197f4f5180e6b66f7b87f Gerrit-Change-Number: 50765 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Add a translation generator function to EmulationPageTable.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50762 )
Change subject: mem: Add a translation generator function to
EmulationPageTable.
..
mem: Add a translation generator function to EmulationPageTable.
This lets the caller iterate over translated address ranges over the
requested total virtual address region.
Change-Id: I50bd59bdbb12c055fa9ace9b1d5ff972e382cb85
---
M src/mem/page_table.cc
M src/mem/page_table.hh
2 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 57707a5..d715e07 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -169,6 +169,20 @@
}
void
+EmulationPageTable::PageTableTranslationGen::translate(Range ) const
+{
+const Addr page_size = pt->pageSize();
+
+Addr next = roundUp(range.vaddr, page_size);
+if (next == range.vaddr)
+next += page_size;
+range.size = std::min(range.size, next - range.vaddr);
+
+if (!pt->translate(range.vaddr, range.paddr))
+range.fault = Fault(new GenericPageTableFault(range.vaddr));
+}
+
+void
EmulationPageTable::serialize(CheckpointOut ) const
{
ScopedCheckpointSection sec(cp, "ptable");
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index c115a41..a17250c 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -42,6 +42,7 @@
#include "base/intmath.hh"
#include "base/types.hh"
#include "mem/request.hh"
+#include "mem/translation_gen.hh"
#include "sim/serialize.hh"
namespace gem5
@@ -153,7 +154,32 @@
* @param vaddr The virtual address.
* @return True if translation exists
*/
-bool translate(Addr vaddr) { Addr dummy; return translate(vaddr,
dummy); }
+bool
+translate(Addr vaddr)
+{
+Addr dummy;
+return translate(vaddr, dummy);
+}
+
+class PageTableTranslationGen : public TranslationGen
+{
+ private:
+EmulationPageTable *pt;
+
+void translate(Range ) const override;
+
+ public:
+PageTableTranslationGen(EmulationPageTable *_pt, Addr vaddr,
+Addr size) : TranslationGen(vaddr, size), pt(_pt)
+{}
+};
+
+TranslationGenPtr
+translateRange(Addr vaddr, Addr size)
+{
+return TranslationGenPtr(
+new PageTableTranslationGen(this, vaddr, size));
+}
/**
* Perform a translation on the memory request, fills in paddr
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50762
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I50bd59bdbb12c055fa9ace9b1d5ff972e382cb85
Gerrit-Change-Number: 50762
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Use the MMU's translation generator in translating proxies.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50760 )
Change subject: mem: Use the MMU's translation generator in translating
proxies.
..
mem: Use the MMU's translation generator in translating proxies.
Use the more flexible MMU translation generator which does not need to
be told what page size to use, and which will be able to do flexible
things like translate across varying page sizes.
Change-Id: Ibfefc39d833f37bc35d703c505b193ea68988ab0
---
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/mem/translating_port_proxy.cc
M src/mem/translating_port_proxy.hh
4 files changed, 57 insertions(+), 74 deletions(-)
diff --git a/src/mem/se_translating_port_proxy.cc
b/src/mem/se_translating_port_proxy.cc
index 1a5fe96..8f4544c 100644
--- a/src/mem/se_translating_port_proxy.cc
+++ b/src/mem/se_translating_port_proxy.cc
@@ -52,15 +52,17 @@
{}
bool
-SETranslatingPortProxy::fixupAddr(Addr addr, BaseMMU::Mode mode) const
+SETranslatingPortProxy::fixupRange(const TranslationGen::Range ,
+BaseMMU::Mode mode) const
{
auto *process = _tc->getProcessPtr();
if (mode == BaseMMU::Write) {
if (allocating == Always) {
-process->allocateMem(roundDown(addr, pageBytes), pageBytes);
+process->allocateMem(range.vaddr, range.size);
return true;
-} else if (allocating == NextPage && process->fixupFault(addr)) {
+} else if (allocating == NextPage &&
+process->fixupFault(range.vaddr)) {
// We've accessed the next page on the stack.
return true;
}
diff --git a/src/mem/se_translating_port_proxy.hh
b/src/mem/se_translating_port_proxy.hh
index f46cfe4..0d7af4a 100644
--- a/src/mem/se_translating_port_proxy.hh
+++ b/src/mem/se_translating_port_proxy.hh
@@ -61,7 +61,8 @@
AllocType allocating;
protected:
-bool fixupAddr(Addr addr, BaseMMU::Mode mode) const override;
+bool fixupRange(const TranslationGen::Range ,
+BaseMMU::Mode mode) const override;
public:
SETranslatingPortProxy(ThreadContext *tc, AllocType alloc=NextPage,
diff --git a/src/mem/translating_port_proxy.cc
b/src/mem/translating_port_proxy.cc
index 466b778..8ab859f 100644
--- a/src/mem/translating_port_proxy.cc
+++ b/src/mem/translating_port_proxy.cc
@@ -56,87 +56,69 @@
TranslatingPortProxy::TranslatingPortProxy(
ThreadContext *tc, Request::Flags _flags) :
-PortProxy(tc, tc->getSystemPtr()->cacheLineSize()), _tc(tc),
- pageBytes(tc->getSystemPtr()->getPageBytes()),
- flags(_flags)
+PortProxy(tc, tc->getSystemPtr()->cacheLineSize()), _tc(tc),
flags(_flags)
{}
bool
-TranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseMMU::Mode mode) const
+TranslatingPortProxy::tryOnBlob(BaseMMU::Mode mode, TranslationGenPtr gen,
+std::function func) const
{
-BaseMMU *mmu = _tc->getMMUPtr();
-return mmu->translateFunctional(req, _tc, mode) == NoFault ||
- mmu->translateFunctional(req, _tc, BaseMMU::Execute) == NoFault;
-}
+// Wether we're trying to get past a fault.
+bool faulting = false;
+for (const auto : *gen) {
+// Was there a fault this time?
+if (range.fault) {
+// If there was a fault last time too, or the fixup this time
+// fails, then the operation has failed.
+if (faulting || !fixupRange(range, mode))
+return false;
+// This must be the first time we've tried this translation, so
+// record that we're making a second attempt and continue.
+faulting = true;
+continue;
+}
-bool
-TranslatingPortProxy::tryTLBs(RequestPtr req, BaseMMU::Mode mode) const
-{
-// If at first this doesn't succeed, try to fixup and translate again.
If
-// it still fails, report failure.
-return tryTLBsOnce(req, mode) ||
-(fixupAddr(req->getVaddr(), mode) && tryTLBsOnce(req, mode));
+// Run func() on this successful translation.
+faulting = false;
+func(range);
+}
+return true;
}
bool
TranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
{
-for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
- gen.next())
-{
-auto req = std::make_shared(
-gen.addr(), gen.size(), flags, Request::funcRequestorId, 0,
-_tc->contextId());
-
-if (!tryTLBs(req, BaseMMU::Read))
-return false;
-
-PortProxy::readBlobPhys(
-req->getPaddr(), req->getFlags(), p, gen.size());
-
-p = static_cast(p) + gen.size();
-}
-return true;
+constexpr auto mode = BaseMMU::Read;
+return tryOnBlob(mode, _tc->getMMUPtr()->translateFunctional(
+addr, size, _tc, mode, flags),
+
[gem5-dev] Change in gem5/gem5[develop]: arch: Add a MMUTranslationGen class to the BaseMMU.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50759 )
Change subject: arch: Add a MMUTranslationGen class to the BaseMMU.
..
arch: Add a MMUTranslationGen class to the BaseMMU.
This translation generator is returned by the new version of the
TranslateFunctional method which translates a region rather than a
single address. That method is currently virtual with a default
implementation which is not overloaded, but the plan is for the other
MMUs to override that method and inject their own page size minimally.
In the future, the MMUTranslationGen class and the implementations in
the MMUs may be updated so that they can, for instance, handle varying
page sizes across a single translation.
Change-Id: I39479f0f0e8150fc6e3e1a7097a0c8bd8d22d4e0
---
M src/arch/generic/mmu.cc
M src/arch/generic/mmu.hh
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/src/arch/generic/mmu.cc b/src/arch/generic/mmu.cc
index 1d2f2b7..3d1de81 100644
--- a/src/arch/generic/mmu.cc
+++ b/src/arch/generic/mmu.cc
@@ -43,6 +43,8 @@
#include "arch/generic/mmu.hh"
#include "arch/generic/tlb.hh"
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
namespace gem5
{
@@ -126,6 +128,40 @@
return getTlb(mode)->finalizePhysical(req, tc, mode);
}
+BaseMMU::MMUTranslationGen::MMUTranslationGen(Addr page_bytes,
+Addr new_start, Addr new_size, ThreadContext *new_tc,
+BaseMMU *new_mmu, BaseMMU::Mode new_mode, Request::Flags
new_flags) :
+TranslationGen(new_start, new_size), tc(new_tc), cid(tc->contextId()),
+mmu(new_mmu), mode(new_mode), flags(new_flags),
+pageBytes(page_bytes)
+{}
+
+void
+BaseMMU::MMUTranslationGen::translate(Range ) const
+{
+Addr next = roundUp(range.vaddr, pageBytes);
+if (next == range.vaddr)
+next += pageBytes;
+range.size = std::min(range.size, next - range.vaddr);
+
+auto req = std::make_shared(
+range.vaddr, range.size, flags, Request::funcRequestorId, 0,
cid);
+
+range.fault = mmu->translateFunctional(req, tc, mode);
+
+if (range.fault == NoFault)
+range.paddr = req->getPaddr();
+}
+
+TranslationGenPtr
+BaseMMU::translateFunctional(Addr start, Addr size, ThreadContext *tc,
+BaseMMU::Mode mode, Request::Flags flags)
+{
+return TranslationGenPtr(new MMUTranslationGen(
+tc->getSystemPtr()->getPageBytes(), start, size, tc, this,
+mode, flags));
+}
+
void
BaseMMU::takeOverFrom(BaseMMU *old_mmu)
{
diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index e12ad6f..92752ec 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -40,8 +40,9 @@
#include
-#include "params/BaseMMU.hh"
#include "mem/request.hh"
+#include "mem/translation_gen.hh"
+#include "params/BaseMMU.hh"
#include "sim/sim_object.hh"
namespace gem5
@@ -122,6 +123,27 @@
translateFunctional(const RequestPtr , ThreadContext *tc,
Mode mode);
+class MMUTranslationGen : public TranslationGen
+{
+ private:
+ThreadContext *tc;
+ContextID cid;
+BaseMMU *mmu;
+BaseMMU::Mode mode;
+Request::Flags flags;
+const Addr pageBytes;
+
+void translate(Range ) const override;
+
+ public:
+MMUTranslationGen(Addr page_bytes, Addr new_start, Addr new_size,
+ThreadContext *new_tc, BaseMMU *new_mmu,
+BaseMMU::Mode new_mode, Request::Flags new_flags);
+};
+
+virtual TranslationGenPtr translateFunctional(Addr start, Addr size,
+ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags);
+
virtual Fault
finalizePhysical(const RequestPtr , ThreadContext *tc,
Mode mode) const;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50759
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I39479f0f0e8150fc6e3e1a7097a0c8bd8d22d4e0
Gerrit-Change-Number: 50759
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev,gpu-compute: Use a TranslationGen in DmaVirtDevice.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50763 )
Change subject: dev,gpu-compute: Use a TranslationGen in DmaVirtDevice.
..
dev,gpu-compute: Use a TranslationGen in DmaVirtDevice.
Use a TranslationGen to iterate over the translations for a region,
rather than using a ChunkGenerator with a fixed page size the device
needs to know.
Change-Id: I5da565232bd5282074ef279ca74e556daeffef70
---
M src/dev/dma_virt_device.cc
M src/dev/dma_virt_device.hh
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
M src/gpu-compute/gpu_command_processor.cc
M src/gpu-compute/gpu_command_processor.hh
6 files changed, 24 insertions(+), 36 deletions(-)
diff --git a/src/dev/dma_virt_device.cc b/src/dev/dma_virt_device.cc
index 2a392c24..e3e5050 100644
--- a/src/dev/dma_virt_device.cc
+++ b/src/dev/dma_virt_device.cc
@@ -36,11 +36,6 @@
namespace gem5
{
-DmaVirtDevice::DmaVirtDevice(const Params& p)
-: DmaDevice(p), pageBytes(p.system->getPageBytes())
-{
-}
-
void
DmaVirtDevice::dmaReadVirt(Addr host_addr, unsigned size,
DmaCallback *cb, void *data, Tick delay)
@@ -68,17 +63,12 @@
// move the buffer data pointer with the chunks
uint8_t *loc_data = (uint8_t*)data;
-for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
gen.next()) {
-Addr phys;
-
-// translate pages into their corresponding frames
-translateOrDie(gen.addr(), phys);
+for (const auto : *translate(addr, size)) {
+fatal_if(range.fault, "Failed translation: vaddr 0x%x",
range.vaddr);
Event *event = cb ? cb->getChunkEvent() : nullptr;
-
-(this->*dmaFn)(phys, gen.size(), event, loc_data, delay);
-
-loc_data += gen.size();
+(this->*dmaFn)(range.paddr, range.size, event, loc_data, delay);
+loc_data += range.size;
}
}
diff --git a/src/dev/dma_virt_device.hh b/src/dev/dma_virt_device.hh
index 5c36d7b..0563525 100644
--- a/src/dev/dma_virt_device.hh
+++ b/src/dev/dma_virt_device.hh
@@ -35,6 +35,7 @@
#define __DEV_DMA_VIRT_DEVICE_HH__
#include "dev/dma_device.hh"
+#include "mem/translation_gen.hh"
namespace gem5
{
@@ -72,7 +73,7 @@
};
public:
-DmaVirtDevice(const Params& p);
+DmaVirtDevice(const Params& p) : DmaDevice(p) { }
virtual ~DmaVirtDevice() { }
/**
@@ -119,13 +120,15 @@
DmaCallback *cb, void *data, Tick delay = 0);
/**
- * Function used to translate from virtual to physical addresses. All
- * classes inheriting from DmaVirtDevice must define this.
+ * Function used to translate a range of addresses from virtual to
+ * physical addresses. All classes inheriting from DmaVirtDevice must
+ * define this.
*
- * @param vaddr Input virtual address
- * @param paddr Output physical address written by reference
+ * @param vaddr Virtual address of the start of the range
+ * @param size Size of the range in bytes
+ * @return A translation generator for this range
*/
-virtual void translateOrDie(Addr vaddr, Addr ) = 0;
+virtual TranslationGenPtr translate(Addr vaddr, Addr size) = 0;
};
} // namespace gem5
diff --git a/src/dev/hsa/hsa_packet_processor.cc
b/src/dev/hsa/hsa_packet_processor.cc
index 0427def..f15b691 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -159,16 +159,15 @@
return pioDelay;
}
-void
-HSAPacketProcessor::translateOrDie(Addr vaddr, Addr )
+TranslationGenPtr
+HSAPacketProcessor::translate(Addr vaddr, Addr size)
{
// Grab the process and try to translate the virtual address with it;
with
// new extensions, it will likely be wrong to just arbitrarily grab
context
// zero.
auto process = sys->threads[0]->getProcessPtr();
-if (!process->pTable->translate(vaddr, paddr))
-fatal("failed translation: vaddr 0x%x\n", vaddr);
+return process->pTable->translateRange(vaddr, size);
}
/**
diff --git a/src/dev/hsa/hsa_packet_processor.hh
b/src/dev/hsa/hsa_packet_processor.hh
index 9545006..8191e32 100644
--- a/src/dev/hsa/hsa_packet_processor.hh
+++ b/src/dev/hsa/hsa_packet_processor.hh
@@ -321,7 +321,7 @@
typedef HSAPacketProcessorParams Params;
HSAPacketProcessor(const Params );
~HSAPacketProcessor();
-void translateOrDie(Addr vaddr, Addr ) override;
+TranslationGenPtr translate(Addr vaddr, Addr size) override;
void setDeviceQueueDesc(uint64_t hostReadIndexPointer,
uint64_t basePointer,
uint64_t queue_id,
diff --git a/src/gpu-compute/gpu_command_processor.cc
b/src/gpu-compute/gpu_command_processor.cc
index 88d7703..a444c9d 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -65,19 +65,15 @@
return
[gem5-dev] Change in gem5/gem5[develop]: misc: Include static_inst_fwd.hh in sim/faults.hh.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50756 ) Change subject: misc: Include static_inst_fwd.hh in sim/faults.hh. .. misc: Include static_inst_fwd.hh in sim/faults.hh. We only need a StaticInstPtr type, so we don't need to include all of static_inst.hh. Also fix up some other files which were including some other things transitively through sim/faults.hh. Change-Id: I912a84963f33d99617f57d59517c402326f7a494 --- M src/arch/generic/debugfaults.hh M src/cpu/o3/comm.hh M src/sim/faults.hh 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/generic/debugfaults.hh b/src/arch/generic/debugfaults.hh index d3886e0..f54bd7c 100644 --- a/src/arch/generic/debugfaults.hh +++ b/src/arch/generic/debugfaults.hh @@ -42,6 +42,7 @@ #include "base/logging.hh" #include "cpu/null_static_inst.hh" +#include "cpu/static_inst.hh" #include "cpu/thread_context.hh" #include "sim/faults.hh" diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index 013ef99..fc10848 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -46,6 +46,7 @@ #include "arch/pcstate.hh" #include "base/types.hh" +#include "config/the_isa.hh" #include "cpu/inst_seq.hh" #include "cpu/o3/dyn_inst_ptr.hh" #include "cpu/o3/limits.hh" diff --git a/src/sim/faults.hh b/src/sim/faults.hh index b1c358c..d2e091e 100644 --- a/src/sim/faults.hh +++ b/src/sim/faults.hh @@ -43,7 +43,7 @@ #include "base/types.hh" #include "cpu/null_static_inst.hh" -#include "cpu/static_inst.hh" +#include "cpu/static_inst_fwd.hh" #include "mem/htm.hh" #include "sim/stats.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50756 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I912a84963f33d99617f57d59517c402326f7a494 Gerrit-Change-Number: 50756 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Align process memory allocations.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50757 )
Change subject: sim: Align process memory allocations.
..
sim: Align process memory allocations.
Align allocation requests in Process::allocateMem to page boundaries,
rather than assume that they already are. This frees the caller from
having to know what boundary to align things to. The older version would
make the caller more aware of the extent of the allocation in theory,
but in reality the caller would just blindly perform the alignment like
this function is anyway.
Change-Id: I897714d4481d961255a9e44ae080135e507be199
---
M src/sim/process.cc
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 71bb494..3a631a5 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -316,6 +316,10 @@
void
Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
+const auto page_size = pTable->pageSize();
+
+const Addr page_addr = roundDown(vaddr, page_size);
+
// Check if the page has been mapped by other cores if not to clobber.
// When running multithreaded programs in SE-mode with DerivO3CPU
model,
// there are cases where two or more cores have page faults on the same
@@ -324,16 +328,17 @@
// a physical page frame to map with the virtual page. Other cores can
// return if the page has been mapped and `!clobber`.
if (!clobber) {
-const EmulationPageTable::Entry *pte = pTable->lookup(vaddr);
+const EmulationPageTable::Entry *pte = pTable->lookup(page_addr);
if (pte) {
warn("Process::allocateMem: addr %#x already mapped\n", vaddr);
return;
}
}
-int npages = divCeil(size, pTable->pageSize());
-Addr paddr = seWorkload->allocPhysPages(npages);
-pTable->map(vaddr, paddr, size,
+const int npages = divCeil(size, page_size);
+const Addr paddr = seWorkload->allocPhysPages(npages);
+const Addr pages_size = npages * page_size;
+pTable->map(page_addr, paddr, pages_size,
clobber ? EmulationPageTable::Clobber :
EmulationPageTable::MappingFlags(0));
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50757
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I897714d4481d961255a9e44ae080135e507be199
Gerrit-Change-Number: 50757
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] failing ARM dual CPU tests?
Hi folks. When I run the test script main.py locally on an otherwise passing tree, I get 8 test failures. 6 of those are from x86 dynamic linking tests which use a host library which uses a system call gem5 doesn't implement. That is annoying, but I understand that problem. The other 2 are from ARM dual CPU tests (like realview64-simple-timing-dual-ARM-x86_64-opt-MatchFileRegex) which fail because the second CPU doesn't come up, and the check doesn't see the message it expects. This is very surprising to me, since I don't think these tests would have any host dependence, and I'm *pretty* sure that the files they use would come from the resources thing and should be up to date, etc. The system in the test seems to otherwise boot up, it's just that the second CPU never comes online and linux prints an error message about it instead of the normal one. Does anybody know of something else I can try to update, etc, which might fix these tests? Could there be stale system files it's using floating around somewhere? I would really like to get that sorted out, since that could affect whether I can successfully test my locked memory helper function change, since the earlier version of that had caused problems with O3 multi-CPU tests for ARM, sort of right in line with this false positive on these tests. Thanks! Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Add GCC-11 to the compiler tests
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50749 )
Change subject: tests: Add GCC-11 to the compiler tests
..
tests: Add GCC-11 to the compiler tests
Change-Id: I3701e850433b597fb0d6d06e058a21607e4efc88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50749
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M tests/compiler-tests.sh
1 file changed, 3 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index bf1d281..699d134 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -10,7 +10,8 @@
build_dir="${gem5_root}/build"
# All Docker images in the gem5 testing GCR which we want to compile with.
-images=("gcc-version-10"
+images=("gcc-version-11"
+"gcc-version-10"
"gcc-version-9"
"gcc-version-8"
"gcc-version-7"
@@ -29,7 +30,7 @@
# A subset of the above list: these images will build against every target,
# ignoring builds_per_compiler.
-comprehensive=("gcc-version-10"
+comprehensive=("gcc-version-11")
"clang-version-11")
# All build targets in build_opt/ which we want to build using each image.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50749
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3701e850433b597fb0d6d06e058a21607e4efc88
Gerrit-Change-Number: 50749
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add a GCC-11 Dockerfile
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50748 ) Change subject: util-docker: Add a GCC-11 Dockerfile .. util-docker: Add a GCC-11 Dockerfile This can be built to create an image that uses the GCC-11 compiler. At present GCC-11 cannot be installed using APT by default. This Dockerfile uses a special APT repository to do this and is therefore a separate Dockerfile to the other GCC version targets. Change-Id: Iafee92415d9047eedf3586c78722f973010f6050 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50748 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile 1 file changed, 52 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile b/util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile new file mode 100644 index 000..4effd9c --- /dev/null +++ b/util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile @@ -0,0 +1,52 @@ +# Copyright (c) 2021 The Regents of the University of California +# All Rights Reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +FROM ubuntu:20.04 + +# At the time of this Dockerfile's creation, Ubuntu 20.04 APT does not +# distribute gcc-11 by default. A special APT repository is needed. We hope +# this Dockerfile will merge with ubuntu-20.04_gcc-version once GCC-11 can be +# installed via APT more easily. + +ENV DEBIAN_FRONTEND=noninteractive +RUN apt -y update +RUN apt -y upgrade +RUN apt -y install git m4 scons zlib1g zlib1g-dev libprotobuf-dev \ +protobuf-compiler libprotoc-dev libgoogle-perftools-dev python3-dev \ +python3-six python-is-python3 doxygen libboost-all-dev libhdf5-serial-dev \ +python3-pydot libpng-dev make software-properties-common + +RUN add-apt-repository \ +'deb http://mirrors.kernel.org/ubuntu hirsute main universe' +RUN apt -y install gcc-11 g++-11 + +RUN update-alternatives --install \ +/usr/bin/g++ g++ /usr/bin/g++-11 100 +RUN update-alternatives --install \ +/usr/bin/gcc gcc /usr/bin/gcc-11 100 +RUN update-alternatives --install \ +/usr/bin/c++ c++ /usr/bin/g++-11 100 +RUN update-alternatives --install \ +/usr/bin/cc cc /usr/bin/gcc-11 100 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50748 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iafee92415d9047eedf3586c78722f973010f6050 Gerrit-Change-Number: 50748 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: misc: Update gem5's README file.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50755 ) Change subject: misc: Update gem5's README file. .. misc: Update gem5's README file. Remove references to alpha and SWIG. Change the list of configs to be a list of configs and not ISAs even though they are frequently named after the ISA, say that the options are in build_opts, add in missing top level directories, update and generalize the description of full system, re-wrap some text. Change-Id: Id2fb9323dcb9d8bf8e86c78fb5e9aa6afed1c5b8 --- M README 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/README b/README index e24e7a3..554624e 100644 --- a/README +++ b/README @@ -8,29 +8,33 @@ http://www.gem5.org/documentation/learning_gem5/introduction. To build gem5, you will need the following software: g++ or clang, -Python (gem5 links in the Python interpreter), SCons, SWIG, zlib, m4, -and lastly protobuf if you want trace capture and playback -support. Please see http://www.gem5.org/documentation/general_docs/building -for more details concerning the minimum versions of the aforementioned tools. +Python (gem5 links in the Python interpreter), SCons, zlib, m4, and lastly +protobuf if you want trace capture and playback support. Please see +http://www.gem5.org/documentation/general_docs/building for more details +concerning the minimum versions of these tools. Once you have all dependencies resolved, type 'scons -build//gem5.opt' where ARCH is one of ARM, NULL, MIPS, POWER, SPARC, -or X86. This will build an optimized version of the gem5 binary (gem5.opt) -for the the specified architecture. See -http://www.gem5.org/documentation/general_docs/building for more details and -options. +build//gem5.opt' where CONFIG is one of the options in build_opts like +ARM, NULL, MIPS, POWER, SPARC, X86, Garnet_standalone, etc. This will build an +optimized version of the gem5 binary (gem5.opt) with the the specified +configuration. See http://www.gem5.org/documentation/general_docs/building for +more details and options. -The basic source release includes these subdirectories: +The main source tree includes these subdirectories: + - build_opts: pre-made default configurations for gem5 + - build_tools: tools used internally by gem5's build process. - configs: example simulation configuration scripts - ext: less-common external packages needed to build gem5 + - include: include files for use in other programs + - site_scons: modular components of the build system - src: source code of the gem5 simulator - system: source for some optional system software for simulated systems - tests: regression tests - util: useful utility programs and files -To run full-system simulations, you will need compiled system firmware -(console and PALcode for Alpha), kernel binaries and one or more disk -images. +To run full-system simulations, you may need compiled system firmware, kernel +binaries and one or more disk images, depending on gem5's configuration and +what type of workload you're trying to run. If you have questions, please send mail to gem5-us...@gem5.org -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50755 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id2fb9323dcb9d8bf8e86c78fb5e9aa6afed1c5b8 Gerrit-Change-Number: 50755 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Make disk image optional for riscv-board
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50754 )
Change subject: python: Make disk image optional for riscv-board
..
python: Make disk image optional for riscv-board
This resource allows booting Linux without using a disk image.
https://gem5-review.googlesource.com/c/public/gem5-resources/+/50547
Change-Id: I15723e3c22ce116660767068e75da7920c7b8be2
Signed-off-by: Hoa Nguyen
---
M src/python/gem5/components/boards/riscv_board.py
1 file changed, 40 insertions(+), 26 deletions(-)
diff --git a/src/python/gem5/components/boards/riscv_board.py
b/src/python/gem5/components/boards/riscv_board.py
index 2cc151d..7b3c2af 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -84,6 +84,7 @@
processor: AbstractProcessor,
memory: AbstractMemorySystem,
cache_hierarchy: AbstractCacheHierarchy,
+use_disk_image: bool = True
) -> None:
super().__init__(clk_freq, processor, memory, cache_hierarchy)
@@ -110,17 +111,20 @@
self.iobus = IOXBar()
# The virtio disk
-self.disk = MmioVirtIO(
-vio=VirtIOBlock(),
-interrupt_id=0x8,
-pio_size=4096,
-pio_addr=0x10008000,
-)
+if use_disk_image:
+self.disk = MmioVirtIO(
+vio=VirtIOBlock(),
+interrupt_id=0x8,
+pio_size=4096,
+pio_addr=0x10008000,
+)
# Note: This overrides the platform's code because the platform
isn't
# general enough.
self._on_chip_devices = [self.platform.clint, self.platform.plic]
-self._off_chip_devices = [self.platform.uart, self.disk]
+self._off_chip_devices = [self.platform.uart]
+if use_disk_image:
+self._off_chip_devices.append(self.disk)
def _setup_io_devices(self) -> None:
"""Connect the I/O devices to the I/O bus"""
@@ -175,7 +179,9 @@
memory.set_memory_range(self.mem_ranges)
def set_workload(
-self, bootloader: AbstractResource, disk_image: AbstractResource,
+self, bootloader: AbstractResource,
+disk_image: Optional[AbstractResource],
+kernel_boot_params: Optional[str] = "console=ttyS0 root=/dev/vda
ro",
command: Optional[str] = None
) -> None:
"""Setup the full system files
@@ -199,18 +205,24 @@
with the kernel as a payload
:param disk_image: The resource encapsulating the disk image
containing
the OS data. The first partition should be the root partition.
+:param kernel_boot_params: The options for booting a Linux kernel.
+More information about options is available at
+
www.kernel.org/doc/html/latest/admin-guide/kernel-parameters.html
:param command: The command(s) to run with bash once the OS is
booted
"""
self.workload.object_file = bootloader.get_local_path()
-image = CowDiskImage(
-child=RawDiskImage(read_only=True), read_only=False
-)
-image.child.image_file = disk_image.get_local_path()
-self.disk.vio.image = image
+use_disk_image = not (disk_image == None)
-self.workload.command_line = "console=ttyS0 root=/dev/vda ro"
+if use_disk_image:
+image = CowDiskImage(
+child=RawDiskImage(read_only=True), read_only=False
+)
+image.child.image_file = disk_image.get_local_path()
+self.disk.vio.image = image
+
+self.workload.command_line = kernel_boot_params
# Note: This must be called after set_workload because it looks
for an
# attribute named "disk" and connects
@@ -224,12 +236,12 @@
# We need to wait to generate the device tree until after the disk
is
# set up. Now that the disk and workload are set, we can generate
the
# device tree file.
-self.generate_device_tree(m5.options.outdir)
+self.generate_device_tree(m5.options.outdir, use_disk_image)
self.workload.dtb_filename = os.path.join(
m5.options.outdir, "device.dtb"
)
-def generate_device_tree(self, outdir: str) -> None:
+def generate_device_tree(self, outdir: str, use_disk_image: bool) ->
None:
"""Creates the dtb and dts files.
Creates two files in the outdir: 'device.dtb' and 'device.dts'
@@ -360,16 +372,18 @@
soc_node.append(uart_node)
# VirtIO MMIO disk node
-disk = self.disk
-disk_node = disk.generateBasicPioDeviceNode(
-soc_state, "virtio_mmio", disk.pio_addr, disk.pio_size
-)
-disk_node.append(FdtPropertyWords("interrupts",
[disk.interrupt_id]))
-disk_node.append(
-
[gem5-dev] Change in gem5/gem5[develop]: python: Add simulate.py to the gem5 library
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50753 )
Change subject: python: Add simulate.py to the gem5 library
..
python: Add simulate.py to the gem5 library
This replaces the `m5.simulate` and `m5.instantiate` functions, thereby
removing some gem5 boilerplate code.
Change-Id: I4706119478464efcf4d92e3a1da05bddd0953b6a
---
A src/python/gem5/simulate.py
M tests/gem5/configs/x86_boot_exit_run.py
2 files changed, 62 insertions(+), 12 deletions(-)
diff --git a/src/python/gem5/simulate.py b/src/python/gem5/simulate.py
new file mode 100644
index 000..6aaddd8
--- /dev/null
+++ b/src/python/gem5/simulate.py
@@ -0,0 +1,58 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import m5
+from m5.objects import Root
+
+from typing import Optional
+
+from components.boards.abstract_board import AbstractBoard
+from components.processors.cpu_types import CPUTypes
+
+instantiated: bool = False
+
+def instantiate(board: AbstractBoard, full_system: bool = True) -> None:
+
+
+if instantiated:
+raise Exception("This board has already been instantiated.")
+
+root = Root(full_system=full_system, system=board)
+
+if CPUTypes.KVM in [
+core.get_type() for core in board.get_processor().get_cores()
+]:
+root.sim_quantum = int(1e9)
+
+m5.instantiate()
+
+def simulate(to_tick: Optional[int] = None):
+if not instantiated:
+raise Exception("This board has not been instantiated.")
+
+if to_tick:
+return m5.simulate(to_tick)
+return m5.simulate()
\ No newline at end of file
diff --git a/tests/gem5/configs/x86_boot_exit_run.py
b/tests/gem5/configs/x86_boot_exit_run.py
index 6c5488d..be25e66 100644
--- a/tests/gem5/configs/x86_boot_exit_run.py
+++ b/tests/gem5/configs/x86_boot_exit_run.py
@@ -29,7 +29,6 @@
"""
import m5
-from m5.objects import Root
from gem5.runtime import (
get_runtime_coherence_protocol,
@@ -43,6 +42,7 @@
from gem5.isas import ISA
from gem5.coherence_protocol import CoherenceProtocol
from gem5.resources.resource import Resource
+from gem5.simulate import instantiate, simulate
import argparse
@@ -214,27 +214,19 @@
kernel_args=additional_kernal_args,
)
-
# Begin running of the simulation. This will exit once the Linux system
boot
# is complete.
print("Running with ISA: " + get_runtime_isa().name)
print("Running with protocol: " + get_runtime_coherence_protocol().name)
print()
-root = Root(full_system=True, system=motherboard)
-
-if args.cpu == "kvm":
-# TODO: This of annoying. Is there a way to fix this to happen
-# automatically when running KVM?
-root.sim_quantum = int(1e9)
-
-m5.instantiate()
+instantiate(board=motherboard)
print("Beginning simulation!")
if args.tick_exit != None:
-exit_event = m5.simulate(args.tick_exit)
+exit_event = simulate(args.tick_exit)
else:
-exit_event = m5.simulate()
+exit_event = simulate()
print(
"Exiting @ tick {} because {}.".format(m5.curTick(),
exit_event.getCause())
)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50753
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4706119478464efcf4d92e3a1da05bddd0953b6a
Gerrit-Change-Number: 50753
[gem5-dev] Change in gem5/gem5[develop]: python: Get rid of some unused cruft in main.py.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50707 )
Change subject: python: Get rid of some unused cruft in main.py.
..
python: Get rid of some unused cruft in main.py.
There was some code at the end of main.py which would let you run it
directly. This would parse options passed to the script, and show you
what they equaled.
Also, the "main" function would optionally let you pass in options to
override whatever it would find with parse_arguments. This is no longer
used.
Change-Id: Ib0effa7ac2b4a51b68994372a7c7fcf1c9b4dc13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50707
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/m5/main.py
1 file changed, 2 insertions(+), 19 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index f3be50f..37a7002 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -214,7 +214,7 @@
fatal("Tracing is not enabled. Compile with TRACING_ON")
-def main(*args):
+def main():
import m5
import _m5.core
@@ -229,12 +229,7 @@
from .util import inform, fatal, panic, isInteractive
from m5.util.terminal_formatter import TerminalFormatter
-if len(args) == 0:
-options, arguments = parse_options()
-elif len(args) == 2:
-options, arguments = args
-else:
-raise TypeError("main() takes 0 or 2 arguments (%d given)" %
len(args))
+options, arguments = parse_options()
m5.options = options
@@ -462,15 +457,3 @@
# once the script is done
if options.interactive:
interact(scope)
-
-if __name__ == '__main__':
-from pprint import pprint
-
-options, arguments = parse_options()
-
-print('opts:')
-pprint(options, indent=4)
-print()
-
-print('args:')
-pprint(arguments, indent=4)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50707
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib0effa7ac2b4a51b68994372a7c7fcf1c9b4dc13
Gerrit-Change-Number: 50707
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Get rid of version arg in OptionParser constructor.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50708 ) Change subject: python: Get rid of version arg in OptionParser constructor. .. python: Get rid of version arg in OptionParser constructor. This will report that gem5 is version 2.0, which is WILDLY out of date. There are other ways of reporting the version of gem5 which are actually kept up to date. Change-Id: Ie09cdc8f3ef59696fe197c3491db102bda41ade0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50708 Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/m5/main.py 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Andreas Sandberg: Looks good to me, but someone else must approve kokoro: Regressions pass diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 37a7002..b81da7a 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -45,7 +45,6 @@ __all__ = [ 'options', 'arguments', 'main' ] usage="%prog [gem5 options] script.py [script options]" -version="%prog 2.0" brief_copyright=\ "gem5 is copyrighted software; use the --copyright option for details." @@ -65,8 +64,7 @@ from . import config from .options import OptionParser -options = OptionParser(usage=usage, version=version, - description=brief_copyright) +options = OptionParser(usage=usage, description=brief_copyright) option = options.add_option group = options.set_group -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50708 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie09cdc8f3ef59696fe197c3491db102bda41ade0 Gerrit-Change-Number: 50708 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Get rid of ipython 0.10 and older support code.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50709 ) Change subject: python: Get rid of ipython 0.10 and older support code. .. python: Get rid of ipython 0.10 and older support code. Version 0.11 was actually the first version of ipython which even supported python 3 at all, as far as I can tell. Because we have a requirement to use at least python 3 (and not just 3.0 at that), we can assume that the user must be using at least version 0.11 of ipython. That means we can remove code which supported older versions. Change-Id: I7f88aae9f64f6c6f027be52741cda0686f5ca5be Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50709 Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/m5/main.py 1 file changed, 9 insertions(+), 20 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Andreas Sandberg: Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/m5/main.py b/src/python/m5/main.py index b81da7a..f649e77 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -172,30 +172,19 @@ prompt_in1 = "gem5 \\#> " prompt_out = "gem5 \\#: " -# Is IPython version 0.10 or earlier available? try: -from IPython.Shell import IPShellEmbed -ipshell = IPShellEmbed(argv=["-prompt_in1", prompt_in1, - "-prompt_out", prompt_out], - banner=banner, user_ns=scope) +import IPython +from IPython.config.loader import Config +from IPython.terminal.embed import InteractiveShellEmbed + +cfg = Config() +cfg.PromptManager.in_template = prompt_in1 +cfg.PromptManager.out_template = prompt_out +ipshell = InteractiveShellEmbed(config=cfg, user_ns=scope, +banner1=banner) except ImportError: pass -# Is IPython version 0.11 or later available? -if not ipshell: -try: -import IPython -from IPython.config.loader import Config -from IPython.terminal.embed import InteractiveShellEmbed - -cfg = Config() -cfg.PromptManager.in_template = prompt_in1 -cfg.PromptManager.out_template = prompt_out -ipshell = InteractiveShellEmbed(config=cfg, user_ns=scope, -banner1=banner) -except ImportError: -pass - if ipshell: ipshell() else: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50709 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7f88aae9f64f6c6f027be52741cda0686f5ca5be Gerrit-Change-Number: 50709 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Adding tests to evaluate memory modules.
Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50752 )
Change subject: tests: Adding tests to evaluate memory modules.
..
tests: Adding tests to evaluate memory modules.
This change adds a script to validate the statistics reported
by gem5.
Change-Id: Iae0e61c1763c099cf10924a08b3e4989dc31e220
---
A tests/gem5/configs/eval_memory_modules.py
1 file changed, 116 insertions(+), 0 deletions(-)
diff --git a/tests/gem5/configs/eval_memory_modules.py
b/tests/gem5/configs/eval_memory_modules.py
new file mode 100644
index 000..a92ac55
--- /dev/null
+++ b/tests/gem5/configs/eval_memory_modules.py
@@ -0,0 +1,116 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script creates a simple traffic generator. The simulator starts with a
+linear traffic generator, and ends with a random traffic generator. It is
used
+for testing purposes.
+"""
+
+import m5
+import argparse
+
+from m5.objects import Root
+from gem5.components.memory.single_channel import *
+from gem5.components.boards.test_board import TestBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+from gem5.components.memory.single_channel import (
+SingleChannelDDR3_1600,
+SingleChannelDDR4_2400,
+SingleChannelHBM,
+)
+
+mem_class_map = {
+"ddr3": SingleChannelDDR3_1600,
+"ddr4": SingleChannelDDR4_2400,
+"hbm": SingleChannelHBM,
+}
+
+generator_class_map = {"linear": LinearGenerator, "random":
RandomGenerator}
+
+parser = argparse.ArgumentParser(
+description="A traffic generator that can be used to test a gem5 "
+"memory component."
+)
+
+parser.add_argument(
+"traffic_mode",
+type=str,
+help="Type of traffic to simulate, could be linear or random.",
+)
+
+parser.add_argument(
+"traffic_rate",
+type=str,
+help="Rate at which requests to the memory are created. "
+"Remember to include the unit. example: 100GB/s",
+)
+
+parser.add_argument(
+"mem_class", type=str, help="Class of memory to be simulated."
+)
+
+parser.add_argument(
+"rd_perc",
+type=int,
+help="Percentage of read requests among all the created requests.",
+)
+
+args = parser.parse_args()
+
+# This setup does not require a cache heirarchy. We therefore use the
`NoCache`
+# setup.
+cache_hierarchy = NoCache()
+
+memory_class = mem_class_map[args.mem_class]
+memory = memory_class()
+
+generator_class = generator_class_map[args.traffic_mode]
+generator = generator_class(rate=args.traffic_rate)
+
+# We use the Test Board. This is a special board to run traffic generation
+# tasks
+motherboard = TestBoard(
+clk_freq="4GHz",
+processor=generator, # We pass the traffic generator as the processor.
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+motherboard.connect_things()
+
+root = Root(full_system=False, system=motherboard)
+
+m5.instantiate()
+
+generator.start_traffic()
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print(
+"Exiting @ tick {} because {}.".format(m5.curTick(),
exit_event.getCause())
+)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50752
To unsubscribe, or for help writing mail filters, visit
[gem5-dev] Change in gem5/gem5[develop]: tests: Fix gem5 resources import in parsec test
Austin Harris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50787 ) Change subject: tests: Fix gem5 resources import in parsec test .. tests: Fix gem5 resources import in parsec test Change-Id: I271cf89130f31777ef43b00e0c15cf44835977e3 --- M tests/gem5/configs/parsec_disk_run.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem5/configs/parsec_disk_run.py b/tests/gem5/configs/parsec_disk_run.py index c354cdf..401e88a 100644 --- a/tests/gem5/configs/parsec_disk_run.py +++ b/tests/gem5/configs/parsec_disk_run.py @@ -40,7 +40,7 @@ from m5.objects import Root -from gem5.components.resources.resource import Resource +from gem5.resources.resource import Resource from gem5.components.boards.x86_board import X86Board from gem5.components.memory.single_channel import SingleChannelDDR3_1600 from gem5.components.processors.simple_switchable_processor import ( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50787 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I271cf89130f31777ef43b00e0c15cf44835977e3 Gerrit-Change-Number: 50787 Gerrit-PatchSet: 1 Gerrit-Owner: Austin Harris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-vector-stats]: misc: Update the version to v21.1.0.2
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50750 ) Change subject: misc: Update the version to v21.1.0.2 .. misc: Update the version to v21.1.0.2 Change-Id: I4013ed678b367f95bb0f69e4a827ad04995cc3c0 --- M src/Doxyfile M src/base/version.cc 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Doxyfile b/src/Doxyfile index cee1d0a..4c9f958 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = v21.1.0.1 +PROJECT_NUMBER = v21.1.0.2 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index 9104884..3a01cb6 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -32,6 +32,6 @@ /** * @ingroup api_base_utils */ -const char *gem5Version = "21.1.0.1"; +const char *gem5Version = "21.1.0.2"; } // namespace gem5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50750 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: hotfix-vector-stats Gerrit-Change-Id: I4013ed678b367f95bb0f69e4a827ad04995cc3c0 Gerrit-Change-Number: 50750 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-vector-stats]: misc: Update RELEASE-NOTES.md for v21.1.0.2
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50751 ) Change subject: misc: Update RELEASE-NOTES.md for v21.1.0.2 .. misc: Update RELEASE-NOTES.md for v21.1.0.2 Change-Id: Ib573775b9ef7de7663893f18980bb34b3d412210 --- M RELEASE-NOTES.md 1 file changed, 6 insertions(+), 0 deletions(-) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index a3517c1..6f672a8 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -1,3 +1,9 @@ +# Version 21.1.0.2 + +**[HOTFIX]** [A commit introduced `std::vector` with `resize()` to initialize all storages](https://gem5-review.googlesource.com/c/public/gem5/+/27085). +This caused data duplication in statistics and broke the Vector statistics. +This hotfix initializes using loops which fixes the broken statistics. + # Version 21.1.0.1 **[HOTFIX]** [A "'deprecated' attribute directive ignored" warning was being thrown frequently when trying to build v21.1.0.0](https://gem5.atlassian.net/browse/GEM5-1063). While this issue did not break the build, it made reading the build output difficult and caused confused. As such a patch has been applied to fix this issue. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50751 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: hotfix-vector-stats Gerrit-Change-Id: Ib573775b9ef7de7663893f18980bb34b3d412210 Gerrit-Change-Number: 50751 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add a GCC-11 Dockerfile
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50748 ) Change subject: util-docker: Add a GCC-11 Dockerfile .. util-docker: Add a GCC-11 Dockerfile This can be built to create an image that uses the GCC-11 compiler. At present GCC-11 cannot be installed using APT by default. This Dockerfile uses a special APT repository to do this and is therefore a separate Dockerfile to the other GCC version targets. Change-Id: Iafee92415d9047eedf3586c78722f973010f6050 --- A util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile 1 file changed, 52 insertions(+), 0 deletions(-) diff --git a/util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile b/util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile new file mode 100644 index 000..4effd9c --- /dev/null +++ b/util/dockerfiles/ubuntu-20.04_gcc-version-11/Dockerfile @@ -0,0 +1,52 @@ +# Copyright (c) 2021 The Regents of the University of California +# All Rights Reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +FROM ubuntu:20.04 + +# At the time of this Dockerfile's creation, Ubuntu 20.04 APT does not +# distribute gcc-11 by default. A special APT repository is needed. We hope +# this Dockerfile will merge with ubuntu-20.04_gcc-version once GCC-11 can be +# installed via APT more easily. + +ENV DEBIAN_FRONTEND=noninteractive +RUN apt -y update +RUN apt -y upgrade +RUN apt -y install git m4 scons zlib1g zlib1g-dev libprotobuf-dev \ +protobuf-compiler libprotoc-dev libgoogle-perftools-dev python3-dev \ +python3-six python-is-python3 doxygen libboost-all-dev libhdf5-serial-dev \ +python3-pydot libpng-dev make software-properties-common + +RUN add-apt-repository \ +'deb http://mirrors.kernel.org/ubuntu hirsute main universe' +RUN apt -y install gcc-11 g++-11 + +RUN update-alternatives --install \ +/usr/bin/g++ g++ /usr/bin/g++-11 100 +RUN update-alternatives --install \ +/usr/bin/gcc gcc /usr/bin/gcc-11 100 +RUN update-alternatives --install \ +/usr/bin/c++ c++ /usr/bin/g++-11 100 +RUN update-alternatives --install \ +/usr/bin/cc cc /usr/bin/gcc-11 100 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50748 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iafee92415d9047eedf3586c78722f973010f6050 Gerrit-Change-Number: 50748 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Add GCC-11 to the compiler tests
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50749 )
Change subject: tests: Add GCC-11 to the compiler tests
..
tests: Add GCC-11 to the compiler tests
Change-Id: I3701e850433b597fb0d6d06e058a21607e4efc88
---
M tests/compiler-tests.sh
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index bf1d281..699d134 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -10,7 +10,8 @@
build_dir="${gem5_root}/build"
# All Docker images in the gem5 testing GCR which we want to compile with.
-images=("gcc-version-10"
+images=("gcc-version-11"
+"gcc-version-10"
"gcc-version-9"
"gcc-version-8"
"gcc-version-7"
@@ -29,7 +30,7 @@
# A subset of the above list: these images will build against every target,
# ignoring builds_per_compiler.
-comprehensive=("gcc-version-10"
+comprehensive=("gcc-version-11")
"clang-version-11")
# All build targets in build_opt/ which we want to build using each image.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50749
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3701e850433b597fb0d6d06e058a21607e4efc88
Gerrit-Change-Number: 50749
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-vector-stats]: base-stats: fix storage initializing
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50747 ) Change subject: base-stats: fix storage initializing .. base-stats: fix storage initializing Commit (70194795c3f41cc3f1e361b3cac24f839d86dd67) introduced std::vector with resize() to initializing all storages. This method caused data duplication in statistics. Storage is now initialized using loops. Change-Id: I4350863a83671fc10cc02b5cb7d3b38e6cf4f565 --- M src/base/statistics.hh 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 18f52cb..8fc71eb 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -952,7 +952,10 @@ fatal_if(s <= 0, "Storage size must be positive"); fatal_if(check(), "Stat has already been initialized"); -storage.resize(s, new Storage(this->info()->getStorageParams())); +storage.reserve(s); +for (size_type i = 0; i < s; ++i) +storage.push_back(new Storage(this->info()->getStorageParams())); + this->setInit(); } @@ -1178,7 +1181,10 @@ info->x = _x; info->y = _y; -storage.resize(x * y, new Storage(info->getStorageParams())); +storage.reserve(x * y); +for (size_type i = 0; i < x * y; ++i) +storage.push_back(new Storage(this->info()->getStorageParams())); + this->setInit(); return self; @@ -1387,7 +1393,10 @@ fatal_if(s <= 0, "Storage size must be positive"); fatal_if(check(), "Stat has already been initialized"); -storage.resize(s, new Storage(this->info()->getStorageParams())); +storage.reserve(s); +for (size_type i = 0; i < s; ++i) +storage.push_back(new Storage(this->info()->getStorageParams())); + this->setInit(); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50747 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: hotfix-vector-stats Gerrit-Change-Id: I4350863a83671fc10cc02b5cb7d3b38e6cf4f565 Gerrit-Change-Number: 50747 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-CC: Meng Chen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Fix hang while terminating threads with fork
Austin Harris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50710 )
Change subject: sim: Fix hang while terminating threads with fork
..
sim: Fix hang while terminating threads with fork
It is possible that gem5 is forked multiple times before the threads are
re-created, so don't wait for the barrier if the threads were already
terminated.
Change-Id: Ia04db2f3b1341c4d432178a37812fd882e148ec2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50710
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/sim/simulate.cc
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index ec46cbf..c5d0794 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -118,6 +118,8 @@
terminateThreads()
{
assert(!terminate);
+if (threads.empty())
+return;
/* This function should only be called when the simulator is
* handling a global exit event (typically from Python). This
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50710
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia04db2f3b1341c4d432178a37812fd882e148ec2
Gerrit-Change-Number: 50710
Gerrit-PatchSet: 2
Gerrit-Owner: Austin Harris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Austin Harris
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove useless indirection from lsq to cpu
Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50731 )
Change subject: cpu-o3: remove useless indirection from lsq to cpu
..
cpu-o3: remove useless indirection from lsq to cpu
Change-Id: Idd2d4277b542da728f0740590ae7ef9ae9b76629
---
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.cc
2 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 6a02cb8..d7d660a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -646,20 +646,6 @@
flags, res, std::move(amo_op), byte_enable);
}
-/** CPU read function, forwards read to LSQ. */
-Fault
-read(LSQRequest* req, int load_idx)
-{
-return iew.ldstQueue.read(req, load_idx);
-}
-
-/** CPU write function, forwards write to LSQ. */
-Fault
-write(LSQRequest* req, uint8_t *data, int store_idx)
-{
-return iew.ldstQueue.write(req, data, store_idx);
-}
-
/** Used by the fetch unit to get a hold of the instruction port. */
Port &
getInstPort() override
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 110c58a..babfa92 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -834,9 +834,9 @@
}
Fault fault;
if (isLoad)
-fault = cpu->read(req, inst->lqIdx);
+fault = read(req, inst->lqIdx);
else
-fault = cpu->write(req, data, inst->sqIdx);
+fault = write(req, data, inst->sqIdx);
// inst->getFault() may have the first-fault of a
// multi-access split request at this point.
// Overwrite that only if we got another type of fault
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50731
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idd2d4277b542da728f0740590ae7ef9ae9b76629
Gerrit-Change-Number: 50731
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: replace 'stores' counter per storeQueue.size()
Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50730 )
Change subject: cpu-o3: replace 'stores' counter per storeQueue.size()
..
cpu-o3: replace 'stores' counter per storeQueue.size()
Change-Id: If816c1f03969665010a5bd7e993fe7f87ac4d0a3
---
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
2 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index b4f8477..675f12f 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -202,7 +202,7 @@
LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
: lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),
- stores(0), storesToWB(0),
+ storesToWB(0),
htmStarts(0), htmStops(0),
lastRetiredHtmUid(0),
cacheBlockMask(0), stalled(false),
@@ -236,7 +236,7 @@
void
LSQUnit::resetState()
{
-stores = storesToWB = 0;
+storesToWB = 0;
// hardware transactional memory
// nesting depth
@@ -391,7 +391,7 @@
{
// Make sure it is not full before inserting an instruction.
assert(!storeQueue.full());
-assert(stores < storeQueue.capacity());
+assert(storeQueue.size() < storeQueue.capacity());
DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
store_inst->pcState(), storeQueue.tail(), store_inst->seqNum);
@@ -403,8 +403,6 @@
store_inst->lqIt = loadQueue.end();
storeQueue.back().set(store_inst);
-
-++stores;
}
DynInstPtr
@@ -433,8 +431,8 @@
//SQ has an extra dummy entry to differentiate
//empty/full conditions. Subtract 1 from the free entries.
DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n",
-1 + storeQueue.capacity(), stores);
-return storeQueue.capacity() - stores;
+1 + storeQueue.capacity(), storeQueue.size());
+return storeQueue.capacity() - storeQueue.size();
}
@@ -668,7 +666,7 @@
LSQUnit::executeStore(const DynInstPtr _inst)
{
// Make sure that a store exists.
-assert(stores != 0);
+assert(storeQueue.size() != 0);
int store_idx = store_inst->sqIdx;
@@ -763,7 +761,7 @@
void
LSQUnit::commitStores(InstSeqNum _inst)
{
-assert(stores == 0 || storeQueue.front().valid());
+assert(storeQueue.size() == 0 || storeQueue.front().valid());
/* Forward iterate the store queue (age order). */
for (auto& x : storeQueue) {
@@ -938,14 +936,15 @@
inst->seqNum);
}
}
-assert(stores >= 0 && storesToWB >= 0);
+assert(storesToWB >= 0);
}
void
LSQUnit::squash(const InstSeqNum _num)
{
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
-"(Loads:%i Stores:%i)\n", squashed_num, loadQueue.size(),
stores);
+"(Loads:%i Stores:%i)\n", squashed_num, loadQueue.size(),
+storeQueue.size());
while (loadQueue.size() != 0 &&
loadQueue.back().instruction()->seqNum > squashed_num) {
@@ -1021,7 +1020,7 @@
memDepViolator = NULL;
}
-while (stores != 0 &&
+while (storeQueue.size() != 0 &&
storeQueue.back().instruction()->seqNum > squashed_num) {
// Instructions marked as can WB are already committed.
if (storeQueue.back().canWB()) {
@@ -1049,7 +1048,6 @@
// memory. This is quite ugly. @todo: Figure out the proper
// place to really handle request deletes.
storeQueue.back().clear();
---stores;
storeQueue.pop_back();
++stats.squashedStores;
@@ -1175,7 +1173,6 @@
do {
storeQueue.front().clear();
storeQueue.pop_front();
---stores;
} while (storeQueue.front().completed() &&
!storeQueue.empty());
@@ -1285,7 +1282,7 @@
}
cprintf("\n");
-cprintf("Store queue size: %i\n", stores);
+cprintf("Store queue size: %i\n", storeQueue.size());
cprintf("Store queue: ");
for (const auto& e: storeQueue) {
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 19f190b..5b31d20 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -304,7 +304,7 @@
int numLoads() { return loadQueue.size(); }
/** Returns the number of stores in the SQ. */
-int numStores() { return stores; }
+int numStores() { return storeQueue.size(); }
// hardware transactional memory
int numHtmStarts() const { return htmStarts; }
@@ -334,10 +334,10 @@
bool lqEmpty() const { return loadQueue.size() == 0; }
/** Returns if the SQ is empty. */
-bool sqEmpty() const { return stores == 0; }
+bool sqEmpty() const { return storeQueue.size() == 0; }
/** Returns the number of instructions in the LSQ. */
-unsigned getCount() { return loadQueue.size() + stores; }
+unsigned getCount() { return loadQueue.size() + storeQueue.size(); }
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: replace 'loads' counter per loadQueue.size()
Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50729 )
Change subject: cpu-o3: replace 'loads' counter per loadQueue.size()
..
cpu-o3: replace 'loads' counter per loadQueue.size()
Change-Id: Id65776b385f571e4e325b0ffa022bfa765c224bf
---
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
2 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 34f65b9..b4f8477 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -202,7 +202,7 @@
LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
: lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),
- loads(0), stores(0), storesToWB(0),
+ stores(0), storesToWB(0),
htmStarts(0), htmStops(0),
lastRetiredHtmUid(0),
cacheBlockMask(0), stalled(false),
@@ -236,7 +236,7 @@
void
LSQUnit::resetState()
{
-loads = stores = storesToWB = 0;
+stores = storesToWB = 0;
// hardware transactional memory
// nesting depth
@@ -330,7 +330,7 @@
LSQUnit::insertLoad(const DynInstPtr _inst)
{
assert(!loadQueue.full());
-assert(loads < loadQueue.capacity());
+assert(loadQueue.size() < loadQueue.capacity());
DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
load_inst->pcState(), loadQueue.tail(), load_inst->seqNum);
@@ -346,8 +346,6 @@
assert(load_inst->lqIdx > 0);
load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx);
-++loads;
-
// hardware transactional memory
// transactional state and nesting depth must be tracked
// in the in-order part of the core.
@@ -425,8 +423,8 @@
//LQ has an extra dummy entry to differentiate
//empty/full conditions. Subtract 1 from the free entries.
DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n",
-1 + loadQueue.capacity(), loads);
-return loadQueue.capacity() - loads;
+1 + loadQueue.capacity(), loadQueue.size());
+return loadQueue.capacity() - loadQueue.size();
}
unsigned
@@ -749,16 +747,14 @@
loadQueue.front().clear();
loadQueue.pop_front();
-
---loads;
}
void
LSQUnit::commitLoads(InstSeqNum _inst)
{
-assert(loads == 0 || loadQueue.front().valid());
+assert(loadQueue.size() == 0 || loadQueue.front().valid());
-while (loads != 0 && loadQueue.front().instruction()->seqNum
+while (loadQueue.size() != 0 && loadQueue.front().instruction()->seqNum
<= youngest_inst) {
commitLoad();
}
@@ -949,9 +945,9 @@
LSQUnit::squash(const InstSeqNum _num)
{
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
-"(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
+"(Loads:%i Stores:%i)\n", squashed_num, loadQueue.size(),
stores);
-while (loads != 0 &&
+while (loadQueue.size() != 0 &&
loadQueue.back().instruction()->seqNum > squashed_num) {
DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
"[sn:%lli]\n",
@@ -983,8 +979,6 @@
loadQueue.back().instruction()->setSquashed();
loadQueue.back().clear();
---loads;
-
loadQueue.pop_back();
++stats.squashedLoads;
}
@@ -1282,7 +1276,7 @@
LSQUnit::dumpInsts() const
{
cprintf("Load store queue: Dumping instructions.\n");
-cprintf("Load queue size: %i\n", loads);
+cprintf("Load queue size: %i\n", loadQueue.size());
cprintf("Load queue: ");
for (const auto& e: loadQueue) {
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 686ca16..19f190b 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -301,7 +301,7 @@
unsigned numFreeStoreEntries();
/** Returns the number of loads in the LQ. */
-int numLoads() { return loads; }
+int numLoads() { return loadQueue.size(); }
/** Returns the number of stores in the SQ. */
int numStores() { return stores; }
@@ -331,13 +331,13 @@
bool sqFull() { return storeQueue.full(); }
/** Returns if the LQ is empty. */
-bool lqEmpty() const { return loads == 0; }
+bool lqEmpty() const { return loadQueue.size() == 0; }
/** Returns if the SQ is empty. */
bool sqEmpty() const { return stores == 0; }
/** Returns the number of instructions in the LSQ. */
-unsigned getCount() { return loads + stores; }
+unsigned getCount() { return loadQueue.size() + stores; }
/** Returns if there are any stores to writeback. */
bool hasStoresToWB() { return storesToWB; }
@@ -495,8 +495,6 @@
/** Should loads be checked for dependency issues */
bool checkLoads;
-/** The number of load instructions in the LQ. */
-int loads;
/** The number of store instructions in the SQ. */
int stores;
/** The number of store instructions in the SQ waiting to writeback. */
--
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove false dummy entry in LSQ
Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50732 )
Change subject: cpu-o3: remove false dummy entry in LSQ
..
cpu-o3: remove false dummy entry in LSQ
The constructor of the LoadQueue and StoreQueue were adding
an additional entry compared to the giben configuration
The removed comment was saying that this additional entry was
used as a dummy entry.
This is not necessary anymore with the current structure.
It was even leading to incorrect behavior as a loadQueue
could have one more outstanding load than specified by the configuration.
Valgrind does not spot any illegal access.
Change-Id: I41507d003e4d55e91215e21f57119af7b3e4d465
---
M src/cpu/o3/lsq_unit.cc
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 675f12f..d324b7a 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -201,7 +201,7 @@
}
LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
-: lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),
+: lsqID(-1), storeQueue(sqEntries), loadQueue(lqEntries),
storesToWB(0),
htmStarts(0), htmStops(0),
lastRetiredHtmUid(0),
@@ -418,20 +418,16 @@
unsigned
LSQUnit::numFreeLoadEntries()
{
-//LQ has an extra dummy entry to differentiate
-//empty/full conditions. Subtract 1 from the free entries.
DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n",
-1 + loadQueue.capacity(), loadQueue.size());
+loadQueue.capacity(), loadQueue.size());
return loadQueue.capacity() - loadQueue.size();
}
unsigned
LSQUnit::numFreeStoreEntries()
{
-//SQ has an extra dummy entry to differentiate
-//empty/full conditions. Subtract 1 from the free entries.
DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n",
-1 + storeQueue.capacity(), storeQueue.size());
+storeQueue.capacity(), storeQueue.size());
return storeQueue.capacity() - storeQueue.size();
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50732
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I41507d003e4d55e91215e21f57119af7b3e4d465
Gerrit-Change-Number: 50732
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu: add perfect Branch Predictor
Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50727 )
Change subject: cpu: add perfect Branch Predictor
..
cpu: add perfect Branch Predictor
This commit adds a oracle branch predictor based on a trace file.
This BP have 0 missprediction on commited branches.
The trace file is generated by an earlier run and contains in order
the pc, upc and target of each taken branch. An option was added to
generate this file with the simple and o3 cpu.
The perfect branch predictor works for now with only 1 cpu, no smt
and checkpoints are not supported.
The trace can be generated with '--trace-BP' on the simple or o3 CPU.
The trace can be used with '--perfect-BP'.
Change-Id: Ib5c9e61c26d12edc040de2e2751c62835465cb95
---
M configs/common/Options.py
M configs/common/Simulation.py
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/o3/commit.cc
M src/cpu/o3/commit.hh
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/SConscript
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
A src/cpu/pred/perfect.cc
A src/cpu/pred/perfect.hh
M src/cpu/simple/base.cc
14 files changed, 510 insertions(+), 7 deletions(-)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 7d72d4a..1187dac 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -263,6 +263,22 @@
parser.add_argument("-l", "--lpae", action="store_true")
parser.add_argument("-V", "--virtualisation", action="store_true")
+parser.add_argument("--trace-BP", action="store", type=str,
+help="""BranchPredictor trace file name. Will
record
+information about all the taken branches of this
run.
+This created file, located in the output directory,
+can be used by a later run by the branch predictor
+with the option '--perfect-BP'.
+By appending '.gz' to the file name the trace will
be
+written in a compressed format (gzip)
+Only works with a O3 or Base CPU""")
+
+parser.add_argument("--perfect-BP", action="store", type=str,
+help="""Path to the branch predictor trace file.
+Will be used by the branch predictor to make
+predictions. This trace file can be generated by
using
+the option '--trace-BP'.
+The file can be gzip compressed.""")
# dist-gem5 options
parser.add_argument("--dist", action="store_true",
help="Parallel distributed gem5 simulation.")
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 3b9efc0..ac9f167 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -444,6 +444,18 @@
if options.repeat_switch and options.take_checkpoints:
fatal("Can't specify both --repeat-switch and --take-checkpoints")
+if options.trace_BP:
+if (len(testsys.cpu) != 1 or options.smt):
+fatal("Can't use --trace-BP with more than 1 cpu or smt")
+testsys.cpu[0].trace_BP = True
+testsys.cpu[0].trace_file_BP = options.trace_BP
+if options.perfect_BP:
+if (len(testsys.cpu) != 1 or options.smt):
+fatal("Can't use --perfect-BP with more than 1 cpu or smt")
+testsys.cpu[0].branchPred.perfect = True
+testsys.cpu[0].branchPred.perfectBranchPredictorTrace\
+= options.perfect_BP
+
# Setup global stat filtering.
stat_root_simobjs = []
for stat_root_str in options.stats_root:
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index fb5cbe6..cce688f 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -170,6 +170,13 @@
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
+trace_BP = Param.Bool(False,
+"Generate a file with the Branch Predictor trace")
+trace_file_BP = Param.String("", "Name of the BP trace file to
create. "\
+"Add the suffix '.bz' to automatically create compressed "\
+"traces")
+
+
icache_port = RequestPort("Instruction Port")
dcache_port = RequestPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 0b7ef88..e3ab509 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -146,6 +146,13 @@
_cpuId = cpuList.size();
}
+// Generate a file with the trace of the branch predictor
+if (p.trace_BP) {
+// Open file in binary mode with possible bz compression
+trace_bp_file = simout.create(p.trace_file_BP, true, false);
+}
+
+
// add self to global list of CPUs
cpuList.push_back(this);
@@ -728,6 +735,21 @@
}
}
+void
[gem5-dev] Change in gem5/gem5[develop]: tests: add tests for the perfect BP
Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50728 ) Change subject: tests: add tests for the perfect BP .. tests: add tests for the perfect BP Change-Id: Ic81192fab6318e0744031b1b1e97d538538c3821 --- M src/cpu/o3/commit.cc M tests/gem5/configs/simple_binary_run.py A tests/gem5/options/perfect_bp/ARM_hello_trace_BP.gz A tests/gem5/options/perfect_bp/GCN3_X86_hello_trace_BP.gz A tests/gem5/options/perfect_bp/test_perfect_bp.py M tests/gem5/verifier.py 6 files changed, 255 insertions(+), 3 deletions(-) diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index 2325118..c02eee6 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -191,7 +191,6 @@ commitSquashedInsts.prereq(commitSquashedInsts); commitNonSpecStalls.prereq(commitNonSpecStalls); -branchMispredicts.prereq(branchMispredicts); numCommittedDist .init(0,commit->commitWidth,1) diff --git a/tests/gem5/configs/simple_binary_run.py b/tests/gem5/configs/simple_binary_run.py index 2c27ef7..e5d4ad5 100644 --- a/tests/gem5/configs/simple_binary_run.py +++ b/tests/gem5/configs/simple_binary_run.py @@ -75,6 +75,20 @@ help="Override a local resource if the hashes do not match.", ) +parser.add_argument( +"--trace-BP", +type=str, +required=False, +help="Used to test the generation of the branch trace" +) + +parser.add_argument( +"--perfect-BP", +type=str, +required=False, +help="Used to test the perfect branch predictor" +) + args = parser.parse_args() def input_to_cputype(input: str) -> CPUTypes: @@ -111,6 +125,18 @@ root = Root(full_system=False, system=motherboard) + +# Used in the tests from 'options/perfect_bp/test_perfect_bp.py' +if args.trace_BP: +core = root.system.get_processor().get_cores()[0].get_simobject() +core.trace_BP = True +core.trace_file_BP = args.trace_BP +if args.perfect_BP: +core = root.system.get_processor().get_cores()[0].get_simobject() +core.branchPred.perfect = True +core.branchPred.perfectBranchPredictorTrace = args.perfect_BP + + if args.cpu == "kvm": # TODO: This of annoying. Is there a way to fix this to happen # automatically when running KVM? diff --git a/tests/gem5/options/perfect_bp/ARM_hello_trace_BP.gz b/tests/gem5/options/perfect_bp/ARM_hello_trace_BP.gz new file mode 100644 index 000..d113012 --- /dev/null +++ b/tests/gem5/options/perfect_bp/ARM_hello_trace_BP.gz Binary files differ diff --git a/tests/gem5/options/perfect_bp/GCN3_X86_hello_trace_BP.gz b/tests/gem5/options/perfect_bp/GCN3_X86_hello_trace_BP.gz new file mode 100644 index 000..6e61fc6 --- /dev/null +++ b/tests/gem5/options/perfect_bp/GCN3_X86_hello_trace_BP.gz Binary files differ diff --git a/tests/gem5/options/perfect_bp/test_perfect_bp.py b/tests/gem5/options/perfect_bp/test_perfect_bp.py new file mode 100644 index 000..4d32f6a --- /dev/null +++ b/tests/gem5/options/perfect_bp/test_perfect_bp.py @@ -0,0 +1,186 @@ +# Copyright (c) 2021 Huawei International +# Copyright (c) 2020 The Regents of the University of California +# All rights reserved. +# +# Copyright (c) 2020 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO,
[gem5-dev] Change in gem5/gem5[develop]: sim: Fix hang while terminating threads with fork
Austin Harris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50710 )
Change subject: sim: Fix hang while terminating threads with fork
..
sim: Fix hang while terminating threads with fork
It is possible that gem5 is forked multiple times before the threads are
re-created, so don't wait for the barrier if the threads were already
terminated.
Change-Id: Ia04db2f3b1341c4d432178a37812fd882e148ec2
---
M src/sim/simulate.cc
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index ec46cbf..c5d0794 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -118,6 +118,8 @@
terminateThreads()
{
assert(!terminate);
+if (threads.empty())
+return;
/* This function should only be called when the simulator is
* handling a global exit event (typically from Python). This
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50710
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia04db2f3b1341c4d432178a37812fd882e148ec2
Gerrit-Change-Number: 50710
Gerrit-PatchSet: 1
Gerrit-Owner: Austin Harris
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
