[gem5-dev] Re: multi-ISA gem5 proof of concept

[Gabe Black via gem5-dev]

On Mon, Nov 8, 2021 at 2:13 PM Gabe Black  wrote:

>
>
> On Mon, Nov 8, 2021 at 8:40 AM Jason Lowe-Power 
> wrote:
>
>> This looks quite promising! Uploading a branch to gerrit is a good idea.
>>
>
> Ok, I'll do that. All but 4 of the changes in this composite branch are
> uploaded for review, and these few extras are because they depend on all of
> the switching header files being gone.
>
>

https://gem5.googlesource.com/public/gem5/+/refs/heads/multi-isa
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove unneeded imports in the gem5 Python Library

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52203 )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Remove unneeded imports in the gem5 Python Library
..

stdlib: Remove unneeded imports in the gem5 Python Library

Change-Id: I6d4ccc4e18bd36d4a9dad9b6782ebcc0e64c4e44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52203
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/python/gem5/components/boards/simple_board.py
M src/python/gem5/components/boards/test_board.py
M src/python/gem5/components/processors/simple_switchable_processor.py
M src/python/gem5/components/processors/simple_processor.py
M src/python/gem5/components/boards/x86_board.py
5 files changed, 14 insertions(+), 12 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/simple_board.py  
b/src/python/gem5/components/boards/simple_board.py

index ad11df9..2385ce4 100644
--- a/src/python/gem5/components/boards/simple_board.py
+++ b/src/python/gem5/components/boards/simple_board.py
@@ -26,11 +26,8 @@

 from m5.objects import (
 AddrRange,
-SrcClockDomain,
-VoltageDomain,
 IOXBar,
 Port,
-ClockDomain,
 )

 from .abstract_board import AbstractBoard
diff --git a/src/python/gem5/components/boards/test_board.py  
b/src/python/gem5/components/boards/test_board.py

index b591a6e..9010843 100644
--- a/src/python/gem5/components/boards/test_board.py
+++ b/src/python/gem5/components/boards/test_board.py
@@ -25,9 +25,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.objects import (
-SrcClockDomain,
-ClockDomain,
-VoltageDomain,
 Port,
 IOXBar,
 AddrRange,
diff --git a/src/python/gem5/components/boards/x86_board.py  
b/src/python/gem5/components/boards/x86_board.py

index 51e3e25..53a577b 100644
--- a/src/python/gem5/components/boards/x86_board.py
+++ b/src/python/gem5/components/boards/x86_board.py
@@ -59,8 +59,7 @@
 from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

 from ...utils.requires import requires

-import os
-from typing import List, Optional, Sequence
+from typing import List, Sequence


 class X86Board(AbstractBoard, KernelDiskWorkload):
diff --git a/src/python/gem5/components/processors/simple_processor.py  
b/src/python/gem5/components/processors/simple_processor.py

index 8bc7f8b..4f602ed 100644
--- a/src/python/gem5/components/processors/simple_processor.py
+++ b/src/python/gem5/components/processors/simple_processor.py
@@ -35,8 +35,6 @@
 from .cpu_types import CPUTypes
 from ..boards.abstract_board import AbstractBoard

-from typing import List
-

 class SimpleProcessor(AbstractProcessor):
 """
diff --git  
a/src/python/gem5/components/processors/simple_switchable_processor.py  
b/src/python/gem5/components/processors/simple_switchable_processor.py

index 3614aca..4cc4cfb 100644
--- a/src/python/gem5/components/processors/simple_switchable_processor.py
+++ b/src/python/gem5/components/processors/simple_switchable_processor.py
@@ -32,8 +32,6 @@

 from ...utils.override import *

-from m5.objects import KvmVM
-

 class SimpleSwitchableProcessor(SwitchableProcessor):
 """

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52203
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6d4ccc4e18bd36d4a9dad9b6782ebcc0e64c4e44
Gerrit-Change-Number: 52203
Gerrit-PatchSet: 10
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib,tests,configs: Create 'SEBinaryWorkload' class

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52186 )


 (

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib,tests,configs: Create 'SEBinaryWorkload' class
..

stdlib,tests,configs: Create 'SEBinaryWorkload' class

This enables an SE mode execution of binary if added a Board's
superclass.

This has been abstracted from the SimpleBoard.

The 'set_workload' function has been renamed 'set_se_binary_workload'.
This is clearer on its purpose and doesn't overlap with other
'set_workload' functions.

Change-Id: I714425a3b6b98b91e762ad076eba583bc5953ddd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52186
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/python/gem5/components/boards/simple_board.py
M configs/example/gem5_library/arm-hello.py
M src/python/SConscript
M tests/gem5/configs/simple_binary_run.py
A src/python/gem5/components/boards/se_binary_workload.py
5 files changed, 86 insertions(+), 25 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index dc4266c..540a96b 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -79,7 +79,7 @@
 # program compiled to the ARM ISA. The `Resource` class will automatically
 # download the binary from the gem5 Resources cloud bucket if it's not  
already

 # present.
-board.set_workload(
+board.set_se_binary_workload(
 # The `Resource` class reads the `resources.json` file from the gem5
 # resources repository:
 # https://gem5.googlesource.com/public/gem5-resource.
diff --git a/src/python/SConscript b/src/python/SConscript
index db564ef..d210960 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -42,6 +42,8 @@
 PySource('gem5.components.boards', 'gem5/components/boards/x86_board.py')
 PySource('gem5.components.boards',
 "gem5/components/boards/kernel_disk_workload.py")
+PySource('gem5.components.boards',
+"gem5/components/boards/se_binary_workload.py")
 PySource('gem5.components.cachehierarchies',
 'gem5/components/cachehierarchies/__init__.py')
 PySource('gem5.components.cachehierarchies',
diff --git a/src/python/gem5/components/boards/se_binary_workload.py  
b/src/python/gem5/components/boards/se_binary_workload.py

new file mode 100644
index 000..485c1a3
--- /dev/null
+++ b/src/python/gem5/components/boards/se_binary_workload.py
@@ -0,0 +1,56 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from ...resources.resource import AbstractResource
+
+from m5.objects import SEWorkload, Process
+
+class SEBinaryWorkload:
+"""
+This class is used to enable simple Syscall-Execution (SE) mode  
execution

+of a binary.
+
+For this to function correctly the SEBinaryWorkload class should be  
added

+as a superclass to a board (i.e., something that inherits from
+AbstractBoard).
+"""
+
+def set_se_binary_workload(self, binary: AbstractResource) -> None:
+"""Set up the system to run a specific binary.
+
+**Limitations**
+* Only supports single threaded applications
+* Dynamically 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove 'exit_on_work_items' from boards' constructor

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52223 )


 (

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: stdlib: Remove 'exit_on_work_items' from boards'  
constructor

..

stdlib: Remove 'exit_on_work_items' from boards' constructor

This has been moved to the `set_kernel_disk_workload` function, and is
set to True by default.

Change-Id: I9df2fa2946dd942b5011f05b948542097310352e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52223
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/python/gem5/components/boards/simple_board.py
M src/python/gem5/components/boards/riscv_board.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M src/python/gem5/components/boards/x86_board.py
M src/python/gem5/components/boards/kernel_disk_workload.py
M tests/gem5/configs/x86_boot_exit_run.py
M src/python/gem5/components/boards/abstract_board.py
9 files changed, 23 insertions(+), 18 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index ce86ab4..51555d0 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -67,7 +67,6 @@
 processor: "AbstractProcessor",
 memory: "AbstractMemory",
 cache_hierarchy: "AbstractCacheHierarchy",
-exit_on_work_items: bool = False,
 ) -> None:
 super(AbstractBoard, self).__init__()
 """
@@ -75,8 +74,6 @@
 :param processor: The processor for this board.
 :param memory: The memory for this board.
 :param cache_hierarchy: The Cachie Hierarchy for this board.
-:param exit_on_work_items: Whether the simulation should exit
-on work items.
 """

 # Set up the clock domain and the voltage domain.
@@ -84,9 +81,6 @@
 self.clk_domain.clock = clk_freq
 self.clk_domain.voltage_domain = VoltageDomain()

-# Set whether to exit on work items.
-self.exit_on_work_items = exit_on_work_items
-
 # Set the processor, memory, and cache hierarchy.
 self.processor = processor
 self.memory = memory
diff --git a/src/python/gem5/components/boards/kernel_disk_workload.py  
b/src/python/gem5/components/boards/kernel_disk_workload.py

index 424d839..031fc60 100644
--- a/src/python/gem5/components/boards/kernel_disk_workload.py
+++ b/src/python/gem5/components/boards/kernel_disk_workload.py
@@ -136,6 +136,7 @@
 readfile: Optional[str] = None,
 readfile_contents: Optional[str] = None,
 kernel_args: Optional[List[str]] = None,
+exit_on_work_items: bool = True,
 ) -> None:
 """
 This function allows the setting of a full-system run with a Kernel
@@ -151,6 +152,8 @@
 be created with the value of `readfile_contents`.
 :param kernel_args: An optional parameter for setting arguments to  
be
 passed to the kernel. By default set to  
`get_default_kernel_args()`.
+:param exit_on_work_items: Whether the simulation should exit on  
work

+items. True by default.
 """

 # Set the kernel to use.
@@ -176,3 +179,6 @@
 file.close()

 self._add_disk_to_board(disk_image=disk_image)
+
+# Set whether to exit on work items.
+self.exit_on_work_items = exit_on_work_items
\ No newline at end of file
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index ac8440d..f64640c 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -85,11 +85,8 @@
 processor: AbstractProcessor,
 memory: AbstractMemorySystem,
 cache_hierarchy: AbstractCacheHierarchy,
-exit_on_work_items: bool = False,
 ) -> None:
-super().__init__(
-clk_freq, processor, memory, cache_hierarchy,  
exit_on_work_items

-)
+super().__init__(clk_freq, processor, memory, cache_hierarchy)
 requires(isa_required=ISA.RISCV)

 @overrides(AbstractBoard)
diff --git a/src/python/gem5/components/boards/simple_board.py  
b/src/python/gem5/components/boards/simple_board.py

index 2385ce4..3242cf0 100644
--- a/src/python/gem5/components/boards/simple_board.py
+++ b/src/python/gem5/components/boards/simple_board.py
@@ -57,14 +57,12 @@
 processor: AbstractProcessor,
 memory: AbstractMemorySystem,
 cache_hierarchy: AbstractCacheHierarchy,
-exit_on_work_items: 

[gem5-dev] Change in gem5/gem5[develop]: stdlib,tests,configs: Replace Resource override download

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52086 )


Change subject: stdlib,tests,configs: Replace Resource override download
..

stdlib,tests,configs: Replace Resource override download

The override parameter in the constructor has been renamed to to
'download_md5_mismatch'. This makes the purpose of this parameter
clearer.

The default value has been changed from False to True. We found in most
cases we want to re-download files if the md5 values have changes. Not
wanting to do so is the corner case. This allows us to remove a lot of
parameters from test and example scripts, included in this patch.

Change-Id: I99fc7743f5adf78bf6f4f8efc6222e6df83ac6da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52086
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M configs/example/gem5_library/arm-hello.py
M src/python/gem5/resources/downloader.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M src/python/gem5/resources/resource.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M tests/gem5/hello_se/test_hello_se.py
M tests/gem5/stats/test_hdf5.py
M configs/example/gem5_library/x86-ubuntu-run.py
M tests/gem5/parsec-benchmarks/test_parsec.py
M tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/simple_binary_run.py
M tests/gem5/m5_util/test_exit.py
M tests/gem5/configs/x86_boot_exit_run.py
M tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
18 files changed, 46 insertions(+), 94 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 7dbc8a2..067c867 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -84,20 +84,13 @@
 # download the binary from the gem5 Resources cloud bucket if it's not  
already

 # present.
 board.set_workload(
-Resource(
-# The `Resource` class reads the `resources.json` file from the  
gem5

-# resources repository:
-# https://gem5.googlesource.com/public/gem5-resource.
-# Any resource specified in this file will be automatically  
retrieved.
-# At the time of writing, this file is a WIP and does not contain  
all
-# resources. Jira ticket:  
https://gem5.atlassian.net/browse/GEM5-1096

-"arm-hello64-static",
-# `override=True` means the if the binary already exists locally  
within
-# the resource directory, and the hash's differ to that in the  
cloud
-# bucket, the local copy will be overwritten. If this were set to  
false

-# an exception would be thrown in this case.
-override=True,
-)
+# The `Resource` class reads the `resources.json` file from the gem5
+# resources repository:
+# https://gem5.googlesource.com/public/gem5-resource.
+# Any resource specified in this file will be automatically retrieved.
+# At the time of writing, this file is a WIP and does not contain all
+# resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
+Resource("arm-hello64-static")
 )

 # Lastly we setup the root, instantiate the design, and run the simulation.
diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index de7cc0a..ce3d637 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -122,16 +122,10 @@
 board.set_kernel_disk_workload(
 # The x86 linux kernel will be automatically downloaded to the if not
 # already present.
-kernel=Resource(
-"x86-linux-kernel-5.4.49",
-override=True,
-),
+kernel=Resource("x86-linux-kernel-5.4.49"),
 # The x86 ubuntu image will be automatically downloaded to the if not
 # already present.
-disk_image=Resource(
-"x86-ubuntu-img",
-override=True,
-),
+disk_image=Resource("x86-ubuntu-img"),
 readfile_contents=command,
 )

diff --git a/src/python/gem5/resources/downloader.py  
b/src/python/gem5/resources/downloader.py

index fab7864..86ddefb 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -198,7 +198,7 @@
 resource_name: str,
 to_path: str,
 unzip: bool = True,
-override: bool = False,
+download_md5_mismatch: bool = True,
 ) -> None:
 """
 Obtains a gem5 resource and stored it to a specified location. If the
@@ -212,10 +212,10 @@
 :param unzip: If true, gzipped resources will be unzipped prior to  
saving

 to `to_path`. True by default.

-:param override: 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Move 'connect_things' to AbstractBoard constructor

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52184 )


Change subject: stdlib: Move 'connect_things' to AbstractBoard constructor
..

stdlib: Move 'connect_things' to AbstractBoard constructor

This patch moves 'connect_things' to the AbstractBoard constructor,
thereby meaning it does not need to be called directly in gem5
configuration scripts. This method has been changed to private as a
result.

As boards that inherit from AbstractBoard require certain things to be
setup prior to `connect_things` being called, a new abstract function,
`_setup_board` has been created. This is called in the AbstractBoard
constructor before `connect_things` and can be overridden by boards to
setup board properties as required.

Change-Id: I558a4321b850a6b19e20b7d56d0bcae5805114b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52184
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/riscv-fs.py
M src/python/gem5/components/boards/simple_board.py
M src/python/gem5/components/boards/riscv_board.py
M configs/example/gem5_library/arm-hello.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M src/python/gem5/components/boards/test_board.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M configs/example/gem5_library/x86-ubuntu-run.py
M src/python/gem5/components/boards/x86_board.py
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/simple_binary_run.py
M tests/gem5/configs/simple_traffic_run.py
M tests/gem5/configs/x86_boot_exit_run.py
M src/python/gem5/components/boards/abstract_board.py
15 files changed, 49 insertions(+), 26 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 067c867..dc4266c 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -75,10 +75,6 @@
 cache_hierarchy=cache_hierarchy,
 )

-# This method must be called to connect all the components specified during
-# the board's construction.
-board.connect_things()
-
 # Here we set the workload. In this case we want to run a simple "Hello  
World!"

 # program compiled to the ARM ISA. The `Resource` class will automatically
 # download the binary from the gem5 Resources cloud bucket if it's not  
already
diff --git a/configs/example/gem5_library/riscv-fs.py  
b/configs/example/gem5_library/riscv-fs.py

index 35a7250..f46a345 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -78,8 +78,6 @@
 cache_hierarchy=cache_hierarchy,
 )

-board.connect_things()
-
 # Set the Full System workload.
 board.set_kernel_disk_workload(
kernel=Resource("riscv-bootloader-vmlinux-5.10"),
diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index ce3d637..1ab9f3a 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -102,8 +102,6 @@
 cache_hierarchy=cache_hierarchy,
 )

-board.connect_things()
-
 # Here we set the Full System workload.
 # The `set_kernel_disk_workload` function for the X86Board takes a kernel,  
a

 # disk image, and, optionally, a command to run.
diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index 60ce0de..ce86ab4 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -92,7 +92,12 @@
 self.memory = memory
 self.cache_hierarchy = cache_hierarchy

-self.setup_memory_ranges()
+
+# Setup board properties unique to the board being constructed.
+self._setup_board()
+
+# Connect the memory, processor, and cache hierarchy.
+self._connect_things()

 def get_processor(self) -> "AbstractProcessor":
 """Get the processor connected to the board.
@@ -135,11 +140,20 @@

 def get_clock_domain(self) -> ClockDomain:
 """Get the clock domain.
-
 :returns: The clock domain.
 """
 return self.clk_domain

+@abstractmethod
+def _setup_board(self) -> None:
+"""
+This function is called in the AbstractBoard constructor, before  
the
+memory, processor, and cache hierarchy components are incorporated  
via

+`_connect_thing()`. This function should be overridden by boards to
+specify components, connections unique to that board.
+"""
+raise NotImplementedError
+
 # Technically `get_dma_ports` returns a list. This list could be empty  
to

 # indicate the presense of dma ports. Though I quite like 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Move 'connect_things' to the AbstractBoard

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52183 )


 (

12 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Move 'connect_things' to the AbstractBoard
..

stdlib: Move 'connect_things' to the AbstractBoard

This is in order to enforce a strict ordering of how gem5 components are
incorporated into a board. The `connect_things` function is now final so
it cannot be overridden.

Change-Id: I4c0e7ac9d307b399854f5326bb57bcf561f92054
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52183
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/python/gem5/components/boards/simple_board.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/components/boards/test_board.py
M src/python/gem5/components/boards/x86_board.py
M src/python/gem5/components/boards/abstract_board.py
5 files changed, 46 insertions(+), 54 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index 845ccb2..60ce0de 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -37,7 +37,7 @@
 VoltageDomain,
 )

-from typing import List
+from typing import List, final


 class AbstractBoard(System):
@@ -219,15 +219,24 @@
 """
 raise NotImplementedError

-@abstractmethod
+@final
 def connect_things(self) -> None:
 """Connects all the components to the board.

-This should be called after the constructor.
+The order of this board is always:

-When implementing this function, derived boards should use this to
-hook up the memory, process, and cache hierarchy as a *second*  
stage.
-You should use this function to connect things together when you  
need

-to know that everything has already been constructed.
+1. Connect the memory.
+2. Connect the processor.
+3. Connect the cache hierarchy.
+
+Developers may build upon this assumption when creating components.
 """
-raise NotImplementedError
+
+# Incorporate the memory into the motherboard.
+self.get_memory().incorporate_memory(self)
+
+# Incorporate the processor into the motherboard.
+self.get_processor().incorporate_processor(self)
+
+# Incorporate the cache hierarchy for the motherboard.
+self.get_cache_hierarchy().incorporate_cache(self)
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index 18c742e..2b3261d 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -123,6 +123,9 @@
 self._on_chip_devices = [self.platform.clint, self.platform.plic]
 self._off_chip_devices = [self.platform.uart, self.disk]

+# Set up the memory ranges
+self.setup_memory_ranges()
+
 def _setup_io_devices(self) -> None:
 """Connect the I/O devices to the I/O bus"""

@@ -192,20 +195,6 @@
 self.mem_ranges = [AddrRange(start=0x8000, size=mem_size)]
 memory.set_memory_range(self.mem_ranges)

-@overrides(AbstractBoard)
-def connect_things(self) -> None:
-# Before incorporating the memory, set up the memory ranges
-self.setup_memory_ranges()
-
-# Incorporate the cache hierarchy for the motherboard.
-self.get_cache_hierarchy().incorporate_cache(self)
-
-# Incorporate the processor into the motherboard.
-self.get_processor().incorporate_processor(self)
-
-# Incorporate the memory into the motherboard.
-self.get_memory().incorporate_memory(self)
-
 def generate_device_tree(self, outdir: str) -> None:
 """Creates the dtb and dts files.

diff --git a/src/python/gem5/components/boards/simple_board.py  
b/src/python/gem5/components/boards/simple_board.py

index efe1736..3645ed8 100644
--- a/src/python/gem5/components/boards/simple_board.py
+++ b/src/python/gem5/components/boards/simple_board.py
@@ -72,16 +72,8 @@
 exit_on_work_items=exit_on_work_items,
 )

-@overrides(AbstractBoard)
-def connect_things(self) -> None:
-# Incorporate the cache hierarchy for the motherboard.
-self.get_cache_hierarchy().incorporate_cache(self)
-
-# Incorporate the processor into the motherboard.
-self.get_processor().incorporate_processor(self)
-
-# Incorporate the memory into the motherboard.
-self.get_memory().incorporate_memory(self)
+# Set up the memory ranges
+

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Automatically set disk root partition in set_workload

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51948 )


Change subject: stdlib: Automatically set disk root partition in  
set_workload

..

stdlib: Automatically set disk root partition in set_workload

The linux kernel `root` parameter must be specified in the board's
`set_workload` function. However, the root partition on a disk image
passed to this function can change. Therefore, for gem5 resources disk
images, we inspect the metadata to obtain the root partition and
automatically set this.

This patch is dependent on the following gem5 resources change to
function correctly:
https://gem5-review.googlesource.com/c/public/gem5-resources/+/51887

Note: This patch will only automatically set the root partition
information for disk images in gem5 resources.

Issue-on: https://gem5.atlassian.net/browse/GEM5-1102
Change-Id: I9a19706f3ba78bf026b6bfdff4bff84a3c8ccdb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51948
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/resources/resource.py
M src/python/gem5/components/boards/x86_board.py
3 files changed, 75 insertions(+), 9 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index 43a5112..3fc15cb 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -240,7 +240,19 @@
 image.child.image_file = disk_image.get_local_path()
 self.disk.vio.image = image

-self.workload.command_line = "console=ttyS0 root=/dev/vda ro"
+# Determine where the root exists in the disk image. This is done  
by

+# inspecting the resource metadata.
+root_val = "/dev/vda"
+try:
+partition_val =  
disk_image.get_metadata()["additional_metadata"]\

+ ["root_partition"]
+except KeyError:
+partition_val = None
+
+if partition_val is not None:
+root_val += partition_val
+
+self.workload.command_line = f"console=ttyS0 root={root_val} ro"

 # Note: This must be called after set_workload because it looks  
for an

 # attribute named "disk" and connects
diff --git a/src/python/gem5/components/boards/x86_board.py  
b/src/python/gem5/components/boards/x86_board.py

index c6ce459..a32ee7d 100644
--- a/src/python/gem5/components/boards/x86_board.py
+++ b/src/python/gem5/components/boards/x86_board.py
@@ -288,20 +288,34 @@
 first partition should be the root partition.
 :param command: The command(s) to run with bash once the OS is  
booted
 :param kernel_args: Additional arguments to be passed to the  
kernel.

-`earlyprintk=ttyS0 console=ttyS0 lpj=723 root=/dev/hda1` are
-already passed. This parameter is used to pass additional  
arguments.

+`earlyprintk=ttyS0 console=ttyS0 lpj=723
+root=/dev/hda` are already passed  
(`` is
+automatically inferred from resource metadata). This parameter is  
used

+to pass additional arguments.
 """

 # Set the Linux kernel to use.
 self.workload.object_file = kernel.get_local_path()

+# Determine where the root exists in the disk image. This is done  
by

+# inspecting the resource metadata.
+root_val = "/dev/hda"
+try:
+partition_val =  
disk_image.get_metadata()["additional_metadata"]\

+ ["root_partition"]
+except KeyError:
+partition_val = None
+
+if partition_val is not None:
+root_val += partition_val
+
 # Options specified on the kernel command line.
 self.workload.command_line = " ".join(
 [
 "earlyprintk=ttyS0",
 "console=ttyS0",
 "lpj=723",
-"root=/dev/hda1",
+f"root={root_val}",
 ] + kernel_args
 )

diff --git a/src/python/gem5/resources/resource.py  
b/src/python/gem5/resources/resource.py

index 07c6a80..b054b09 100644
--- a/src/python/gem5/resources/resource.py
+++ b/src/python/gem5/resources/resource.py
@@ -28,9 +28,9 @@
 import os
 from pathlib import Path

-from .downloader import get_resource
+from .downloader import get_resource, get_resources_json_obj

-from typing import Optional
+from typing import Optional, Dict

 """
 A Resource object encapsulates a gem5 resource. Resources are items needed  
to

@@ -50,12 +50,21 @@

 __metaclass__ = ABCMeta

-def __init__(self, local_path: str):
+def 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Create 'KernelDiskWorkload' abstract class

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51949 )


Change subject: stdlib: Create 'KernelDiskWorkload' abstract class
..

stdlib: Create 'KernelDiskWorkload' abstract class

The purpose of this class is to:

* Create a standard way to set a typical kernel/disk image workload.
* Cleans up the manner in which readfile values/contents are set.
* Allows a user to specify their own kernel arguments, but still sets
sensible defaults.

As of this commit, this interface has been added to the X86Board and the
RISCVBoard.

Change-Id: I34f4c2b829f1ae5c1cae12039436cbb345a89d09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51949
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/riscv-fs.py
M src/python/gem5/components/boards/riscv_board.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M src/python/SConscript
M configs/example/gem5_library/x86-ubuntu-run.py
M src/python/gem5/components/boards/x86_board.py
M tests/gem5/configs/riscv_boot_exit_run.py
A src/python/gem5/components/boards/kernel_disk_workload.py
M tests/gem5/configs/x86_boot_exit_run.py
11 files changed, 290 insertions(+), 173 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/riscv-fs.py  
b/configs/example/gem5_library/riscv-fs.py

index 762743c..35a7250 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -81,8 +81,10 @@
 board.connect_things()

 # Set the Full System workload.
-board.set_workload(disk_image=Resource("riscv-disk-img"),
-   bootloader=Resource("riscv-bootloader-vmlinux-5.10"))
+board.set_kernel_disk_workload(
+   kernel=Resource("riscv-bootloader-vmlinux-5.10"),
+   disk_image=Resource("riscv-disk-img"),
+)

 root = Root(full_system=True, system=board)

diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index 17cabcb..860707a 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -107,8 +107,8 @@
 board.connect_things()

 # Here we set the Full System workload.
-# The `set_workload` function for the X86Board takes a kernel, a disk  
image,

-# and, optionally, a command to run.
+# The `set_kernel_disk_workload` function for the X86Board takes a kernel,  
a

+# disk image, and, optionally, a command to run.

 # This is the command to run after the system has booted. The first `m5  
exit`
 # will stop the simulation so we can switch the CPU cores from KVM to  
timing

@@ -121,7 +121,7 @@
 + "sleep 1;" \
 + "m5 exit;"

-board.set_workload(
+board.set_kernel_disk_workload(
 # The x86 linux kernel will be automatically downloaded to the
 # `tests/gem5/resources` directory if not already present.
 kernel=Resource(
@@ -158,9 +158,10 @@
 ),
 override=True,
 ),
-command=command,
+readfile_contents=command,
 )

+
 root = Root(full_system=True, system=board)
 root.sim_quantum = int(1e9)  # sim_quantum must be st if KVM cores are  
used.


diff --git a/src/python/SConscript b/src/python/SConscript
index e750829..db564ef 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -40,6 +40,8 @@
  
PySource('gem5.components.boards', 'gem5/components/boards/simple_board.py')

 PySource('gem5.components.boards', 'gem5/components/boards/test_board.py')
 PySource('gem5.components.boards', 'gem5/components/boards/x86_board.py')
+PySource('gem5.components.boards',
+"gem5/components/boards/kernel_disk_workload.py")
 PySource('gem5.components.cachehierarchies',
 'gem5/components/cachehierarchies/__init__.py')
 PySource('gem5.components.cachehierarchies',
diff --git a/src/python/gem5/components/boards/kernel_disk_workload.py  
b/src/python/gem5/components/boards/kernel_disk_workload.py

new file mode 100644
index 000..424d839
--- /dev/null
+++ b/src/python/gem5/components/boards/kernel_disk_workload.py
@@ -0,0 +1,178 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# 

[gem5-dev] Change in gem5/gem5[develop]: stdlib,configs: Remove setting resource_directory in examples

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51950 )


 (

12 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: stdlib,configs: Remove setting resource_directory in  
examples

..

stdlib,configs: Remove setting resource_directory in examples

As part of https://gem5-review.googlesource.com/c/public/gem5/+/51369
we have a default resource directory. We therefore no longer need to set
`resource_directory` to get a consistent download location.

Change-Id: I0bef9930db9157a999dc063bd49377de1fe75102
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51950
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M configs/example/gem5_library/arm-hello.py
M configs/example/gem5_library/x86-ubuntu-run.py
2 files changed, 21 insertions(+), 46 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 9641d2b..7dbc8a2 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -53,8 +53,6 @@
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes

-import os
-
 # This check ensures the gem5 binary is compiled to the ARM ISA target. If  
not,

 # an exception will be thrown.
 requires(isa_required=ISA.ARM)
@@ -99,20 +97,6 @@
 # bucket, the local copy will be overwritten. If this were set to  
false

 # an exception would be thrown in this case.
 override=True,
-# We hardcode the resource directory to `tests/gem5/resources`. The
-# `arm-hello64-static` binary will be downloaded and stored there.
-resource_directory=os.path.join(
-os.path.dirname(
-os.path.dirname(
-os.path.dirname(
-os.path.dirname(os.path.realpath(__file__))
-)
-)
-),
-"tests",
-"gem5",
-"resources",
-),
 )
 )

diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index 860707a..de7cc0a 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -55,8 +55,6 @@
 from gem5.coherence_protocol import CoherenceProtocol
 from gem5.resources.resource import Resource

-import os
-
 # This runs a check to ensure the gem5 binary is compiled to X86 and to the
 # MESI Two Level coherence protocol.
 requires(
@@ -122,40 +120,16 @@
 + "m5 exit;"

 board.set_kernel_disk_workload(
-# The x86 linux kernel will be automatically downloaded to the
-# `tests/gem5/resources` directory if not already present.
+# The x86 linux kernel will be automatically downloaded to the if not
+# already present.
 kernel=Resource(
 "x86-linux-kernel-5.4.49",
-resource_directory=os.path.join(
-os.path.dirname(
-os.path.dirname(
-os.path.dirname(
-os.path.dirname(os.path.realpath(__file__))
-)
-)
-),
-"tests",
-"gem5",
-"resources",
-),
 override=True,
 ),
-# The x86 ubuntu image will be automatically downloaded to the
-# `tests/gem5/resources` directory if not already present.
+# The x86 ubuntu image will be automatically downloaded to the if not
+# already present.
 disk_image=Resource(
 "x86-ubuntu-img",
-resource_directory=os.path.join(
-os.path.dirname(
-os.path.dirname(
-os.path.dirname(
-os.path.dirname(os.path.realpath(__file__))
-)
-)
-),
-"tests",
-"gem5",
-"resources",
-),
 override=True,
 ),
 readfile_contents=command,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0bef9930db9157a999dc063bd49377de1fe75102
Gerrit-Change-Number: 51950
Gerrit-PatchSet: 14
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Add missing @overrides to RISCVBoard

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52185 )


Change subject: stdlib: Add missing @overrides to RISCVBoard
..

stdlib: Add missing @overrides to RISCVBoard

Change-Id: I6879c9744c28038c5d40984785f2f502a2fd1c5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52185
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/riscv_board.py
1 file changed, 15 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index 99bb630..ac8440d 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -183,9 +183,11 @@
 def get_io_bus(self) -> IOXBar:
 return self.iobus

+@overrides(AbstractBoard)
 def has_coherent_io(self) -> bool:
 return True

+@overrides(AbstractBoard)
 def get_mem_side_coherent_io_port(self) -> Port:
 return self.iobus.mem_side_ports


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6879c9744c28038c5d40984785f2f502a2fd1c5a
Gerrit-Change-Number: 52185
Gerrit-PatchSet: 12
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove SimpleBoard as a superclass

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51790 )


Change subject: stdlib: Remove SimpleBoard as a superclass
..

stdlib: Remove SimpleBoard as a superclass

Previously SimpleBoard inherited from AbstractBoard and X86Board and
RiscvBoard inherited from the SimpleBoard. This has been shown to be a
needless level of abstraction. As such, this commit refactors the code
to have X86Board and RiscvBoard inherit directly from AbstractBoard.
Code common to the SimpleBoard, X86Board, and RiscvBoard has been moved
to the AbstractBoard.

Change-Id: I5a2c7404efeb4f8ddcb5d8006e3c163d10b88b2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51790
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/simple_board.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/components/boards/test_board.py
M src/python/gem5/components/boards/x86_board.py
M src/python/gem5/components/boards/abstract_board.py
5 files changed, 96 insertions(+), 63 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index 165b0d9..845ccb2 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -26,9 +26,16 @@

 from abc import ABCMeta, abstractmethod

-from .mem_mode import MemMode
+from .mem_mode import MemMode, mem_mode_to_string

-from m5.objects import System, Port, IOXBar, ClockDomain
+from m5.objects import (
+System,
+Port,
+IOXBar,
+ClockDomain,
+SrcClockDomain,
+VoltageDomain,
+)

 from typing import List

@@ -56,17 +63,31 @@

 def __init__(
 self,
+clk_freq: str,
 processor: "AbstractProcessor",
 memory: "AbstractMemory",
 cache_hierarchy: "AbstractCacheHierarchy",
+exit_on_work_items: bool = False,
 ) -> None:
 super(AbstractBoard, self).__init__()
 """
+:param clk_freq: The clock frequency for this board.
 :param processor: The processor for this board.
 :param memory: The memory for this board.
 :param cache_hierarchy: The Cachie Hierarchy for this board.
+:param exit_on_work_items: Whether the simulation should exit
+on work items.
 """

+# Set up the clock domain and the voltage domain.
+self.clk_domain = SrcClockDomain()
+self.clk_domain.clock = clk_freq
+self.clk_domain.voltage_domain = VoltageDomain()
+
+# Set whether to exit on work items.
+self.exit_on_work_items = exit_on_work_items
+
+# Set the processor, memory, and cache hierarchy.
 self.processor = processor
 self.memory = memory
 self.cache_hierarchy = cache_hierarchy
@@ -101,6 +122,24 @@
 """
 return self.cache_line_size

+def connect_system_port(self, port: Port) -> None:
+self.system_port = port
+
+def set_mem_mode(self, mem_mode: MemMode) -> None:
+"""
+Set the memory mode of the board.
+
+:param mem_mode: The memory mode the board is to be set to.
+"""
+self.mem_mode = mem_mode_to_string(mem_mode=mem_mode)
+
+def get_clock_domain(self) -> ClockDomain:
+"""Get the clock domain.
+
+:returns: The clock domain.
+"""
+return self.clk_domain
+
 # Technically `get_dma_ports` returns a list. This list could be empty  
to

 # indicate the presense of dma ports. Though I quite like having this
 # boolean to quickly check a board.
@@ -165,27 +204,6 @@
 raise NotImplementedError

 @abstractmethod
-def get_clock_domain(self) -> ClockDomain:
-"""Get the clock domain.
-
-:returns: The clock domain.
-"""
-raise NotImplementedError
-
-@abstractmethod
-def connect_system_port(self, port: Port) -> None:
-raise NotImplementedError
-
-@abstractmethod
-def set_mem_mode(self, mem_mode: MemMode) -> None:
-"""
-Set the memory mode of the board.
-
-:param mem_mode: The memory mode the board is to be set to.
-"""
-raise NotImplementedError
-
-@abstractmethod
 def setup_memory_ranges(self) -> None:
 """
 Set the memory ranges for this board.
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index d42cfd5..43a5112 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -25,10 +25,9 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 import os
-from typing import Optional
+from typing 

[gem5-dev] Change in gem5/gem5[develop]: tests: Update RISCV boot tests to use Ubuntu resource

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52089 )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Update RISCV boot tests to use Ubuntu resource
..

tests: Update RISCV boot tests to use Ubuntu resource

This ubuntu disk image will execute an 'm5 exit' after boot and can
therefore be used to execute "boot exit" tests as part of our
long/nightly tests. These are included in this patch.

Change-Id: Ia5bdb1bfc3d9100b2ea15e23bddb49f7c4faf32d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52089
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/configs/riscv_boot_exit_run.py
2 files changed, 83 insertions(+), 22 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index 93069f8..629a0d0 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -80,7 +80,7 @@
 "-t",
 "--tick-exit",
 type=int,
-required=True,
+required=False,
 help="The tick to exit the simulation.",
 )

@@ -152,7 +152,7 @@
 resource_directory=args.resource_directory,
 ),
 disk_image=Resource(
-"riscv-disk-img",
+"riscv-ubuntu-20.04-img",
 resource_directory=args.resource_directory,
 ),
 )
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py  
b/tests/gem5/riscv-boot-tests/test_linux_boot.py

index 8cced2d..7c70d1d 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -26,6 +26,8 @@

 import re

+from typing import Optional
+
 from testlib import *

 if config.bin_path:
@@ -38,10 +40,11 @@
 cpu: str,
 num_cpus: int,
 cache_type: str,
-to_tick: int,
 length: str,
+to_tick: Optional[int] = None,
 ):
-name = "{}-cpu_{}-{}-cores_riscv-boot-test_to-tick".format(
+
+name = "{}-cpu_{}-{}-cores_riscv-boot-test".format(
 cpu, str(num_cpus), cache_type)

 verifiers = []
@@ -52,6 +55,21 @@
 )
 verifiers.append(verifier.MatchRegex(exit_regex))

+config_args=[
+"--cpu",
+cpu,
+"--num-cpus",
+str(num_cpus),
+"--mem-system",
+cache_type,
+"--resource-directory",
+resource_path,
+]
+
+if to_tick:
+name += "_to-tick"
+config_args += ["--tick-exit", str(to_tick)]
+
 gem5_verify_config(
 name=name,
 verifiers=verifiers,
@@ -63,18 +81,7 @@
 "configs",
 "riscv_boot_exit_run.py",
 ),
-config_args=[
-"--cpu",
-cpu,
-"--num-cpus",
-str(num_cpus),
-"--mem-system",
-cache_type,
-"--tick-exit",
-str(to_tick),
-"--resource-directory",
-resource_path,
-],
+config_args=config_args,
 valid_isas=(constants.riscv_tag,),
 valid_hosts=constants.supported_hosts,
 length=length,
@@ -87,46 +94,83 @@
 cpu="atomic",
 num_cpus=1,
 cache_type="classic",
-to_tick=100,  # Simulates 1/100th of a second.
 length=constants.quick_tag,
+to_tick=100,  # Simulates 1/100th of a second.
 )

 test_boot(
 cpu="timing",
 num_cpus=1,
 cache_type="classic",
-to_tick=100,
 length=constants.quick_tag,
+to_tick=100,
 )

 test_boot(
 cpu="timing",
 num_cpus=1,
 cache_type="mi_example",
-to_tick=100,
 length=constants.quick_tag,
+to_tick=100,
 )

 test_boot(
 cpu="o3",
 num_cpus=1,
 cache_type="classic",
-to_tick=100,
 length=constants.quick_tag,
+to_tick=100,
 )

 test_boot(
 cpu="timing",
 num_cpus=4,
 cache_type="classic",
-to_tick=100,
 length=constants.quick_tag,
+to_tick=100,
 )

 test_boot(
 cpu="timing",
 num_cpus=4,
 cache_type="mi_example",
-to_tick=100,
 length=constants.quick_tag,
+to_tick=100,
+)
+
+ The long (Nightly) tests 
+
+test_boot(
+cpu="atomic",
+num_cpus=1,
+cache_type="classic",
+length=constants.long_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=1,
+cache_type="mi_example",
+length=constants.long_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=4,
+cache_type="mi_example",
+length=constants.long_tag,
+)
+
+test_boot(
+cpu="atomic",
+num_cpus=4,
+cache_type="classic",
+length=constants.long_tag,
+)
+
+test_boot(
+cpu="o3",

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Fix resource downloader download to cwd upon failure

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52423 )


Change subject: stdlib: Fix resource downloader download to cwd upon failure
..

stdlib: Fix resource downloader download to cwd upon failure

There are some cases where default downloading to `~/.cache/gem5` will
not work (for example, running gem5 in a Docker container, an error
observed here:
https://gem5-review.googlesource.com/c/public/gem5/+/51950).

To fix this, the `_get_default_resource_dir` has been altered to iterate
through a list of default resource directory targets. This change will
mean if `~/.cache/gem5` is not available then the resource is downloaded
to the current working directory of gem5.

Change-Id: I84e523f3adc182e140959243ff9335510d6b7185
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52423
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/python/gem5/resources/resource.py
1 file changed, 46 insertions(+), 3 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/resources/resource.py  
b/src/python/gem5/resources/resource.py

index b054b09..1abc9b4 100644
--- a/src/python/gem5/resources/resource.py
+++ b/src/python/gem5/resources/resource.py
@@ -102,7 +102,7 @@
 :param resource_directory: The location of the directory in which  
the
 resource is to be stored. If this parameter is not set, it will  
set to
 the environment variable `GEM5_RESOURCE_DIR`. If the environment  
is not

-set it will default to `~/.cache/gem5`.
+set it will default to `~/.cache/gem5` if available, otherwise the  
CWD.

 :param override: If the resource is present, but does not have the
 correct md5 value, the resoruce will be deleted and re-downloaded  
if

 this value is True. Otherwise an exception will be thrown. False by
@@ -137,8 +137,28 @@

 def _get_default_resource_dir(cls) -> str:
 """
-Obtain the default gem5 resources directory on the host system.
+Obtain the default gem5 resources directory on the host system.  
This
+function will iterate through sensible targets until it finds one  
that

+works on the host system.

 :returns: The default gem5 resources directory.
 """
-return os.path.join(Path.home(), ".cache", "gem5")
+test_list = [
+# First try `~/.cache/gem5`.
+os.path.join(Path.home(), ".cache", "gem5"),
+# Last resort, just put things in the cwd.
+os.path.join(Path.cwd(), "resources"),
+]
+
+for path in test_list:
+if os.path.exists(path): # If the path already exists...
+if os.path.isdir(path): # Check to see the path is a  
directory.

+return path # If so, the path is valid and can be used.
+else: # If the path does not exist, try to create it.
+try:
+os.makedirs(path, exist_ok=False)
+return path
+except OSError:
+continue # If the path cannot be created, then try  
another.

+
+raise Exception("Cannot find a valid location to download  
resources")


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52423
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I84e523f3adc182e140959243ff9335510d6b7185
Gerrit-Change-Number: 52423
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add a weekly test for SST integration.

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52564 )



Change subject: tests: Add a weekly test for SST integration.
..

tests: Add a weekly test for SST integration.

This test includes,
- A dockerfile creating a Docker image containing SST-Core
and SST-Elements installed. The image also contains the
bbl-busybox-boot-exit binary from gem5-resources.
- A week test involving compiling gem5 as a library, and
booting a linux kernel without a disk image using SST where
gem5 TimingSimpleCPU is the CPU core.

Change-Id: I2bf90b4121ed0d38300451648f2e358a7c3fffe2
Signed-off-by: Hoa Nguyen 
---
M tests/weekly.sh
A util/dockerfiles/sst-11.1.0/Dockerfile
2 files changed, 108 insertions(+), 0 deletions(-)



diff --git a/tests/weekly.sh b/tests/weekly.sh
index 393c66f..882da7b 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -39,7 +39,26 @@
 threads=$1
 fi

+build_and_run_SST () {
+isa=$1
+variant=$2
+
+docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" --rm TODO? \
+bash -c "\
+scons build/${isa}/libgem5_${variant}.so -j${threads} --without-tcmalloc; \
+cd ext/sst; \
+make clean; make -j ${threads}; \
+ln -s /resources/bbl-busybox-boot-exit; \
+sst --add-lib-path=./ sst/example.py; \
+"
+}
+
 # Run the gem5 very-long tests.
 docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
 "${gem5_root}"/tests --rm  
gcr.io/gem5-test/ubuntu-20.04_all-dependencies \

 ./main.py run --length very-long -j${threads} -t${threads}
+
+# Run an SST test.
+build_and_run_SST RISCV opt
+
diff --git a/util/dockerfiles/sst-11.1.0/Dockerfile  
b/util/dockerfiles/sst-11.1.0/Dockerfile

new file mode 100644
index 000..e30cdea
--- /dev/null
+++ b/util/dockerfiles/sst-11.1.0/Dockerfile
@@ -0,0 +1,71 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+FROM ubuntu:20.04
+
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
+libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

+python3-dev python3-six python-is-python3 doxygen libboost-all-dev \
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config pip \
+python3-venv wget
+
+ENV SST_CORE_HOME="/sst/"
+
+# SST Stuff
+RUN mkdir /sst
+
+# Download and build SST-Core without MPI support
+WORKDIR /sst/
+RUN wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.1.0_Final/sstcore-11.1.0.tar.gz;  
\

+tar xf sstcore-11.1.0.tar.gz;
+WORKDIR /sst/sstcore-11.1.0/
+RUN ./configure --prefix=$SST_CORE_HOME  
--with-python=/usr/bin/python3-config \

+--disable-mpi; \
+make all -j $(nproc); \
+make install;
+
+# Download and build SST-Elements
+WORKDIR /sst
+RUN wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.1.0_Final/sstelements-11.1.0.tar.gz;  
\

+tar xf sstelements-11.1.0.tar.gz;
+WORKDIR /sst/sst-elements-library-11.1.0/
+RUN ./configure --prefix=$SST_CORE_HOME  
--with-python=/usr/bin/python3-config \

+--with-sst-core=$SST_CORE_HOME; \
+make all -j $(nproc); \
+make install;
+
+# Download the disk image
+RUN mkdir /resources/
+WORKDIR /resources/
+RUN wget  

[gem5-dev] Re: multi-ISA gem5 proof of concept

[Gabe Black via gem5-dev]

This is discussed here:

https://gem5.atlassian.net/browse/GEM5-1058

The CPUs are ISA specific as used, and this makes that more explicit. It
also makes it clear whether a CPU is supported with a particular ISA, since
if it isn't, it's not possible to put it into a config without adding the
plumbing.

By having those ISA specific CPU variants, they just show up as options for
--cpu-type which makes se.py usable without modification. It would be
possible to make configs work with an option like --isa, but there are at
least three problems with that sort of approach.

First, we should move away from this swiss army knife approach to writing
configs where it can do anything, and we try to figure out how to make it
work with complicated logic in the config. It's not likely that someone
doing research would need to be able to transparently switch from using X86
to using RISCV without changing their config.

Second, while many of our existing configs are single ISA, that is not
required. On this branch, you could write a config which uses all 6 ISAs
simultaneously as different machines in the same simulation, or even as a
single frankenstein machine. Practically speaking, that can be useful (or
even necessary) if there are different types of devices talking to each
other in a network, or if the main SOC or application processor uses one
architecture, but then subcomponents like accelerators, peripherals,
management processors, etc, use some other architecture. On modern systems,
there are usually many additional CPUs tucked into all kinds of places
running various firmwares, and they don't always use the same ISA as the
user sees.

Third, that perpetuates having a big drop down box with ISAs on it, as if
ISAs were paint that could be applied to a system after it was constructed,
and as if ISAs were single, well defined options which were completely
defined by this one choice. There are many variations of ARM CPUs, x86
CPUs, etc, and in RISCV there are even supposedly many variations of the
ISA itself, depending on what extensions are enabled. Which ISA you pick is
more integral and more specific than we've treated it in our configs, and
using a --isa option would continue to bake that in.

That said, while I think having a --isa option has a lot of problems and is
not a good practice, exactly how a config script decides what components to
use is really up to that script. If we want to build some mechanism which
uses tables or long if-then trees in functions to figure out how to build
up a system with a given ISA, nothing here would stop that.

Gabe

On Mon, Nov 8, 2021 at 11:03 AM Bobby Bruce  wrote:

> Looks good to me.
>
> Perhaps this is explained elsewhere, but what's the logic in coupling the
> CPU Type (Timing, Atomic, o3) with the ISA? Why do we interact with this
> like `--cpu-type=X86AtomicSimpleCPU` and not `--cpu-type AtomicSimpleCPU
> --isa=X86`? Current CPU types are switchable during a simulation, so they
> are a parameter that can change, but the simulation's ISA, I assume, will
> always fixed for the entirety of a run.
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Mon, Nov 8, 2021 at 8:40 AM Jason Lowe-Power via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> This looks quite promising! Uploading a branch to gerrit is a good idea.
>>
>> A couple of notes:
>> 1. We are going to have to be very careful with when/how we merge this
>> and its effect on users. For instance, changing the CPU from
>> "AtomicSimpleCPU" to "ArmAtomicSimpleCPU" will break many users' use cases.
>> 2. I just noticed that there's something wrong with the Arm hello
>> application: "Simulated exit code not 0! Exit code is 13" It looks like
>> current develop also has this problem, but it's a bit worrying. I can't
>> figure out why the hello application wouldn't exit with code 0...
>>
>> Cheers,
>> Jason
>>
>> On Sun, Nov 7, 2021 at 5:38 PM Gabe Black via gem5-dev 
>> wrote:
>>
>>> Build performance improvements:
>>>
>>>
>>> Building all 6 ISAs separately.
>>>
>>> $ time scons build/ARM/gem5.opt build/MIPS/gem5.opt build/POWER/gem5.opt
>>> build/RISCV/gem5.opt build/SPARC/gem5.opt build/X86/gem5.opt
>>>
>>> real37m0.210s
>>> user764m20.963s
>>> sys 46m18.113s
>>>
>>> $ du -sh build
>>> 16G build
>>>
>>>
>>> Building "ALL" which has all 6 ISAs enabled together.
>>>
>>> $ time scons build/ALL/gem5.opt
>>>
>>> real10m28.289s
>>> user194m31.505s
>>> sys 9m36.281s
>>>
>>> $ du -sh build
>>> 4.2Gbuild
>>>
>>>
>>> Which is a build time reduction of about 72% on my system, and a build
>>> directory size reduction of about 73%.
>>>
>>> Gabe
>>>
>>> On Sat, Nov 6, 2021 at 12:29 AM Gabe Black  wrote:
>>>
 As mentioned in the other thread, I can upload this hash as a branch on
 gerrit if people want to try it out.

 Gabe

 $ git log --oneline origin/develop..multiarch | wc -l
 203

 $ 

[gem5-dev] Re: multi-ISA gem5 proof of concept

[Gabe Black via gem5-dev]

On Mon, Nov 8, 2021 at 8:40 AM Jason Lowe-Power  wrote:

> This looks quite promising! Uploading a branch to gerrit is a good idea.
>

Ok, I'll do that. All but 4 of the changes in this composite branch are
uploaded for review, and these few extras are because they depend on all of
the switching header files being gone.


>
> A couple of notes:
> 1. We are going to have to be very careful with when/how we merge this and
> its effect on users. For instance, changing the CPU from "AtomicSimpleCPU"
> to "ArmAtomicSimpleCPU" will break many users' use cases.
>

As written, are compatibility aliases which are enabled if there is exactly
one ISA enabled, so existing users will be able to keep using their
existing build configuration and config scripts, as will we as we
transition things over.


> 2. I just noticed that there's something wrong with the Arm hello
> application: "Simulated exit code not 0! Exit code is 13" It looks like
> current develop also has this problem, but it's a bit worrying. I can't
> figure out why the hello application wouldn't exit with code 0...
>
>
This is a known issue. I think it was because we don't explicitly return
anything from main, and so the return value from printf is still in the
return value register, which is the number of characters printed.


> Cheers,
> Jason
>
> On Sun, Nov 7, 2021 at 5:38 PM Gabe Black via gem5-dev 
> wrote:
>
>> Build performance improvements:
>>
>>
>> Building all 6 ISAs separately.
>>
>> $ time scons build/ARM/gem5.opt build/MIPS/gem5.opt build/POWER/gem5.opt
>> build/RISCV/gem5.opt build/SPARC/gem5.opt build/X86/gem5.opt
>>
>> real37m0.210s
>> user764m20.963s
>> sys 46m18.113s
>>
>> $ du -sh build
>> 16G build
>>
>>
>> Building "ALL" which has all 6 ISAs enabled together.
>>
>> $ time scons build/ALL/gem5.opt
>>
>> real10m28.289s
>> user194m31.505s
>> sys 9m36.281s
>>
>> $ du -sh build
>> 4.2Gbuild
>>
>>
>> Which is a build time reduction of about 72% on my system, and a build
>> directory size reduction of about 73%.
>>
>> Gabe
>>
>> On Sat, Nov 6, 2021 at 12:29 AM Gabe Black  wrote:
>>
>>> As mentioned in the other thread, I can upload this hash as a branch on
>>> gerrit if people want to try it out.
>>>
>>> Gabe
>>>
>>> $ git log --oneline origin/develop..multiarch | wc -l
>>> 203
>>>
>>> $ build/ALL/gem5.opt configs/example/se.py --cpu-type=ArmAtomicSimpleCPU
>>> -c tests/test-progs/hello/bin/arm/linux/hello
>>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy
>>> stat. Legacy stat is a stat that does not belong to any statistics::Group.
>>> Legacy stat is deprecated.
>>> gem5 Simulator System.  http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 version [DEVELOP-FOR-V21.2]
>>> gem5 compiled Nov  6 2021 00:23:55
>>> gem5 started Nov  6 2021 00:25:58
>>> gem5 executing on cake, pid 999191
>>> command line: build/ALL/gem5.opt configs/example/se.py
>>> --cpu-type=ArmAtomicSimpleCPU -c tests/test-progs/hello/bin/arm/linux/hello
>>>
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> Global frequency set at 1 ticks per second
>>> build/ALL/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (512 Mbytes)
>>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>>  REAL SIMULATION 
>>> build/ALL/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
>>> simulation...
>>> Hello world!
>>> Exiting @ tick 2916500 because exiting with last active thread context
>>> Simulated exit code not 0! Exit code is 13
>>>
>>>
>>>
>>> [gblack@cake work]$ build/ALL/gem5.opt configs/example/se.py
>>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello
>>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy
>>> stat. Legacy stat is a stat that does not belong to any statistics::Group.
>>> Legacy stat is deprecated.
>>> gem5 Simulator System.  http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 version [DEVELOP-FOR-V21.2]
>>> gem5 compiled Nov  6 2021 00:23:55
>>> gem5 started Nov  6 2021 00:26:10
>>> gem5 executing on cake, pid 999224
>>> command line: build/ALL/gem5.opt configs/example/se.py
>>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello
>>>
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is 

[gem5-dev] Re: failing kvm tests

[Bobby Bruce via gem5-dev]

Yip, I accidentally added some X86 tests to the quick/Kokoro tests. Thanks
for pointing that out. The fix can be found here:
https://gem5-review.googlesource.com/c/public/gem5/+/52563

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Mon, Nov 8, 2021 at 5:03 AM Gabe Black  wrote:

> Just a quick note, I noticed when running quick regressions now that it
> builds both GC_X86 and X86. I'm assuming that's because the KVM tests are
> still set up to use X86? It would be nice to fix that to avoid building for
> an additional target.
>
> Gabe
>
> On Wed, Nov 3, 2021 at 10:55 AM Bobby Bruce  wrote:
>
>> Hey Gabe,
>>
>> At present our Jenkins doesn't have KVM enabled so I believe no tests
>> that use KVM were being run regularly. I intend to get KVM enabled on the
>> Jenkins server over the next few days. I also found the bugs you were
>> referring to when running the long (nightly) and very-long (weekly) tests
>> on my local machine (where I have KVM). The long tests are fixed with this
>> patch: https://gem5-review.googlesource.com/c/public/gem5/+/52384, and
>> I'm currently looking into the bugs in the very-long tests.
>>
>> Kind regards,
>> Bobby
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Wed, Nov 3, 2021 at 4:22 AM Gabe Black via gem5-dev 
>> wrote:
>>
>>> Hey folks, I recently discovered KVM wasn't set up on my desktop, which
>>> I just corrected. Now that it's enabled, the KVM tests have started
>>> running, and they are also failing. This could be sort of weird issue on my
>>> machine, and I'm currently looking into the failure itself.
>>>
>>> The thing I wanted to ask was, do we have any KVM tests that run
>>> anywhere? Do we have them in the quick regressions but not the long
>>> regressions? Do we have KVM enabled on the nightly server? I can imagine it
>>> (KVM) not being enabled on kokoro, but hopefully we can run those on the
>>> nightlies?
>>>
>>> Gabe
>>> ___
>>> gem5-dev mailing list -- gem5-dev@gem5.org
>>> To unsubscribe send an email to gem5-dev-le...@gem5.org
>>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>
>>
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[gem5-dev] Change in gem5/gem5[develop]: tests: Move MI_Example tests to Long/Nightly

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52563 )



Change subject: tests: Move MI_Example tests to Long/Nightly
..

tests: Move MI_Example tests to Long/Nightly

Two tests, one in test_kvm_fork_run.py and another in
test_kvm_cpu_switch.py, were trying to run the MI_Example protocol as
part of the quick/kokoro run. MI_Example requires the building of X86,
though we try to use GCN3_X86 exclusively to avoid compiling an
additional target. As such, these MI_Example tests have been moved to
the long/nightly run.

Change-Id: I3c196e7e336148a1b7a124b5810348a2e587fe24
---
M tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
M tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
2 files changed, 22 insertions(+), 6 deletions(-)



diff --git a/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py  
b/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py

index c62211e..6471034 100644
--- a/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
+++ b/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
@@ -108,15 +108,15 @@
 cpu="timing", num_cpus=4, mem_system="classic",  
length=constants.quick_tag

 )

+### The long (nightly) tests 
+
 test_kvm_fork_run(
 cpu="timing",
 num_cpus=4,
 mem_system="mi_example",
-length=constants.quick_tag,
+length=constants.long_tag,
 )

-### The long (nightly) tests 
-
 test_kvm_fork_run(
 cpu="timing",
 num_cpus=1,
diff --git a/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py  
b/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py

index a8cbce1..36473d4 100644
--- a/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
+++ b/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
@@ -106,15 +106,15 @@
 cpu="timing", num_cpus=4, mem_system="classic",  
length=constants.quick_tag

 )

+### The long (nightly) tests 
+
 test_kvm_switch(
 cpu="timing",
 num_cpus=4,
 mem_system="mi_example",
-length=constants.quick_tag,
+length=constants.long_tag,
 )

-### The long (nightly) tests 
-
 test_kvm_switch(
 cpu="timing",
 num_cpus=1,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52563
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3c196e7e336148a1b7a124b5810348a2e587fe24
Gerrit-Change-Number: 52563
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Re: multi-ISA gem5 proof of concept

[Bobby Bruce via gem5-dev]

Looks good to me.

Perhaps this is explained elsewhere, but what's the logic in coupling the
CPU Type (Timing, Atomic, o3) with the ISA? Why do we interact with this
like `--cpu-type=X86AtomicSimpleCPU` and not `--cpu-type AtomicSimpleCPU
--isa=X86`? Current CPU types are switchable during a simulation, so they
are a parameter that can change, but the simulation's ISA, I assume, will
always fixed for the entirety of a run.

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Mon, Nov 8, 2021 at 8:40 AM Jason Lowe-Power via gem5-dev <
gem5-dev@gem5.org> wrote:

> This looks quite promising! Uploading a branch to gerrit is a good idea.
>
> A couple of notes:
> 1. We are going to have to be very careful with when/how we merge this and
> its effect on users. For instance, changing the CPU from "AtomicSimpleCPU"
> to "ArmAtomicSimpleCPU" will break many users' use cases.
> 2. I just noticed that there's something wrong with the Arm hello
> application: "Simulated exit code not 0! Exit code is 13" It looks like
> current develop also has this problem, but it's a bit worrying. I can't
> figure out why the hello application wouldn't exit with code 0...
>
> Cheers,
> Jason
>
> On Sun, Nov 7, 2021 at 5:38 PM Gabe Black via gem5-dev 
> wrote:
>
>> Build performance improvements:
>>
>>
>> Building all 6 ISAs separately.
>>
>> $ time scons build/ARM/gem5.opt build/MIPS/gem5.opt build/POWER/gem5.opt
>> build/RISCV/gem5.opt build/SPARC/gem5.opt build/X86/gem5.opt
>>
>> real37m0.210s
>> user764m20.963s
>> sys 46m18.113s
>>
>> $ du -sh build
>> 16G build
>>
>>
>> Building "ALL" which has all 6 ISAs enabled together.
>>
>> $ time scons build/ALL/gem5.opt
>>
>> real10m28.289s
>> user194m31.505s
>> sys 9m36.281s
>>
>> $ du -sh build
>> 4.2Gbuild
>>
>>
>> Which is a build time reduction of about 72% on my system, and a build
>> directory size reduction of about 73%.
>>
>> Gabe
>>
>> On Sat, Nov 6, 2021 at 12:29 AM Gabe Black  wrote:
>>
>>> As mentioned in the other thread, I can upload this hash as a branch on
>>> gerrit if people want to try it out.
>>>
>>> Gabe
>>>
>>> $ git log --oneline origin/develop..multiarch | wc -l
>>> 203
>>>
>>> $ build/ALL/gem5.opt configs/example/se.py --cpu-type=ArmAtomicSimpleCPU
>>> -c tests/test-progs/hello/bin/arm/linux/hello
>>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy
>>> stat. Legacy stat is a stat that does not belong to any statistics::Group.
>>> Legacy stat is deprecated.
>>> gem5 Simulator System.  http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 version [DEVELOP-FOR-V21.2]
>>> gem5 compiled Nov  6 2021 00:23:55
>>> gem5 started Nov  6 2021 00:25:58
>>> gem5 executing on cake, pid 999191
>>> command line: build/ALL/gem5.opt configs/example/se.py
>>> --cpu-type=ArmAtomicSimpleCPU -c tests/test-progs/hello/bin/arm/linux/hello
>>>
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> Global frequency set at 1 ticks per second
>>> build/ALL/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
>>> Mbytes) does not match the address range assigned (512 Mbytes)
>>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>>  REAL SIMULATION 
>>> build/ALL/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
>>> simulation...
>>> Hello world!
>>> Exiting @ tick 2916500 because exiting with last active thread context
>>> Simulated exit code not 0! Exit code is 13
>>>
>>>
>>>
>>> [gblack@cake work]$ build/ALL/gem5.opt configs/example/se.py
>>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello
>>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy
>>> stat. Legacy stat is a stat that does not belong to any statistics::Group.
>>> Legacy stat is deprecated.
>>> gem5 Simulator System.  http://gem5.org
>>> gem5 is copyrighted software; use the --copyright option for details.
>>>
>>> gem5 version [DEVELOP-FOR-V21.2]
>>> gem5 compiled Nov  6 2021 00:23:55
>>> gem5 started Nov  6 2021 00:26:10
>>> gem5 executing on cake, pid 999224
>>> command line: build/ALL/gem5.opt configs/example/se.py
>>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello
>>>
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>>> warn: membus.slave is deprecated. `slave` is 

[gem5-dev] Re: multi-ISA gem5 proof of concept

[Jason Lowe-Power via gem5-dev]

This looks quite promising! Uploading a branch to gerrit is a good idea.

A couple of notes:
1. We are going to have to be very careful with when/how we merge this and
its effect on users. For instance, changing the CPU from "AtomicSimpleCPU"
to "ArmAtomicSimpleCPU" will break many users' use cases.
2. I just noticed that there's something wrong with the Arm hello
application: "Simulated exit code not 0! Exit code is 13" It looks like
current develop also has this problem, but it's a bit worrying. I can't
figure out why the hello application wouldn't exit with code 0...

Cheers,
Jason

On Sun, Nov 7, 2021 at 5:38 PM Gabe Black via gem5-dev 
wrote:

> Build performance improvements:
>
>
> Building all 6 ISAs separately.
>
> $ time scons build/ARM/gem5.opt build/MIPS/gem5.opt build/POWER/gem5.opt
> build/RISCV/gem5.opt build/SPARC/gem5.opt build/X86/gem5.opt
>
> real37m0.210s
> user764m20.963s
> sys 46m18.113s
>
> $ du -sh build
> 16G build
>
>
> Building "ALL" which has all 6 ISAs enabled together.
>
> $ time scons build/ALL/gem5.opt
>
> real10m28.289s
> user194m31.505s
> sys 9m36.281s
>
> $ du -sh build
> 4.2Gbuild
>
>
> Which is a build time reduction of about 72% on my system, and a build
> directory size reduction of about 73%.
>
> Gabe
>
> On Sat, Nov 6, 2021 at 12:29 AM Gabe Black  wrote:
>
>> As mentioned in the other thread, I can upload this hash as a branch on
>> gerrit if people want to try it out.
>>
>> Gabe
>>
>> $ git log --oneline origin/develop..multiarch | wc -l
>> 203
>>
>> $ build/ALL/gem5.opt configs/example/se.py --cpu-type=ArmAtomicSimpleCPU
>> -c tests/test-progs/hello/bin/arm/linux/hello
>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy
>> stat. Legacy stat is a stat that does not belong to any statistics::Group.
>> Legacy stat is deprecated.
>> gem5 Simulator System.  http://gem5.org
>> gem5 is copyrighted software; use the --copyright option for details.
>>
>> gem5 version [DEVELOP-FOR-V21.2]
>> gem5 compiled Nov  6 2021 00:23:55
>> gem5 started Nov  6 2021 00:25:58
>> gem5 executing on cake, pid 999191
>> command line: build/ALL/gem5.opt configs/example/se.py
>> --cpu-type=ArmAtomicSimpleCPU -c tests/test-progs/hello/bin/arm/linux/hello
>>
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> Global frequency set at 1 ticks per second
>> build/ALL/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
>> Mbytes) does not match the address range assigned (512 Mbytes)
>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>  REAL SIMULATION 
>> build/ALL/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
>> simulation...
>> Hello world!
>> Exiting @ tick 2916500 because exiting with last active thread context
>> Simulated exit code not 0! Exit code is 13
>>
>>
>>
>> [gblack@cake work]$ build/ALL/gem5.opt configs/example/se.py
>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello
>> build/ALL/base/statistics.hh:280: warn: One of the stats is a legacy
>> stat. Legacy stat is a stat that does not belong to any statistics::Group.
>> Legacy stat is deprecated.
>> gem5 Simulator System.  http://gem5.org
>> gem5 is copyrighted software; use the --copyright option for details.
>>
>> gem5 version [DEVELOP-FOR-V21.2]
>> gem5 compiled Nov  6 2021 00:23:55
>> gem5 started Nov  6 2021 00:26:10
>> gem5 executing on cake, pid 999224
>> command line: build/ALL/gem5.opt configs/example/se.py
>> --cpu-type=X86AtomicSimpleCPU -c tests/test-progs/hello/bin/x86/linux/hello
>>
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>> warn: membus.master is deprecated. `master` is now called `mem_side_ports`
>> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
>> Global frequency set at 1 ticks per second
>> build/ALL/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
>> Mbytes) does not match the address range assigned (512 Mbytes)
>> 0: system.remote_gdb: listening for remote gdb on port 7000
>>  REAL SIMULATION 
>> build/ALL/sim/simulate.cc:194: info: Entering 

[gem5-dev] Re: failing kvm tests

[Gabe Black via gem5-dev]

Just a quick note, I noticed when running quick regressions now that it
builds both GC_X86 and X86. I'm assuming that's because the KVM tests are
still set up to use X86? It would be nice to fix that to avoid building for
an additional target.

Gabe

On Wed, Nov 3, 2021 at 10:55 AM Bobby Bruce  wrote:

> Hey Gabe,
>
> At present our Jenkins doesn't have KVM enabled so I believe no tests
> that use KVM were being run regularly. I intend to get KVM enabled on the
> Jenkins server over the next few days. I also found the bugs you were
> referring to when running the long (nightly) and very-long (weekly) tests
> on my local machine (where I have KVM). The long tests are fixed with this
> patch: https://gem5-review.googlesource.com/c/public/gem5/+/52384, and
> I'm currently looking into the bugs in the very-long tests.
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Wed, Nov 3, 2021 at 4:22 AM Gabe Black via gem5-dev 
> wrote:
>
>> Hey folks, I recently discovered KVM wasn't set up on my desktop, which I
>> just corrected. Now that it's enabled, the KVM tests have started running,
>> and they are also failing. This could be sort of weird issue on my machine,
>> and I'm currently looking into the failure itself.
>>
>> The thing I wanted to ask was, do we have any KVM tests that run
>> anywhere? Do we have them in the quick regressions but not the long
>> regressions? Do we have KVM enabled on the nightly server? I can imagine it
>> (KVM) not being enabled on kokoro, but hopefully we can run those on the
>> nightlies?
>>
>> Gabe
>> ___
>> gem5-dev mailing list -- gem5-dev@gem5.org
>> To unsubscribe send an email to gem5-dev-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
>
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[gem5-dev] Jenkins build is back to normal : nightly #36

[jenkins-no-reply--- via gem5-dev]

See 
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[gem5-dev] Change in gem5/gem5[develop]: Fix for 11.16 fastmodel

[Earl Ou (Gerrit) via gem5-dev]

Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52543 )



Change subject: Fix for 11.16 fastmodel
..

Fix for 11.16 fastmodel

Change-Id: Id6bfa1c374e9c9e65f2c234654f87567d2b29c09
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 60 insertions(+), 51 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index 735e06d..ff82bbe 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -310,67 +310,67 @@
 { ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
 // ArmISA::MISCREG_CSSELR_NS?
 // ArmISA::MISCREG_CSSELR_S?
-{ ArmISA::MISCREG_VPIDR, "VPIDR" },
-{ ArmISA::MISCREG_VMPIDR, "VMPIDR" },
+// ArmISA::MISCREG_VPIDR?
+// ArmISA::MISCREG_VMPIDR?,
 // ArmISA::MISCREG_SCTLR?
 // ArmISA::MISCREG_SCTLR_NS?
 // ArmISA::MISCREG_SCTLR_S?
 // ArmISA::MISCREG_ACTLR?
 // ArmISA::MISCREG_ACTLR_NS?
 // ArmISA::MISCREG_ACTLR_S?
-{ ArmISA::MISCREG_CPACR, "CPACR" },
+// ArmISA::MISCREG_CPACR?
 { ArmISA::MISCREG_SCR, "SCR" },
 { ArmISA::MISCREG_SDER, "SDER" },
-{ ArmISA::MISCREG_NSACR, "NSACR" },
-{ ArmISA::MISCREG_HSCTLR, "HSCTLR" },
-{ ArmISA::MISCREG_HACTLR, "HACTLR" },
-{ ArmISA::MISCREG_HCR, "HCR" },
-{ ArmISA::MISCREG_HDCR, "HDCR" },
-{ ArmISA::MISCREG_HCPTR, "HCPTR" },
+// ArmISA::MISCREG_NSACR?
+// ArmISA::MISCREG_HSCTLR?
+// ArmISA::MISCREG_HACTLR?
+// ArmISA::MISCREG_HCR?
+// ArmISA::MISCREG_HDCR?
+// ArmISA::MISCREG_HCPTR?
 { ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
-{ ArmISA::MISCREG_HACR, "HACR" },
+// ArmISA::MISCREG_HACR?
 // ArmISA::MISCREG_TTBR0?
-{ ArmISA::MISCREG_TTBR0_NS, "NS_TTBR0" }, //XXX verify
+// ArmISA::MISCREG_TTBR0_NS?
 // ArmISA::MISCREG_TTBR0_S?
 // ArmISA::MISCREG_TTBR1?
-{ ArmISA::MISCREG_TTBR1_NS, "NS_TTBR1" }, //XXX verify
+// ArmISA::MISCREG_TTBR1_NS?
 // ArmISA::MISCREG_TTBR1_S?
 // ArmISA::MISCREG_TTBCR?
-{ ArmISA::MISCREG_TTBCR_NS, "NS_TTBCR" }, //XXX verify
+// ArmISA::MISCREG_TTBCR_NS?
 // ArmISA::MISCREG_TTBCR_S?
 // ArmISA::MISCREG_HTCR?
 // ArmISA::MISCREG_VTCR?
 // ArmISA::MISCREG_DACR?
-{ ArmISA::MISCREG_DACR_NS, "NS_DACR" }, //XXX verify
+// ArmISA::MISCREG_DACR_NS?
 // ArmISA::MISCREG_DACR_S?
 // ArmISA::MISCREG_DFSR?
-{ ArmISA::MISCREG_DFSR_NS, "NS_DFSR" }, //XXX verify
+// ArmISA::MISCREG_DFSR_NS?
 // ArmISA::MISCREG_DFSR_S?
 // ArmISA::MISCREG_IFSR?
-{ ArmISA::MISCREG_IFSR_NS, "NS_IFSR" },
+// ArmISA::MISCREG_IFSR_NS?
 // ArmISA::MISCREG_IFSR_S?
-{ ArmISA::MISCREG_ADFSR, "ADFSR" },
+// { ArmISA::MISCREG_ADFSR, "ADFSR" },
 // ArmISA::MISCREG_ADFSR_NS?
 // ArmISA::MISCREG_ADFSR_S?
-{ ArmISA::MISCREG_AIFSR, "AIFSR" },
+// ArmISA::MISCREG_AIFSR?
 // ArmISA::MISCREG_AIFSR_NS?
 // ArmISA::MISCREG_AIFSR_S?
 // ArmISA::MISCREG_HADFSR?
 // ArmISA::MISCREG_HAIFSR?
-{ ArmISA::MISCREG_HSR, "HSR" },
+// ArmISA::MISCREG_HSR?
 // ArmISA::MISCREG_DFAR?
-{ ArmISA::MISCREG_DFAR_NS, "NS_DFAR" }, //XXX verify
+// ArmISA::MISCREG_DFAR_NS?
 // ArmISA::MISCREG_DFAR_S?
 // ArmISA::MISCREG_IFAR?
-{ ArmISA::MISCREG_IFAR_NS, "NS_IFAR" }, //XXX verify
+// ArmISA::MISCREG_IFAR_NS?
 // ArmISA::MISCREG_IFAR_S?
-{ ArmISA::MISCREG_HDFAR, "HDFAR" },
-{ ArmISA::MISCREG_HIFAR, "HIFAR" },
-{ ArmISA::MISCREG_HPFAR, "HPFAR" },
+// ArmISA::MISCREG_HDFAR?
+// ArmISA::MISCREG_HIFAR?
+// ArmISA::MISCREG_HPFAR?
 { ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
 // ArmISA::MISCREG_BPIALLIS?
 // ArmISA::MISCREG_PAR?
-{ ArmISA::MISCREG_PAR_NS, "NS_PAR" }, //XXX verify
+// ArmISA::MISCREG_PAR_NS?
 // ArmISA::MISCREG_PAR_S?
 { ArmISA::MISCREG_ICIALLU, "ICIALLU" },
 { ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
@@ -445,50 +445,50 @@
 // ArmISA::MISCREG_L2CTLR?
 // ArmISA::MISCREG_L2ECTLR?
 // ArmISA::MISCREG_PRRR?
-{ ArmISA::MISCREG_PRRR_NS, "NS_PRRR" }, //XXX verify
+// ArmISA::MISCREG_PRRR_NS?
 // ArmISA::MISCREG_PRRR_S?
 // ArmISA::MISCREG_MAIR0?
 // ArmISA::MISCREG_MAIR0_NS?
 // ArmISA::MISCREG_MAIR0_S?
 // ArmISA::MISCREG_NMRR?
-{ ArmISA::MISCREG_NMRR_NS, "NS_NMRR" }, //XXX verify
+// ArmISA::MISCREG_NMRR_NS?