[gem5-dev] Change in gem5/gem5[develop]: tests: Disable failing tests until root cause determined
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/53504 ) Change subject: tests: Disable failing tests until root cause determined .. tests: Disable failing tests until root cause determined This should be a temporary change. Due to an issue, outlined here: https://gem5.atlassian.net/browse/GEM5-1120, these tests have been disabled. One of these tests, if not a combination of them, is causing a timeout event to occur in the Nightly tests. They have therefore been disabled until the exact cause of failure is established. Change-Id: I4303e7b157dcf32a7879b014a9f5a88efa62b756 --- M tests/gem5/x86-boot-tests/test_linux_boot.py M tests/gem5/riscv-boot-tests/test_linux_boot.py 2 files changed, 61 insertions(+), 37 deletions(-) diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py b/tests/gem5/riscv-boot-tests/test_linux_boot.py index 7c70d1d..9eb9ae3 100644 --- a/tests/gem5/riscv-boot-tests/test_linux_boot.py +++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py @@ -140,37 +140,41 @@ The long (Nightly) tests -test_boot( -cpu="atomic", -num_cpus=1, -cache_type="classic", -length=constants.long_tag, -) +# Due to Nightly test timeout issues, outlined here: +# https://gem5.atlassian.net/browse/GEM5-1120, these tests have been disabled +# until the exact error causing the Nightly tests to timeout is established. -test_boot( -cpu="timing", -num_cpus=1, -cache_type="mi_example", -length=constants.long_tag, -) +#test_boot( +#cpu="atomic", +#num_cpus=1, +#cache_type="classic", +#length=constants.long_tag, +#) -test_boot( -cpu="timing", -num_cpus=4, -cache_type="mi_example", -length=constants.long_tag, -) +#test_boot( +#cpu="timing", +#num_cpus=1, +#cache_type="mi_example", +#length=constants.long_tag, +#) -test_boot( -cpu="atomic", -num_cpus=4, -cache_type="classic", -length=constants.long_tag, -) +#test_boot( +#cpu="timing", +#num_cpus=4, +#cache_type="mi_example", +#length=constants.long_tag, +#) -test_boot( -cpu="o3", -num_cpus=8, -cache_type="mi_example", -length=constants.long_tag, -) +#test_boot( +#cpu="atomic", +#num_cpus=4, +#cache_type="classic", +#length=constants.long_tag, +#) + +#test_boot( +#cpu="o3", +#num_cpus=8, +#cache_type="mi_example", +#length=constants.long_tag, +#) diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py b/tests/gem5/x86-boot-tests/test_linux_boot.py index 600d04b..ebf520e 100644 --- a/tests/gem5/x86-boot-tests/test_linux_boot.py +++ b/tests/gem5/x86-boot-tests/test_linux_boot.py @@ -170,13 +170,18 @@ length=constants.long_tag, ) -test_boot( -cpu="o3", -num_cpus=2, -mem_system="mesi_two_level", -boot_type="init", -length=constants.long_tag, -) + +# Due to Nightly test timeout issues, outlined here: +# https://gem5.atlassian.net/browse/GEM5-1120, this test has been disabled +# until the exact error causing the Nightly tests to timeout is established. + +#test_boot( +#cpu="o3", +#num_cpus=2, +#mem_system="mesi_two_level", +#boot_type="init", +#length=constants.long_tag, +#) The very-long (Weekly) tests -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53504 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4303e7b157dcf32a7879b014a9f5a88efa62b756 Gerrit-Change-Number: 53504 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Update nightly.sh to separate compile and run threads
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53483 )
Change subject: tests: Update nightly.sh to separate compile and run threads
..
tests: Update nightly.sh to separate compile and run threads
This allows us to set a high number of threads for gem5 compilation
tasks, and a lower number of threads for running gem5. The latter is
more memory intensive and, therefore, we cannot always use the maximum
number of threads in a system.
Change-Id: I699d9f74b21d31841bf31e3589d323b007cb4601
---
M tests/nightly.sh
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/tests/nightly.sh b/tests/nightly.sh
index b785d55..26f8cfe 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -32,11 +32,18 @@
dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
gem5_root="${dir}/.."
-# We assume the lone argument is the number of threads. If no argument is
-# given we default to one.
-threads=1
+# The first argument is the number of threads to be used for compilation.
If no
+# argument is given we default to one.
+compile_threads=1
if [[ $# -gt 0 ]]; then
-threads=$1
+compile_threads=$1
+fi
+
+# The second argument is the number of threads used to run gem5 (one gem5
+# instance per thread). If no argument is given we default to one.
+run_threads=1
+if [[ $# -gt 1 ]]; then
+run_threads=$2
fi
build_target () {
@@ -47,8 +54,8 @@
# compilation: https://gem5.atlassian.net/browse/GEM5-753
docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" --rm gcr.io/gem5-test/ubuntu-20.04_all-dependencies
\
-bash -c "scons build/${isa}/gem5.opt -j${threads} \
-|| (rm -rf build && scons build/${isa}/gem5.opt
-j${threads})"
+bash -c "scons build/${isa}/gem5.opt -j${compile_threads} \
+|| (rm -rf build && scons build/${isa}/gem5.opt
-j${compile_threads})"
}
unit_test () {
@@ -56,7 +63,7 @@
docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" --rm gcr.io/gem5-test/ubuntu-20.04_all-dependencies
\
-scons build/NULL/unittests.${build} -j${threads}
+scons build/NULL/unittests.${build} -j${compile_threads}
}
# Ensure we have the latest docker images.
@@ -78,15 +85,15 @@
# Run the gem5 long tests.
docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}"/tests --rm
gcr.io/gem5-test/ubuntu-20.04_all-dependencies \
-./main.py run --length long -j${threads} -t${threads} -vv
+./main.py run --length long -j${compile_threads} -t${run_threads}
-vv
# Run the GPU tests.
# For the GPU tests we compile and run GCN3_X86 inside a gcn-gpu container.
docker pull gcr.io/gem5-test/gcn-gpu:latest
docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest bash -c \
-"scons build/GCN3_X86/gem5.opt -j${threads} \
-|| (rm -rf build && scons build/GCN3_X86/gem5.opt -j${threads})"
+"scons build/GCN3_X86/gem5.opt -j${compile_threads} \
+|| (rm -rf build && scons build/GCN3_X86/gem5.opt
-j${compile_threads})"
# get square
wget -qN http://dist.gem5.org/dist/develop/test-progs/square/square
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I699d9f74b21d31841bf31e3589d323b007cb4601
Gerrit-Change-Number: 53483
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: CheckLinkFlag() only adds to flags if test succeeds
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/53025 )
Change subject: scons: CheckLinkFlag() only adds to flags if test succeeds
..
scons: CheckLinkFlag() only adds to flags if test succeeds
Previously, did not check the return of TryLink() before appending, so
unsupported flags can be used when building shared libraries. This
patch adds checking.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1115
Change-Id: Ief62be15009cae9e0281b4d9c2d7b26e0223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53025
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M site_scons/gem5_scons/configure.py
1 file changed, 22 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/site_scons/gem5_scons/configure.py
b/site_scons/gem5_scons/configure.py
index 3993686..b335673 100644
--- a/site_scons/gem5_scons/configure.py
+++ b/site_scons/gem5_scons/configure.py
@@ -61,7 +61,7 @@
ret = context.TryLink('int main(int, char *[]) { return 0; }', '.cc')
if not (ret and autoadd):
context.env['LINKFLAGS'] = last_linkflags
-if set_for_shared:
+if (ret and set_for_shared):
assert(autoadd)
context.env.Append(SHLINKFLAGS=[flag])
context.Result(ret)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53025
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief62be15009cae9e0281b4d9c2d7b26e0223
Gerrit-Change-Number: 53025
Gerrit-PatchSet: 2
Gerrit-Owner: Arun Rodrigues
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Update ext/sst/INSTALL.md
Hoa Nguyen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/53463 ) Change subject: ext: Update ext/sst/INSTALL.md .. ext: Update ext/sst/INSTALL.md Currently, the installation instructions are for installing SST-core and SST-elements version 11.0.0. This change updates instructions to the current SST-core and SST-element version, 11.1.0. This change also reflects that manually downloading the `bbl-busybox-boot-exit` is no longer necessary as the example gem5 config will download automatically. Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53463 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M ext/sst/INSTALL.md 1 file changed, 35 insertions(+), 15 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/ext/sst/INSTALL.md b/ext/sst/INSTALL.md index 4268724..46ff4f0 100644 --- a/ext/sst/INSTALL.md +++ b/ext/sst/INSTALL.md @@ -11,14 +11,14 @@ ### Downloading the SST-Core Source Code ```sh -wget https://github.com/sstsimulator/sst-core/releases/download/v11.0.0_Final/sstcore-11.0.0.tar.gz -tar xf sstcore-11.0.0.tar.gz +wget https://github.com/sstsimulator/sst-core/releases/download/v11.1.0_Final/sstcore-11.1.0.tar.gz +tar xf sstcore-11.1.0.tar.gz ``` ### Installing SST-Core ```sh -cd sstcore-11.0.0 +cd sstcore-11.1.0 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \ --disable-mpi # optional, used when MPI is not available. make all -j$(nproc) @@ -36,14 +36,14 @@ ### Downloading the SST-Elements Source Code ```sh -wget https://github.com/sstsimulator/sst-elements/releases/download/v11.0.0_Final/sstelements-11.0.0.tar.gz -tar xf sstelements-11.0.0.tar.gz +wget https://github.com/sstsimulator/sst-elements/releases/download/v11.1.0_Final/sstelements-11.1.0.tar.gz +tar xf sstelements-11.1.0.tar.gz ``` ### Installing SST-Elements -```shs -cd sst-elements-library-11.0.0 +```sh +cd sst-elements-library-11.1.0 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \ --with-sst-core=$SST_CORE_HOME make all -j$(nproc) @@ -75,20 +75,17 @@ ### Running an example simulation -Downloading the built bootloader containing a Linux Kernel and a workload, - -```sh -wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit -``` - Running the simulation ```sh sst --add-lib-path=./ sst/example.py ``` -`bbl-busybox-boot-exit` contains an m5 binary, and `m5 exit` will be called -upon the booting process reaching the early userspace. +The example SST system configuration will instantiate the gem5 system +as specified in the gem5 system configuration located at +`gem5/configs/example/sst/riscv_fs.py`. This configuration will download +the `bbl-busybox-boot-exit` resource, which contains an m5 binary, and +`m5 exit` will be called upon the booting process reaching the early userspace. More information about building a bootloader containing a Linux Kernel and a customized workload is available at [https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-boot-exit-nodisk/]. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53463 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962 Gerrit-Change-Number: 53463 Gerrit-PatchSet: 2 Gerrit-Owner: Hoa Nguyen Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: Incorrect disassembly/register width in Aarch64 ?
Hi Giacomo, Thank you for the explanation, the base register is indeed SP here. I will look into how your suggestion (intWidth per register) can be implemented. Arthur On 12/1/21 11:58 AM, Giacomo Travaglini wrote: Hi Arthur, this is a known issue in disassembling and arises when multiple register operands have different width. For example your load is likely using the 64-bit SP as base register and loading the value into 32-bit w1. Gem5 is not capturing this per-operand-width and it is reporting a single intWidth of 64. A proper fix would involve having a per-operand intWidth variable (or something similar) Kind Regards Giacomo *From: *Arthur Perais via gem5-dev *Date: *Tuesday, 30 November 2021 at 17:06 *To: *gem5-dev@gem5.org *Cc: *Arthur Perais *Subject: *[gem5-dev] Incorrect disassembly/register width in Aarch64 ? Hi all, I am using a fairly old gem5 version (566c113de1eb08ccbfba6e4b074f96c9977a0e16 from Nov 2020), but I noticed that the disassembly (and the register width) of some Aarch64 instructions seems to be incorrectly reported by gem5. Notably, instruction : ldr w1, [sp, #168] (0xb940abe1 according to objdump) Is reported in gem5 as ldr x1, [sp, #168] (0xf94057e1 according to objdump) And the getIntWidth() method that can be called on the staticInst reports 64 (when it reports 32 for instructions that write into a "word" register). I have not found a patch addressing this but maybe this has been fixed already, or maybe this is known to happen under some specific configuration of an Aarch64 system. Best, Arthur Perais ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: Incorrect disassembly/register width in Aarch64 ?
Hi Arthur, this is a known issue in disassembling and arises when multiple register operands have different width. For example your load is likely using the 64-bit SP as base register and loading the value into 32-bit w1. Gem5 is not capturing this per-operand-width and it is reporting a single intWidth of 64. A proper fix would involve having a per-operand intWidth variable (or something similar) Kind Regards Giacomo From: Arthur Perais via gem5-dev Date: Tuesday, 30 November 2021 at 17:06 To: gem5-dev@gem5.org Cc: Arthur Perais Subject: [gem5-dev] Incorrect disassembly/register width in Aarch64 ? Hi all, I am using a fairly old gem5 version (566c113de1eb08ccbfba6e4b074f96c9977a0e16 from Nov 2020), but I noticed that the disassembly (and the register width) of some Aarch64 instructions seems to be incorrectly reported by gem5. Notably, instruction : ldr w1, [sp, #168] (0xb940abe1 according to objdump) Is reported in gem5 as ldr x1, [sp, #168] (0xf94057e1 according to objdump) And the getIntWidth() method that can be called on the staticInst reports 64 (when it reports 32 for instructions that write into a "word" register). I have not found a patch addressing this but maybe this has been fixed already, or maybe this is known to happen under some specific configuration of an Aarch64 system. Best, Arthur Perais ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
