date:20220302

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Reset stats in Ruby correctly

2022-03-02 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57269 )


Change subject: mem-ruby: Reset stats in Ruby correctly
..

mem-ruby: Reset stats in Ruby correctly

Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57269
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/mem/ruby/system/RubySystem.cc
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 76d3f25..91c4bc3 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -477,6 +477,7 @@
 for (auto& network : m_networks) {
 network->resetStats();
 }
+ClockedObject::resetStats();
 }

 #ifndef PARTIAL_FUNC_READS

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Gerrit-Change-Number: 57269
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Simplify the VecElemOperand class.

2022-03-02 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49722 )


 (

57 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch: Simplify the VecElemOperand class.
..

arch: Simplify the VecElemOperand class.

Oddly, makeDecl would conditionally declare the operand, but only
because makeRead would also declare it. Instead, make makeRead work like
normal, and get rid of the custom makeDecl.

Change-Id: I26c6f01f971778ad5075f8d3f49d9816f371f5b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49722
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser/operand_types.py
1 file changed, 18 insertions(+), 7 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py

index 51d1dcb..cdca6a6 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -394,12 +394,6 @@
 class VecElemOperand(RegOperand):
 reg_class = 'VecElemClass'

-def makeDecl(self):
-if self.is_dest and not self.is_src:
-return '\n\t%s %s;' % (self.ctype, self.base_name)
-else:
-return ''
-
 def makeRead(self, predRead):
 c_read = f'xc->getRegOperand(this, {self.src_reg_idx})'

@@ -408,7 +402,7 @@
 elif self.ctype == 'double':
 c_read = f'bitsToFloat64({c_read})'

-return f'\n\t{self.ctype} {self.base_name} = {c_read};\n'
+return f'{self.base_name} = {c_read};\n'

 def makeWrite(self, predWrite):
 val = self.base_name

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I26c6f01f971778ad5075f8d3f49d9816f371f5b3
Gerrit-Change-Number: 49722
Gerrit-PatchSet: 59
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #146

2022-03-02 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[giacomo.travaglini] arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap

[giacomo.travaglini] arch-arm: Reuse MCR15 trapping code in DC instructions

[kyleroarty1716] arch-vega: Handle signed offsets in Global/Scratch instructions

[gabe.black] cpu-o3: Manage per-register-type free lists with an array.

[gabe.black] cpu-o3: Initialize register maps and free lists with loops.

[gabe.black] arch: Introduce an intermediate RegOperand class in 
operand_types.py.

[gabe.black] arch: Get rid of the is${Type}Reg methods of the Operand class.


--
[...truncated 1.49 MB...]
Starting Test Suite: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
 
Starting Test Case: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
Test: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
 Passed
Logging call to command: 
/nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d 
/tmp/gem5out3ga95em5 -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
 LinearGenerator 1 MESITwoLevel gem5.components.memory DualChannelDDR3_2133 
512MiB
Starting Test Suite: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
 
Starting Test Case: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
Test: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR3_2133-512MiB-NULL-x86_64-opt-MESI_Two_Level
 Passed
Logging call to command: 
/nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d 
/tmp/gem5oututhxr0n_ -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
 LinearGenerator 1 MESITwoLevel gem5.components.memory DualChannelDDR4_2400 
512MiB
Starting Test Suite: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
 
Starting Test Case: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
Test: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelDDR4_2400-512MiB-NULL-x86_64-opt-MESI_Two_Level
 Passed
Logging call to command: 
/nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d 
/tmp/gem5outrfj5snls -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
 LinearGenerator 1 MESITwoLevel gem5.components.memory DualChannelLPDDR3_1600 
512MiB
Starting Test Suite: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
 
Starting Test Case: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
Test: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-DualChannelLPDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
 Passed
Logging call to command: 
/nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d 
/tmp/gem5outi7umomll -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
 LinearGenerator 1 MESITwoLevel gem5.components.memory HBM2Stack 512MiB
Starting Test Suite: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-HBM2Stack-512MiB-NULL-x86_64-opt-MESI_Two_Level
 
Starting Test Case: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-HBM2Stack-512MiB-NULL-x86_64-opt-MESI_Two_Level
Test: 
test-memory-LinearGenerator-1-MESITwoLevel-gem5.components.memory-HBM2Stack-512MiB-NULL-x86_64-opt-MESI_Two_Level
 Passed
Logging call to command: 
/nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d 
/tmp/gem5out6_q655ui -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/traffic_gen/simple_traffic_run.py
 RandomGenerator 1 MESITwoLevel gem5.components.memory SingleChannelDDR3_1600 
512MiB
Starting Test Suite: 
test-memory-RandomGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
 
Starting Test Case: 
test-memory-RandomGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
Test: 
test-memory-RandomGenerator-1-MESITwoLevel-gem5.components.memory-SingleChannelDDR3_1600-512MiB-NULL-x86_64-opt-MESI_Two_Level
 Passed
Logging call to command: 
/nobackup/jenkins/workspace/nightly/build/NULL_MESI_Two_Level/gem5.opt -d 
/tmp/gem5out3w4a7nhw -re --silent-redirect

[gem5-dev] Change in gem5/gem5[develop]: arch: Consolidate all the make_constructor methods in the ISA parser.

2022-03-02 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49721 )


 (

57 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch: Consolidate all the make_constructor methods in the  
ISA parser.

..

arch: Consolidate all the make_constructor methods in the ISA parser.

These methods were all identical, except that IntRegOperand and
CCRegOperand classes had logic to handle operand predication. Since the
other operand types won't have predicates set, we can use the superset
version, and the other types will reduce to what they used to in
practice.

Change-Id: I51eeedcacb7cfc6e2c136742701ee9bf80ec4e15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49721
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser/operand_types.py
1 file changed, 22 insertions(+), 75 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py

index bf8184f..51d1dcb 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -153,9 +153,6 @@
 def isReg(self):
 return 1

-class IntRegOperand(RegOperand):
-reg_class = 'IntRegClass'
-
 def makeConstructor(self, predRead, predWrite):
 c_src = ''
 c_dest = ''
@@ -175,6 +172,9 @@

 return c_src + c_dest

+class IntRegOperand(RegOperand):
+reg_class = 'IntRegClass'
+
 def makeRead(self, predRead):
 if (self.ctype == 'float' or self.ctype == 'double'):
 error('Attempt to read integer register as FP')
@@ -222,19 +222,6 @@
 class FloatRegOperand(RegOperand):
 reg_class = 'FloatRegClass'

-def makeConstructor(self, predRead, predWrite):
-c_src = ''
-c_dest = ''
-
-if self.is_src:
-c_src = self.src_reg_constructor % (self.reg_class,  
self.reg_spec)

-
-if self.is_dest:
-c_dest = self.dst_reg_constructor % (self.reg_class,  
self.reg_spec)

-c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
-
-return c_src + c_dest
-
 def makeRead(self, predRead):
 if self.read_code != None:
 return self.buildReadCode(predRead, 'getRegOperand')
@@ -304,19 +291,6 @@
 else:
 return ''

-def makeConstructor(self, predRead, predWrite):
-c_src = ''
-c_dest = ''
-
-if self.is_src:
-c_src = self.src_reg_constructor % (self.reg_class,  
self.reg_spec)

-
-if self.is_dest:
-c_dest = self.dst_reg_constructor % (self.reg_class,  
self.reg_spec)

-c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
-
-return c_src + c_dest
-
 # Read destination register to write
 def makeReadWElem(self, elem_op):
 (elem_name, elem_ext) = elem_op
@@ -426,20 +400,6 @@
 else:
 return ''

-def makeConstructor(self, predRead, predWrite):
-c_src = ''
-c_dest = ''
-
-if self.is_src:
-c_src = ('\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));' %
-(self.reg_class, self.reg_spec))
-
-if self.is_dest:
-c_dest = ('\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s));' %
-(self.reg_class, self.reg_spec))
-c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
-return c_src + c_dest
-
 def makeRead(self, predRead):
 c_read = f'xc->getRegOperand(this, {self.src_reg_idx})'

@@ -464,19 +424,6 @@
 def makeDecl(self):
 return ''

-def makeConstructor(self, predRead, predWrite):
-c_src = ''
-c_dest = ''
-
-if self.is_src:
-c_src = self.src_reg_constructor % (self.reg_class,  
self.reg_spec)

-
-if self.is_dest:
-c_dest = self.dst_reg_constructor % (self.reg_class,  
self.reg_spec)

-c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
-
-return c_src + c_dest
-
 def makeRead(self, predRead):
 func = 'getRegOperand'
 if self.read_code != None:
@@ -535,25 +482,6 @@
 class CCRegOperand(RegOperand):
 reg_class = 'CCRegClass'

-def makeConstructor(self, predRead, predWrite):
-c_src = ''
-c_dest = ''
-
-if self.is_src:
-c_src = self.src_reg_constructor % (self.reg_class,  
self.reg_spec)

-if self.hasReadPred():
-c_src = '\n\tif (%s) {%s\n\t}' % \
-(self.read_predicate, c_src)
-
-if self.is_dest:
-c_dest = self.dst_reg_constructor % (self.reg_class,  
self.reg_spec)

-c_dest +=

[gem5-dev] Re: resource downloader failure

2022-03-02 Thread Bobby Bruce via gem5-dev

I've added some code that should help here:
https://gem5-review.googlesource.com/c/public/gem5/+/57275

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Tue, Mar 1, 2022 at 10:41 AM Bobby Bruce  wrote:

> I'll change my answer slightly: It seems like this error is happening from
> trying to download the resources.json file (hosted in the resources repo)
> too much. I suspect there are similar restrictions here.  I think I can fix
> it too. I'll probably add a wait-and-retry for the resource downloader
> anyway as it'll make the downloader more stable.
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Tue, Mar 1, 2022 at 10:28 AM Bobby Bruce  wrote:
>
>> Nice find Gabe. That would certainly explain a lot. Turns out there's a
>> 50Gbps quota that will return a 429 error if hit:
>> https://cloud.google.com/storage/quotas. I'll see if I can get this
>> increased and, either way, I'll implement a wait-and-retry strategy in the
>> downloader for when this error is received. I suspect this is hit when lots
>> of Kokoro instances are spun up at one time.
>>
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Tue, Mar 1, 2022 at 2:08 AM Giacomo Travaglini via gem5-dev <
>> gem5-dev@gem5.org> wrote:
>>
>>> Hi Gabe,
>>>
>>>
>>>
>>> A possible workaround could be to use the --bin-path option in testlib
>>>
>>>
>>>
>>> Kind Regards
>>>
>>>
>>>
>>> Giacomo
>>>
>>>
>>>
>>> *From: *Gabe Black via gem5-dev 
>>> *Date: *Tuesday, 1 March 2022 at 04:10
>>> *To: *gem5 Developer List 
>>> *Cc: *Gabe Black 
>>> *Subject: *[gem5-dev] resource downloader failure
>>>
>>> Hi folks. I've been trying to run tests locally, and I've been running
>>> into occasional flakiness due to a problem with the resource downloader.
>>> This reminds me somewhat of flakiness I was seeing in kokoro as well, so
>>> they are probably related. The error output is this:
>>>
>>>
>>>
>>> $ cat
>>> ./testing-results/SuiteUID:atomic-cpu_1-cores_classic_kvm-fork-run-test-GCN3_X86-x86_64-opt/TestUID:atomic-cpu_1-cores_classic_kvm-fork-run-test-GCN3_X86-x86_64-opt/simerr
>>> warn: .kvm_vm already has parent not resetting parent.
>>> Note: kvm_vm is not a parameter of X86Board
>>> warn: (Previously declared as .processor.kvm_vm
>>> HTTPError: HTTP Error 429: Too Many Requests
>>>
>>> At:
>>>   /usr/lib/python3.10/urllib/request.py(643): http_error_default
>>>   /usr/lib/python3.10/urllib/request.py(496): _call_chain
>>>   /usr/lib/python3.10/urllib/request.py(563): error
>>>   /usr/lib/python3.10/urllib/request.py(634): http_response
>>>   /usr/lib/python3.10/urllib/request.py(525): open
>>>   /usr/lib/python3.10/urllib/request.py(216): urlopen
>>>   build/GCN3_X86/python/gem5/resources/downloader.py(77):
>>> _get_resources_json
>>>   build/GCN3_X86/python/gem5/resources/downloader.py(207):
>>> get_resources_json_obj
>>>   build/GCN3_X86/python/gem5/resources/resource.py(162): __init__
>>>   /home/gblack/gem5/work/tests/gem5/configs/boot_kvm_fork_run.py(205):
>>> 
>>>   build/GCN3_X86/python/m5/main.py(434): main
>>>
>>>
>>>
>>>
>>>
>>> Is there a limit that needs to be bumped up? Some way to consolidate
>>> requests so we're not hitting the existing limit?
>>>
>>>
>>>
>>> Gabe
>>> IMPORTANT NOTICE: The contents of this email and any attachments are
>>> confidential and may also be privileged. If you are not the intended
>>> recipient, please notify the sender immediately and do not disclose the
>>> contents to any other person, use it for any purpose, or store or copy the
>>> information in any medium. Thank you.
>>> ___
>>> gem5-dev mailing list -- gem5-dev@gem5.org
>>> To unsubscribe send an email to gem5-dev-le...@gem5.org
>>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>
>>
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Update the downloader to retry on failure

2022-03-02 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57274 )



Change subject: stdlib: Update the downloader to retry on failure
..

stdlib: Update the downloader to retry on failure

On occasion HTTP status codes, such as 429, are returned when
downloading the resources and/or the "resources.json" file. In such
cases it makes sense to retry the download.

This patch adds a Truncated Exponential Backoff algorithm to the
downloader to retry downloads, with a default maximum of 6 attempts.
This is done in cases where HTTP status codes 408, 429, and 5xx are
returned.

So this feature is applied to both the retrieval of the resources and
the "resource.json" file, the downloading of the "resources.json" file
has been modified to utilize the `_download` function as is used to
download resources

Change-Id: Icb52f0f71d294fccec9de3140beece5f7576
---
M src/python/gem5/resources/downloader.py
1 file changed, 100 insertions(+), 13 deletions(-)



diff --git a/src/python/gem5/resources/downloader.py  
b/src/python/gem5/resources/downloader.py

index 5afceeb..2647c56 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -32,6 +32,10 @@
 import gzip
 import hashlib
 import base64
+import time
+import random
+from tempfile import gettempdir
+from urllib.error import HTTPError
 from typing import List, Dict

 from ..utils.filelock import FileLock
@@ -55,6 +59,33 @@

 return uri

+def _get_resources_json_at_url(url: str) -> Dict:
+'''
+Returns a resource JSON, in the form of a Python Dict. The URL location
+of the JSON must be specified.
+
+**Note**: The URL is assumed to be the location within a Google Source
+repository. Special processing is done to handle this. This is the  
primary

+reason there are separate functions for handling the retrieving of the
+resources JSON comapared to just using the `_download` function  
directly.

+
+:param url: The URL of the JSON file.
+'''
+
+file_path = os.path.join(
+gettempdir(),
+f"gem5-resources-{hashlib.md5(url.encode()).hexdigest()}.base64",
+)
+
+_download(url, file_path)
+
+# Note: Google Source does not properly support obtaining files as raw
+# text. Therefore when we open the URL we receive the JSON in base64
+# format. Conversion is needed before it can be loaded.
+with open(file_path) as file:
+to_return =  
json.loads(base64.b64decode(file.read()).decode("utf-8"))

+
+return to_return

 def _get_resources_json() -> Dict:
 """
@@ -63,23 +94,16 @@
 :returns: The Resources JSON (as a Python Dictionary).
 """

-# Note: Google Source does not properly support obtaining files as raw
-# text. Therefore when we open the URL we receive the JSON in base64
-# format. Conversion is needed before it can be loaded.
-with urllib.request.urlopen(_get_resources_json_uri()) as url:
-to_return =  
json.loads(base64.b64decode(url.read()).decode("utf-8"))

+to_return = _get_resources_json_at_url(url = _get_resources_json_uri())

 # If the current version pulled is not correct, look up the
 # "previous-versions" field to find the correct one.
 version = _resources_json_version_required()
 if to_return["version"] != version:
 if version in to_return["previous-versions"].keys():
-with urllib.request.urlopen(
-to_return["previous-versions"][version]
-) as url:
-to_return = json.loads(
-base64.b64decode(url.read()).decode("utf-8")
-)
+to_return = _get_resources_json_at_url(
+url = to_return["previous-versions"][version]
+)
 else:
 # This should never happen, but we thrown an exception to  
explain

 # that we can't find the version.
@@ -170,18 +194,58 @@
 return md5_object.hexdigest()


-def _download(url: str, download_to: str) -> None:
+def _download(
+url: str,
+download_to: str,
+attempt: int = 0,
+max_attempts = 6,
+) -> None:
 """
 Downloads a file.

+The function will run a Truncated Exponential Backoff algorithm to  
retry

+the download if the HTTP Status Code returned is deemed retryable.
+
 :param url: The URL of the file to download.

 :param download_to: The location the downloaded file is to be stored.
+
+:param attempt: The number of download attempts thus far. This is used  
for

+recursion and not meant to be used directly when using this function.
+
+:param max_attempts: The max number of download attempts before  
stopping.
+The default is 6. This translates to roughly 1 minute of retrying  
before

+stopping
 """

 # TODO: This whole setup will only work for single files we can get via
 # wget. We also

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Cache the resources.json download

2022-03-02 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57275 )



Change subject: stdlib: Cache the resources.json download
..

stdlib: Cache the resources.json download

"resources.json" is referenced when a resource is requested. The
"resources.json" file may be updated at any time and therefore, the
downloader was engineered to retrieve this file from the gem5-resources
repo on each request. However, this can lead to excessively frequently
pulls over short periods of time which is uncessary given how
infrequently this file changes.

To combat this, this patch caches the "resources.json" file and will
use it for up to an hour after creation before re-retrieving it.

Change-Id: I3b4907cbadce8a54df21d85f8021bf3603ae0f6f
---
M src/python/gem5/resources/downloader.py
1 file changed, 32 insertions(+), 2 deletions(-)



diff --git a/src/python/gem5/resources/downloader.py  
b/src/python/gem5/resources/downloader.py

index 2647c56..db68b82 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -59,17 +59,23 @@

 return uri

-def _get_resources_json_at_url(url: str) -> Dict:
+def _get_resources_json_at_url(url: str, use_caching: bool = True) -> Dict:
 '''
 Returns a resource JSON, in the form of a Python Dict. The URL location
 of the JSON must be specified.

+If `use_caching` is True, a copy of the JSON will be cached locally,  
and

+used for up to an hour after retrieval.
+
 **Note**: The URL is assumed to be the location within a Google Source
 repository. Special processing is done to handle this. This is the  
primary

 reason there are separate functions for handling the retrieving of the
 resources JSON comapared to just using the `_download` function  
directly.


 :param url: The URL of the JSON file.
+:param use_caching: True if a cached file is to be used (up to an  
hour),

+otherwise the file will be retrieved from the URL regardless. True by
+default.
 '''

 file_path = os.path.join(
@@ -77,7 +83,12 @@
 f"gem5-resources-{hashlib.md5(url.encode()).hexdigest()}.base64",
 )

-_download(url, file_path)
+# The resources.json file can change at any time, but to avoid  
excessive
+# retrieval we cache a version locally and use it for up to an hour  
before

+# obtaining a fresh copy.
+if not use_caching or not os.path.exists(file_path) or \
+(time.time() - os.path.getmtime(file_path)) > 3600:
+_download(url, os.path.join(gettempdir(), file_path))

 # Note: Google Source does not properly support obtaining files as raw
 # text. Therefore when we open the URL we receive the JSON in base64

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3b4907cbadce8a54df21d85f8021bf3603ae0f6f
Gerrit-Change-Number: 57275
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove unused caches in ruby_fs.py

2022-03-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57272 )



Change subject: configs: Remove unused caches in ruby_fs.py
..

configs: Remove unused caches in ruby_fs.py

The script is using the ruby memory subsystem, therefore the instantiated
classic cache models are left unbound

Change-Id: Ic083ef20a3fff63238a64f1478f25fe501e6d8e8
Signed-off-by: Giacomo Travaglini 
---
M configs/example/arm/ruby_fs.py
1 file changed, 20 insertions(+), 14 deletions(-)



diff --git a/configs/example/arm/ruby_fs.py b/configs/example/arm/ruby_fs.py
index d820f86..c2fc226 100644
--- a/configs/example/arm/ruby_fs.py
+++ b/configs/example/arm/ruby_fs.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2020-2021 Arm Limited
+# Copyright (c) 2016-2017, 2020-2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -57,18 +57,11 @@
 default_root_device = '/dev/vda1'


-# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
-# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

-# the cache class may be 'None' if the particular cache is not present.
+# Pre-defined CPU configurations.
 cpu_types = {
-
-"noncaching" : ( NonCachingSimpleCPU, None, None, None),
-"minor" : (MinorCPU,
-   devices.L1I, devices.L1D,
-   devices.L2),
-"hpi" : ( HPI.HPI,
-  HPI.HPI_ICache, HPI.HPI_DCache,
-  HPI.HPI_L2)
+"noncaching" : NonCachingSimpleCPU,
+"minor" : MinorCPU,
+"hpi" : HPI.HPI,
 }

 def create_cow_image(name):
@@ -100,7 +93,7 @@
 print("Error: Bootscript %s does not exist" % args.script)
 sys.exit(1)

-cpu_class = cpu_types[args.cpu][0]
+cpu_class = cpu_types[args.cpu]
 mem_mode = cpu_class.memory_mode()

 system = devices.ArmRubySystem(args.mem_size,
@@ -115,7 +108,7 @@
 devices.CpuCluster(system,
args.num_cpus,
args.cpu_freq, "1.0V",
-   *cpu_types[args.cpu]),
+   cpu_class, None, None, None),
 ]

 # Add the PCI devices we need for this system. The base system

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic083ef20a3fff63238a64f1478f25fe501e6d8e8
Gerrit-Change-Number: 57272
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add O3 option in starter_fs.py and ruby_fs.py

2022-03-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Ciro Santilli.

Hello Ciro Santilli,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/57273

to review the following change.


Change subject: configs: Add O3 option in starter_fs.py and ruby_fs.py
..

configs: Add O3 option in starter_fs.py and ruby_fs.py

Change-Id: I2d59d15cb8acdd7b2675653335af879e35b0d6b3
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Ciro Santilli 
---
M configs/example/arm/ruby_fs.py
M configs/example/arm/starter_fs.py
2 files changed, 23 insertions(+), 9 deletions(-)



diff --git a/configs/example/arm/ruby_fs.py b/configs/example/arm/ruby_fs.py
index c2fc226..ecca22b 100644
--- a/configs/example/arm/ruby_fs.py
+++ b/configs/example/arm/ruby_fs.py
@@ -46,7 +46,7 @@
 from common import ObjectList
 from common import Options
 from common import SysPaths
-from common.cores.arm import HPI
+from common.cores.arm import O3_ARM_v7a, HPI
 from ruby import Ruby

 import devices
@@ -62,6 +62,7 @@
 "noncaching" : NonCachingSimpleCPU,
 "minor" : MinorCPU,
 "hpi" : HPI.HPI,
+"o3" : O3_ARM_v7a.O3_ARM_v7a_3,
 }

 def create_cow_image(name):
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index a5a013f..140f102 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2020 ARM Limited
+# Copyright (c) 2016-2017, 2020, 2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -50,7 +50,7 @@
 from common import SysPaths
 from common import ObjectList
 from common import MemConfig
-from common.cores.arm import HPI
+from common.cores.arm import O3_ARM_v7a, HPI

 import devices

@@ -61,17 +61,19 @@


 # Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
-# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# l1_icache_class, l1_dcache_class, l2_Cache_class). Any of
 # the cache class may be 'None' if the particular cache is not present.
 cpu_types = {
-
-"atomic" : ( AtomicSimpleCPU, None, None, None),
+"atomic" : (AtomicSimpleCPU, None, None, None),
 "minor" : (MinorCPU,
devices.L1I, devices.L1D,
devices.L2),
-"hpi" : ( HPI.HPI,
-  HPI.HPI_ICache, HPI.HPI_DCache,
-  HPI.HPI_L2)
+"hpi" : (HPI.HPI,
+ HPI.HPI_ICache, HPI.HPI_DCache,
+ HPI.HPI_L2),
+"o3" : (O3_ARM_v7a.O3_ARM_v7a_3,
+O3_ARM_v7a.O3_ARM_v7a_ICache, O3_ARM_v7a.O3_ARM_v7a_DCache,
+O3_ARM_v7a.O3_ARM_v7aL2),
 }

 def create_cow_image(name):

--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I2d59d15cb8acdd7b2675653335af879e35b0d6b3
Gerrit-Change-Number: 57273
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Avoid calling .front() on a possibly empty std::list

2022-03-02 Thread Alex Richardson (Gerrit) via gem5-dev

Alex Richardson has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57249 )


Change subject: mem-cache: Avoid calling .front() on a possibly empty  
std::list

..

mem-cache: Avoid calling .front() on a possibly empty std::list

In the call to MSHR::promoteWritable() the deferredTargets list can be
empty, so we should check that case before calling .front(). The new logic
matches MSHR::promoteReadable().

Change-Id: Ic1d05e42f32b2c02226ca88d2155225f592f667f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57249
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/cache/mshr.cc
1 file changed, 21 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 8477048..871125a 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -678,6 +678,9 @@
 void
 MSHR::promoteWritable()
 {
+if (deferredTargets.empty()) {
+return;
+}
 PacketPtr def_tgt_pkt = deferredTargets.front().pkt;
 if (deferredTargets.needsWritable &&
 !(hasPostInvalidate() || hasPostDowngrade()) &&

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic1d05e42f32b2c02226ca88d2155225f592f667f
Gerrit-Change-Number: 57249
Gerrit-PatchSet: 2
Gerrit-Owner: Alex Richardson 
Gerrit-Reviewer: Alex Richardson 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly 1-thread #3

2022-03-02 Thread jenkins-no-reply--- via gem5-dev

See 


Changes:

[giacomo.travaglini] arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap

[giacomo.travaglini] arch-arm: Reuse MCR15 trapping code in DC instructions

[kyleroarty1716] arch-vega: Handle signed offsets in Global/Scratch instructions

[gabe.black] cpu-o3: Manage per-register-type free lists with an array.

[gabe.black] cpu-o3: Initialize register maps and free lists with loops.

[gabe.black] arch: Introduce an intermediate RegOperand class in 
operand_types.py.

[gabe.black] arch: Get rid of the is${Type}Reg methods of the Operand class.

[giacomo.travaglini] sim: Avoid -Werror=unused-variable in bufval unittests

[giacomo.travaglini] arch-arm: Implement DSB Shareable with a separate class

[giacomo.travaglini] arch-arm: Implement TLBI instructions with a separate class

[giacomo.travaglini] mem: Add TLB invalidation flags to the Request object

[giacomo.travaglini] cpu: Fix SimpleExecContext coding style


--
[...truncated 77.59 KB...]
 [ TRACING]  -> NULL/debug/Registers.cc
 [ CXX] NULL/debug/MiscRegs.cc -> .o
 [ TRACING]  -> NULL/debug/Registers.hh
 [ CXX] NULL/debug/Registers.cc -> .o
 [ TRACING]  -> NULL/debug/Decoder.cc
 [ TRACING]  -> NULL/debug/Decoder.hh
 [ CXX] NULL/debug/Decoder.cc -> .o
 [ TRACING]  -> NULL/debug/Faults.cc
 [ TRACING]  -> NULL/debug/TLBVerbose.cc
 [ TRACING]  -> NULL/debug/Faults.hh
 [ TRACING]  -> NULL/debug/TLBVerbose.hh
 [ CXX] NULL/debug/Faults.cc -> .o
 [ CXX] NULL/debug/TLBVerbose.cc -> .o
 [ CXX] NULL/arch/generic/htm.cc -> .o
 [SO Param] m5.objects.BaseMMU, BaseMMU -> NULL/params/BaseMMU.hh
 [ENUMDECL] m5.objects.BaseTLB, TypeTLB -> NULL/enums/TypeTLB.hh
 [SO Param] m5.objects.BaseTLB, BaseTLB -> NULL/params/BaseTLB.hh
 [ CXX] NULL/arch/generic/BaseInterrupts.py.cc -> .o
 [SO Param] m5.objects.BaseInterrupts, BaseInterrupts -> 
NULL/python/_m5/param_BaseInterrupts.cc
 [ CXX] NULL/arch/generic/BaseISA.py.cc -> .o
 [ CXX] NULL/arch/generic/mmu.cc -> .o
 [SO Param] m5.objects.BaseInterrupts, BaseInterrupts -> 
NULL/params/BaseInterrupts.hh
 [ CXX] NULL/python/_m5/param_BaseInterrupts.cc -> .o
 [SO Param] m5.objects.BaseISA, BaseISA -> NULL/python/_m5/param_BaseISA.cc
 [ CXX] NULL/arch/generic/BaseMMU.py.cc -> .o
 [SO Param] m5.objects.BaseISA, BaseISA -> NULL/params/BaseISA.hh
 [ CXX] NULL/python/_m5/param_BaseISA.cc -> .o
 [SO Param] m5.objects.BaseMMU, BaseMMU -> NULL/python/_m5/param_BaseMMU.cc
 [ CXX] NULL/arch/generic/BaseTLB.py.cc -> .o
 [ CXX] NULL/python/_m5/param_BaseMMU.cc -> .o
 [SO Param] m5.objects.BaseTLB, BaseTLB -> NULL/python/_m5/param_BaseTLB.cc
 [ CXX] NULL/python/_m5/param_BaseTLB.cc -> .o
 [ENUM STR] m5.objects.BaseTLB, TypeTLB -> NULL/enums/TypeTLB.cc
 [ CXX] NULL/enums/TypeTLB.cc -> .o
 [ CXX] NULL/arch/generic/InstDecoder.py.cc -> .o
 [SO Param] m5.objects.InstDecoder, InstDecoder -> 
NULL/python/_m5/param_InstDecoder.cc
 [SO Param] m5.objects.InstDecoder, InstDecoder -> NULL/params/InstDecoder.hh
 [ TRACING]  -> NULL/debug/PageTableWalker.cc
 [ TRACING]  -> NULL/debug/PageTableWalker.hh
 [ CXX] NULL/debug/PageTableWalker.cc -> .o
 [ CXX] NULL/python/_m5/param_InstDecoder.cc -> .o
 [ TRACING]  -> NULL/debug/TLB.cc
 [ TRACING]  -> NULL/debug/TLB.hh
 [ CXX] NULL/debug/TLB.cc -> .o
 [ CXX] NULL/arch/generic/decoder.cc -> .o
 [ CXX] NULL/sst/OutgoingRequestBridge.py.cc -> .o
 [SO Param] m5.objects.OutgoingRequestBridge, OutgoingRequestBridge -> 
NULL/python/_m5/param_OutgoingRequestBridge.cc
 [SO Param] m5.objects.OutgoingRequestBridge, OutgoingRequestBridge -> 
NULL/params/OutgoingRequestBridge.hh
 [ CXX] NULL/sst/sst_responder_interface.cc -> .o
 [ TRACING]  -> NULL/debug/Activity.cc
 [ TRACING]  -> NULL/debug/Activity.hh
 [ CXX] NULL/sst/outgoing_request_bridge.cc -> .o
 [ CXX] NULL/debug/Activity.cc -> .o
 [ CXX] NULL/python/_m5/param_OutgoingRequestBridge.cc -> .o
 [ TRACING]  -> NULL/debug/Commit.cc
 [ TRACING]  -> NULL/debug/Commit.hh
 [ CXX] NULL/debug/Commit.cc -> .o
 [ TRACING]  -> NULL/debug/Context.cc
 [ TRACING]  -> NULL/debug/Context.hh
 [ TRACING]  -> NULL/debug/Decode.cc
 [ CXX] NULL/debug/Context.cc -> .o
 [ TRACING]  -> NULL/debug/DynInst.cc
 [ TRACING]  -> NULL/debug/Decode.hh
 [ TRACING]  -> NULL/debug/DynInst.hh
 [ TRACING]  -> NULL/debug/ExecEnable.cc
 [ CXX] NULL/debug/Decode.cc -> .o
 [ TRACING]  -> NULL/debug/ExecCPSeq.cc
 [ CXX] NULL/debug/DynInst.cc -> .o
 [ TRACING]  -> NULL/debug/ExecEnable.hh
 [ TRACING]  -> NULL/debug/ExecCPSeq.hh
 [ CXX] NULL/debug/ExecEnable.cc -> .o
 [ CXX] NULL/debug/ExecCPSeq.cc -> .o
 [ TRACING]  -> NULL/debug/ExecEffAddr.cc
 [ TRACING]  -> NULL/debug/ExecEffAddr.hh
 [ CXX] NULL/debug/ExecEffAddr.cc -> .o
 [ TRACING]  -> NULL/debug/ExecFaulting.cc
 [ TRACING]  -> NULL/debug/ExecFetchSeq.cc
 [ TRACING]  -> NULL/debug/ExecFaulting.hh
 [

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement DSB Shareable with a separate class

2022-03-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56594 )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement DSB Shareable with a separate class
..

arch-arm: Implement DSB Shareable with a separate class

This is an initial step towards making DSB shareable issue a memory
operation (generating DVM messages)

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: Ia7225acc13008ba1ebdf0b091941f6b494e9d4d6
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56594
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
2 files changed, 44 insertions(+), 9 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 0c67645..3c30be6 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2011-2020 ARM Limited
+// Copyright (c) 2011-2021 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -401,7 +401,16 @@
   case 0x2:
 return new Clrex64(machInst);
   case 0x4:
-return new Dsb64(machInst);
+switch (bits(crm, 3, 2)) {
+  case 0x1: // Non-Shareable
+return new Dsb64Local(machInst);
+  case 0x0: // OuterShareable
+  case 0x2: // InnerShareable
+  case 0x3: // FullSystem
+return new Dsb64Shareable(machInst);
+  default:
+GEM5_UNREACHABLE;
+}
   case 0x5:
 return new Dmb64(machInst);
   case 0x6:
diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index d516c53..9151b88 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013, 2016-2018, 2020 ARM Limited
+// Copyright (c) 2011-2013, 2016-2018, 2020-2021 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -172,12 +172,19 @@
 decoder_output += BasicConstructor64.subst(isbIop)
 exec_output += BasicExecute.subst(isbIop)

-dsbIop = ArmInstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
-  ['IsReadBarrier', 'IsWriteBarrier',
-   'IsSerializeAfter'])
-header_output += BasicDeclare.subst(dsbIop)
-decoder_output += BasicConstructor64.subst(dsbIop)
-exec_output += BasicExecute.subst(dsbIop)
+dsbLocalIop =  
ArmInstObjParams("dsb", "Dsb64Local", "ArmStaticInst", "",

+   ['IsReadBarrier', 'IsWriteBarrier',
+   'IsSerializeAfter'])
+header_output += BasicDeclare.subst(dsbLocalIop)
+decoder_output += BasicConstructor64.subst(dsbLocalIop)
+exec_output += BasicExecute.subst(dsbLocalIop)
+
+dsbShareableIop =  
ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst", "",

+   ['IsReadBarrier', 'IsWriteBarrier',
+   'IsSerializeAfter'])
+header_output += BasicDeclare.subst(dsbShareableIop)
+decoder_output += BasicConstructor64.subst(dsbShareableIop)
+exec_output += BasicExecute.subst(dsbShareableIop)

 dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
   ['IsReadBarrier', 'IsWriteBarrier'])

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia7225acc13008ba1ebdf0b091941f6b494e9d4d6
Gerrit-Change-Number: 56594
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add TLB invalidation flags to the Request object

2022-03-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56596 )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: mem: Add TLB invalidation flags to the Request object
..

mem: Add TLB invalidation flags to the Request object

Some ISAs implement TLB invalidation across multiple cores (TLB
shootdown) by broadcasting invalidation messages to every PE in a
target shareability domain.

These messages originate by specific instructions and can be
cathegorized in two macro groups

1) TLB Invalidation instructions: generating the invalidation
request

Example:
* Arm: TLBI instruction [1]
* AMD64: INVLPGB instruction [2]

2) TLB Invalidation sync instructions: serialization point, ensuring
completion of outstanding invalidation requests

Example:
* Arm: DSB instruction [1]
* AMD64: TLBSYNC instruction [2]

This patch is introducing TLBI and SYNC operations in the memory
subsystem by adding the following Request flags:

* TLBI (1)
* TLBI_SYNC (2)

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

[1]: https://developer.arm.com/documentation/ddi0487/gb/
[2]: https://www.amd.com/system/files/TechDocs/24594.pdf

Change-Id: Ib5b025d0f6bc0edaf4f11a66593947a72ba32b8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56596
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/mem/request.hh
1 file changed, 60 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/request.hh b/src/mem/request.hh
index 3b884a9..867cbb0 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013,2017-2020 ARM Limited
+ * Copyright (c) 2012-2013,2017-2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -237,6 +237,12 @@
 // This separation is necessary to ensure the disjoint components
 // of the system work correctly together.

+/** The Request is a TLB shootdown */
+TLBI= 0x1000,
+
+/** The Request is a TLB shootdown sync */
+TLBI_SYNC   = 0x2000,
+
 /**
  * These flags are *not* cleared when a Request object is
  * reused (assigned a new address).
@@ -249,6 +255,8 @@
 static const FlagsType HTM_CMD = HTM_START | HTM_COMMIT |
 HTM_CANCEL | HTM_ABORT;

+static const FlagsType TLBI_CMD = TLBI | TLBI_SYNC;
+
 /** Requestor Ids that are statically allocated
  * @{*/
 enum : RequestorID
@@ -975,6 +983,10 @@
 isHTMCancel() || isHTMAbort());
 }

+bool isTlbi() const { return _flags.isSet(TLBI); }
+bool isTlbiSync() const { return _flags.isSet(TLBI_SYNC); }
+bool isTlbiCmd() const { return isTlbi() || isTlbiSync(); }
+
 bool
 isAtomic() const
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib5b025d0f6bc0edaf4f11a66593947a72ba32b8f
Gerrit-Change-Number: 56596
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix SimpleExecContext coding style

2022-03-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56597 )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: cpu: Fix SimpleExecContext coding style
..

cpu: Fix SimpleExecContext coding style

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I3b9107943732503055008f843a21925574dad930
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56597
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/cpu/simple/exec_context.hh
1 file changed, 27 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 98adf36..22ccafe 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -430,20 +430,23 @@
 byte_enable);
 }

-Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
- Request::Flags flags, AtomicOpFunctorPtr amo_op) override
+Fault
+amoMem(Addr addr, uint8_t *data, unsigned int size,
+   Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 {
 return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
 }

-Fault initiateMemAMO(Addr addr, unsigned int size,
- Request::Flags flags,
- AtomicOpFunctorPtr amo_op) override
+Fault
+initiateMemAMO(Addr addr, unsigned int size,
+   Request::Flags flags,
+   AtomicOpFunctorPtr amo_op) override
 {
 return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
 }

-Fault initiateHtmCmd(Request::Flags flags) override
+Fault
+initiateHtmCmd(Request::Flags flags) override
 {
 return cpu->initiateHtmCmd(flags);
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3b9107943732503055008f843a21925574dad930
Gerrit-Change-Number: 56597
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Avoid -Werror=unused-variable in bufval unittests

2022-03-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57229 )


Change subject: sim: Avoid -Werror=unused-variable in bufval unittests
..

sim: Avoid -Werror=unused-variable in bufval unittests

Some compilers (e.g. gcc-7.5) throw a warning/error when a structured
binding variable is not used.

Change-Id: Ib5090508d135e4a72c39f18b316c76674c3bd8f3
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57229
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/sim/bufval.test.cc
1 file changed, 18 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/bufval.test.cc b/src/sim/bufval.test.cc
index 91c074a..e5a0635 100644
--- a/src/sim/bufval.test.cc
+++ b/src/sim/bufval.test.cc
@@ -40,8 +40,7 @@
 bool
 pairFail(const std::pair )
 {
-auto &[first, success] = p;
-return !success;
+return !p.second;
 }

 bool

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib5090508d135e4a72c39f18b316c76674c3bd8f3
Gerrit-Change-Number: 57229
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Reset stats in Ruby correctly

[gem5-dev] Change in gem5/gem5[develop]: arch: Simplify the VecElemOperand class.

[gem5-dev] Build failed in Jenkins: nightly #146

[gem5-dev] Change in gem5/gem5[develop]: arch: Consolidate all the make_constructor methods in the ISA parser.

[gem5-dev] Re: resource downloader failure

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Update the downloader to retry on failure

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Cache the resources.json download

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove unused caches in ruby_fs.py

[gem5-dev] Change in gem5/gem5[develop]: configs: Add O3 option in starter_fs.py and ruby_fs.py

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Avoid calling .front() on a possibly empty std::list

[gem5-dev] Build failed in Jenkins: nightly 1-thread #3

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement DSB Shareable with a separate class

[gem5-dev] Change in gem5/gem5[develop]: mem: Add TLB invalidation flags to the Request object

[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix SimpleExecContext coding style

[gem5-dev] Change in gem5/gem5[develop]: sim: Avoid -Werror=unused-variable in bufval unittests

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