[gem5-dev] Change in gem5/gem5[develop]: mem: Add option to remove shared memory at the end

2022-03-16 Thread Jui-min Lee (Gerrit) via gem5-dev 
Jui-min Lee has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57469 )


Change subject: mem: Add option to remove shared memory at the end
..

mem: Add option to remove shared memory at the end

Add a new option `auto_unlink_shared_backstore` to System so it will
remove the shared backstore used in physical memories when the System is
getting destructed. This will prevent unintended memory leak.

If the shared memory is designed to live through multiple round of
simulations, you may set the option to false to prevent the removal.

Test: Run a simulation with shared_backstore set, and see whether there
is anything left in /dev/shm/ after simulation ends.
Change-Id: I0267b643bd24e62cb7571674fe98f831c13a586d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57469
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
Tested-by: kokoro 
---
M src/mem/physical.cc
M src/mem/physical.hh
M src/sim/System.py
M src/sim/system.cc
4 files changed, 36 insertions(+), 3 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index a7e261f..08707eb 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -55,6 +55,7 @@
 #include "debug/Checkpoint.hh"
 #include "mem/abstract_mem.hh"
 #include "sim/serialize.hh"
+#include "sim/sim_exit.hh"

 /**
  * On Linux, MAP_NORESERVE allow us to simulate a very large memory
@@ -77,10 +78,16 @@
 PhysicalMemory::PhysicalMemory(const std::string& _name,
const std::vector&  
_memories,

bool mmap_using_noreserve,
-   const std::string& shared_backstore) :
+   const std::string& shared_backstore,
+   bool auto_unlink_shared_backstore) :
 _name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve),
 sharedBackstore(shared_backstore), sharedBackstoreSize(0)
 {
+// Register cleanup callback if requested.
+if (auto_unlink_shared_backstore && !sharedBackstore.empty()) {
+registerExitCallback([=]() { shm_unlink(shared_backstore.c_str());  
});

+}
+
 if (mmap_using_noreserve)
 warn("Not reserving swap space. May cause SIGSEGV on actual  
usage\n");


diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index bb90664..ff0dc61 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -174,7 +174,8 @@
 PhysicalMemory(const std::string& _name,
const std::vector& _memories,
bool mmap_using_noreserve,
-   const std::string& shared_backstore);
+   const std::string& shared_backstore,
+   bool auto_unlink_shared_backstore);

 /**
  * Unmap all the backing store we have used.
diff --git a/src/sim/System.py b/src/sim/System.py
index 499cf9b..b5bd5df 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -87,6 +87,9 @@
 shared_backstore = Param.String("", "backstore's shmem segment  
filename, "
 "use to directly address the backstore from another host-OS  
process. "

 "Leave this empty to unset the MAP_SHARED flag.")
+auto_unlink_shared_backstore = Param.Bool(False, "Automatically remove  
the "

+"shmem segment file upon destruction. This is used only if "
+"shared_backstore is non-empty.")

 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

diff --git a/src/sim/system.cc b/src/sim/system.cc
index d5e5e3f..b7fba8a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -182,7 +182,7 @@
   physProxy(_systemPort, p.cache_line_size),
   workload(p.workload),
   physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
-  p.shared_backstore),
+  p.shared_backstore, p.auto_unlink_shared_backstore),
   ShadowRomRanges(p.shadow_rom_ranges.begin(),
   p.shadow_rom_ranges.end()),
   memoryMode(p.mem_mode),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0267b643bd24e62cb7571674fe98f831c13a586d
Gerrit-Change-Number: 57469
Gerrit-PatchSet: 8
Gerrit-Owner: Jui-min Lee 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add system request flag for dGPUs

2022-03-16 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51852 )


Change subject: mem: Add system request flag for dGPUs
..

mem: Add system request flag for dGPUs

dGPUs can translate a virtual address and will not know if the address
resides in system/host memory or device/dGPU memory until the
translation is complete. In order to mark requests as going to either
system memory or device memory we add a field to the Request class.

Change-Id: Ib1e80e8d03ecdfeb11c24d979ccc4b912ce07f91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51852
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/mem/request.hh
1 file changed, 29 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git a/src/mem/request.hh b/src/mem/request.hh
index 85a9bed..b68edd2 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -436,6 +436,12 @@
  */
 uint32_t _substreamId = 0;

+/**
+ * For fullsystem GPU simulation, this determines if a requests
+ * destination is system (host) memory or dGPU (device) memory.
+ */
+bool _systemReq = 0;
+
 /** The virtual address of the request. */
 Addr _vaddr = MaxAddr;

@@ -862,6 +868,10 @@
 return _contextId;
 }

+/* For GPU fullsystem mark this request is not to device memory. */
+void setSystemReq(bool sysReq) { _systemReq = sysReq; }
+bool systemReq() const { return _systemReq; }
+
 bool
 hasStreamId() const
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib1e80e8d03ecdfeb11c24d979ccc4b912ce07f91
Gerrit-Change-Number: 51852
Gerrit-PatchSet: 6
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: weekly #33

2022-03-16 Thread Bobby Bruce via gem5-dev 
These two tests failed on jenkins with very similar errors:

```
JSONDecodeError: Unterminated string starting at: line 266 column 31 (char
12245)

At:
  /usr/lib/python3.8/json/decoder.py(355): raw_decode
  /usr/lib/python3.8/json/decoder.py(337): decode
  /usr/lib/python3.8/json/__init__.py(357): loads
  build/GCN3_X86/python/gem5/resources/downloader.py(104):
_get_resources_json_at_url
  build/GCN3_X86/python/gem5/resources/downloader.py(122):
_get_resources_json
  build/GCN3_X86/python/gem5/resources/downloader.py(287):
get_resources_json_obj
  build/GCN3_X86/python/gem5/resources/resource.py(162): __init__

/nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py(205):

  build/GCN3_X86/python/m5/main.py(434): main
```

and

```
JSONDecodeError: Expecting value: line 1 column 1 (char 0)

At:
  /usr/lib/python3.8/json/decoder.py(355): raw_decode
  /usr/lib/python3.8/json/decoder.py(337): decode
  /usr/lib/python3.8/json/__init__.py(357): loads
  build/GCN3_X86/python/gem5/resources/downloader.py(104):
_get_resources_json_at_url
  build/GCN3_X86/python/gem5/resources/downloader.py(122):
_get_resources_json
  build/GCN3_X86/python/gem5/resources/downloader.py(287):
get_resources_json_obj
  build/GCN3_X86/python/gem5/resources/downloader.py(403): get_resource
  build/GCN3_X86/python/gem5/resources/resource.py(163): __init__

/nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py(205):

  build/GCN3_X86/python/m5/main.py(434): main
```

I couldn't recreate these locally. One possible cause of this is my new
resources.json downloader functionality,
https://gem5-review.googlesource.com/c/public/gem5/+/57275, is causing a
situation where the resources.json file is being read while it's also being
downloaded by another instance of gem5. This would make sense as the weekly
tests run many gem5 threads and, as the tests take over an hour, the
resources.json file will be re-downloaded at times. I can't be sure this is
the problem, but I've created a fix here:
https://gem5-review.googlesource.com/c/public/gem5/+/57789.

Even if this doesn't fix things, it makes the code slightly less
error-prone.

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Tue, Mar 15, 2022 at 4:11 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See 
>
> Changes:
>
> [gabe.black] dev,arch-x86: Create an x86 QEMU fw cfg, and an E820 entry
> type.
>
> [gabe.black] arch-x86: Get rid of the soft int Fault class.
>
> [gabe.black] arch-x86: Subtract the base from the PC when entering faults.
>
> [gabe.black] arch-x86: Use inline initializers for members of Interrupts.
>
> [gabe.black] scons: Move the build of ext/ into the variant dirs.
>
> [gabe.black] arch-x86,dev: Add an INTA like transaction for I8259.
>
> [gabe.black] arch-x86,dev: Use INTA to get the vector for the IO APIC.
>
> [gabe.black] arch-x86: Implement the LINT0 pin for the LAPIC.
>
> [gabe.black] arch-x86,dev: Use default initializers in the I8259.
>
> [gabe.black] arch-x86,dev: Make the I8259::getVector method protected.
>
> [matthew.poremba] mem-ruby: Remove DataBlk from MOESI_AMD DirectoryEntry
>
> [matthew.poremba] mem-ruby: Enhance MOESI_AMD DmaWrite
>
> [matthew.poremba] configs: Make VIPER memory MessageBuffers ordered
>
> [matthew.poremba] gpu-compute: Fix default MTYPE initialization
>
> [gabe.black] dev: Add a qemu fw config item for a byte array.
>
> [gabe.black] dev,arch-x86: Fix a panic in the i8042 device.
>
> [gabe.black] dev,arch-x86: Change the i8042 to a normal PioDevice.
>
> [gabe.black] arch-x86: Fix a bug in the protected mode IRET.
>
> [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.
>
> [gabe.black] arch-x86: Detect when entering virtual 8086 mode.
>
> [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.
>
> [gabe.black] arch-x86: Use the right bits in the page table walker.
>
> [gabe.black] arch-x86: Make the flags microops handle reserved bits better.
>
> [matthew.poremba] sim-se: Initialize shared page table base upon clone
>
> [Bobby R. Bruce] util-docker: Adding docker-compose.yaml
>
> [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests
>
> [Bobby R. Bruce] util: Remove util/cloudbuild
>
> [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.
>
> [gabe.black] dev,arch-x86: Implement some self test 8042 commands.
>
> [gabe.black] scons: Process the SConsopts files for each variant.
>
> [gabe.black] scons: Turn a lot of compiler flag vars into env vars.
>
> [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.
>
> [gabe.black] arch: Make the DummyVec... types the same size as RegVal.
>
>
> --
> [...truncated 820.16 KB...]
>  [SHCC] X86/ext/softfloat/s_shortShiftRight128.c -> .os
>  [SHCC] X86/ext/softfloat/s_shortShiftRightExtendM.c -> .os
>  [SH

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Add file lock to the resources.json download

2022-03-16 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57789 )



Change subject: stdlib: Add file lock to the resources.json download
..

stdlib: Add file lock to the resources.json download

There have been failures on the weekly tests during the decoding of the
downloaded resources.json base64 file. These errors suggested an
incomplete download or some form of file corruption. These errors only
ever seem to occur when multiple threads of gem5 are running. It has
therefore been proposed that perhaps, in some cases, the cached
downloaded file was bring re-downloaded while also being read by
another thread. For this reason this patch adds a filelock so only one
instance of gem5, at any one time, can download and read the
resources.json file. Even if this is not the cause of the weekly test
errors, it still adds some additional safeguards.

Change-Id: I7c6e1c1786c1919e8519587e53b6a77f4aafa932
---
M src/python/gem5/resources/downloader.py
1 file changed, 46 insertions(+), 19 deletions(-)



diff --git a/src/python/gem5/resources/downloader.py  
b/src/python/gem5/resources/downloader.py

index 5ca7387..828ebc8 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -83,27 +83,34 @@
 f"gem5-resources-{hashlib.md5(url.encode()).hexdigest()}.base64",
 )

-# The resources.json file can change at any time, but to avoid  
excessive
-# retrieval we cache a version locally and use it for up to an hour  
before

-# obtaining a fresh copy.
-#
-# `time.time()` and `os.path.getmtime(..)` both return an unix epoch  
time

-# in seconds. Therefore, the value of "3600" here represents an hour
-# difference between the two values. `time.time()` gets the current  
time,
-# and `os.path.getmtime()` gets the modification time of the  
file.
-# This is the most portable solution as other ideas, like "file  
creation

-# time", are  not always the same concept between operating systems.
-if not use_caching or not os.path.exists(file_path) or \
-(time.time() - os.path.getmtime(file_path)) > 3600:
-_download(url, file_path)
+# We apply a lock on the resources file for when it's downloaded, or
+# re-downloaded, and read. This stops a corner-case from occuring where
+# the file is re-downloaded while being read by another gem5 thread.
+# Note the timeout is 120 so the `_download` function is given time to  
run

+# its Truncated Exponential Backoff algorithm
+# (maximum of roughly 1 minute). Typically this code will run quickly.
+with FileLock("{}.lock".format(file_path), timeout=120):

-# Note: Google Source does not properly support obtaining files as raw
-# text. Therefore when we open the URL we receive the JSON in base64
-# format. Conversion is needed before it can be loaded.
-with open(file_path) as file:
-to_return =  
json.loads(base64.b64decode(file.read()).decode("utf-8"))

+# The resources.json file can change at any time, but to avoid
+# excessive retrieval we cache a version locally and use it for up  
to

+# an hour before obtaining a fresh copy.
+#
+# `time.time()` and `os.path.getmtime(..)` both return an unix  
epoch
+# time in seconds. Therefore, the value of "3600" here represents  
an

+# hour difference between the two values. `time.time()` gets the
+# current time, and `os.path.getmtime()` gets the  
modification
+# time of the file. This is the most portable solution as other  
ideas,
+# like "file creation time", are  not always the same concept  
between

+# operating systems.
+if not use_caching or not os.path.exists(file_path) or \
+(time.time() - os.path.getmtime(file_path)) > 3600:
+_download(url, file_path)

-return to_return
+# Note: Google Source does not properly support obtaining files as  
raw
+# text. Therefore when we open the URL we receive the JSON in  
base64

+# format. Conversion is needed before it can be loaded.
+with open(file_path) as file:
+return  
json.loads(base64.b64decode(file.read()).decode("utf-8"))


 def _get_resources_json() -> Dict:
 """

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7c6e1c1786c1919e8519587e53b6a77f4aafa932
Gerrit-Change-Number: 57789
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define ESR.ISS field as a SubBitUnion

2022-03-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57489 )


Change subject: arch-arm: Define ESR.ISS field as a SubBitUnion
..

arch-arm: Define ESR.ISS field as a SubBitUnion

This will make it easier for an ArmFault to setup the ISS
field of the syndrome register

Signed-off-by: Giacomo Travaglini 
Change-Id: I970dfea474f2de0a696bef27712bc42daed9f1a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57489
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/regs/misc_types.hh
3 files changed, 126 insertions(+), 62 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba5bcc9..4e3d10d 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2014, 2016-2019 ARM Limited
+ * Copyright (c) 2010, 2012-2014, 2016-2019, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -397,42 +397,41 @@
 void
 ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
 {
-uint32_t value;
+ESR esr = 0;
 uint32_t exc_class = (uint32_t) ec(tc);
-uint32_t issVal = iss();
+uint32_t iss_val = iss();

 assert(!from64 || ArmSystem::highestELIs64(tc));

-value = exc_class << 26;
+esr.ec = exc_class;

 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts  
(0x24,

 // 0x25) for which the ISS information is not valid (ARMv7).
 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
 // valid it is treated as RES1.
 if (to64) {
-value |= 1 << 25;
+esr.il = 1;
 } else if ((bits(exc_class, 5, 3) != 4) ||
-   (bits(exc_class, 2) && bits(issVal, 24))) {
+   (bits(exc_class, 2) && bits(iss_val, 24))) {
 if (!machInst.thumb || machInst.bigThumb)
-value |= 1 << 25;
+esr.il = 1;
 }
 // Condition code valid for EC[5:4] nonzero
 if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
 (bits(exc_class, 3, 0) != 0))) {
+
 if (!machInst.thumb) {
-uint32_t  cond;
-ConditionCode condCode = (ConditionCode) (uint32_t)  
machInst.condCode;
+ConditionCode cond_code = (ConditionCode) (uint32_t)  
machInst.condCode;
 // If its on unconditional instruction report with a cond code  
of

 // 0xE, ie the unconditional code
-cond  = (condCode == COND_UC) ? COND_AL : condCode;
-value |= cond << 20;
-value |= 1<< 24;
+esr.cond_iss.cv = 1;
+esr.cond_iss.cond = (cond_code == COND_UC) ? COND_AL :  
cond_code;

 }
-value |= bits(issVal, 19, 0);
+esr.cond_iss.iss = bits(iss_val, 19, 0);
 } else {
-value |= issVal;
+esr.iss = iss_val;
 }
-tc->setMiscReg(syndrome_reg, value);
+tc->setMiscReg(syndrome_reg, esr);
 }

 void
@@ -1250,18 +1249,6 @@
 }

 template
-uint32_t
-AbortFault::iss() const
-{
-uint32_t val;
-
-val  = srcEncoded & 0x3F;
-val |= write << 6;
-val |= s1ptw << 7;
-return (val);
-}
-
-template
 bool
 AbortFault::isMMUFault() const
 {
@@ -1311,6 +1298,18 @@
 }
 }

+uint32_t
+PrefetchAbort::iss() const
+{
+ESR esr = 0;
+auto& iss = esr.instruction_abort_iss;
+
+iss.ifsc = srcEncoded & 0x3F;
+iss.s1ptw = s1ptw;
+
+return iss;
+}
+
 bool
 PrefetchAbort::routeToMonitor(ThreadContext *tc) const
 {
@@ -1406,28 +1405,29 @@
 uint32_t
 DataAbort::iss() const
 {
-uint32_t val;
+ESR esr = 0;
+auto& iss = esr.data_abort_iss;

-// Add on the data abort specific fields to the generic abort ISS value
-val  = AbortFault::iss();
-
-val |= cm << 8;
+iss.dfsc = srcEncoded & 0x3F;
+iss.wnr = write;
+iss.s1ptw = s1ptw;
+iss.cm = cm;

 // ISS is valid if not caused by a stage 1 page table walk, and when  
taken

 // to AArch64 only when directed to EL2
 if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
-val |= isv << 24;
+iss.isv = isv;
 if (isv) {
-val |= sas << 22;
-val |= sse << 21;
-val |= srt << 16;
+iss.sas = sas;
+iss.sse = sse;
+iss.srt = srt;
 // AArch64 only. These assignments are safe on AArch32 as well
 // because these vars are initialized to false
-val |= sf << 15;
-val |= ar << 14;
+iss.sf = sf;
+

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding tyle of faults.{cc,hh}

2022-03-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57569 )


Change subject: arch-arm: Fix coding tyle of faults.{cc,hh}
..

arch-arm: Fix coding tyle of faults.{cc,hh}

Change-Id: Iaf7858ab08fc858b7c2f932240e24657dc48bbe4
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57569
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 86 insertions(+), 59 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 4e3d10d..0efcd27 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -934,8 +934,8 @@
 }


-HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
-ArmFaultVals(_machInst, _imm)
+HypervisorCall::HypervisorCall(ExtMachInst mach_inst, uint32_t _imm) :
+ArmFaultVals(mach_inst, _imm)
 {
 bStep = true;
 }
@@ -1613,8 +1613,8 @@
 }


-SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t  
_iss)

-: ArmFaultVals(_mach_inst, _iss)
+SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst mach_inst, uint32_t  
_iss)

+: ArmFaultVals(mach_inst, _iss)
 {}

 bool
@@ -1633,8 +1633,8 @@
 return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec;
 }

-HardwareBreakpoint::HardwareBreakpoint(Addr _vaddr,  uint32_t _iss)
-: ArmFaultVals(0x0, _iss), vAddr(_vaddr)
+HardwareBreakpoint::HardwareBreakpoint(Addr vaddr,  uint32_t _iss)
+: ArmFaultVals(0x0, _iss), vAddr(vaddr)
 {}

 bool
@@ -1683,9 +1683,9 @@

 }

-Watchpoint::Watchpoint(ExtMachInst _mach_inst, Addr _vaddr,
+Watchpoint::Watchpoint(ExtMachInst mach_inst, Addr _vaddr,
bool _write, bool _cm)
-: ArmFaultVals(_mach_inst), vAddr(_vaddr),
+: ArmFaultVals(mach_inst), vAddr(_vaddr),
   write(_write), cm(_cm)
 {}

@@ -1744,9 +1744,9 @@
 return EC_WATCHPOINT_LOWER_EL;
 }

-SoftwareStepFault::SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx,
+SoftwareStepFault::SoftwareStepFault(ExtMachInst mach_inst, bool is_ldx,
  bool _stepped)
-: ArmFaultVals(_mach_inst), isldx(is_ldx),
+: ArmFaultVals(mach_inst), isldx(is_ldx),
   stepped(_stepped)
 {
 bStep = true;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 906f704..660a2b7 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -193,26 +193,27 @@
 // (exceptions taken in HYP mode or in AArch64 state)
 const ExceptionClass ec;

-FaultVals(const FaultName& name_, const FaultOffset& offset_,
-const uint16_t& currELTOffset_, const uint16_t&  
currELHOffset_,

-const uint16_t& lowerEL64Offset_,
-const uint16_t& lowerEL32Offset_,
-const OperatingMode& nextMode_, const uint8_t&  
armPcOffset_,
-const uint8_t& thumbPcOffset_, const uint8_t&  
armPcElrOffset_,
-const uint8_t& thumbPcElrOffset_, const bool&  
hypTrappable_,

-const bool& abortDisable_, const bool& fiqDisable_,
-const ExceptionClass& ec_)
-: name(name_), offset(offset_), currELTOffset(currELTOffset_),
-  currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
-  lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
-  armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
-  armPcElrOffset(armPcElrOffset_),  
thumbPcElrOffset(thumbPcElrOffset_),

-  hypTrappable(hypTrappable_), abortDisable(abortDisable_),
-  fiqDisable(fiqDisable_), ec(ec_) {}
+FaultVals(const FaultName& name_, FaultOffset offset_,
+  uint16_t curr_elt_offset, uint16_t curr_elh_offset,
+  uint16_t lower_el64_offset,
+  uint16_t lower_el32_offset,
+  OperatingMode next_mode, uint8_t arm_pc_offset,
+  uint8_t thumb_pc_offset, uint8_t arm_pc_elr_offset,
+  uint8_t thumb_pc_elr_offset, bool hyp_trappable,
+  bool abort_disable, bool fiq_disable,
+  ExceptionClass ec_)
+: name(name_), offset(offset_), currELTOffset(curr_elt_offset),
+  currELHOffset(curr_elh_offset),  
lowerEL64Offset(lower_el64_offset),

+  lowerEL32Offset(lower_el32_offset), nextMode(next_mode),
+  armPcOffset(arm_pc_offset), thumbPcOffset(thumb_pc_offset),
+  armPcElrOffset(arm_pc_elr_offset),
+  thumbPcElrOffset(thumb_pc_elr_offset),
+  hypTrappable(hyp_tra

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix setup of ESR.IL field

2022-03-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57570 )


Change subject: arch-arm: Fix setup of ESR.IL field
..

arch-arm: Fix setup of ESR.IL field

The ESR.IL field (Instruction Lenght) is set to 0 if the exception
has been triggered by a 16-bit instruction (Thumb) and 1 otherwise.

Current implementation has been implemented more or less correctly
for AArch32 but not for AArch64; by doing:

if (to64) {
esr.il = 1;
} ... [AArch32]

We are directly setting ESR.IL to 1 in case the exception is taken in
AArch64 mode. This is not covering the case of a thumb instruction
faulting to AArch64.

We are fixing this by defining a virtual method returning the ESR.IL
bitfield depending on the exception cause/type. This is following
the Arm Architectural Reference Manual, which states ESR.IL bit should
be set to 1 for 32-bit instructions and for cases where the fault
doesn't really depend on the instruction:

* SError interrupt
* Instruction Abort exception
* PC alignment exception
* SP alignment exception
* Data Abort exception for which the value of the ISV bit is 0.
* Illegal Execution state exception.
* Debug exception except for Breakpoint instruction exceptions
* Exception reported using EC value 0b00.

Change-Id: I79c9ba8397248c526490e2ed83088fe968029b0e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57570
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 116 insertions(+), 27 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0efcd27..4ab45d4 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -404,18 +404,8 @@
 assert(!from64 || ArmSystem::highestELIs64(tc));

 esr.ec = exc_class;
+esr.il = il(tc);

-// HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts  
(0x24,

-// 0x25) for which the ISS information is not valid (ARMv7).
-// @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
-// valid it is treated as RES1.
-if (to64) {
-esr.il = 1;
-} else if ((bits(exc_class, 5, 3) != 4) ||
-   (bits(exc_class, 2) && bits(iss_val, 24))) {
-if (!machInst.thumb || machInst.bigThumb)
-esr.il = 1;
-}
 // Condition code valid for EC[5:4] nonzero
 if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
 (bits(exc_class, 3, 0) != 0))) {
@@ -1367,6 +1357,12 @@
 }

 bool
+DataAbort::il(ThreadContext *tc) const
+{
+return !isv? true : AbortFault::il(tc);
+}
+
+bool
 DataAbort::routeToMonitor(ThreadContext *tc) const
 {
 SCR scr = 0;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 660a2b7..6c0cda6 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -249,8 +249,9 @@
 virtual bool abortDisable(ThreadContext *tc) = 0;
 virtual bool fiqDisable(ThreadContext *tc) = 0;
 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
-virtual uint32_t vectorCatchFlag() const { return 0x0; }
+virtual bool il(ThreadContext *tc) const = 0;
 virtual uint32_t iss() const = 0;
+virtual uint32_t vectorCatchFlag() const { return 0x0; }
 virtual bool isStage2() const { return false; }
 virtual FSR getFsr(ThreadContext *tc) const { return 0; }
 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
@@ -298,7 +299,15 @@
 uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
 bool abortDisable(ThreadContext* tc) override { return  
vals.abortDisable; }

 bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
+
+/** Syndrome methods */
 ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
+bool
+il(ThreadContext *tc) const override
+{
+// ESR.IL = 1 if exception cause is unknown (EC = 0)
+return ec(tc) == EC_UNKNOWN || !machInst.thumb ||  
machInst.bigThumb;

+}
 uint32_t iss() const override { return issRaw; }
 };

@@ -339,9 +348,11 @@
 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 nullStaticInstPtr) override;
 bool routeToHyp(ThreadContext *tc) const override;
+uint32_t vectorCatchFlag() const override { return 0x0202; }
+
+/** Syndrome methods */
 ExceptionClass ec(ThreadContext *tc) const override;
 uint32_t iss() const override;
-uint32_t vectorCatchFlag() const override { return 0x0202; }
 };

 class SupervisorCall : public ArmFaultVals
@@ -360,9 +371,11 @@

[gem5-dev] Change in gem5/gem5[develop]: scons: Turn all global sticky variables into variant ones.

2022-03-16 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56753 )


Change subject: scons: Turn all global sticky variables into variant ones.
..

scons: Turn all global sticky variables into variant ones.

Saved option files are processed twice, once to load the value of the
EXTRAS variable, and then again once variables have been set up by
SConsopts.

Change-Id: Id8d49051c8fe684142a68259c470ed7c86bdab53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56753
Reviewed-by: Andreas Sandberg 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
A SConsopts
M SConstruct
M src/SConscript
3 files changed, 132 insertions(+), 82 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConsopts b/SConsopts
new file mode 100644
index 000..bb2de86
--- /dev/null
+++ b/SConsopts
@@ -0,0 +1,53 @@
+# Copyright (c) 2013, 2015-2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import os.path
+
+from gem5_scons import warning
+
+Import('*')
+
+sticky_vars.AddVariables(
+('BATCH', 'Use batch pool for build and tests', False),
+('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
+('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
+('USE_EFENCE', 'Link with Electric Fence malloc debugger', False),
+)
diff --git a/SConstruct b/SConstruct
index 000e526..beecd03 100755
--- a/SConstruct
+++ b/SConstruct
@@ -243,49 +243,12 @@

 
 #
-# Set up global sticky variables... these are common to an entire build
-# tree (not specific to a particular build like X86)
-#
-
-
-global_vars_file = os.path.join(build_root, 'variables.global')
-
-global_vars = Variables(global_vars_file, args=ARGUMENTS)
-
-global_vars.AddVariables(
-('BATCH', 'Use batch pool for build and tests', False),
-('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
-('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
-('EXTRAS', 'Add extra directories to the compilation', '')
-)
-
-# Update main environment with values from ARGUMENTS & global_vars_file
-global_vars.Update(main)
-Help('''
-Global build variables:
-{help}
-'''.format(help=global_vars.GenerateHelpText(main)), append=True)
-
-# Save sticky variable settings back to current variables file
-global_vars.Save(global_vars_file, main)
-
-
-
-#
 # Set up various paths.
 #
 ###

[gem5-dev] Re: Build failed in Jenkins: nightly #161

2022-03-16 Thread Jason Lowe-Power via gem5-dev 
Thanks, Gabe!

On Tue, Mar 15, 2022 at 9:28 PM Gabe Black via gem5-dev 
wrote:

> https://gem5-review.googlesource.com/c/public/gem5/+/57749
>
> On Tue, Mar 15, 2022 at 12:59 PM Gabe Black  wrote:
>
>> It looks like the problem is that the aapcs test calls ThreadContext
>> which returns a TheISA::VecRegContainer, where since that test is for ARM
>> it *should* really be working with an ARM VecRegContainer. Because this is
>> being built for NULL, that uses the dummy versions which are not complete
>> enough to have "as" template methods like the real classes.
>>
>> I think the solution is either to restrict that test to when building
>> with ARM, or to add as<>() to the dummy classes. In the short term the
>> offending change can be reverted, or we can wait until this evening when
>> I'll have a chance to find a proper fix. This is what is right now probably
>> a unique corner case where we have a unit test which is ISA dependent, and
>> while it will *become* possible to run reasonably under any build once the
>> ThreadContext doesn't build in what data type vector registers should be,
>> in the mean time it either won't work because of this problem, or even when
>> it would work, it would be operating on an inappropriate data type.
>>
>> Gabe
>>
>> On Tue, Mar 15, 2022 at 8:13 AM Jason Lowe-Power 
>> wrote:
>>
>>> Looks like the problem is  [gabe.black] arch: Make the DummyVec... types
>>> the same size as RegVal.
>>>
>>> Can you take a look, Gabe?
>>>
>>> Thanks,
>>> Jason
>>>
>>> On Tue, Mar 15, 2022 at 1:46 AM jenkins-no-reply--- via gem5-dev <
>>> gem5-dev@gem5.org> wrote:
>>>
 See <
 https://jenkins.gem5.org/job/nightly/161/display/redirect?page=changes>

 Changes:

 [gabe.black] arch-x86: Fix a bug in the protected mode IRET.

 [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.

 [gabe.black] arch-x86: Detect when entering virtual 8086 mode.

 [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.

 [gabe.black] arch-x86: Use the right bits in the page table walker.

 [gabe.black] arch-x86: Make the flags microops handle reserved bits
 better.

 [matthew.poremba] sim-se: Initialize shared page table base upon clone

 [Bobby R. Bruce] util-docker: Adding docker-compose.yaml

 [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests

 [Bobby R. Bruce] util: Remove util/cloudbuild

 [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.

 [gabe.black] dev,arch-x86: Implement some self test 8042 commands.

 [gabe.black] scons: Process the SConsopts files for each variant.

 [gabe.black] scons: Turn a lot of compiler flag vars into env vars.

 [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.

 [gabe.black] arch: Make the DummyVec... types the same size as RegVal.

 [gabe.black] ext,scons: Make kconfiglib available for use in SCons.

 [gabe.black] scons: Make all sticky variables automatically exported.

 [gabe.black] dev: Implement PS/2 keyboard echo and set scan code
 commands.

 [gabe.black] arch-x86: Specialize some instructions for virtual 8086
 mode.


 --
 [...truncated 1.17 MB...]
 [ RUN  ] LoggingFixture.Warn
 [   OK ] LoggingFixture.Warn (0 ms)
 [ RUN  ] LoggingFixture.Inform
 [   OK ] LoggingFixture.Inform (0 ms)
 [ RUN  ] LoggingFixture.Hack
 [   OK ] LoggingFixture.Hack (0 ms)
 [ RUN  ] LoggingFixture.WarnOnce
 [   OK ] LoggingFixture.WarnOnce (0 ms)
 [ RUN  ] LoggingFixture.InformOnce
 [   OK ] LoggingFixture.InformOnce (0 ms)
 [ RUN  ] LoggingFixture.HackOnce
 [   OK ] LoggingFixture.HackOnce (0 ms)
 [ RUN  ] LoggingFixture.WarnIf
 [   OK ] LoggingFixture.WarnIf (0 ms)
 [ RUN  ] LoggingFixture.WarnIfOnce
 [   OK ] LoggingFixture.WarnIfOnce (0 ms)
 [--] 21 tests from LoggingFixture (0 ms total)

 [--] Global test environment tear-down
 [==] 34 tests from 2 test suites ran. (1638 ms total)
 [  PASSED  ] 34 tests.
  [LINK]  -> NULL/arch/generic/vec_pred_reg.test.opt
 build/NULL/arch/generic/vec_reg.test.opt
 --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_reg.test.xml
 Running main() from
 build/NULL/ext/googletest/googletest/src/gtest_main.cc
 [==] Running 8 tests from 2 test suites.
 [--] Global test environment set-up.
 [--] 2 tests from VecReg
 [ RUN  ] VecReg.Size
 [   OK ] VecReg.Size (0 ms)
 [ RUN  ] VecReg.Zero
 [   OK ] VecReg.Zero (0 ms)
 [--] 2 tests from VecReg (0 ms total)

 [--] 6 tests from TwoDifferentVecRegs
 [ RUN  ] TwoDifferentVecRegs.Assignment
 [

[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Add aperture base definitions file

2022-03-16 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57769 )



Change subject: dev-amdgpu: Add aperture base definitions file
..

dev-amdgpu: Add aperture base definitions file

These are used in subsequent patches. Adding all of them at once.

Change-Id: Idbb43b7daba1732a32d8033adcb1178a1c581b43
---
A src/dev/amdgpu/amdgpu_defines.hh
1 file changed, 103 insertions(+), 0 deletions(-)



diff --git a/src/dev/amdgpu/amdgpu_defines.hh  
b/src/dev/amdgpu/amdgpu_defines.hh

new file mode 100644
index 000..9407a68
--- /dev/null
+++ b/src/dev/amdgpu/amdgpu_defines.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2021 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are  
met:

+ *
+ * 1. Redistributions of source code must retain the above copyright  
notice,

+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright  
notice,
+ * this list of conditions and the following disclaimer in the  
documentation

+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from  
this

+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS  
IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,  
THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS  
BE

+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_AMDGPU_AMDGPU_DEFINES_HH__
+#define __DEV_AMDGPU_AMDGPU_DEFINES_HH__
+
+namespace gem5
+{
+
+/* Types of queues supported by device */
+enum QueueType
+{
+Compute,
+Gfx,
+SDMAGfx,
+SDMAPage,
+ComputeAQL,
+InterruptHandler,
+RLC
+};
+
+/* Names of BARs used by the device. */
+constexpr int FRAMEBUFFER_BAR = 0;
+constexpr int DOORBELL_BAR = 2;
+constexpr int MMIO_BAR = 5;
+
+/* By default the X86 kernel expects the vga ROM at 0xc. */
+constexpr uint32_t VGA_ROM_DEFAULT = 0xc;
+constexpr uint32_t ROM_SIZE = 0x2;// 128kB
+
+/* SDMA base, size, mmio offset shift. */
+static constexpr uint32_t SDMA0_BASE  = 0x4980;
+static constexpr uint32_t SDMA1_BASE  = 0x5180;
+static constexpr uint32_t SDMA_SIZE  = 0x800;
+static constexpr uint32_t SDMA_OFFSET_SHIFT  = 2;
+
+/* Interrupt handler base, size, mmio offset shift. */
+static constexpr uint32_t IH_BASE = 0x4280;
+static constexpr uint32_t IH_SIZE = 0x700;
+static constexpr uint32_t IH_OFFSET_SHIFT = 2;
+
+/* Graphics register bus manager base, size, mmio offset shift. */
+static constexpr uint32_t GRBM_BASE  = 0x8000;
+static constexpr uint32_t GRBM_SIZE  = 0x5000;
+static constexpr uint32_t GRBM_OFFSET_SHIFT  = 2;
+
+/* GFX base, size, mmio offset shift. */
+static constexpr uint32_t GFX_BASE  = 0x28000;
+static constexpr uint32_t GFX_SIZE  = 0x17000;
+static constexpr uint32_t GFX_OFFSET_SHIFT  = 2;
+
+/* MMHUB base, size, mmio offset shift. */
+static constexpr uint32_t MMHUB_BASE = 0x68000;
+static constexpr uint32_t MMHUB_SIZE = 0x2120;
+static constexpr uint32_t MMHUB_OFFSET_SHIFT = 2;
+
+/* NBIO base and size. */
+static constexpr uint32_t NBIO_BASE = 0x0;
+static constexpr uint32_t NBIO_SIZE = 0x4280;
+
+} // namespace gem5
+
+#endif // __DEV_AMDGPU_AMDGPU_DEFINES_HH__
+

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idbb43b7daba1732a32d8033adcb1178a1c581b43
Gerrit-Change-Number: 57769
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch: Add an "as" template to dummy vec regs.

2022-03-16 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57749 )


Change subject: arch: Add an "as" template to dummy vec regs.
..

arch: Add an "as" template to dummy vec regs.

Keep the unit tests compiling until the generic dummy vec and vec pred
regs are unnecessary and are eliminated.

Change-Id: I65d99cd3f4c41e89834b71a8af90872d8d5a4590
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57749
Maintainer: Gabe Black 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
2 files changed, 21 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 9495911..a9b264e 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -400,6 +400,8 @@
 RegVal filler = 0;
 bool operator == (const DummyVecPredRegContainer &d) const { return  
true; }
 bool operator != (const DummyVecPredRegContainer &d) const { return  
true; }

+template 
+VecElem *as() { return nullptr; }
 };
 template <>
 struct ParseParam
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index c818b1c..fecd5c6 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -270,6 +270,8 @@
 RegVal filler = 0;
 bool operator == (const DummyVecRegContainer &d) const { return true; }
 bool operator != (const DummyVecRegContainer &d) const { return true; }
+template 
+VecElem *as() { return nullptr; }
 };
 template <>
 struct ParseParam

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65d99cd3f4c41e89834b71a8af90872d8d5a4590
Gerrit-Change-Number: 57749
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Eliminate the "func" parameter to build(Read|Write)Code.

2022-03-16 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49737 )


 (

62 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch: Eliminate the "func" parameter to build(Read| 
Write)Code.

..

arch: Eliminate the "func" parameter to build(Read|Write)Code.

The correct accessor is well known by the code providing a template for
buildReadCode/buildWriteCode, and so can be simply inserted without the
indirection. This makes the code a little easier to read, and those
templating functions simpler and easier to understand.

Change-Id: I403c6e4c291708f8b58cce08bfa32ee2a930c296
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49737
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/operand_types.py
2 files changed, 35 insertions(+), 17 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 88d45c4..0b0d381 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -63,19 +63,20 @@

 let {{
 maybePCRead = '''
-((%(reg_idx)s == PCReg) ? readPC(xc) :  
xc->%(func)s(this, %(op_idx)s))

+((%(reg_idx)s == PCReg) ? readPC(xc) :
+ xc->getRegOperand(this, %(op_idx)s))
 '''
 maybeAlignedPCRead = '''
 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
- xc->%(func)s(this, %(op_idx)s))
+ xc->getRegOperand(this, %(op_idx)s))
 '''
 maybePCWrite = '''
 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
- xc->%(func)s(this, %(op_idx)s, %(final_val)s))
+ xc->setRegOperand(this, %(op_idx)s, %(final_val)s))
 '''
 maybeIWPCWrite = '''
 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
- xc->%(func)s(this, %(op_idx)s, %(final_val)s))
+ xc->setRegOperand(this, %(op_idx)s, %(final_val)s))
 '''
 maybeAIWPCWrite = '''
 if (%(reg_idx)s == PCReg) {
@@ -86,26 +87,27 @@
 setIWNextPC(xc, %(final_val)s);
 }
 } else {
-xc->%(func)s(this, %(op_idx)s, %(final_val)s);
+xc->setRegOperand(this, %(op_idx)s, %(final_val)s);
 }
 '''
 aarch64Read = '''
-((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
+((xc->getRegOperand(this, %(op_idx)s)) & mask(intWidth))
 '''
 aarch64Write = '''
-xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
+xc->setRegOperand(this, %(op_idx)s, (%(final_val)s) &  
mask(intWidth))

 '''
 aarchX64Read = '''
-((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
+((xc->getRegOperand(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
 '''
 aarchX64Write = '''
-xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ?  
64 : 32))

+xc->setRegOperand(this, %(op_idx)s, (%(final_val)s) &
+mask(aarch64 ? 64 : 32))
 '''
 aarchW64Read = '''
-((xc->%(func)s(this, %(op_idx)s)) & mask(32))
+((xc->getRegOperand(this, %(op_idx)s)) & mask(32))
 '''
 aarchW64Write = '''
-xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
+xc->setRegOperand(this, %(op_idx)s, (%(final_val)s) & mask(32))
 '''
 cntrlNsBankedWrite = '''
 xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py

index 342bd6f..b5cfccf 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -103,9 +103,8 @@
 src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));'
 dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++,  
RegId(%s, %s));'


-def buildReadCode(self, predRead, func='getRegOperand'):
+def buildReadCode(self, predRead):
 subst_dict = {"name": self.base_name,
-  "func": func,
   "reg_idx": self.reg_spec,
   "ctype": self.ctype}
 if hasattr(self, 'src_reg_idx'):
@@ -114,9 +113,8 @@
 code = self.read_code % subst_dict
 return '%s = %s;\n' % (self.base_name, code)

-def buildWriteCode(self, predWrite, func='setRegOperand'):
+def buildWriteCode(self, predWrite):
 subst_dict = {"name": self.base_name,
-  "func": func,
   "reg_idx": self.reg_spec,
   "ctype": self.ctype,
   "final_val": self.base_name}
@@ -515,7 +513,7 @@
 if (self.ctype == 'float' or self.ctype == 'double'):
 error('Attempt to read contr

[gem5-dev] Change in gem5/gem5[develop]: arch: Disable unused read/write code overrides in the ISA parser.

2022-03-16 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49736 )


 (

62 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch: Disable unused read/write code overrides in the ISA  
parser.

..

arch: Disable unused read/write code overrides in the ISA parser.

Some operand types had read/write code overrides, I think largely by
pattern matching other operand types, and not because that code was
actually expected to be used or to work. Instead, we should just assert
that that code isn't used and remove the implementation. This method of
affecting reading and writing code is going away anyway, and if this is
needed in the future it can be replaced in the new system.

Change-Id: Idae886153aa343570109069cbe54e2c1699a34e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49736
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser/operand_types.py
1 file changed, 22 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py

index 27e0ac7..342bd6f 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -341,9 +341,7 @@
 return c_read

 def makeReadW(self, predWrite):
-func = 'getWritableRegOperand'
-if self.read_code != None:
-return self.buildReadCode(predWrite, func)
+assert(self.read_code == None)

 if predWrite:
 rindex = '_destIndex++'
@@ -454,9 +452,7 @@
 return c_read

 def makeReadW(self, predWrite):
-func = 'getWritableRegOperand'
-if self.read_code != None:
-return self.buildReadCode(predWrite, 'getWritableRegOperand')
+assert(self.read_code == None)

 if predWrite:
 rindex = '_destIndex++'

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idae886153aa343570109069cbe54e2c1699a34e5
Gerrit-Change-Number: 49736
Gerrit-PatchSet: 64
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #162

2022-03-16 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[Giacomo Travaglini] arch-arm: Add DVM enabled flag in the Decoder class

[Giacomo Travaglini] mem: Add external TLBI flags to the Request object

[Giacomo Travaglini] mem: Add TlbiExtSync packet type

[hoanguyen] util-docker: Add docker container for building riscv target


--
[...truncated 781.65 KB...]
[   OK ] PortDeathTest.TakeOverDisconnected (150 ms)
[ RUN  ] PortDeathTest.TakeOverConnected
[   OK ] LoggingDeathTest.HackLoggerExitHelper (146 ms)
[ RUN  ] LoggingDeathTest.FatalLoggerExitHelper
[   OK ] LoggingDeathTest.FatalLoggerExitHelper (1 ms)
[ RUN  ] LoggingDeathTest.PanicLoggerExitHelper
[   OK ] PortDeathTest.TakeOverConnected (148 ms)
[ RUN  ] PortDeathTest.TakeOverOneSided
[   OK ] LoggingDeathTest.PanicLoggerExitHelper (152 ms)
[ RUN  ] LoggingDeathTest.ExitMessage
[   OK ] PortDeathTest.TakeOverOneSided (150 ms)
[--] 4 tests from PortDeathTest (631 ms total)

[--] 7 tests from PortTest
[ RUN  ] PortTest.GetId
[   OK ] PortTest.GetId (0 ms)
[ RUN  ] PortTest.OneSidedConnection
[   OK ] PortTest.OneSidedConnection (0 ms)
[ RUN  ] PortTest.TwoSidedConnection
[   OK ] PortTest.TwoSidedConnection (0 ms)
[ RUN  ] PortTest.OverwriteConnection
[   OK ] PortTest.OverwriteConnection (0 ms)
[ RUN  ] PortTest.TakeOverOneSided
[   OK ] PortTest.TakeOverOneSided (0 ms)
[ RUN  ] PortTest.TakeOver
[   OK ] PortTest.TakeOver (0 ms)
[ RUN  ] PortTest.Print
[   OK ] PortTest.Print (0 ms)
[--] 7 tests from PortTest (0 ms total)

[--] Global test environment tear-down
[==] 11 tests from 2 test suites ran. (631 ms total)
[  PASSED  ] 11 tests.
[   OK ] LoggingDeathTest.ExitMessage (147 ms)
[ RUN  ] LoggingDeathTest.Panic
[   OK ] LoggingDeathTest.Panic (146 ms)
[ RUN  ] LoggingDeathTest.Fatal
[   OK ] LoggingDeathTest.Fatal (2 ms)
[ RUN  ] LoggingDeathTest.PanicIf
[   OK ] LoggingDeathTest.PanicIf (146 ms)
[ RUN  ] LoggingDeathTest.FatalIf
[   OK ] LoggingDeathTest.FatalIf (1 ms)
[ RUN  ] LoggingDeathTest.gem5Assert
 [LINK]  -> NULL/gem5py_m5
[   OK ] LoggingDeathTest.gem5Assert (295 ms)
[--] 13 tests from LoggingDeathTest (1714 ms total)

[--] 21 tests from LoggingFixture
[ RUN  ] LoggingFixture.BasicPrint
[   OK ] LoggingFixture.BasicPrint (0 ms)
[ RUN  ] LoggingFixture.VariadicCharPrint
[   OK ] LoggingFixture.VariadicCharPrint (0 ms)
[ RUN  ] LoggingFixture.VariadicStringPrint
[   OK ] LoggingFixture.VariadicStringPrint (0 ms)
[ RUN  ] LoggingFixture.VariadicCharMissingPrint
[   OK ] LoggingFixture.VariadicCharMissingPrint (0 ms)
[ RUN  ] LoggingFixture.VariadicStringMissingPrint
[   OK ] LoggingFixture.VariadicStringMissingPrint (0 ms)
[ RUN  ] LoggingFixture.DisabledPrint
[   OK ] LoggingFixture.DisabledPrint (0 ms)
[ RUN  ] LoggingFixture.WarnLoggerPrint
[   OK ] LoggingFixture.WarnLoggerPrint (0 ms)
[ RUN  ] LoggingFixture.InfoLoggerPrint
[   OK ] LoggingFixture.InfoLoggerPrint (0 ms)
[ RUN  ] LoggingFixture.HackLoggerPrint
[   OK ] LoggingFixture.HackLoggerPrint (0 ms)
[ RUN  ] LoggingFixture.FatalLoggerPrint
[   OK ] LoggingFixture.FatalLoggerPrint (0 ms)
[ RUN  ] LoggingFixture.PanicLoggerPrint
[   OK ] LoggingFixture.PanicLoggerPrint (0 ms)
[ RUN  ] LoggingFixture.BaseMessage
[   OK ] LoggingFixture.BaseMessage (0 ms)
[ RUN  ] LoggingFixture.BaseMessageOnce
[   OK ] LoggingFixture.BaseMessageOnce (0 ms)
[ RUN  ] LoggingFixture.Warn
[   OK ] LoggingFixture.Warn (0 ms)
[ RUN  ] LoggingFixture.Inform
[   OK ] LoggingFixture.Inform (0 ms)
[ RUN  ] LoggingFixture.Hack
[   OK ] LoggingFixture.Hack (0 ms)
[ RUN  ] LoggingFixture.WarnOnce
[   OK ] LoggingFixture.WarnOnce (0 ms)
[ RUN  ] LoggingFixture.InformOnce
[   OK ] LoggingFixture.InformOnce (0 ms)
[ RUN  ] LoggingFixture.HackOnce
[   OK ] LoggingFixture.HackOnce (0 ms)
[ RUN  ] LoggingFixture.WarnIf
[   OK ] LoggingFixture.WarnIf (0 ms)
[ RUN  ] LoggingFixture.WarnIfOnce
[   OK ] LoggingFixture.WarnIfOnce (0 ms)
[--] 21 tests from LoggingFixture (0 ms total)

[--] Global test environment tear-down
[==] 34 tests from 2 test suites ran. (1714 ms total)
[  PASSED  ] 34 tests.
 [SO Param] m5.objects.SimObject, SimObject -> NULL/params/SimObject.hh
 [ENUMDECL] m5.objects.StaticInstFlags, StaticInstFlags -> 
NULL/enums/StaticInstFlags.hh
 [ENUMDECL] m5.objects.SimObject, ByteOrder -> NULL/enums/ByteOrder.hh
 [ENUMDECL] m5.objects.FuncUnit, OpClass -> NULL/enums/OpClass.hh
build/NULL/base/socket.test.opt 
--gtest_output=xml:build/NULL/unittests.opt/base/socket.test.xml
build/NULL/sim/byteswap.test.opt 
--gtest_output=xml:build/NULL/unittests.o